[all-commits] [llvm/llvm-project] d7da49: [clang][flang][docs] Re-land Markdown CLI ref gene...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Wed Sep 9 05:20:00 PDT 2026
Branch: refs/heads/users/alexey-bataev/spr/slpdrop-unprofitable-splat-gather-subtrees-when-nothing-was-trimmed
Home: https://github.com/llvm/llvm-project
Commit: d7da49ea2bbc11a93f162ab2ef9755e57843075d
https://github.com/llvm/llvm-project/commit/d7da49ea2bbc11a93f162ab2ef9755e57843075d
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/docs/CMakeLists.txt
M clang/include/clang/Options/ClangOptionDocs.td
M clang/include/clang/Options/FlangOptions.td
M clang/include/clang/Options/Options.td
M clang/utils/TableGen/ClangOptionDocEmitter.cpp
M flang/docs/CMakeLists.txt
M flang/docs/FlangOptionsDocs.td
M flang/docs/FlangOptionsMan.td
Log Message:
-----------
[clang][flang][docs] Re-land Markdown CLI ref generator (#222147)
Reverts llvm/llvm-project#221937
Relands llvm/llvm-project#220385
This time, the migration includes flang command line reference
documentation, so the change passes `ninja docs-flang-html/man`.
Tracking issue: #201242
Assisted-By: Codex
Commit: 4383c7f120edc4e31294eb148a57c762d7d53170
https://github.com/llvm/llvm-project/commit/4383c7f120edc4e31294eb148a57c762d7d53170
Author: Shanzhi Chen <chenshanzhi at huawei.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
Log Message:
-----------
[BOLT][AArch64] Fix relocation type for `LDRSW` (#221939)
Fix the incorrect relocation type for `LDRSW`. It should be
`ELF::R_AARCH64_LDST32_ABS_LO12_NC`, but it was mistakenly set to
`ELF::R_AARCH64_LDST64_ABS_LO12_NC` in PR #196051.
Commit: 7209c7af3323615c632a3409a2a776b29fbac528
https://github.com/llvm/llvm-project/commit/7209c7af3323615c632a3409a2a776b29fbac528
Author: Vy Nguyen <1762963+oontvoo at users.noreply.github.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/test/Driver/modules-driver-depscan-log.cpp
Log Message:
-----------
[clang][Driver][test] Specify output path in modules-driver-depscan-log.cpp (#222209)
In `clang/test/Driver/modules-driver-depscan-log.cpp`, `%clang -c` is
invoked on `%t/A.cppm` without an explicit output file (`-o`). By
default, Clang writes the resulting object file (`A.o`) to the current
working directory.
In sandboxed or hermetic test environments where the test runner
executes with a read-only working directory (e.g., Bazel, Nix, or remote
build executors), the test fails with:
```text
error: unable to open output file 'A.o': 'Permission denied'
1 error generated.
Commit: dea8e298844a7721d6db80e2474c178d454b148c
https://github.com/llvm/llvm-project/commit/dea8e298844a7721d6db80e2474c178d454b148c
Author: Shengxin Pei <TPPPP72 at outlook.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/test/SemaCXX/cxx20-default-compare.cpp
R clang/test/SemaCXX/gh147127.cpp
Log Message:
-----------
[clang][test] Move test `gh147127.cpp` to `cxx20-default-compare.cpp` NFC (#222208)
Follow-up #198830
Commit: e1683efa7ce0c77dbd2f3b04e05e18313aee4338
https://github.com/llvm/llvm-project/commit/e1683efa7ce0c77dbd2f3b04e05e18313aee4338
Author: Justin Bogner <mail at justinbogner.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/IR/Type.cpp
M llvm/test/CodeGen/DirectX/ResourceAccess/handle-cases.ll
M llvm/test/CodeGen/DirectX/ResourceAccess/handle-to-index.ll
M llvm/test/CodeGen/DirectX/ResourceAccess/looped-phi-nodes-resolved.ll
M llvm/test/CodeGen/DirectX/ResourceAccess/looped-phi-nodes.ll
M llvm/test/Transforms/GVN/PRE/no-phi-translate.ll
M llvm/test/Transforms/GVN/PRE/no-pre-load-for-token-like.ll
M llvm/test/Transforms/LCSSA/token-like-live-out.ll
M llvm/test/Transforms/SimpleLoopUnswitch/token-uses.ll
R llvm/test/Transforms/SimplifyCFG/token_like_type.ll
M llvm/test/Verifier/tokenlike1.ll
M llvm/test/Verifier/tokenlike5.ll
M llvm/test/Verifier/tokenlike6.ll
M llvm/test/Verifier/tokenlike7.ll
M llvm/unittests/Transforms/Utils/LocalTest.cpp
Log Message:
-----------
[IR][DirectX] Drop IsTokenLike from `dx.*` target types (#222130)
We made the DirectX resource types "token-like" a while ago in order to
prevent transforms from moving them into PHIs and the like in ways that
made determining their provenance more difficult. However, there are
patterns in HLSL that can generate the problematic IR directly and we've
since implemented logic in `DXILResourceAccess` to handle such cases
anyway. Because of this, we aren't really getting any benefit from the
types being `IsTokenLike`, and in some cases we're working with
intermediate IR that doesn't actually pass the verifier.
Drop `IsTokenLike` from the `dx.*` types since it's no longer correct or
useful. I've updated the tests to use `amdgpu.stridemark` instead, and
slightly abused `llvm.ssa.copy` in order to manufacture SSA values of
that type. I had to drop the test that actually needed a load from a
value depending on the token-like type, as there just isn't really a way
for that to come up without the resource types.
Commit: 33898fffd3c09eba75e4199749117923bc1beee2
https://github.com/llvm/llvm-project/commit/33898fffd3c09eba75e4199749117923bc1beee2
Author: Shengxin Pei <TPPPP72 at outlook.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/test/SemaCXX/ms-ctor-closure.cpp
Log Message:
-----------
[clang][test] Add test for #67685 NFC (#222212)
Commit: 8c7d76bfc1b5c75effc7bd8ecc4892be9970ea5d
https://github.com/llvm/llvm-project/commit/8c7d76bfc1b5c75effc7bd8ecc4892be9970ea5d
Author: Teresa Johnson <tejohnson at google.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/test/ThinLTO/X86/memprof-funcassigncloning.ll
M llvm/test/ThinLTO/X86/memprof-funcassigncloning2.ll
M llvm/test/Transforms/MemProfContextDisambiguation/duplicate-context-ids.ll
M llvm/test/Transforms/MemProfContextDisambiguation/funcassigncloning.ll
M llvm/test/Transforms/MemProfContextDisambiguation/funcassigncloning2.ll
M llvm/test/Transforms/MemProfContextDisambiguation/funcassigncloningrecursion.ll
M llvm/test/Transforms/MemProfContextDisambiguation/inlined3.ll
Log Message:
-----------
[MemProf] Use NodeId to break ties deterministically in identifyClones (#222126)
In identifyClones(), ties between caller edges with identical allocation
types and matching clone candidates were previously broken by comparing
the first element of ContextIds (*A->ContextIds.begin() <
*B->ContextIds.begin()).
Because ContextIds is a DenseSet, its iteration order depends on hash
table
layout and bucket distribution, introducing non-determinism across
different
runs or architectures.
Replace this tie-breaker with caller NodeId (A->Caller->NodeId <
B->Caller->NodeId),
which provides a deterministic and stable ordering. Also apply
Callee->NodeId
in CalleeCallerEdgeLessThan for consistency.
Update tests whose remark or dump order depended on the previous
tie-breaker.
For tests that verify multi-clone greedy assignment behavior
(funcassigncloning*.ll),
reorder the input MIB contexts so caller NodeIds reproduce the visit
order
exercising the extra clone creation.
Assisted-by: Gemini
Commit: b113e2640849cd75a39efeae6256d5aecc3f1446
https://github.com/llvm/llvm-project/commit/b113e2640849cd75a39efeae6256d5aecc3f1446
Author: Anshul Nigham <nigham at google.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
Log Message:
-----------
Fix Bazel build for 52d922a (#222219)
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=52d922aa153b1232813470e014635419ce006023
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 5503fa587536afa2624971224dbfc6e25d762d37
https://github.com/llvm/llvm-project/commit/5503fa587536afa2624971224dbfc6e25d762d37
Author: Thrrreeee <shijinrui at bytedance.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M bolt/lib/Passes/FixRISCVCallsPass.cpp
M bolt/test/RISCV/call-link-register.s
M bolt/test/RISCV/relax.s
Log Message:
-----------
[BOLT][RISCV] Remove redundant AUIPCs when rewriting call pairs (#221965)
`FixRISCVCallsPass` replaces the AUIPC instruction with a Noop when
converting an AUIPC/JALR pair into a call or tail-call pseudo. Add the
`NOP` annotation so the existing RemoveNops pass can remove it, avoiding
an unnecessary instruction in the output.
Commit: 7caac9be9a7f9ecda3f31802ef451a25f2b61658
https://github.com/llvm/llvm-project/commit/7caac9be9a7f9ecda3f31802ef451a25f2b61658
Author: Thrrreeee <shijinrui at bytedance.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/include/bolt/Passes/LivenessAnalysis.h
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
M bolt/lib/Target/X86/X86MCPlusBuilder.cpp
M bolt/unittests/Core/MCPlusBuilder.cpp
Log Message:
-----------
[BOLT][RISCV] Implement register analysis hooks (#220581)
This patch implements the RISC-V register-analysis hooks in
`RISCVMCPlusBuilder` that previously fell back to the unimplemented
base-class methods.
The `MCPlusBuilder` unittests fixture is also extended to create a
RISC-V binary context. New tests cover the flags-register result,
zeroing-XOR recognition, ABI register masks, general-purpose register
masks, and non-scavengeable registers. These hooks provide the
target-specific register information required by BOLT analyses and
transformations on RISC-V.
BTW, this is split out as a prerequisite fo LongJump pass implement for
RISCV.
Commit: 6ef30f15d71bab018de258496f83b8dee529ce60
https://github.com/llvm/llvm-project/commit/6ef30f15d71bab018de258496f83b8dee529ce60
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
Log Message:
-----------
[GlobalISel] Use getTypeFromIdx instead of direct table indexing in GIR_AddCImm (#222114)
Commit: 83728c8a9fe27b1427cf0125e5a7896bbb55b6ae
https://github.com/llvm/llvm-project/commit/83728c8a9fe27b1427cf0125e5a7896bbb55b6ae
Author: Dave Lee <davelee.com at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M lldb/docs/resources/formatterbytecode.md
M lldb/include/lldb/DataFormatters/FormatterBytecode.def
M lldb/include/lldb/DataFormatters/FormatterBytecode.h
M lldb/source/DataFormatters/FormatterBytecode.cpp
M lldb/source/DataFormatters/TypeSummary.cpp
M lldb/source/DataFormatters/TypeSynthetic.cpp
M lldb/unittests/DataFormatter/FormatterBytecodeTest.cpp
Log Message:
-----------
[lldb] Add APSInt representation to formatter bytecode (#220665)
Adopt a single representation for integers in the formatter bytecode
interpreter. This simplifies code generation, where the (now deprecated)
distinction of `uint64_t` and `int64_t` types could make conditionals
and other operations more complicated, by having to have code paths for
signed and unsigned.
Depends on https://github.com/llvm/llvm-project/pull/218801
Assisted-by: claude
Commit: 1261f5003d93e83295b93782b871be06db2564c4
https://github.com/llvm/llvm-project/commit/1261f5003d93e83295b93782b871be06db2564c4
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-print-before-after-all.ll
M llvm/test/Transforms/LoopVectorize/X86/funclet.ll
M llvm/test/Transforms/LoopVectorize/vplan-print-before-after.ll
Log Message:
-----------
[VPlan] Split simplifyRecipes into simplifyRecipes and combineRecipes (#221924)
Bringing it in line with InstSimplify and InstCombine, split up
simplifyRecipe into a function that modifies and creates recipes
(combineRecipe), and one that is analysis-only (simplifyRecipe).
This allows us to avoid adding simplficiation only folds to the worklist
in #213899.
The funclet.ll test no longer erases the constant-folded intrinsic call
because vputils::isDeadRecipe returns false.
Commit: bcef85f08355c76d1e7e98604ed68fa1d93c2022
https://github.com/llvm/llvm-project/commit/bcef85f08355c76d1e7e98604ed68fa1d93c2022
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPMemoryUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPMemoryUtils.h
Log Message:
-----------
[SLP][modularisation][NFC] Move compress load/store helpers to SLPMemoryUtils (#222038)
Move the following BoUpSLP-independent masked-load/store compress
helpers out of SLPVectorizer.cpp into
SLPVectorizer/SLPMemoryUtils.{h,cpp}:
isMaskedLoadCompress (both overloads)
isMaskedStoreCompress
buildCompressMask, used only by isMaskedLoadCompress, moves alongside
them and stays file-local. isMaskedLoadCompress reads the file-local
SLPReVec cl::opt; the option stays static in SLPVectorizer.cpp and the
moved helper takes its value as an explicit bool parameter. Behavior is
unchanged.
Part of the SLPVectorizer.cpp modularization effort:
https://discourse.llvm.org/t/modularizing-slpvectorizer-cpp/90922
Assisted by AI
Commit: 4f45ae199557874671659bf59b2875e06ec2a0ff
https://github.com/llvm/llvm-project/commit/4f45ae199557874671659bf59b2875e06ec2a0ff
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/CMakeLists.txt
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPReductionUtils.cpp
A llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPReductionUtils.h
M llvm/utils/gn/secondary/llvm/lib/Transforms/Vectorize/BUILD.gn
Log Message:
-----------
[SLP][modularisation][NFC] Move reduction match helpers to SLPReductionUtils (#222052)
Move the following BoUpSLP-independent reduction pattern-match helpers
out of SLPVectorizer.cpp into a new
SLPVectorizer/SLPReductionUtils.{h,cpp}:
getNonPhiOperand
isReductionCandidate
matchRdxBop, used only by these two, moves alongside them and stays
file-local. Behavior is unchanged.
Part of the SLPVectorizer.cpp modularization effort:
https://discourse.llvm.org/t/modularizing-slpvectorizer-cpp/90922
Assisted by AI
Commit: 90e4efa54ff95f7895522fbe152a8da86bf4e446
https://github.com/llvm/llvm-project/commit/90e4efa54ff95f7895522fbe152a8da86bf4e446
Author: Thrrreeee <shijinrui at bytedance.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M bolt/unittests/Core/CMakeLists.txt
Log Message:
-----------
[BOLT][NFC] Fix CoreTests linking with shared libraries (#222225)
`CoreTests` directly uses `Triple` and `SubtargetFeatures` constructors
from `LLVMTargetParser` but does not declare the dependency. This causes
undefined-symbol errors with BUILD_SHARED_LIBS=ON.
https://github.com/llvm/llvm-project/pull/220581
Fix https://lab.llvm.org/buildbot/#/builders/218/builds/6464.
Commit: 7c4aac7e60f9f813df5693dcc735bda7873594f7
https://github.com/llvm/llvm-project/commit/7c4aac7e60f9f813df5693dcc735bda7873594f7
Author: Jason Molenda <jmolenda at apple.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M lldb/unittests/API/CMakeLists.txt
Log Message:
-----------
[lldb] Link API unit tests against LLVMTestingSupport. (#222206)
Changes to lldb have added a dependency on llvm::detail::TakeError, this
fails to link on my desktop without the dependency. Most other unittests
already link to LLVMTestingSupport.
Commit: 23074079b992a232aabca0d982ee15d818a5b4a7
https://github.com/llvm/llvm-project/commit/23074079b992a232aabca0d982ee15d818a5b4a7
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/bedrock/Session.h
M orc-rt/test/unit/bedrock/SessionTest.cpp
Log Message:
-----------
[orc-rt] Add Session::attach for pre-mode ControllerAccesses. (#222227)
Allow clients to attach a session using a pre-constructed
ControllerAccess object. This allows clients to use non-trivial
construction methods (e.g. factories) to build ControllerAccess objects.
Commit: 786ba30e072e92648840ddbb5bc3f76e0af35b07
https://github.com/llvm/llvm-project/commit/786ba30e072e92648840ddbb5bc3f76e0af35b07
Author: Dharuni R Acharya <125176188+DharuniRAcharya at users.noreply.github.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/include/llvm/IR/Intrinsics.td
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
M llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
Log Message:
-----------
[LLVM][AutoUpgrade] Support default args on undeclared multi-call upgrades (#216246)
When an `.ll` file contains multiple calls to an intrinsic without an explicit
declaration, only the first call is upgraded successfully, and the remaining
subsequent calls fail.
`LLParser` builds one temporary Function per call, so after the first
upgrade occupies the canonical name the later functions are uniquified
(eg. `llvm.foo.1`). The intrinsic ID was previously looked up using `F->getName()`,
which requires an exact name match. So, the uniquified names resolved to `not_intrinsic`,
causing the upgrade to return and the default arguments were not applied.
This patch fixes this issue by using the cached `F->getIntrinsicID()`,
which is set when the temporary function is created from the original name.
It also `rename(F)` before inserting the full declaration, so the temporary
function no longer occupies the canonical name.
---------
Signed-off-by: DharuniRAcharya <dharunira at nvidia.com>
Commit: 1fddb91bf4ad2c3012c107f0cf792e2b2a5a9b67
https://github.com/llvm/llvm-project/commit/1fddb91bf4ad2c3012c107f0cf792e2b2a5a9b67
Author: ShashwathiNavada <shashwathinavada at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Semantics/modfile86.f90
A flang/test/Semantics/modfile87.f90
A flang/test/Semantics/resolve132.f90
Log Message:
-----------
[Flang][Semantics] Diagnose missing MODULE prefix in submodule procedures (#197173)
Add a portability warning when a submodule procedure is missing the
MODULE prefix required by a MODULE PROCEDURE interface in its parent
module.
Commit: b53c11f42061e7e020af1a0e2a54f53b4a2dde3f
https://github.com/llvm/llvm-project/commit/b53c11f42061e7e020af1a0e2a54f53b4a2dde3f
Author: Anshul Nigham <nigham at google.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/OpenACC/Support/BUILD.bazel
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/OpenACC/Transforms/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Fix Bazel build (#222232)
Add missing deps and update sharding for ROCDLDialect
Commit: 8d4c923371a73b9f60bee93d91c1cc0c3b49b89e
https://github.com/llvm/llvm-project/commit/8d4c923371a73b9f60bee93d91c1cc0c3b49b89e
Author: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
A clang-tools-extra/docs/clang-tidy/checks/readability/function-cognitive-complexity.md
R clang-tools-extra/docs/clang-tidy/checks/readability/function-cognitive-complexity.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/function-size.md
R clang-tools-extra/docs/clang-tidy/checks/readability/function-size.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/identifier-length.md
R clang-tools-extra/docs/clang-tidy/checks/readability/identifier-length.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/identifier-naming.md
R clang-tools-extra/docs/clang-tidy/checks/readability/identifier-naming.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/implicit-bool-conversion.md
R clang-tools-extra/docs/clang-tidy/checks/readability/implicit-bool-conversion.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/inconsistent-declaration-parameter-name.md
R clang-tools-extra/docs/clang-tidy/checks/readability/inconsistent-declaration-parameter-name.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/inconsistent-ifelse-braces.md
R clang-tools-extra/docs/clang-tidy/checks/readability/inconsistent-ifelse-braces.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/isolate-declaration.md
R clang-tools-extra/docs/clang-tidy/checks/readability/isolate-declaration.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/magic-numbers.md
R clang-tools-extra/docs/clang-tidy/checks/readability/magic-numbers.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/make-member-function-const.md
R clang-tools-extra/docs/clang-tidy/checks/readability/make-member-function-const.rst
Log Message:
-----------
[clang-tidy][docs] Rename readability check docs to Markdown [2/5] (#221528)
Tracking issue: #201242
See the [migration guide] for more information.
[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
This is the second part of the mechanical rename of the check
documentations in readability module.
The rewrite is provided by the next PR in this stack.
Commit: 30e244ed348addbc4611466404dd717d5906a1a7
https://github.com/llvm/llvm-project/commit/30e244ed348addbc4611466404dd717d5906a1a7
Author: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang-tools-extra/docs/clang-tidy/checks/readability/function-cognitive-complexity.md
M clang-tools-extra/docs/clang-tidy/checks/readability/function-size.md
M clang-tools-extra/docs/clang-tidy/checks/readability/identifier-length.md
M clang-tools-extra/docs/clang-tidy/checks/readability/identifier-naming.md
M clang-tools-extra/docs/clang-tidy/checks/readability/implicit-bool-conversion.md
M clang-tools-extra/docs/clang-tidy/checks/readability/inconsistent-declaration-parameter-name.md
M clang-tools-extra/docs/clang-tidy/checks/readability/inconsistent-ifelse-braces.md
M clang-tools-extra/docs/clang-tidy/checks/readability/isolate-declaration.md
M clang-tools-extra/docs/clang-tidy/checks/readability/magic-numbers.md
M clang-tools-extra/docs/clang-tidy/checks/readability/make-member-function-const.md
Log Message:
-----------
[clang-tidy][docs] Rewrite readability check docs to Markdown [2/5] (#221529)
Tracking issue: #201242
See the [migration guide] for more information.
[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
This is the second part of rewriting check documentations in readability
module from reST to MyST Markdown.
AI Usage: This was prepared with rnk's fork of rst2myst and
GPT5.6-assisted cleanup.
I manually verified that the documentation renders as expected.
Preview site:
https://broken.life/llvm-staging/readability-markdown-port/index.html
---------
Co-authored-by: EugeneZelenko <eugene.zelenko at gmail.com>
Commit: c1872e7fd3307679a2da53f9d83de0ccf234b4ad
https://github.com/llvm/llvm-project/commit/c1872e7fd3307679a2da53f9d83de0ccf234b4ad
Author: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M .mailmap
Log Message:
-----------
[mailmap] Add entry for Zeyi Xu (#222237)
Commit: 5e973ba5721412c7d31349e56172ed9086f4c5e2
https://github.com/llvm/llvm-project/commit/5e973ba5721412c7d31349e56172ed9086f4c5e2
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/test/AST/absurdly_big_struct.cpp
Log Message:
-----------
[clang][test] Make new absurdly_big_struct test more targeted (#219897)
The previous version of `y()` used `c2[i]`, which can't be evaluated at
compile-time.
The emitted diagnostic depends on something calling
`ASTContext::getASTRecordLayout()` for `b`, which currently happens in
the constant evaluator. If the evaluator decides to evaluate `c2[i]`
before calling `getASTRecordLayout()`, the test fails since the
diagnostic is never emitted.
Fix this by simply using `c2[0]` instead.
Commit: 60969adcbc2fca5779580ca93ba00a7b06cc0e40
https://github.com/llvm/llvm-project/commit/60969adcbc2fca5779580ca93ba00a7b06cc0e40
Author: Steven Wu <stevenwu at apple.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/include/llvm/Support/FileSystem.h
Log Message:
-----------
[Support][FileSystem] Prefer `status` with `file_t` parameter. NFC. (#157581)
When searching the documentation for LLVM for `llvm::sys::fs::status`,
only the version with file descriptor can be found because the
documentation is built on the UNIX host and the file handle version is
defined out.
In reality, file handle version is more portable and should be displayed
instead. On UNIX, these two functions have the same underlying type,
thus it shouldn't matter which one is declared, and both versions are
still available on Windows for compatibility.
Commit: bf1d0038c9715c93e8d3ec95bf5923d57acd2b39
https://github.com/llvm/llvm-project/commit/bf1d0038c9715c93e8d3ec95bf5923d57acd2b39
Author: Letu Ren <fantasquex at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
Log Message:
-----------
[mlir][LLVM] Add clmul intrinsics (#222113)
Assisted-by: gpt-5.6-sol
Signed-off-by: Letu Ren <fantasquex at gmail.com>
Commit: 79f1047ae03783dbcf7506b99d265e5a803fbd3c
https://github.com/llvm/llvm-project/commit/79f1047ae03783dbcf7506b99d265e5a803fbd3c
Author: Wenju He <wenju.he at intel.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/include/llvm/Passes/PassBuilder.h
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/test/Other/new-pm-O0-ep-callbacks.ll
M llvm/test/Other/new-pm-thinlto-postlink-defaults.ll
M llvm/tools/opt/NewPMDriver.cpp
Log Message:
-----------
[PassBuilder] Add ThinLTO EP callbacks mirroring FullLinkTimeOptimizationEarly/Last (#221857)
Our downstream has a request to add customization pass into
ThinLinkTimeOptimizationEarlyEPCallback, but buildThinLTODefaultPipeline
has no equivalent EPCallback like buildLTODefaultPipeline does. This PR
add it and ThinLinkTimeOptimizationLastEPCallback as well.
Co-authored-by: Claude <noreply at anthropic.com>
Commit: b61bc342396753be2c56dc6abb7d06cfc6be6b25
https://github.com/llvm/llvm-project/commit/b61bc342396753be2c56dc6abb7d06cfc6be6b25
Author: David Green <david.green at arm.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/arm64-vmul.ll
M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
Log Message:
-----------
[AArch64] Update and regenerate vec-combine-compare-to-bitmask.ll. NFC (#222242)
Commit: b4b7775cfa79d7e3382657037eb037f8c7cb2428
https://github.com/llvm/llvm-project/commit/b4b7775cfa79d7e3382657037eb037f8c7cb2428
Author: Steffen Larsen <sholstla at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/test/CIR/CodeGen/atomic-scoped.c
M clang/test/CIR/CodeGen/atomic.c
Log Message:
-----------
[CIR] Preserve volatile semantics for atomic operations (#220874)
This commit fixes the preservation of volatile semantics for atomic RMW
operations in CIR CodeGen.
Signed-off-by: Steffen Holst Larsen <sholstla at amd.com>
Commit: e3a60a700dfa488adebd546705424aae7c8b3a35
https://github.com/llvm/llvm-project/commit/e3a60a700dfa488adebd546705424aae7c8b3a35
Author: Vishank Singh <vishanksinghh at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M libcxx/docs/Status/Cxx26Issues.csv
M libcxx/include/__ranges/lazy_split_view.h
A libcxx/test/std/ranges/range.adaptors/range.lazy.split/range.lazy.split.outer.value/ctor.compile.pass.cpp
R libcxx/test/std/ranges/range.adaptors/range.lazy.split/range.lazy.split.outer.value/ctor.default.pass.cpp
R libcxx/test/std/ranges/range.adaptors/range.lazy.split/range.lazy.split.outer.value/ctor.iter.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.lazy.split/range.lazy.split.outer/deref.pass.cpp
Log Message:
-----------
[libc++][ranges] Implement LWG4013: Make `lazy_split_view::outer-iterator::value_type` non-default-constructible (#221919)
Remove the default constructor of `outer-iterator::value_type` and make
the remaining constructor private (exposition-only), as required by LWG
4013.
Update the corresponding tests:
- `ctor.default.pass.cpp` and `ctor.iter.pass.cpp` are now deleted.
- `ctor.compile.pass.cpp` is added to verify `value_type` is not
default-constructible and its construction from iterator is not
available.
- Cases testing construction of `value_type` via `operator*` are moved
to `range.lazy.split.outer/deref.pass.cpp`.
Closes #105321
Commit: 580484b5032d55cf6adac0fe1274a4ee8eaa0c2a
https://github.com/llvm/llvm-project/commit/580484b5032d55cf6adac0fe1274a4ee8eaa0c2a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/test/TableGen/AMDGPUTargetDefSubArchSpelling.td
M llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
Log Message:
-----------
AMDGPU: Remove unused getBaseArchNameAMDGCN (#222157)
This ended up unused for gfx1250-strict
Co-authored-by: Claude <noreply at anthropic.com>
Commit: 1e744320ff27ee748c1a2a121fe226984efddc1b
https://github.com/llvm/llvm-project/commit/1e744320ff27ee748c1a2a121fe226984efddc1b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
Log Message:
-----------
GlobalISel: Drop AllowFPOpFusion from CombinerHelper FMA formation (#221918)
Only rely on the contract flags.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 27e964eceb2f15fb99618e73bd92f02f4a938816
https://github.com/llvm/llvm-project/commit/27e964eceb2f15fb99618e73bd92f02f4a938816
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Shared/SymbolNameSpec.h
Log Message:
-----------
[ORC] Require symbol name kind in SymbolNameSpec constructor. (#222238)
Require clients to spell out the naming level that SymbolNameSpecs are
expressed in. (An implicit default is a footgun, and adds limited
convenience)
Commit: 7bb9b13816ef9616425525651ea629f2138b194f
https://github.com/llvm/llvm-project/commit/7bb9b13816ef9616425525651ea629f2138b194f
Author: Frederik Harwath <frederik.harwath at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
M llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
M llvm/test/MC/AMDGPU/gfx13_asm_vop3.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
Log Message:
-----------
[AMDGPU] Rework pseudo-scalar transcendental inline constant restriction handling (#208459)
The f16 pseudo-scalar transcendental instructions do not support inline
constants on gfx12. The existing handling of this restriction is
incomplete. It involves checking the
hasNoF16PseudoScalarTransInlineConstants function in the right places.
For the SIInstrInfo::isInlineConstant function, for instance, this has
led to a situation where some overloads respect the restriction and
others do not. This approach also relies on completely disabling the
folding of constant operands. The machine code emission does still use
the inline constant encoding if it encounters a suitable operand.
Introduce a new "noinline" operand type and use it for the instruction
variant that is used on gfx12. This does also enable the use of literal
constants.
Commit: f4b84aa292909aa0e737cc0cdfa9eda7ef4bd4f2
https://github.com/llvm/llvm-project/commit/f4b84aa292909aa0e737cc0cdfa9eda7ef4bd4f2
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanValue.h
A llvm/test/Transforms/LoopVectorize/RISCV/scatter-type-mismatch.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-flags.ll
A llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-intrinsic.ll
M llvm/unittests/Transforms/Vectorize/VPDomTreeTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Log Message:
-----------
[VPlan] Consolidate VPIWithType and VPI (NFC) (#203019)
The extra ResultType has been absorbed into VPInstruction, and the
recipe classes can now be consolidated. The patch also fixes missing
flags-printing in the case of WideIVStep, and includes a test to guard
against bad changes, discovered during the review process.
Commit: 962a202be1f642f119921413293e8325e2e06757
https://github.com/llvm/llvm-project/commit/962a202be1f642f119921413293e8325e2e06757
Author: Machillka <machillka2007 at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang-tools-extra/clangd/InlayHints.cpp
M clang-tools-extra/clangd/unittests/InlayHintTests.cpp
Log Message:
-----------
[clangd] Place deduced return type hints after noexcept (#219829)
Deduced return type hints for functions and lambdas could appear before
a `noexcept` specifier, even though a trailing return type belongs after
the exception specification.
Use the end of the function type's local source range when it is
available. For lambdas without a function type location, keep the end of
the lambda introducer as a fallback.
Fixes clangd/clangd#2696
Assisted-by: Codex
Commit: a1f878adc64fee90fca87382a01013eca7e19b2b
https://github.com/llvm/llvm-project/commit/a1f878adc64fee90fca87382a01013eca7e19b2b
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/lib/Serialization/ASTWriter.cpp
A clang/test/Modules/pr222002.cppm
Log Message:
-----------
[C++20] [Modules] Keep DeductionGuideDecl in the general lookup table (#222246)
Close https://github.com/llvm/llvm-project/issues/222002
The root cause of the problem is, the deduction guide was not in the
general lookup table. The fix is to move them into the general lookup
table. This should be fine as the DeductionGuide may not pollute the
name lookup results.
Commit: 6dc6c67b786260486641eb62546c34b48143e131
https://github.com/llvm/llvm-project/commit/6dc6c67b786260486641eb62546c34b48143e131
Author: David Spickett <david.spickett at arm.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M libcxx/CMakeLists.txt
M libcxxabi/CMakeLists.txt
A runtimes/cmake/Modules/GetSanitizerFlags.cmake
Log Message:
-----------
[libcxx][libcxxabi][cmake] Deduplicate sanitizer flags function (#221757)
While experimenting with flang-rt builds I realised there were two
copies of this function.
We don't need it in flang-rt right now but I figure reducing duplication
is good anyway.
Commit: 3a8bd232cfa8c08a6c7e88801696af65ed1562ea
https://github.com/llvm/llvm-project/commit/3a8bd232cfa8c08a6c7e88801696af65ed1562ea
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper-image.c
M llvm/lib/Frontend/Offloading/OffloadWrapper.cpp
M llvm/test/tools/llvm-offload-wrapper/offload-wrapper.ll
Log Message:
-----------
[OffloadWrapper] Use getPtrAdd() instead of getGetElementPtr() (#222014)
One case has a redundant zero-offset GEP. The other two just add
a byte offset in a convoluted way.
Commit: 1c1ea3793471775c5dc1bb2a4757a5ea32097967
https://github.com/llvm/llvm-project/commit/1c1ea3793471775c5dc1bb2a4757a5ea32097967
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/MustExecute.h
M llvm/lib/Analysis/MustExecute.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
Log Message:
-----------
[LoopSafetyInfo] Compute block colors lazily (NFC) (#221954)
Computing the block colors is fairly expensive, but only rarely actually
needed. We can delay computation to first use.
Fixes https://github.com/llvm/llvm-project/issues/221162.
Commit: 590a3b87dba125069e962956d562802a8173dc38
https://github.com/llvm/llvm-project/commit/590a3b87dba125069e962956d562802a8173dc38
Author: Steffen Larsen <sholstla at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/lib/CIR/Dialect/Transforms/HoistAllocas.cpp
M clang/test/CIR/Transforms/hoist-allocas.cir
Log Message:
-----------
[CIR] Reposition entry-block allocas ahead of control flow (#220496)
HoistAllocas returns early when an alloca was already in the entry
block, but being in the block is not the same as being ahead of the
control flow in it. The pass runs before FlattenCFG, which splits the
body at each structured control-flow op, so an alloca sitting after one
is left in a block that is no longer the entry block.
That matters because SROA only collects allocas from the entry block. An
alloca stranded behind a scope is invisible to it and never promoted, so
anything whose address it holds stays in memory.
Commit: ddf2077559587500f47e3666c696b7366bb36af0
https://github.com/llvm/llvm-project/commit/ddf2077559587500f47e3666c696b7366bb36af0
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/FinalizeISel.cpp
M llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
Log Message:
-----------
[GlobalISel] Fix duplicate finalizeLowering calls (NFC) (#221902)
Improves CTMark geomean -0.07% on aarch64-O0-g.
https://llvm-compile-time-tracker.com/compare.php?from=97cbc1e404b980edc58bfbcabb6f1c61793b624b&to=d8b1a78ba013d5e687acc0e8bf00d3d77749f3db&stat=instructions:u
Assisted-by: codex
Commit: cdd1900816f625eb1f38a6e755c49ccadec56209
https://github.com/llvm/llvm-project/commit/cdd1900816f625eb1f38a6e755c49ccadec56209
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/FastISel.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/IR/Attributes.h
M llvm/include/llvm/IR/Attributes.td
M llvm/include/llvm/IR/InstrTypes.h
M llvm/lib/Analysis/Lint.cpp
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TypePromotion.cpp
M llvm/lib/IR/Attributes.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/IR/VerifierAMDGPU.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Transforms/IPO/ExpandVariadics.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
M llvm/test/Analysis/BasicAA/call-attrs.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
M llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll
M llvm/test/CodeGen/AArch64/GlobalISel/swiftself.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
M llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll
M llvm/test/CodeGen/AMDGPU/waterfall-call-inreg-agpr.ll
M llvm/test/CodeGen/ARM/returned-ext.ll
M llvm/test/CodeGen/ARM/struct-byval-loop.ll
M llvm/test/CodeGen/M68k/multiple-return.ll
M llvm/test/CodeGen/NVPTX/forward-ld-param.ll
M llvm/test/CodeGen/RISCV/rvv/shrinkwrap.ll
M llvm/test/CodeGen/RISCV/shrinkwrap.ll
M llvm/test/CodeGen/SPARC/64abi.ll
M llvm/test/CodeGen/SystemZ/args-14.ll
M llvm/test/CodeGen/SystemZ/call-zos-01.ll
M llvm/test/CodeGen/VE/Scalar/call.ll
M llvm/test/CodeGen/VE/Scalar/va_callee.ll
M llvm/test/CodeGen/VE/Vector/fastcc_caller.ll
M llvm/test/CodeGen/WebAssembly/signext-zeroext-callsite.ll
M llvm/test/CodeGen/X86/bool-zext.ll
M llvm/test/CodeGen/X86/return-ext.ll
M llvm/test/Instrumentation/ThreadSanitizer/tsan_basic.ll
M llvm/test/Transforms/DeadArgElim/deadexternal.ll
M llvm/test/Transforms/Inline/access-attributes-prop.ll
M llvm/test/Transforms/PhaseOrdering/pr64289-tce.ll
M llvm/test/Transforms/SROA/readonlynocapture.ll
M llvm/test/Transforms/SimplifyCFG/hoist-sink-swifterror-store.ll
M llvm/unittests/IR/AttributesTest.cpp
Log Message:
-----------
[IR] Do not inherit ABI attributes from the callee (#207173)
Usually attributes that are missing on the call-site are inherited form
the callee instead. This is fine for optional optimization attributes,
but problematic for ABI-affecting attributes.
ABI attributes generally must be placed at the call-site as well,
because there is no callee to inherit from for indirect calls. Failing
to specify ABI attributes at the call-site generally indicates a bug.
The motivation for being stricter about this (apart from just being the
right thing to do) is to properly support cases where the attributes at
the call-site and the callee actually differ. Two examples I'm aware of
are:
* During cross-language LTO, it's possible to have one side use a `ptr`
argument and the other a `ptr byval(ptr)` argument. Both represent the
same ABI using different IR encodings, but you can't just inherit the
`byval` attribute from one to the other (because the byval case requires
an additional level of indirection in use of the argument).
* To fix our incompatibility with the x86-64 psABI, I believe we'll want
to do something like emit zeroext/signext at function returns and
call-site arguments only, so that we both don't assume incoming values
are zero/sign-extended, but still zero/sign-extend outgoing values. This
makes sure we still remain compatible with old Clang-generated object
files.
We've attempted to make a change like this previously, but ran into
substantial issues with missing call-site attributes on
compiler-inserted calls. The issue was particularly severe on s390x,
which requires zeroext/signext on more values than other architectures.
I believe that the situation here has improved a lot in the meantime,
with libcalls now inferring mandatory ABI attributes, and s390x also
using a noext attribute plus validation logic in the backend to detect
cases where the necessary attributes are missing.
-----
ABI attributes on call-sites must be queried using `hasABIParamAttr()`
and `hasABIRetAttr()` instead of `paramHasAttr()` and `hasRetAttr()`
now. Passing an ABI attribute to the latter two will result in an
assertion failure.
Commit: 8c3cb9c166e8f5ade26bc90a4a4cf5ec628f894f
https://github.com/llvm/llvm-project/commit/8c3cb9c166e8f5ade26bc90a4a4cf5ec628f894f
Author: Vikram Hegde <Vikram.Hegde at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-epilog-phi.mir
M llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-gen-structure.mir
M llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-loop-carried-mem.mir
Log Message:
-----------
[CodeGen][NPM] Port MachinePipeliner to NPM (#221676)
changes of note,
1. registers the pass with AMDGPUCodeGenPassBuilder::addPreRegAlloc()
2. Changes the core MachinePipeliner::run() method to return actual
"Changed" state
Commit: d0a59913f8cfc3041c9d284e36858aedbf8dfa0e
https://github.com/llvm/llvm-project/commit/d0a59913f8cfc3041c9d284e36858aedbf8dfa0e
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/include/llvm/IR/DerivedTypes.h
M llvm/include/llvm/IR/Type.h
M llvm/include/llvm/SandboxIR/Type.h
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/IR/Type.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/unittests/SandboxIR/TypesTest.cpp
Log Message:
-----------
[IR] Remove obsolete visited sets from type queries (NFC) (#221743)
Recursive types have been rejected since 2024 (#114799), making the
visited sets in type queries unnecessary.
Improves CTMark geomean -0.08% on aarch64-O0-g. Also improves
compile-time slightly for several other targets.
https://llvm-compile-time-tracker.com/compare.php?from=97cbc1e404b980edc58bfbcabb6f1c61793b624b&to=45c1423e7e38b6950ae760fc159ecb69cafdd691&stat=instructions%3Au
Assisted-by: codex
Commit: 531a8ac4c959dbdabcb4fea4a31beecde36bcdd9
https://github.com/llvm/llvm-project/commit/531a8ac4c959dbdabcb4fea4a31beecde36bcdd9
Author: Manuel Carrasco <Manuel.Carrasco at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
M llvm/test/CodeGen/SPIRV/debug-info/debug-function-definition-call-before-alloca.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-function-definition-calls.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-function-definition-external-call.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-inlined-at-recursive.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-inlined-at.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-block.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-calls.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-if-phi.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-loop-merge.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-loop.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-selection-merge.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-shared.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-no-line.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-scope-block.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-scope-no-scope-block.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-scope-no-scope.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-scope-same-line.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-scope-shared.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-scope.ll
Log Message:
-----------
Add support for NSDI DebugScope, DebugNoScope and DebugInlinedAt (#218959)
Add support for NSDI
[DebugScope](https://github.khronos.org/SPIRV-Registry/nonsemantic/NonSemantic.Shader.DebugInfo.html#DebugScope),
[DebugNoScope](https://github.khronos.org/SPIRV-Registry/nonsemantic/NonSemantic.Shader.DebugInfo.html#DebugNoScope)
and
[DebugInlinedAt](https://github.khronos.org/SPIRV-Registry/nonsemantic/NonSemantic.Shader.DebugInfo.html#DebugInlinedAt).
DebugScope/DebugNoScope are region delimiters following the same region
rule as DebugLine/DebugNoLine. The two regions are tracked separately
because a DebugScope region could span several DebugLine regions, and
either can skip emission on a cache miss at different times.
DebugInlinedAt is not an region instruction, so it is emitted at module
scope. We allow recursive traversal when building them to support
chains.
The PR also adds a test showing a limitation in the DebugLine
deduplication that is at the DILocation pointer level which may lead to
duplicate opcodes.
Commit: c4cd7b73e27839103badad11e4eff9baf3d53d84
https://github.com/llvm/llvm-project/commit/c4cd7b73e27839103badad11e4eff9baf3d53d84
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M lldb/source/Plugins/ExpressionParser/Clang/ClangASTImporter.cpp
M llvm/include/llvm/ADT/DenseMap.h
M llvm/lib/MCA/InstrBuilder.cpp
M llvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Transforms/Scalar/GVNSink.cpp
M llvm/unittests/ADT/DenseMapTest.cpp
M llvm/utils/lldbDataFormatters.py
M third-party/unittest/googletest/include/gtest/internal/custom/gtest-printers.h
Log Message:
-----------
[ADT] Give DenseMapPair its own members instead of a std::pair base. NFC (#221853)
std::pair declares a copy assignment operator, so it is not trivially
copyable. destroyAll and copyFrom therefore ask about KeyT and ValueT
separately. Hold first and second directly.
Conversion to std::pair is explicit; insert also takes a bucket, and a
converting constructor keeps range insert working across pair types.
Co-authored-by: Kazu Hirata <kazu at google.com>
Commit: 5bf967cb132bf6700474813f961f657af6ef83ea
https://github.com/llvm/llvm-project/commit/5bf967cb132bf6700474813f961f657af6ef83ea
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/test/CodeGen/target-data.c
M clang/test/CodeGenHIP/amdgpu-barrier-type.hip
M clang/test/CodeGenOpenCL/amdgpu-env-amdgcn.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
M lld/test/ELF/lto/amdgcn-oses.ll
M lld/test/ELF/lto/amdgcn.ll
M lld/test/ELF/lto/amdgpu.ll
M llvm/docs/AMDGPUUsage.rst
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/Support/AMDGPUAddrSpace.h
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/Type.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerExecSync.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/TargetParser/TargetDataLayout.cpp
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/always_uniform.ll
A llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync-and-module-lds.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync-and-sw-lds.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll
M llvm/test/CodeGen/AMDGPU/attributor-noalias-addrspace.ll
A llvm/test/CodeGen/AMDGPU/barrier-addrspace-dereference.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-named-barrier.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-named-barrier.ll
A llvm/test/CodeGen/AMDGPU/null-named-barrier-gv.ll
M llvm/test/CodeGen/AMDGPU/s-barrier-id-allocation.ll
A llvm/test/CodeGen/AMDGPU/s-barrier-lowering-bad-absolute-symbol.ll
A llvm/test/CodeGen/AMDGPU/s-barrier-lowering-wrong-gv-signature.ll
M llvm/test/CodeGen/AMDGPU/s-barrier-lowering.ll
M llvm/test/CodeGen/AMDGPU/s-barrier-signal-var-gep.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
M mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-barriers-gfx12.mlir
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
Log Message:
-----------
[RFC][AMDGPU] Add BARRIER address space (#209746)
Add a new BARRIER address space that is used for global variables that
are used to represent the barrier IDs in GFX12.5.
These barrier addresses just have values corresponding 1-1 to barrier
IDs. They are still implemented on top of LDS, but the offsetting
happens during an addrspacecast to generic, not whenever the barrier GV
is used.
The motivation for this is to make the relation between LDS and barrier
GVs explicit in the compiler. It does add a bit more complexity, but
that complexity was already there, just hidden by pretending barrier GVs
were actual LDS.
Commit: 59c5d5efb7343424d243e4a3972f7b24a07b115d
https://github.com/llvm/llvm-project/commit/59c5d5efb7343424d243e4a3972f7b24a07b115d
Author: Hans Wennborg <hans at hanshq.net>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
A llvm/test/CodeGen/X86/branch-on-zero.ll
Log Message:
-----------
[X86] Enable preferZeroCompareBranch() (#219919)
This makes CodeGenPrepare reorganize code such as:
```
%c = icmp eq i32 %x, 10
br %c, then, else
%a = add i32 %x, -10
```
into
```
%a = add i32 %x, -10
%cmp = icmp eq %a, 0
%br %cmp, then, else
```
so that the zero-compare and branch gets lowered to a JCC based on the
flags from the arithmetic instruction.
This was already enabled for ARM, SystemZ and RISC-V, but seems a good
fit for X86 too, as mentioned in Issue #58636.
Commit: cdab5d7b28a38112cf91784ea7d404d2d4c6a68e
https://github.com/llvm/llvm-project/commit/cdab5d7b28a38112cf91784ea7d404d2d4c6a68e
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/include/llvm/Support/AMDGPUAddrSpace.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
Log Message:
-----------
[AMDGPU] Add synthetic apertures and use them for barriers (#209748)
Define what a synthetic aperture is, and adjust the barrier AS
to use this new system. This makes the barrier AS even safer to
use as now we can use all 32 bits of it without ever risking
hitting a valid address of any kind (LDS or outside LDS).
Commit: 1770693262b32d2216d7224fd412d78ab07e1bfa
https://github.com/llvm/llvm-project/commit/1770693262b32d2216d7224fd412d78ab07e1bfa
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Add scalar-type-infer assert for casts (NFC) (#222258)
Casts require the ResultTy to be passed: add an assert to
computeScalarTypeForInstruction to guard against incorrect usage.
Commit: 39ffb93f2cc8b24d0b8a588dc042a4d931273ada
https://github.com/llvm/llvm-project/commit/39ffb93f2cc8b24d0b8a588dc042a4d931273ada
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/arm64-abi_align.ll
M llvm/test/CodeGen/AMDGPU/loop-address.ll
M llvm/test/CodeGen/Hexagon/insert4.ll
M llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll
M llvm/test/CodeGen/Hexagon/vect/vect-xor.ll
M llvm/test/Transforms/LoopVectorize/dbg.value.ll
M llvm/test/Transforms/LoopVectorize/vectorize-once.ll
M llvm/test/Transforms/SimplifyCFG/volatile-phioper.ll
Log Message:
-----------
llvm: Remove phantom fp-contract-model attributes from tests (#221925)
This attribute has never been consumed by upstream llvm,
or emitted by upstream clang. I can only guess this existed in
at least one downstream fork.
Commit: f796b25647e378a02482ef383f2db45804d8fb72
https://github.com/llvm/llvm-project/commit/f796b25647e378a02482ef383f2db45804d8fb72
Author: yingopq <115543042+yingopq at users.noreply.github.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.h
A llvm/test/CodeGen/Mips/jalr-no-mangle.ll
Log Message:
-----------
[Mips] Strip \x01 no-mangle prefix from R_MIPS_JALR symbol name (#219427)
R_MIPS_JALR relocation did not strip the \x01 no-mangle prefix, causing
linker to see two different symbols: my_target_sym and
\x01my_target_sym.
Use Mangler::getNameWithPrefix() to process the symbol name.
Fix #207470.
Commit: 68a77b6106d375eabb8a7ec2585a0f3e0382c4a2
https://github.com/llvm/llvm-project/commit/68a77b6106d375eabb8a7ec2585a0f3e0382c4a2
Author: Steffen Larsen <sholstla at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-wave32.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-wave64.hip
Log Message:
-----------
[CIR][AMDGPU] Implement inverse_ballot and read_exec codegen (#221661)
This commit implements the CIR codegen for the following AMDGPU
builtins:
- __builtin_amdgcn_inverse_ballot_w32
- __builtin_amdgcn_inverse_ballot_w64
- __builtin_amdgcn_read_exec
- __builtin_amdgcn_read_exec_lo
- __builtin_amdgcn_read_exec_hi
inverse_ballot_w32/w64 map to llvm.amdgcn.inverse.ballot. read_exec,
read_exec_lo and read_exec_hi read the exec mask as a ballot over an
all-true predicate, at least as wide as the wavefront.
Commit: 411a8eea0c269fff79700da1b3a9e71914718d4b
https://github.com/llvm/llvm-project/commit/411a8eea0c269fff79700da1b3a9e71914718d4b
Author: Robert Imschweiler <robert.imschweiler at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M openmp/runtime/src/i18n/en_US.txt
M openmp/runtime/src/kmp_settings.cpp
M openmp/runtime/src/kmp_traits.cpp
M openmp/runtime/src/kmp_traits.h
M openmp/runtime/unittests/Traits/TestOMPTraitParser.cpp
Log Message:
-----------
[libomp] Parse OMP_DEFAULT_DEVICE with new device trait parser (#176166)
... but do not yet expose the new functionalities to the user. This is a
backward compatible update that is going to be followed by the step to
the OpenMP 6.0 semantics as defined in 4.3.8.
Commit: 9a14832f08551e15620440391910bc6919904775
https://github.com/llvm/llvm-project/commit/9a14832f08551e15620440391910bc6919904775
Author: Valery Pykhtin <valery.pykhtin at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Log Message:
-----------
[AMDGPU] Check a wide copy dst reg against the dst operand's regclass (#221789)
The wide-copy check added in #214561 tested the destination against the
source operand's class. No test change: V_MOV_B64's source class VS_64
also accepts a VGPR destination, which is why it currently works. Adding
@robertvirany.
Co-authored-by: Claude <noreply at anthropic.com>
Commit: cd2f66534d425b3db62fea6df9703ffb87c6c3c5
https://github.com/llvm/llvm-project/commit/cd2f66534d425b3db62fea6df9703ffb87c6c3c5
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/GISelWorkList.h
Log Message:
-----------
[GlobalISel] Lazily reserve worklist maps (NFC) (#221900)
Small -0.03% geomean improvement on CTMark aarch64-O0-g, but consistent
little improvements across the board.
https://llvm-compile-time-tracker.com/compare.php?from=97cbc1e404b980edc58bfbcabb6f1c61793b624b&to=1729db67721b79fcb72469111d543e6df28c1185&stat=instructions:u
Assisted-by: codex
Commit: d6a334df0889026e0d91d3fc5adf452e0bbf0682
https://github.com/llvm/llvm-project/commit/d6a334df0889026e0d91d3fc5adf452e0bbf0682
Author: Petr Kurapov <petr.kurapov at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
A llvm/test/MC/AMDGPU/buffer-op-lds-operand.s
A llvm/test/tools/llvm-mca/AMDGPU/buffer-op-lds-operand.s
Log Message:
-----------
[AMDGPU][AsmParser]: Use dummy operand for parsing buffer LDS isAsync… (#219459)
… operand.
After the introduction of .async for LDS buffer ops variants, there a
similar mca crash addressed in
https://github.com/llvm/llvm-project/pull/165305. This parses a dummy
operand as a placeholder.
Commit: 4b8b168e8b6897fe3816949a316002ee8aff2e98
https://github.com/llvm/llvm-project/commit/4b8b168e8b6897fe3816949a316002ee8aff2e98
Author: Andreas Leitner <leitner.andi at googlemail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/read-register-src-flat-scratch-base.ll
A llvm/test/CodeGen/AMDGPU/read-write-register-src-flat-scratch-base-invalid-subtarget.ll
A llvm/test/CodeGen/AMDGPU/type-mismatch-src-flat-scratch-base.ll
A llvm/test/CodeGen/AMDGPU/write-register-src-flat-scratch-base.ll
Log Message:
-----------
[AMDGPU] Add getRegisterByName support for src_flat_scratch_base (#220560)
Expose `src_flat_scratch_base`, `src_flat_scratch_base_lo`, and
`src_flat_scratch_base_hi` through `llvm.read_register` /
`llvm.write_register`.
The implementation is basically the same as the existing named-register
support for `flat_scratch`
It errors out on targets without `FeatureGloballyAddressableScratch`
(pre-gfx1250).
Commit: 0c62d834abff9b180def1b32d3cf9c225d504994
https://github.com/llvm/llvm-project/commit/0c62d834abff9b180def1b32d3cf9c225d504994
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/LoopVectorize.h
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
M llvm/test/Transforms/LoopVectorize/replicate-region-cost-probability.ll
M llvm/unittests/Transforms/Vectorize/VPlanTestBase.h
Log Message:
-----------
[VPlan] Record estimated branch probabilities on VPlan0 for cost modeling (#216172)
Update execution frequency/probability tracking in VPlan to also include
estimates from BFI, and use the information in VPlan for VPlan-based
cost computations, removing another remaining IR-based lookup.
We need to differentiate between estimated and concrete profile
information when annotating branches with information from BFI (using
custom !vplan.prof.estimated metadata instead of !prof) and track if a
computed frequency contains any estimates using an extra bool which is
also encoded in the metadata (so we do not synthesize !prof
for such frequencies during codegen).
The new code should only request BFI if needed, and compile-time impact
should be in the noise:
https://llvm-compile-time-tracker.com/compare.php?from=8436dd4a2bfe57d0b3fb6c9c11c69d75c1d1bccb&to=4d60694fed5e5765d4f5a2a72aac7b8674e512e2&stat=instructions:u
PR: https://github.com/llvm/llvm-project/pull/216172
Commit: 17b659b8444a957ea2b42cb4e91d65897fee7558
https://github.com/llvm/llvm-project/commit/17b659b8444a957ea2b42cb4e91d65897fee7558
Author: Yao Qi <yao_qi at apple.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M lldb/unittests/Target/MemoryTest.cpp
Log Message:
-----------
[lldb] [unittests] Cover what the memory cache reads from the inferior (#221015)
`MemoryCache`'s tests checked how many bytes a read returned, never
which requests the cache made to get them, so a change to the request
shape could not fail a test. Add four tests over the request log
`DummyProcess` now keeps.
Two assert what the cache sends: `TestReadRequestShape` checks the
address and size of every request, and `TestReadRangesFromCaches` checks
that a range the cache already holds is served without reaching the
inferior.
`TestFlushAtTheTopOfTheAddressSpace` pins `Flush`'s current behavior at
the wrap, not correct behavior. When a flushed range wraps past
`UINT64_MAX`, `Flush` counts cache lines only from the start of the
range to the top of the address space, never the lines the wrapped
portion covers between address 0 and the range's end. This bug predates
this change; the following cache-partition change fixes it, and this
test's assertion that address 0 survives the flush will need to flip
once
that lands.
`TesetMemoryCacheRead` gains one assertion, that a line whose reply
falls short leaves the error alone, next to the two requests it already
checks.
Also add a `CacheTestProcess` helper and use it in the seven cache
tests, so each states its setup in two lines rather than thirteen, and
expose the L2 map next to L1 for assertions.
---------
Co-authored-by: Jonas Devlieghere <jonas at devlieghere.com>
Commit: 7f0421be7f82a64796fa002b85bedbd6eaacc57f
https://github.com/llvm/llvm-project/commit/7f0421be7f82a64796fa002b85bedbd6eaacc57f
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/test/CodeGen/AMDGPU/idemponent-atomics.ll
M llvm/test/CodeGen/AMDGPU/mmra.ll
Log Message:
-----------
[AMDGPU] Remove unsound idempotent atomicrmw to atomic load lowering (#218377)
An idempotent atomicrmw still holds a slot in the modification order, so
folding it to a plain load can drop synchronization the memory model
requires
Commit: 8e84c4a901a7fe6ba80b3c305b200c3e9bbc4606
https://github.com/llvm/llvm-project/commit/8e84c4a901a7fe6ba80b3c305b200c3e9bbc4606
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/arm64-abi_align.ll
M llvm/test/CodeGen/AMDGPU/loop-address.ll
M llvm/test/CodeGen/Hexagon/insert4.ll
M llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll
M llvm/test/CodeGen/Hexagon/vect/vect-xor.ll
M llvm/test/Transforms/LoopVectorize/dbg.value.ll
M llvm/test/Transforms/LoopVectorize/vectorize-once.ll
M llvm/test/Transforms/SimplifyCFG/volatile-phioper.ll
Log Message:
-----------
llvm: Remove phantom ssp-buffers-size attributes from tests (#221928)
"ssp-buffers-size" was never a real function attribute. There is
"stack-protector-buffer-size". This may have existed in a downstream
fork, but it's also irrelevant for these tests.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 4af454042b636fc6f7b1b99e178247989863b8e5
https://github.com/llvm/llvm-project/commit/4af454042b636fc6f7b1b99e178247989863b8e5
Author: Guray Ozen <guray.ozen at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M mlir/docs/Remarks.md
M mlir/include/mlir/IR/Remarks.h
M mlir/lib/IR/Remarks.cpp
M mlir/unittests/IR/RemarkTest.cpp
Log Message:
-----------
[MLIR][Remark] Expose RemarkEngine filter queries (#222262)
Expose following filter APIs publicly:
```
| Query | Answers |
|----------------------------------------------|------------------------------------------------------|
| `isAnyRemarkEnabled()` | At least one category filter is active |
| `isAnyRemarkEnabled(category)` | Some kind of remark is enabled for the category |
| `isRemarkEnabled(kind, category)` | Remarks of `kind` are enabled for the category |
| `is{Passed,Missed,Analysis,Failed}OptRemarkEnabled(category)` | Per-kind query |
```
Assisted by Claude Fable 5.1
Commit: 468a7300de067ec0581f51cbfb56421f4b13eaf0
https://github.com/llvm/llvm-project/commit/468a7300de067ec0581f51cbfb56421f4b13eaf0
Author: David Spickett <david.spickett at arm.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M lldb/source/Host/common/NativeProcessProtocol.cpp
Log Message:
-----------
[lldb][lldb-server] Log possible breakpoint PC in hex (#222285)
Commit: e87fb92a9719c1f1f0112e108f9444bb5b99ac49
https://github.com/llvm/llvm-project/commit/e87fb92a9719c1f1f0112e108f9444bb5b99ac49
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
A llvm/test/CodeGen/AArch64/fp-intrinsics-bf16.ll
Log Message:
-----------
[NFC][LLVM][AArch64] Add test coverage for scalar bfloat constrained intrinsics. (#222076)
Tests are a clone of fp-intrinsics-fp16.ll with s/half/bfloat/ applied
and failing tests (fcmp and i128 variants) removed.
Commit: 4e7628708d6d09c4051fd1fa54cb6b517db326fe
https://github.com/llvm/llvm-project/commit/4e7628708d6d09c4051fd1fa54cb6b517db326fe
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
Log Message:
-----------
[GlobalISel] Restrict value offset tracking to aggregates (NFC) (#221287)
The single-vreg fast path added in d30d5fe8dd5d3 still populated an
offset list, even though offsets are only necessary for aggregate
values.
This wasn't the only place doing so. Avoid creating or updating offset
lists for non-aggregate values and add an assertion to enforce this
invariant.
Small -0.04% geomean improvement on CTMark aarch64-O0-g.
https://llvm-compile-time-tracker.com/compare.php?from=97cbc1e404b980edc58bfbcabb6f1c61793b624b&to=2aeb9d236a2cacf8ab93722b8b629243384bae68&stat=instructions:u
Assisted-by: codex
Commit: cc38b29781cbc0a2b525a18833adf61c51375af2
https://github.com/llvm/llvm-project/commit/cc38b29781cbc0a2b525a18833adf61c51375af2
Author: Tianyi Chen <diannaaav at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/test/Misc/cc1as-darwin-target-variant-sdk-version.s
M clang/test/Misc/cc1as-darwin-target-variant-triple.s
M llvm/test/MC/MachO/diff-with-two-sections.s
M llvm/test/MC/MachO/weakdef.s
M llvm/test/MC/MachO/zero-space.s
A llvm/test/tools/llvm-readobj/MachO/cpu-capabilities.yaml
M llvm/test/tools/llvm-readobj/MachO/file-headers-arm64.test
M llvm/test/tools/llvm-readobj/MachO/file-headers.test
M llvm/tools/llvm-readobj/MachODumper.cpp
Log Message:
-----------
[llvm-readobj] Display Mach-O CPU capability bits (#221617)
The Mach-O file header output masks the capability bits out of
`cpusubtype`
without printing them separately, so this information is missing from
the
output.
Add a `CpuCapabilities` field to print the high byte in hexadecimal,
matching the numeric representation used by `llvm-objdump`.
Fixes #80198.
Assisted-by: OpenAI Codex (implementation, tests, and initial
description).
Commit: 6a20cac62912114cbc9208b565cf88fd73f21377
https://github.com/llvm/llvm-project/commit/6a20cac62912114cbc9208b565cf88fd73f21377
Author: Tianyi Chen <diannaaav at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/docs/CommandGuide/llvm-objdump.md
M llvm/tools/llvm-objdump/ObjdumpOpts.td
Log Message:
-----------
[llvm-objdump] Document selecting symbols containing commas (#221619)
The documentation does not clearly distinguish how
`--disassemble-symbols=`
and `--disassemble=<symbol>` handle their arguments, making it easy to
overlook how to select symbols whose names contain commas.
Update the command guide and help text to explain that the former
accepts
a comma-separated list of symbols, while the latter accepts a single
symbol
name and may be specified multiple times.
Assisted-by: OpenAI Codex
Commit: 95dfce1739bf2719f89a9f6673eb5b23f2d32b09
https://github.com/llvm/llvm-project/commit/95dfce1739bf2719f89a9f6673eb5b23f2d32b09
Author: David Green <david.green at arm.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SchedNeoverseV3.td
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-neon-instructions.s
Log Message:
-----------
[AArch64] Add Neoverse V3 scheduling info for v264 frecpe (#221917)
This was missing, falling back to the default information. It should be
like the others.
This is the Neoverse V3 equivalent of #219115
Commit: 3d2f88da6e15645080d852d52c32435b62aca97b
https://github.com/llvm/llvm-project/commit/3d2f88da6e15645080d852d52c32435b62aca97b
Author: Timur Golubovich <timur.golubovich at intel.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/avx512-masked-op-fusion.ll
Log Message:
-----------
[X86] Fix commuteSelect miscompile with double-used condition value (#219436)
The multi-use loop iterated `Cond->users()` which yields duplicates when
a select uses the condition in multiple operand positions. This caused a
double-commute and iterator corruption, leaving other selects with an
inverted condition but unswapped operands.
Remove the in-place mutation loop and return a new select node. The DAG
combiner visits each select independently and `getSetCC` CSEs the
inverted condition so all commuted selects share it.
Commit: 4200a8e34e488aaf9c1b5b1966aa4c1bbec8b4d5
https://github.com/llvm/llvm-project/commit/4200a8e34e488aaf9c1b5b1966aa4c1bbec8b4d5
Author: Oscar Priego <oscar.priegov at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86CompressEVEX.cpp
M llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
M llvm/test/CodeGen/X86/compress-evex-vpmov-blendv.mir
M llvm/test/CodeGen/X86/compress-evex-vpmov-kill.mir
Log Message:
-----------
[X86] Compress masked VPBLENDM using VBLENDV (#221838)
Fixes #221678.
This extends the X86 EVEX compression pass to recognize compatible
`VPMOVD2M/VPMOVQ2M + VPBLENDMD/VPBLENDMQ` patterns and replace them with
the corresponding VEX `VBLENDVPS/VBLENDVPD` instruction when the mask
width and element granularity match.
For example, the reported AVX-512 sequence:
```asm
vpslld $31, %xmm0, %xmm0
vpmovd2m %xmm0, %k1
vpblendmd %xmm1, %xmm2, %xmm0 {%k1}
```
is reduced to:
```asm
vpslld $31, %xmm0, %xmm0
vblendvps %xmm0, %xmm1, %xmm2, %xmm0
```
The fold is restricted to compatible producer/consumer pairs.
Mixed-width or mixed-element-granularity cases such as
`VPMOVD2MZ128 + VPBLENDMQZ256` are intentionally left unchanged.
The MIR coverage includes:
- 128-bit and 256-bit dword/qword positive cases.
- An incompatible-width negative case.
- Kill/liveness preservation for the reused vector mask.
The existing `avx512-regcall-NoMask.ll` codegen checks are also updated
to reflect the optimized `VBLENDVPS` sequence produced by this fold.
Local validation includes:
- `compress-evex-vpmov-blendv.mir`
- `compress-evex-vpmov-kill.mir`
- `avx512-regcall-NoMask.ll`
- `compress-evex-sign-mask.mir`
- `evex-to-vex-compress.mir`
- `bitcast-sign-mask.ll`
AI-assisted tools were used during investigation and development.
The resulting changes were reviewed, modified, validated, and tested by
me.
Signed-off-by: Oscar Priego Verdugo <oscar.priegov at gmail.com>
Commit: 79230407a26e8d7de47e4c8e7b7f7b0d63bee00c
https://github.com/llvm/llvm-project/commit/79230407a26e8d7de47e4c8e7b7f7b0d63bee00c
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/include/clang/AST/ASTContext.h
M clang/lib/AST/ASTContext.cpp
Log Message:
-----------
[clang][AST][NFC] Make ASTContext::isPFPField() static (#220265)
Commit: 09520670fec80a117bb34307ef684cf8bafbe71b
https://github.com/llvm/llvm-project/commit/09520670fec80a117bb34307ef684cf8bafbe71b
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M lldb/source/Target/StackFrameRecognizer.cpp
M lldb/test/API/commands/frame/recognizer/step-through/TestFrameRecognizerStepThrough.py
Log Message:
-----------
[lldb] Match frame recognizers by function when the frame has no symbol (#222060)
A frame can have a function without having a symbol: a PE/COFF image
built with DWARF carries no symbol table at all, so `symctx.symbol` is
null on Windows while `symctx.function` resolves fine from the debug
info. `GetRecognizerForFrame` bailed out on `!symbol`, so no frame
recognizer ever matched there.
Fall back to the function's start address when there is no symbol. The
symbol still wins when both are present, so this is a no-op on
ELF/Mach-O.
This fixes `TestFrameRecognizerStepThrough.py`.
Commit: 48ae4d3b158042b4ad77a6b23aa412aedac7105a
https://github.com/llvm/llvm-project/commit/48ae4d3b158042b4ad77a6b23aa412aedac7105a
Author: William Tran-Viet <wtranviet at proton.me>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M libcxx/include/__optional/optional_ref.h
M libcxx/test/std/utilities/optional/optional.monadic/transform.pass.cpp
Log Message:
-----------
[libc++] Fix `optional<T>::transform` into `optional<T&>` (#221506)
Resolves #220332
- Make `optional<T>` a friend of `optional<T&>`, and add tests.
Commit: 6b728014512aefa838e3b1674355589c901cdde2
https://github.com/llvm/llvm-project/commit/6b728014512aefa838e3b1674355589c901cdde2
Author: Alexander Wilson <rdtscp at meta.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M bolt/lib/Core/Relocation.cpp
M bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
M bolt/lib/Target/RISCV/RISCVMCSymbolizer.cpp
M bolt/lib/Target/RISCV/RISCVMCSymbolizer.h
A bolt/test/RISCV/call-relocation-pair.s
A bolt/test/RISCV/unsymbolized-call-edge.s
A bolt/test/RISCV/unsymbolized-call-entry.s
A bolt/test/RISCV/unsymbolized-call.s
A bolt/test/RISCV/unsymbolized-long-jump.s
Log Message:
-----------
[BOLT][RISCV] Fix AUIPC/JALR call rewriting (#216882)
This builds on the RISC-V decoder support from #217550 and the BOLT
target symbolizer and GOT relocation handling from #217944, both of
which are now merged.
`R_RISCV_CALL` and `R_RISCV_CALL_PLT` cover an AUIPC/JALR pair, but BOLT
treated them as four-byte relocations and decoded only the AUIPC
immediate. Read both instructions and combine their signed high and low
immediates so relocated call targets retain the low 12 bits.
LTO can also leave linker-resolved intra-section AUIPC/JALR calls
without relocations. On RV64, recognize standard call and tail-call
pairs during disassembly, reconstruct the target (including JALR
target-bit clearing), and attach an exact entry-point symbol before
function reordering. Alternate link-register preservation is provided by
the merged #218408.
This follows the RISC-V Unprivileged ISA sections on AUIPC and JALR:
https://docs.riscv.org/reference/isa/v20260120/unpriv/rv32.html
It also follows the RISC-V ELF psABI procedure-call relocations:
https://riscv-non-isa.github.io/riscv-elf-psabi-doc/#_relocations
Tests cover relocation-backed calls, relocation-free RV64 calls and tail
calls, exact function entry points, signed offsets, JALR target-bit
clearing, and rejection of near matches.
Validation:
- Rebuilt `llvm-bolt`, `llvm-mc`, `llvm-objdump`, `llvm-readelf`, and
`lld`.
- All 658 tests in `bolt/test/RISCV` and `llvm/test/MC/RISCV` pass on
current `main`.
**Scope:** Relocation-free recovery is intentionally RV64-only. RV32
XLEN-wrapped target arithmetic remains out of scope. Symbolizer
infrastructure and GOT correctness are provided by #217944 rather than
this PR.
Assisted-by: Codex
Commit: accf16eec44ec81449fe8cbf0ddd53c1ff567247
https://github.com/llvm/llvm-project/commit/accf16eec44ec81449fe8cbf0ddd53c1ff567247
Author: Mariya Podchishchaeva <Mariya.Podchishchaeva at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/include/clang/Lex/Lexer.h
M clang/lib/Parse/ParseExprCXX.cpp
M clang/lib/Parse/ParseTentative.cpp
A clang/test/Parser/cuda-operator-lesslessless.cu
Log Message:
-----------
[clang][CUDA/HIP] Fix parsing of `operator<<<...>` (#218384)
In CUDA mode Lexer merges `<<<` into a single token and Parser fails to
recognize that it is actually a template specialization of `operator<<`
and not a CUDA kernel call expression. Split `<<<` following operator
token to `<<` and `<`.
Commit: be7f0c897238a2d4ae742d1b6db50283069bdeef
https://github.com/llvm/llvm-project/commit/be7f0c897238a2d4ae742d1b6db50283069bdeef
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/arm64-abi_align.ll
M llvm/test/CodeGen/AMDGPU/loop-address.ll
M llvm/test/CodeGen/Hexagon/insert4.ll
M llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll
M llvm/test/CodeGen/Hexagon/vect/vect-xor.ll
M llvm/test/Transforms/LoopVectorize/dbg.value.ll
M llvm/test/Transforms/LoopVectorize/vectorize-once.ll
M llvm/test/Transforms/SimplifyCFG/volatile-phioper.ll
Log Message:
-----------
llvm: Remove phantom relocation-model attributes from tests (#221931)
"relocation-model" was never a real function attribute.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: a86b58566a2581160938db41fa258ff84457b80c
https://github.com/llvm/llvm-project/commit/a86b58566a2581160938db41fa258ff84457b80c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M lld/test/ELF/amdgpu-tid.s
M llvm/docs/AMDGPUUsage.rst
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/test/MC/AMDGPU/amdgcn-target-directive-conflict.s
M llvm/test/MC/AMDGPU/amdgcn_target_directive_from_eflags.s
M llvm/test/MC/AMDGPU/hsa-diag-v4.s
M llvm/test/MC/AMDGPU/hsa-tg-split.s
M llvm/test/MC/AMDGPU/hsa-v4.s
M llvm/test/MC/AMDGPU/hsa-v5-uses-dynamic-stack.s
M llvm/test/MC/AMDGPU/user-sgpr-count.s
M llvm/test/MC/AMDGPU/xnack-mask.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-cov5.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx10.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx90a.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx950.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-sgpr.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-vgpr.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx10.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx9.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-raw.s
Log Message:
-----------
AMDGPU: Remove xnack and sramecc subtarget features (#212792)
Now that these are controlled by module flags, the subtarget
features were just used for assembler and disassembler controls.
Now that the assembler and disassembler can infer these from
the e_flags and target directives, they are no longer necessary.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Commit: ebeb871f9a5fd31f088b7fb952c99cc4da17eeb1
https://github.com/llvm/llvm-project/commit/ebeb871f9a5fd31f088b7fb952c99cc4da17eeb1
Author: Tuomas Kärnä <tuomas.karna at intel.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
Log Message:
-----------
[MLIR][XeGPU] Restrict XeGPUPropagateLayout analysis scope (#221793)
This PR prevents concurrent access to traversal and mutation of the
shared IR by restricting the walk scope to determine program order
within each gpu.module.
Previously, although the pass is scoped to a single gpu.module, this
walk climbs all the way up to the enclosing top-level builtin.module and
traverses the entire module — including sibling gpu.modules. When there
is multiple gpu.modules, it causes concurrent traversal and mutation of
the shared IR and eventually leads to a segfault.
Assisted-by: Claude
Commit: b3e641630cbe0c25022e6033bdfc1cbf1fc215b4
https://github.com/llvm/llvm-project/commit/b3e641630cbe0c25022e6033bdfc1cbf1fc215b4
Author: Tomohiro Kashiwada <kikairoya at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/test/SemaCXX/dllimport.cpp
Log Message:
-----------
[Clang](NFC) Rewrite test/SemaCXX/dllimport.cpp as done for dllexport.cpp (#191391)
Commit: 2189cea443f1bb69861af2a1994b11f5aaa5be68
https://github.com/llvm/llvm-project/commit/2189cea443f1bb69861af2a1994b11f5aaa5be68
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
A llvm/test/Transforms/LoopVectorize/AArch64/select-first-index-narrow.ll
A llvm/test/Transforms/LoopVectorize/find-last-ptr-induction.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
A llvm/test/Transforms/LoopVectorize/select-first-index-narrow.ll
Log Message:
-----------
[LV] Add tests for argmin/argmax with a narrow index and ptr IVs (NFC) (#222290)
Extend test coverage for argmin/argmax with truncated IVs and pointer
inductions.
Commit: ef208564acbfc9e8fef0d6c436bac1681f1a6778
https://github.com/llvm/llvm-project/commit/ef208564acbfc9e8fef0d6c436bac1681f1a6778
Author: Kareem Ergawy <kergawy at nvidia.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M flang/include/flang/Optimizer/Analysis/AliasAnalysis.h
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/lib/Optimizer/Transforms/LoopInvariantCodeMotion.cpp
A flang/unittests/Optimizer/AliasAnalysisRecursiveEffectsCacheTest.cpp
M flang/unittests/Optimizer/CMakeLists.txt
Log Message:
-----------
[fir][aa] Add opt-in cache for use by fir `AliasAnalysis` clients (#221973)
Adds `AliasAnalysisRecursiveEffectsCache`, an opt-in cache that memoizes
per-operation read/write summaries so that `getModRef` on an operation
with `HasRecursiveMemoryEffects` does not re-walk its nested regions on
every query.
This is independent of the `getSource()` memoization added separately:
that one is keyed on (value, flags) and answers "what memory does this
value refer to", while this one is keyed on the operation and answers
"what does this operation and everything nested in it read and write".
LICM enables both, since it only hoists pure-read ops and so invalidates
neither.
Commit: 5dc123502ac6ef7de22c67685fe3519e88c51ce4
https://github.com/llvm/llvm-project/commit/5dc123502ac6ef7de22c67685fe3519e88c51ce4
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Log Message:
-----------
PowerPC: Drop AllowFPOpFusion from isProfitableToHoist (#221347)
Commit: 173ccf9996f99fd93347ca7f245d954979c811b7
https://github.com/llvm/llvm-project/commit/173ccf9996f99fd93347ca7f245d954979c811b7
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-store-chain.ll
Log Message:
-----------
[SLP]Exclude splat gather subtrees from the store chain retry size
The tree size recorded for a failed store chain attempt gates the
larger-VF retries. The splat gather subtrees are auxiliary to the store
tree and inflated the recorded size, so the deviation check skipped the
VF=4 retry and the chain fell back to VF=2 or scalar.
Reviewers: bababuck, RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/221241
Commit: 57658dfaf3b51450fb00a20c6aca0a5f94a78a0c
https://github.com/llvm/llvm-project/commit/57658dfaf3b51450fb00a20c6aca0a5f94a78a0c
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M .mailmap
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/include/bolt/Passes/LivenessAnalysis.h
M bolt/lib/Core/Relocation.cpp
M bolt/lib/Passes/FixRISCVCallsPass.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
M bolt/lib/Target/RISCV/RISCVMCSymbolizer.cpp
M bolt/lib/Target/RISCV/RISCVMCSymbolizer.h
M bolt/lib/Target/X86/X86MCPlusBuilder.cpp
M bolt/test/RISCV/call-link-register.s
A bolt/test/RISCV/call-relocation-pair.s
M bolt/test/RISCV/relax.s
A bolt/test/RISCV/unsymbolized-call-edge.s
A bolt/test/RISCV/unsymbolized-call-entry.s
A bolt/test/RISCV/unsymbolized-call.s
A bolt/test/RISCV/unsymbolized-long-jump.s
M bolt/unittests/Core/CMakeLists.txt
M bolt/unittests/Core/MCPlusBuilder.cpp
M clang-tools-extra/clangd/InlayHints.cpp
M clang-tools-extra/clangd/unittests/InlayHintTests.cpp
A clang-tools-extra/docs/clang-tidy/checks/readability/function-cognitive-complexity.md
R clang-tools-extra/docs/clang-tidy/checks/readability/function-cognitive-complexity.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/function-size.md
R clang-tools-extra/docs/clang-tidy/checks/readability/function-size.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/identifier-length.md
R clang-tools-extra/docs/clang-tidy/checks/readability/identifier-length.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/identifier-naming.md
R clang-tools-extra/docs/clang-tidy/checks/readability/identifier-naming.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/implicit-bool-conversion.md
R clang-tools-extra/docs/clang-tidy/checks/readability/implicit-bool-conversion.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/inconsistent-declaration-parameter-name.md
R clang-tools-extra/docs/clang-tidy/checks/readability/inconsistent-declaration-parameter-name.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/inconsistent-ifelse-braces.md
R clang-tools-extra/docs/clang-tidy/checks/readability/inconsistent-ifelse-braces.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/isolate-declaration.md
R clang-tools-extra/docs/clang-tidy/checks/readability/isolate-declaration.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/magic-numbers.md
R clang-tools-extra/docs/clang-tidy/checks/readability/magic-numbers.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/make-member-function-const.md
R clang-tools-extra/docs/clang-tidy/checks/readability/make-member-function-const.rst
M clang/docs/CMakeLists.txt
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/Lex/Lexer.h
M clang/include/clang/Options/ClangOptionDocs.td
M clang/include/clang/Options/FlangOptions.td
M clang/include/clang/Options/Options.td
M clang/lib/AST/ASTContext.cpp
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/lib/CIR/Dialect/Transforms/HoistAllocas.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/Parse/ParseExprCXX.cpp
M clang/lib/Parse/ParseTentative.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/test/AST/absurdly_big_struct.cpp
M clang/test/CIR/CodeGen/atomic-scoped.c
M clang/test/CIR/CodeGen/atomic.c
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-wave32.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-wave64.hip
M clang/test/CIR/Transforms/hoist-allocas.cir
M clang/test/CodeGen/target-data.c
M clang/test/CodeGenHIP/amdgpu-barrier-type.hip
M clang/test/CodeGenOpenCL/amdgpu-env-amdgcn.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
M clang/test/Driver/modules-driver-depscan-log.cpp
M clang/test/Misc/cc1as-darwin-target-variant-sdk-version.s
M clang/test/Misc/cc1as-darwin-target-variant-triple.s
A clang/test/Modules/pr222002.cppm
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper-image.c
A clang/test/Parser/cuda-operator-lesslessless.cu
M clang/test/SemaCXX/cxx20-default-compare.cpp
M clang/test/SemaCXX/dllimport.cpp
R clang/test/SemaCXX/gh147127.cpp
M clang/test/SemaCXX/ms-ctor-closure.cpp
M clang/utils/TableGen/ClangOptionDocEmitter.cpp
M flang/docs/CMakeLists.txt
M flang/docs/FlangOptionsDocs.td
M flang/docs/FlangOptionsMan.td
M flang/include/flang/Optimizer/Analysis/AliasAnalysis.h
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/lib/Optimizer/Transforms/LoopInvariantCodeMotion.cpp
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Semantics/modfile86.f90
A flang/test/Semantics/modfile87.f90
A flang/test/Semantics/resolve132.f90
A flang/unittests/Optimizer/AliasAnalysisRecursiveEffectsCacheTest.cpp
M flang/unittests/Optimizer/CMakeLists.txt
M libcxx/CMakeLists.txt
M libcxx/docs/Status/Cxx26Issues.csv
M libcxx/include/__optional/optional_ref.h
M libcxx/include/__ranges/lazy_split_view.h
A libcxx/test/std/ranges/range.adaptors/range.lazy.split/range.lazy.split.outer.value/ctor.compile.pass.cpp
R libcxx/test/std/ranges/range.adaptors/range.lazy.split/range.lazy.split.outer.value/ctor.default.pass.cpp
R libcxx/test/std/ranges/range.adaptors/range.lazy.split/range.lazy.split.outer.value/ctor.iter.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.lazy.split/range.lazy.split.outer/deref.pass.cpp
M libcxx/test/std/utilities/optional/optional.monadic/transform.pass.cpp
M libcxxabi/CMakeLists.txt
M lld/test/ELF/amdgpu-tid.s
M lld/test/ELF/lto/amdgcn-oses.ll
M lld/test/ELF/lto/amdgcn.ll
M lld/test/ELF/lto/amdgpu.ll
M lldb/docs/resources/formatterbytecode.md
M lldb/include/lldb/DataFormatters/FormatterBytecode.def
M lldb/include/lldb/DataFormatters/FormatterBytecode.h
M lldb/source/DataFormatters/FormatterBytecode.cpp
M lldb/source/DataFormatters/TypeSummary.cpp
M lldb/source/DataFormatters/TypeSynthetic.cpp
M lldb/source/Host/common/NativeProcessProtocol.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangASTImporter.cpp
M lldb/source/Target/StackFrameRecognizer.cpp
M lldb/test/API/commands/frame/recognizer/step-through/TestFrameRecognizerStepThrough.py
M lldb/unittests/API/CMakeLists.txt
M lldb/unittests/DataFormatter/FormatterBytecodeTest.cpp
M lldb/unittests/Target/MemoryTest.cpp
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/CommandGuide/llvm-objdump.md
M llvm/include/llvm/ADT/DenseMap.h
M llvm/include/llvm/Analysis/MustExecute.h
M llvm/include/llvm/CodeGen/FastISel.h
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
M llvm/include/llvm/CodeGen/GlobalISel/GISelWorkList.h
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/SymbolNameSpec.h
M llvm/include/llvm/IR/Attributes.h
M llvm/include/llvm/IR/Attributes.td
M llvm/include/llvm/IR/DerivedTypes.h
M llvm/include/llvm/IR/InstrTypes.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/IR/Type.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/Passes/PassBuilder.h
M llvm/include/llvm/SandboxIR/Type.h
M llvm/include/llvm/Support/AMDGPUAddrSpace.h
M llvm/include/llvm/Support/FileSystem.h
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/include/llvm/Transforms/Vectorize/LoopVectorize.h
M llvm/lib/Analysis/Lint.cpp
M llvm/lib/Analysis/MustExecute.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/FinalizeISel.cpp
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TypePromotion.cpp
M llvm/lib/Frontend/Offloading/OffloadWrapper.cpp
M llvm/lib/IR/Attributes.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/Type.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/IR/VerifierAMDGPU.cpp
M llvm/lib/MCA/InstrBuilder.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Target/AArch64/AArch64SchedNeoverseV3.td
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
M llvm/lib/Target/AMDGPU/AMDGPULowerExecSync.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
M llvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.h
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
M llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
M llvm/lib/Target/X86/X86CompressEVEX.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/lib/TargetParser/TargetDataLayout.cpp
M llvm/lib/Transforms/IPO/ExpandVariadics.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Scalar/GVNSink.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
M llvm/lib/Transforms/Vectorize/CMakeLists.txt
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPMemoryUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPMemoryUtils.h
A llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPReductionUtils.cpp
A llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPReductionUtils.h
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/lib/Transforms/Vectorize/VPlanValue.h
M llvm/test/Analysis/BasicAA/call-attrs.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/always_uniform.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
M llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll
M llvm/test/CodeGen/AArch64/GlobalISel/swiftself.ll
M llvm/test/CodeGen/AArch64/arm64-abi_align.ll
M llvm/test/CodeGen/AArch64/arm64-vmul.ll
A llvm/test/CodeGen/AArch64/fp-intrinsics-bf16.ll
M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
A llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync-and-module-lds.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync-and-sw-lds.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll
M llvm/test/CodeGen/AMDGPU/attributor-noalias-addrspace.ll
A llvm/test/CodeGen/AMDGPU/barrier-addrspace-dereference.ll
M llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
M llvm/test/CodeGen/AMDGPU/idemponent-atomics.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-named-barrier.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-named-barrier.ll
M llvm/test/CodeGen/AMDGPU/loop-address.ll
M llvm/test/CodeGen/AMDGPU/mmra.ll
A llvm/test/CodeGen/AMDGPU/null-named-barrier-gv.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
A llvm/test/CodeGen/AMDGPU/read-register-src-flat-scratch-base.ll
A llvm/test/CodeGen/AMDGPU/read-write-register-src-flat-scratch-base-invalid-subtarget.ll
M llvm/test/CodeGen/AMDGPU/s-barrier-id-allocation.ll
A llvm/test/CodeGen/AMDGPU/s-barrier-lowering-bad-absolute-symbol.ll
A llvm/test/CodeGen/AMDGPU/s-barrier-lowering-wrong-gv-signature.ll
M llvm/test/CodeGen/AMDGPU/s-barrier-lowering.ll
M llvm/test/CodeGen/AMDGPU/s-barrier-signal-var-gep.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll
M llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-epilog-phi.mir
M llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-gen-structure.mir
M llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-loop-carried-mem.mir
A llvm/test/CodeGen/AMDGPU/type-mismatch-src-flat-scratch-base.ll
M llvm/test/CodeGen/AMDGPU/waterfall-call-inreg-agpr.ll
A llvm/test/CodeGen/AMDGPU/write-register-src-flat-scratch-base.ll
M llvm/test/CodeGen/ARM/returned-ext.ll
M llvm/test/CodeGen/ARM/struct-byval-loop.ll
M llvm/test/CodeGen/DirectX/ResourceAccess/handle-cases.ll
M llvm/test/CodeGen/DirectX/ResourceAccess/handle-to-index.ll
M llvm/test/CodeGen/DirectX/ResourceAccess/looped-phi-nodes-resolved.ll
M llvm/test/CodeGen/DirectX/ResourceAccess/looped-phi-nodes.ll
M llvm/test/CodeGen/Hexagon/insert4.ll
M llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll
M llvm/test/CodeGen/Hexagon/vect/vect-xor.ll
M llvm/test/CodeGen/M68k/multiple-return.ll
A llvm/test/CodeGen/Mips/jalr-no-mangle.ll
M llvm/test/CodeGen/NVPTX/forward-ld-param.ll
M llvm/test/CodeGen/RISCV/rvv/shrinkwrap.ll
M llvm/test/CodeGen/RISCV/shrinkwrap.ll
M llvm/test/CodeGen/SPARC/64abi.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-function-definition-call-before-alloca.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-function-definition-calls.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-function-definition-external-call.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-inlined-at-recursive.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-inlined-at.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-block.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-calls.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-if-phi.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-loop-merge.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-loop.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-selection-merge.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-shared.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-no-line.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-scope-block.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-scope-no-scope-block.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-scope-no-scope.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-scope-same-line.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-scope-shared.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-scope.ll
M llvm/test/CodeGen/SystemZ/args-14.ll
M llvm/test/CodeGen/SystemZ/call-zos-01.ll
M llvm/test/CodeGen/VE/Scalar/call.ll
M llvm/test/CodeGen/VE/Scalar/va_callee.ll
M llvm/test/CodeGen/VE/Vector/fastcc_caller.ll
M llvm/test/CodeGen/WebAssembly/signext-zeroext-callsite.ll
M llvm/test/CodeGen/X86/avx512-masked-op-fusion.ll
M llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
M llvm/test/CodeGen/X86/bool-zext.ll
A llvm/test/CodeGen/X86/branch-on-zero.ll
M llvm/test/CodeGen/X86/compress-evex-vpmov-blendv.mir
M llvm/test/CodeGen/X86/compress-evex-vpmov-kill.mir
M llvm/test/CodeGen/X86/return-ext.ll
M llvm/test/Instrumentation/ThreadSanitizer/tsan_basic.ll
M llvm/test/MC/AMDGPU/amdgcn-target-directive-conflict.s
M llvm/test/MC/AMDGPU/amdgcn_target_directive_from_eflags.s
A llvm/test/MC/AMDGPU/buffer-op-lds-operand.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
M llvm/test/MC/AMDGPU/gfx13_asm_vop3.s
M llvm/test/MC/AMDGPU/hsa-diag-v4.s
M llvm/test/MC/AMDGPU/hsa-tg-split.s
M llvm/test/MC/AMDGPU/hsa-v4.s
M llvm/test/MC/AMDGPU/hsa-v5-uses-dynamic-stack.s
M llvm/test/MC/AMDGPU/user-sgpr-count.s
M llvm/test/MC/AMDGPU/xnack-mask.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
M llvm/test/MC/MachO/diff-with-two-sections.s
M llvm/test/MC/MachO/weakdef.s
M llvm/test/MC/MachO/zero-space.s
M llvm/test/Other/new-pm-O0-ep-callbacks.ll
M llvm/test/Other/new-pm-thinlto-postlink-defaults.ll
M llvm/test/TableGen/AMDGPUTargetDefSubArchSpelling.td
M llvm/test/ThinLTO/X86/memprof-funcassigncloning.ll
M llvm/test/ThinLTO/X86/memprof-funcassigncloning2.ll
M llvm/test/Transforms/DeadArgElim/deadexternal.ll
M llvm/test/Transforms/GVN/PRE/no-phi-translate.ll
M llvm/test/Transforms/GVN/PRE/no-pre-load-for-token-like.ll
M llvm/test/Transforms/Inline/access-attributes-prop.ll
M llvm/test/Transforms/LCSSA/token-like-live-out.ll
A llvm/test/Transforms/LoopVectorize/AArch64/select-first-index-narrow.ll
A llvm/test/Transforms/LoopVectorize/RISCV/scatter-type-mismatch.ll
M llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
M llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-print-before-after-all.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-flags.ll
A llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-intrinsic.ll
M llvm/test/Transforms/LoopVectorize/X86/funclet.ll
M llvm/test/Transforms/LoopVectorize/dbg.value.ll
A llvm/test/Transforms/LoopVectorize/find-last-ptr-induction.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/replicate-region-cost-probability.ll
A llvm/test/Transforms/LoopVectorize/select-first-index-narrow.ll
M llvm/test/Transforms/LoopVectorize/vectorize-once.ll
M llvm/test/Transforms/LoopVectorize/vplan-print-before-after.ll
M llvm/test/Transforms/MemProfContextDisambiguation/duplicate-context-ids.ll
M llvm/test/Transforms/MemProfContextDisambiguation/funcassigncloning.ll
M llvm/test/Transforms/MemProfContextDisambiguation/funcassigncloning2.ll
M llvm/test/Transforms/MemProfContextDisambiguation/funcassigncloningrecursion.ll
M llvm/test/Transforms/MemProfContextDisambiguation/inlined3.ll
M llvm/test/Transforms/PhaseOrdering/pr64289-tce.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-store-chain.ll
M llvm/test/Transforms/SROA/readonlynocapture.ll
M llvm/test/Transforms/SimpleLoopUnswitch/token-uses.ll
M llvm/test/Transforms/SimplifyCFG/hoist-sink-swifterror-store.ll
R llvm/test/Transforms/SimplifyCFG/token_like_type.ll
M llvm/test/Transforms/SimplifyCFG/volatile-phioper.ll
M llvm/test/Verifier/tokenlike1.ll
M llvm/test/Verifier/tokenlike5.ll
M llvm/test/Verifier/tokenlike6.ll
M llvm/test/Verifier/tokenlike7.ll
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-neon-instructions.s
A llvm/test/tools/llvm-mca/AMDGPU/buffer-op-lds-operand.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-cov5.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx10.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx90a.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx950.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-sgpr.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-vgpr.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx10.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx9.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-raw.s
M llvm/test/tools/llvm-offload-wrapper/offload-wrapper.ll
A llvm/test/tools/llvm-readobj/MachO/cpu-capabilities.yaml
M llvm/test/tools/llvm-readobj/MachO/file-headers-arm64.test
M llvm/test/tools/llvm-readobj/MachO/file-headers.test
M llvm/tools/llvm-objdump/ObjdumpOpts.td
M llvm/tools/llvm-readobj/MachODumper.cpp
M llvm/tools/opt/NewPMDriver.cpp
M llvm/unittests/ADT/DenseMapTest.cpp
M llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
M llvm/unittests/IR/AttributesTest.cpp
M llvm/unittests/SandboxIR/TypesTest.cpp
M llvm/unittests/Transforms/Utils/LocalTest.cpp
M llvm/unittests/Transforms/Vectorize/VPDomTreeTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTestBase.h
M llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
M llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
M llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
M llvm/utils/gn/secondary/llvm/lib/Transforms/Vectorize/BUILD.gn
M llvm/utils/lldbDataFormatters.py
M mlir/docs/Remarks.md
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/include/mlir/IR/Remarks.h
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/lib/IR/Remarks.cpp
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-barriers-gfx12.mlir
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
M mlir/unittests/IR/RemarkTest.cpp
M openmp/runtime/src/i18n/en_US.txt
M openmp/runtime/src/kmp_settings.cpp
M openmp/runtime/src/kmp_traits.cpp
M openmp/runtime/src/kmp_traits.h
M openmp/runtime/unittests/Traits/TestOMPTraitParser.cpp
M orc-rt/include/orc-rt/bedrock/Session.h
M orc-rt/test/unit/bedrock/SessionTest.cpp
A runtimes/cmake/Modules/GetSanitizerFlags.cmake
M third-party/unittest/googletest/include/gtest/internal/custom/gtest-printers.h
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/OpenACC/Support/BUILD.bazel
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/OpenACC/Transforms/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Rebase
Created using spr 1.3.7
Compare: https://github.com/llvm/llvm-project/compare/75c8e63847e7...57658dfaf3b5
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