[all-commits] [llvm/llvm-project] 0c553f: [InstCombine] Use common flags for shl in shl/trun...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Wed Sep 9 05:10:11 PDT 2026
Branch: refs/heads/users/alexey-bataev/spr/slpexclude-splat-gather-subtrees-from-the-store-chain-retry-size
Home: https://github.com/llvm/llvm-project
Commit: 0c553f573a076091f60df21618494584e9641e96
https://github.com/llvm/llvm-project/commit/0c553f573a076091f60df21618494584e9641e96
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/test/Transforms/InstCombine/trunc.ll
Log Message:
-----------
[InstCombine] Use common flags for shl in shl/trunc fold. (#221769)
As pointed out post-commit in
https://github.com/llvm/llvm-project/pull/219443, whether the flags from
the trunc can be transferred directly to the shl depends on the involved
types: https://alive2.llvm.org/ce/z/zN_TFq
For now, just use the common flags.
PR: https://github.com/llvm/llvm-project/pull/221769
Commit: 7297a1eec0d0ea5311775d36a63045a00830811b
https://github.com/llvm/llvm-project/commit/7297a1eec0d0ea5311775d36a63045a00830811b
Author: Giles Payne <gilespayne at telepathix.net>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M llvm/lib/Target/XCore/Disassembler/CMakeLists.txt
Log Message:
-----------
Fix unresolved symbol XCoreMCRegisterClassStorage (#211420)
Fix for #211419
Add missing dependency to XCoreDisAssembler's CMakeLists.txt file
Commit: c70b9c09f691d93c6e46e2692e15fb439dcb2560
https://github.com/llvm/llvm-project/commit/c70b9c09f691d93c6e46e2692e15fb439dcb2560
Author: Addmisol <addmisol9 at gmail.com>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
Log Message:
-----------
[AMDGPU] Fold redundant inf/nan checks into frexp instructions (#214936)
Fixes #204204
The AMDGPU "v_frexp_exp" and "v_frexp_mant" instructions return 0 for
inf/nan inputs. This patch adds a DAG combine
("performFrexpSelectCombine") to fold redundant inf/nan checks with
frexp results, eliminating unnecessary compare and select instructions..
### Patterns folded:
- `select (fcmp uno x, 0), 0, (frexp_exp x)` → `frexp_exp x`
- `select (fcmp oeq |x|, inf), 0, (frexp_exp x)` → `frexp_exp x`
- `select (fcmp ueq |x|, inf), 0, (frexp_exp x)` → `frexp_exp x`
- `select (fcmp ord x, 0), (frexp_exp x), 0` → `frexp_exp x`
- `select (fcmp one |x|, inf), (frexp_exp x), 0` → `frexp_exp x`
- `select (is_fpclass x, finite), (frexp_exp x), 0` → `frexp_exp x`
- Same patterns with `frexp_mant`
The optimization is disabled on SI (Southern Islands) which has
hasFractBug()..
## Test plan
- [x] Added frexp-inf-nan-combine.ll with comprehensive tests for:
- Targets: GFX9, GFX10, GFX11, GFX950 (optimization applies), SI
(optimization does NOT apply)
- Types: f32, f64, f16
- Patterns: NaN clamp, inf clamp, inf-or-nan clamp, reversed select,
not-inf check
- Negative tests: different inputs, non-zero constants, unrelated
comparisons
All existing frexp-related AMDGPU tests pass..
cc @arsenm
---------
Signed-off-by: addmisol <addmisol9 at gmail.com>
Commit: f9a8dec9496fea7c55f591a66a64dbcdc085fc2d
https://github.com/llvm/llvm-project/commit/f9a8dec9496fea7c55f591a66a64dbcdc085fc2d
Author: AZero13 <gfunni234 at gmail.com>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/and-negpow2-cmp.ll
Log Message:
-----------
[RISCV] Fix infinite DAGCombine loop with SETCC and SIGN_EXTEND_INREG (#221593)
We generalized (X & -(1 << C1) & 0xffffffff) == C2 << C1 using `sraiw`.
The combine generates a `SIGN_EXTEND_INREG` when simplifying.
However, when C1 is 0 and the sign bit (bit 31) of X is already known to
be zero, `DAGCombiner` sees that `SIGN_EXTEND_INREG` is semantically
equivalent to `AND X, 0xFFFFFFFF` (zext). Because `DAGCombiner`
considers `AND` to be more canonical than `SIGN_EXTEND_INREG` in this
context, it immediately reverts the node back to `AND`.
This caused an infinite DAGCombine loop. This patch disables the folding
when the C1 is zero. That case is covered by a later combine that already
checks if bit 31 is known to be zero.
Fixes: https://github.com/llvm/llvm-project/issues/221521
Commit: a4dd3554ec3dcde9288af34181a8d2200ecb8c9d
https://github.com/llvm/llvm-project/commit/a4dd3554ec3dcde9288af34181a8d2200ecb8c9d
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
A mlir/test/Target/LLVMIR/openmp-reduction-debug-loc.mlir
Log Message:
-----------
[OMPIRBuilder] Restore the debug location after the reduction alloca (#221253)
`createReductions` emits the array of type-erased pointers to the
private reduction values in the alloca block, which means leaving the
current insertion point and coming back. The insertion point is
re-established but the debug location is not. Everything emitted
afterwards like the `__kmpc_reduce` and the matching __kmpc_end_reduce
inherits whatever the terminator happened to carry, which is usually
nothing. This could result in a verifier error if program is linked with
openmp runtime that has debug information.
Fix it by restoring the debug location along with the InsertPoint.
Commit: 14aebab4c6fe5c9f937efcdf1ea184495de6b737
https://github.com/llvm/llvm-project/commit/14aebab4c6fe5c9f937efcdf1ea184495de6b737
Author: Arseniy Zaostrovnykh <necto.ne at gmail.com>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Core/ExprEngineCXX.cpp
M clang/test/Analysis/dtor-array.cpp
Log Message:
-----------
[analyzer] Fix crash destructing element of a sugared array type
ExprEngine::makeElementRegion falls short trying to determine the
element type of an array that involves a type aliasing a static array
type.
This leads to a crash in ExprEngine::ProcessMemberDtor where it assumes
that element type is a CXXRecordDecl, while it is still a type alias to
a static array type.
getBaseElementType is the canonical way to desugar and peel off the
array dimensions.
Assisted by Claude Opus 5
--
CPP-8838
Commit: d5f72dd27f20499b050a7f855750a7dc2013e1d5
https://github.com/llvm/llvm-project/commit/d5f72dd27f20499b050a7f855750a7dc2013e1d5
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CMakeLists.txt
M clang/lib/CIR/FrontendAction/CMakeLists.txt
M clang/lib/CIR/Interfaces/CMakeLists.txt
M clang/lib/CIR/Lowering/CMakeLists.txt
M clang/lib/CIR/Lowering/DirectToLLVM/CMakeLists.txt
M clang/tools/cir-opt/CMakeLists.txt
Log Message:
-----------
[CMake] Link only the MLIR dialects ClangIR uses (#221616)
CIR's sources reference Arith, DLTI, Func, LLVM, OpenACC, OpenMP and
Ptr, and cir-opt registers only the CIR dialects plus MemRef and LLVM.
Link those instead, which keeps Linalg, Vector, SPIRV, SparseTensor,
Tosa and GPU out of the clang build graph.
CLANG_ENABLE_CIR=ON adds 2135 build edges to the clang target; this
removes 694 of them.
LLM-aided
Commit: 89fe023484bd5b897dccefd290fe5e8536db47b0
https://github.com/llvm/llvm-project/commit/89fe023484bd5b897dccefd290fe5e8536db47b0
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/CMakeLists.txt
A mlir/include/mlir/Dialect/LLVMIR/LLVMAllOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/lib/Dialect/LLVMIR/CMakeLists.txt
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
A mlir/lib/Dialect/LLVMIR/IR/LLVMOps.cpp
A mlir/lib/Dialect/LLVMIR/IR/LLVMOps.h
Log Message:
-----------
[MLIR][LLVM] Shard generated operation definitions (NFC) (#221813)
LLVMDialect.cpp includes both the 55,078-line core operation definitions
and the 95,769-line intrinsic operation definitions. Generate the
combined operation set in eight shards, use the generated registration
hook, and expose only the parser, printer, and type-inference helpers
needed by generated code.
Assisted-by: Codex
Commit: 362194cb4c7e61949d54dfd89b05442a11da25b8
https://github.com/llvm/llvm-project/commit/362194cb4c7e61949d54dfd89b05442a11da25b8
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M clang/test/CIR/Lowering/lifetime.cir
M clang/test/CIR/Lowering/stack-save-restore.cir
M clang/test/CIR/Transforms/abi-lowering/byval-sret-arg-attr-lowering.cir
M clang/test/CIR/Transforms/abi-lowering/extend-signed-arg.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-bitint.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-complex.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-empty-class.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-scalars.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-struct-direct.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-union-coerce-shapes.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-union.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-variadic-call.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-vector.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-vptr.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-wide-floats.cir
M clang/test/CMakeLists.txt
M clang/tools/cir-translate/CMakeLists.txt
M clang/tools/cir-translate/cir-translate.cpp
Log Message:
-----------
[CIR] Register only the LLVM IR translations CIR lowers to (#221797)
The ClangIR tests reach LLVM IR through mlir-translate, which links
every MLIR dialect and translation, so building check-clang builds most
of MLIR. Register mlir-to-llvmir in cir-translate over the same three
dialects and use it instead. Remove the dependency on `mlir-translate`
to run CIR tests.
ninja check-clang drops from 6499 to 5853 build edges.
LLM-aided
Commit: b4488d4c14709dd4dd94afaa0fa1c14cde69ee13
https://github.com/llvm/llvm-project/commit/b4488d4c14709dd4dd94afaa0fa1c14cde69ee13
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/test/Conversion/AMDGPUToROCDL/gfx1250.mlir
Log Message:
-----------
[mlir][AMDGPU] Move gather index vectors at final use (NFC) (#221825)
The gather lowering copies two temporary vectors into the next
construction stage and never reads the source vectors again. Move their
storage instead.
Found by Coverity.
Assisted-by: Codex
Commit: 9fafedaa908f1844f4150ae2ba6e0eec938341c4
https://github.com/llvm/llvm-project/commit/9fafedaa908f1844f4150ae2ba6e0eec938341c4
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
Log Message:
-----------
[MLIR][linalg] Remove discarded failure conversion (#221826)
Silence warning for unused result with a `(void)` cast instead of
converting its result with failed() and then discarding the converted
value.
Fix a Coverity warning, and it's cleaner about the intent.
Assisted-by: Codex
Commit: bc1c4e23e88262a480a081f1a7ecb84e75351b61
https://github.com/llvm/llvm-project/commit/bc1c4e23e88262a480a081f1a7ecb84e75351b61
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Math/IR/MathOps.cpp
Log Message:
-----------
[MLIR][math] Remove dead IPowI fold return (NFC) (#221827)
The folder returns the constant-fold helper result directly, remove the
unreachable fallback after the helper call.
Found by Coverity.
Assisted-by: Codex
Commit: 52bc117e7930694fed38d2ffb327f77e8bd8a474
https://github.com/llvm/llvm-project/commit/52bc117e7930694fed38d2ffb327f77e8bd8a474
Author: Henrich Lauko <xlauko at mail.muni.cz>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M clang/utils/TableGen/CIRLoweringEmitter.cpp
Log Message:
-----------
[CIR] Derive lowering attr names from cppClassName, not the def name (#220891)
CIRLoweringEmitter built its CXX_ABI_ALWAYS_LEGAL_ATTRS entries with
GetOpCppClassName, which splits the TableGen def name at the first
underscore. That works only while every def is named
CIR_<CppClassName>Attr.
When one is not, the emitter writes an `isa<>` for a class that does not
exist, and the failure lands as a compile error in generated code.
Attributes carry the authoritative name in cppClassName, which
GenerateAttrToValueVisitor was already reading. Factor that out as
GetAttrCppClassRef and use it for both attribute paths.
GetOpCppClassName
stays for operations.
Commit: 87d1986bd2264b434e865044745725efbf52dda5
https://github.com/llvm/llvm-project/commit/87d1986bd2264b434e865044745725efbf52dda5
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.cpp
Log Message:
-----------
[mlir][spirv] Avoid copies of local APInt values in folds (NFC) (#221084)
Move locally constructed APInt values into arithmetic operations at
their last use. Expand conditional returns where needed so returning a
local can use implicit move construction.
Found by Coverity.
Assisted-by: Codex
Commit: 44a4dbf32a6b54de32e4d064756d7a6ba5b9e808
https://github.com/llvm/llvm-project/commit/44a4dbf32a6b54de32e4d064756d7a6ba5b9e808
Author: edisongz <edisongz123 at gmail.com>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp
M mlir/test/Dialect/Arith/int-range-narrowing.mlir
Log Message:
-----------
[MLIR][Arith] Don't narrow shifts whose amount can exceed the target width (#218495)
A shift by an amount >= the operand bitwidth is poison. Narrowing
changes that bitwidth, so an amount valid at the original width (e.g. 32
for i64) can become poison at the narrowed one (>= 32 for i32),
miscompiling `4 >> 32` from 0 to 4.
Only narrow shifts when the shift amount is provably below the target
width.
Fixes #218191
Commit: 36b179dff5c85de0a7aca763e618d8c15dd5b2e7
https://github.com/llvm/llvm-project/commit/36b179dff5c85de0a7aca763e618d8c15dd5b2e7
Author: Oliver Hunt <oliver at apple.com>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaDecl.cpp
A clang/test/Sema/global-explicit-register-undefined-type.c
Log Message:
-----------
[clang][Sema] Crash due to asm labeled incomplete global register decls (#219746)
CheckAsmLabel fails to check for an incomplete type before attempting to
get the type layout. Short circuit on an incomplete type as Sema will
already reject a global with an incomplete type.
Commit: 5b4a54a5ae59b44f6e4c898984bb184a4b05d885
https://github.com/llvm/llvm-project/commit/5b4a54a5ae59b44f6e4c898984bb184a4b05d885
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
Log Message:
-----------
[mlir][LLVM] Remove dead constant verifier return (NFC) (#221833)
Every arm of the constant attribute-kind chain returns directly, leaving
the final success return unreachable. Remove the dead statement.
Found by Coverity.
Assisted-by: Codex
Commit: 45930cef5214e430aa7424cacb07e374a07ead12
https://github.com/llvm/llvm-project/commit/45930cef5214e430aa7424cacb07e374a07ead12
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M mlir/lib/Tools/PDLL/CodeGen/MLIRGen.cpp
M mlir/lib/Tools/PDLL/Parser/Parser.cpp
M mlir/test/mlir-pdll/Parser/expr-failure.pdll
Log Message:
-----------
[mlir][PDLL] Reject overflowing unregistered result indices (#221834)
Unregistered operation result access accepts numeric member names, but
code generation emits a nonnegative I32 attribute. Reject values outside
the signed 32-bit range before building the AST and use the matching
type in codegen.
Found by Coverity.
Assisted-by: Codex
Commit: a2ce10c7c93b22ebe3540dbd2c88e5cf202860de
https://github.com/llvm/llvm-project/commit/a2ce10c7c93b22ebe3540dbd2c88e5cf202860de
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/add-nsw.ll
M llvm/test/Transforms/ConstraintElimination/cond-used-in-phi.ll
M llvm/test/Transforms/ConstraintElimination/induction-condition-in-loop-exit-postinc.ll
M llvm/test/Transforms/ConstraintElimination/induction-condition-in-loop-exit.ll
M llvm/test/Transforms/ConstraintElimination/induction-nowrap-from-scev-not-ir.ll
M llvm/test/Transforms/ConstraintElimination/loops.ll
M llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-cfg.ll
M llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-decrement.ll
M llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-wrapping.ll
M llvm/test/Transforms/ConstraintElimination/pr70510.ll
M llvm/test/Transforms/ConstraintElimination/transfer-signed-facts-to-unsigned-is-known-non-negative.ll
M llvm/test/Transforms/ConstraintElimination/wrapping-math.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/trunc-intrinsics.ll
Log Message:
-----------
[ConstraintElim] Use range-based NUW/NSW inferrence for Add. (#221487)
Factor out logic to strengthen NUW/NSW flags based on know no-wrap
regions and also use it for ADD.
This enables a number of additional folds in real-world workloads:
https://github.com/dtcxzyw/llvm-opt-benchmark-nightly/pull/1215
Compile-time impact in the noise for geomean. Per workload there are a
few improvements and one regression `lencod` (stage1-ReleaseThinLTO)
https://llvm-compile-time-tracker.com/compare.php?from=bb577f620571ce3bb97f2e717b53500574a9cf27&to=6de758abcfa6fb6e9de359b1fb5cfb67b689afe5&stat=instructions:u
PR: https://github.com/llvm/llvm-project/pull/221487
Commit: f7ce52f0f4ec943bfdc749bc67de00a1e3ece6bc
https://github.com/llvm/llvm-project/commit/f7ce52f0f4ec943bfdc749bc67de00a1e3ece6bc
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/fdot2.ll
Log Message:
-----------
[AMDGPU] Fix FDOT2 fold for non-constant lane indices (#217646)
The fold only checked that the two lane index nodes were not the same
SDValue, but distinct nodes can still be equal at runtime, silently
picking the wrong lanes
Require both indices to be constant and distinct
Commit: bea94ba6d6424468b60478c4ef1933e4c598f58f
https://github.com/llvm/llvm-project/commit/bea94ba6d6424468b60478c4ef1933e4c598f58f
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/test/CodeGen/AMDGPU/true16-fold.mir
Log Message:
-----------
[AMDGPU][True16][CodeGen] Do not fold hi16 SGPR copy (#220858)
Dropping the subreg on a hi16 copy would read the low half instead
Commit: 415d9c668e4d18908938df4847ada34cb82eb06b
https://github.com/llvm/llvm-project/commit/415d9c668e4d18908938df4847ada34cb82eb06b
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
M mlir/tools/mlir-tblgen/OpFormatGen.h
Log Message:
-----------
[mlir][ODS] Remove unconditional properties query (NFC) (#221844)
All operations emit a Properties struct, including operations without
explicit properties. Remove the stale hasProperties query and fold its
unreachable property-less paths from the operation, adaptor, and format
generators.
Found by Coverity.
Assisted-by: Codex
Commit: 95760fbf5cd5b6b9afcfff0a9639473792da5ed3
https://github.com/llvm/llvm-project/commit/95760fbf5cd5b6b9afcfff0a9639473792da5ed3
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMRequiresSMTraits.h
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/test/Dialect/LLVMIR/nvvm-target-invalid.mlir
Log Message:
-----------
[mlir][NVVM] Reject malformed target chip names (#220873)
Parse the complete sm_<version>[a|f] grammar before using the SM
version. This prevents a failed integer conversion from leaving the
version uninitialized and also rejects overflowing encodings.
Found by Coverity.
Assisted-by: Codex
Commit: 5f9d1397b6a19d6ea23d6b6d27609495d97ffa88
https://github.com/llvm/llvm-project/commit/5f9d1397b6a19d6ea23d6b6d27609495d97ffa88
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Dialect/Tosa/verifier.mlir
Log Message:
-----------
[mlir][Tosa] Handle empty block-scaled reshape shapes (#220872)
Commit: cc9a7010afd7126e8ec45fb6a967d39849613f35
https://github.com/llvm/llvm-project/commit/cc9a7010afd7126e8ec45fb6a967d39849613f35
Author: Thurston Dang <thurston at google.com>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M clang/unittests/Analysis/LifetimeSafetyTest.cpp
Log Message:
-----------
[LifetimeSafety][test] Fix UUM of fields added in #221610 and #205764 (#221843)
New LifetimeSafetyOpts fields were added in
https://github.com/llvm/llvm-project/pull/221610 but they are not
initialized in clang/unittests/Analysis/LifetimeSafetyTest.cpp, leading
to use-of-uninitialized-memory
(https://lab.llvm.org/buildbot/#/builders/164/builds/25165):
```
WARNING: MemorySanitizer: use-of-uninitialized-value
#0 0x555571559cbc in clang::lifetimes::internal::(anonymous namespace)::LifetimeChecker::LifetimeChecker(clang::lifetimes::internal::LoanPropagationAnalysis const&, clang::lifetimes::internal::MovedLoansAnalysis const&, clang::lifetimes::internal::LiveOriginsAnalysis const&, clang::lifetimes::internal::FactManager&, clang::AnalysisDeclContext&, clang::lifetimes::LifetimeSafetySemaHelper*, clang::lifetimes::LifetimeSafetyOpts const&) /home/b/sanitizer-x86_64-linux-bootstrap-msan/build/llvm-project/clang/lib/Analysis/LifetimeSafety/Checker.cpp:108:9
#1 0x5555715453cd in clang::lifetimes::internal::runLifetimeChecker(clang::lifetimes::internal::LoanPropagationAnalysis const&, clang::lifetimes::internal::MovedLoansAnalysis const&, clang::lifetimes::internal::LiveOriginsAnalysis const&, clang::lifetimes::internal::FactManager&, clang::AnalysisDeclContext&, clang::lifetimes::LifetimeSafetySemaHelper*, clang::lifetimes::LifetimeSafetyOpts const&) /home/b/sanitizer-x86_64-linux-bootstrap-msan/build/llvm-project/clang/lib/Analysis/LifetimeSafety/Checker.cpp:575:19
#2 0x555571524c1e in clang::lifetimes::internal::LifetimeSafetyAnalysis::run() /home/b/sanitizer-x86_64-linux-bootstrap-msan/build/llvm-project/clang/lib/Analysis/LifetimeSafety/LifetimeSafety.cpp:98:3
#3 0x55555c3da25b in LifetimeTestRunner /home/b/sanitizer-x86_64-linux-bootstrap-msan/build/llvm-project/clang/unittests/Analysis/LifetimeSafetyTest.cpp:71:15
...
Uninitialized value was stored to memory at
#0 0x55555bcd06c7 in __msan_memcpy /home/b/sanitizer-x86_64-linux-bootstrap-msan/build/llvm-project/compiler-rt/lib/msan/msan_interceptors.cpp:1760:3
#1 0x5555715238ed in clang::lifetimes::internal::LifetimeSafetyAnalysis::LifetimeSafetyAnalysis(clang::AnalysisDeclContext&, clang::lifetimes::LifetimeSafetySemaHelper*, clang::lifetimes::LifetimeSafetyOpts const&) /home/b/sanitizer-x86_64-linux-bootstrap-msan/build/llvm-project/clang/lib/Analysis/LifetimeSafety/LifetimeSafety.cpp:54:39
#2 0x55555c3da1b9 in make_unique<clang::lifetimes::internal::LifetimeSafetyAnalysis, clang::AnalysisDeclContext &, std::nullptr_t, clang::lifetimes::LifetimeSafetyOpts &, 0> /home/b/sanitizer-x86_64-linux-bootstrap-msan/build/libcxx_install_msan_track_origins/include/c++/v1/__memory/unique_ptr.h:713:30
#3 0x55555c3da1b9 in LifetimeTestRunner /home/b/sanitizer-x86_64-linux-bootstrap-msan/build/llvm-project/clang/unittests/Analysis/LifetimeSafetyTest.cpp:70:9
```
This patch fixes the issue by initializing the fields in the test to
true, which maintains the behavior prior to the new fields being added.
Additionally, this patch does a similar drive-by fix to the
SuggestAnnotations field (added in
https://github.com/llvm/llvm-project/pull/205764). Although there has
been no MSan report, that's likely either an MSan false negative or
insufficient test coverage.
Commit: 08b4a7559af99165fcbc1855d923e0e482a42079
https://github.com/llvm/llvm-project/commit/08b4a7559af99165fcbc1855d923e0e482a42079
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 89fe023 (#221823)
This fixes 89fe023484bd5b897dccefd290fe5e8536db47b0 (#221813).
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=89fe023484bd5b897dccefd290fe5e8536db47b0
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: d031640796e10e0fed0a6ed72e844870dc4be8b3
https://github.com/llvm/llvm-project/commit/d031640796e10e0fed0a6ed72e844870dc4be8b3
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M orc-rt/lib/bedrock/CMakeLists.txt
M orc-rt/lib/support/CMakeLists.txt
Log Message:
-----------
[orc-rt] Hide symbols by default in Bedrock and Support libs. (#221848)
Hides C/C++ symbols by default in the orc-rt Bedrock and Support
libraries. Only explicitly annotated APIs should be exposed by these
libraries.
Commit: 2e6c7bc8513ee405ca2e8a3032c1ab41a19ee90f
https://github.com/llvm/llvm-project/commit/2e6c7bc8513ee405ca2e8a3032c1ab41a19ee90f
Author: Larry Meadows <Lawrence.Meadows at amd.com>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M llvm/lib/Transforms/IPO/OpenMPOpt.cpp
A llvm/test/Transforms/OpenMP/indirect_call_specialization_cap.ll
Log Message:
-----------
[OpenMPOpt] Bound indirect-call specialization instead of paying for all of it (#219323)
`registerAAsForFunction()` seeds `AAIndirectCallInfo` unconditionally,
so device
code pays for specializing every indirect call site. Device code routes
many
calls through function-pointer tables and virtual dispatch, so a call
site can
see every address-taken candidate in the module, and the if-cascade
`AAIndirectCallInfo` builds over them is quadratic.
Skip specialization at a call site with more than three possible
callees,
overridable with `-openmp-opt-max-callees-for-specialization`. The bound
is a
threshold on the call site rather than a limit on how many callees get
specialized: the Attributor asks about each callee with the same total,
so a
site above the threshold keeps its indirect call instead of getting
three direct
ones plus a fallback.
Measured on a generated module with a 256-entry device function-pointer
table,
2048 dispatch functions and 64 target regions, gfx90a,
`opt -disable-verify -passes='openmp-opt,lto<O3>'`, min of 3 runs:
| | cap 3 | no cap |
|-----------------------------------------|-------|--------|
| LTO pipeline | 13.3s | 34.4s |
| final module, IR lines | 340k | 511k |
| cascade equality tests after openmp-opt | 310 | 499 |
The cost is not in `openmp-opt` itself, which is 1.23s either way; it is
in what
the rest of the pipeline does with the cascades. Sites at or below the
threshold
are still specialized, which `indirect_call_specialization_cap.ll`
covers from
both sides.
This PR previously carried two other changes, now split out as #221449
(loop
runtime callbacks) and #221450 (the worker-count gate), per @abidh's
request.
Tested on gfx90a: `llvm/test/Transforms/{OpenMP,Attributor}` 260 passed,
1
unsupported.
Commit: 2b7ee868b318f45372933e03d9a22203638e92db
https://github.com/llvm/llvm-project/commit/2b7ee868b318f45372933e03d9a22203638e92db
Author: Timur Baidusenov <timurbaidusenov at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
M llvm/test/Transforms/JumpThreading/update-bpi-bfi-unfold-select.ll
Log Message:
-----------
[JumpThreading] Don't divide by all-zero branch weights (#221846)
Fixes #192165.
Commit: d91284c7f5747ade780b944ef9d4cb6d8bfbbc1e
https://github.com/llvm/llvm-project/commit/d91284c7f5747ade780b944ef9d4cb6d8bfbbc1e
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M openmp/runtime/src/kmp_settings.cpp
Log Message:
-----------
[libomp] Set `KMP_USE_YIELD=2` when `OMP_WAIT_POLICY=active` if it's not specified explicitly (#199628)
This patch sets `KMP_USE_YIELD=0` when `OMP_WAIT_POLICY=active` and
`KMP_USE_YIELD` is not explicitly set by the user. This is the same as
the value of `KMP_BLOCKTIME` is set to infinite when `KMP_BLOCKTIME` is
not explicitly set and `OMP_WAIT_POLICY=active`.
### Background
`KMP_USE_YIELD` is an environment variable for libomp to control the
behavior of threads when they are idle. We can specify 0, 1, or 2 as the
value of `KMP_USE_YIELD`. As I read the code, the behavior is as
follows:
- `KMP_USE_YIELD=0`: Threads will NOT yield the CPU when they are idle.
- `KMP_USE_YIELD=1`: Threads will yield the CPU when they are idle.
- `KMP_USE_YIELD=2`: Threads will yield the CPU when they are idle if we
are oversubscribed (i.e., more threads than CPU cores).
The default value of `KMP_USE_YIELD` is 1, which means that threads will
yield the CPU when they are idle.
On the other hand, there is an environment variable `OMP_WAIT_POLICY`
that controls the waiting behavior of threads in OpenMP. The OpenMP 6.0
Specification
(https://www.openmp.org/wp-content/uploads/OpenMP-API-Specification-6-0.pdf)
states as follows:
> The active value specifies that waiting native threads should mostly
be active, consuming processor cycles, while waiting. A compliant
implementation may, for example, make waiting native threads spin.
Therefore, I think it is more consistent to set `KMP_USE_YIELD=2` when
`OMP_WAIT_POLICY=active`.
Note: Using `KMP_USE_YIELD=2` instead of 0 here to avoid hanging when
oversubscribed.
### Performance
To confirm the effect of this patch, I ran SPEC CPU 2017 with several
configurations, including with and without this patch. As a result, I
observed that the performance of some benchmarks improved significantly
with this patch. Also I didn't see any performance degradation. Here are
the details of the performance improvements:
- Machine: Neoverse V2 (Grace, binding 64 threads to 64 cores)
- Configuration: `OMP_WAIT_POLICY=active OMP_NUM_THREADS=64`
| Benchmark | Performance Improvement |
|-|-|
| 621.wrf_s | 2.6x |
| 628.pop2_s | 5.5x |
---
In conclusion, I think it's reasonable to set `KMP_USE_YIELD=0` (or 2)
by default when `OMP_WAIT_POLICY=active` is specified, when the user
likely expects the threads to be active while waiting.
Resolve #181784.
Commit: 3a8ff8d1ddfe44f19926789170b8c00c9aea3d0c
https://github.com/llvm/llvm-project/commit/3a8ff8d1ddfe44f19926789170b8c00c9aea3d0c
Author: Mircea Trofin <mtrofin at google.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
Add openmp test to xfail list (#221854)
Introduced in PR #219323. Looking at the PR, and given we haven't yet
addressed openmp profcheck failures, the change is highly unlikely to
have introduced a new regression (it's exposing existing ones)
Commit: 8a63b2ea6f9b6b25a6d90e20dcd76919e5bacb8d
https://github.com/llvm/llvm-project/commit/8a63b2ea6f9b6b25a6d90e20dcd76919e5bacb8d
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt-c/bedrock/Session.h
M orc-rt/include/orc-rt-c/support/Logging.h
Log Message:
-----------
[orc-rt] Add missing export annotations to C API. (#221856)
Commit: eb74688f5e2fb0cbd4c412a9fc54d0ed3dc48155
https://github.com/llvm/llvm-project/commit/eb74688f5e2fb0cbd4c412a9fc54d0ed3dc48155
Author: Ruiling, Song <ruiling.song at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll
Log Message:
-----------
[test] auto-generate test check (#221656)
To make later update easy.
Commit: 9eb6467f3f03c7da1dbe3ebdd9a4d3068945e767
https://github.com/llvm/llvm-project/commit/9eb6467f3f03c7da1dbe3ebdd9a4d3068945e767
Author: Zhaoxuan Jiang <jiangzhaoxuan94 at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M lld/MachO/ICF.cpp
M lld/MachO/UnwindInfoSection.cpp
A lld/test/MachO/icf-lsda-reloc.s
Log Message:
-----------
[lld][MachO] Ignore relocated bytes when folding LSDAs (#220155)
AArch64 exception tables reference type info through PC-relative
pointer-to-GOT relocations. The assembler leaves the negated field
offset in each relocated field, which the linker ignores, so identical
tables differ in their raw bytes and are never folded. Treat
__gcc_except_tab like __eh_frame and zero the relocated fields before
ICF hashes and compares it.
Folding these LSDAs exposes a latent issue: the LSDA pointer of a DWARF
FDE is resolved to an InputSection when the FDE is parsed and is never
canonicalized after ICF. A function that is unwound via its FDE and
whose LSDA was folded away therefore gets an __unwind_info LSDA entry
computed from the dead input section. Fixed it in the same commit.
This patch is LLM-driven, but the issue was observed in production and
the test is reduced from the production object.
Commit: c22d6a86d2e47524cd259f81206db7adf593e5a4
https://github.com/llvm/llvm-project/commit/c22d6a86d2e47524cd259f81206db7adf593e5a4
Author: wangjue <wangjue.wangjue at alibaba-inc.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M bolt/lib/Passes/FixRISCVCallsPass.cpp
M bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
A bolt/test/RISCV/conditional-tail-call-relocs.s
Log Message:
-----------
[BOLT][RISCV] Mark newly created tail calls (#221672)
Tail calls created during CFG normalization lack the tail-call
annotation, so FixRISCVCallsPass rewrites them as regular calls that
clobber ra.
Set the annotation in createTailCall(). Clear builder annotations before
moving the originals when rebuilding calls to avoid duplicate annotation
markers.
Add a relocation-mode regression test for a conditional tail call.
Commit: 2b03c66b5f0fdd12f616d845b61417442322f03c
https://github.com/llvm/llvm-project/commit/2b03c66b5f0fdd12f616d845b61417442322f03c
Author: Daedie-git <HC_Daedalus at hotmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/docs/StandardCPlusPlusModules.md
M clang/lib/AST/ODRDiagsEmitter.cpp
M clang/lib/AST/ODRHash.cpp
A clang/test/Modules/odr-hash-using-declarations.cppm
M clang/test/Modules/pr76638.cppm
Log Message:
-----------
[Clang][Modules] Fix ODR handling of types found through using-declarations (#221839)
Fixes #78850.
Clang can diagnose an ODR violation for identical definitions when a
type is
found directly in one module's global module fragment and through a
using-declaration in another. The lookup routes produce different AST
type
wrappers even though they refer to the same declaration.
Normalize `UsingType` to the target declaration's type before hashing
it. Keep
the keyword and qualifier from the use site, rather than from the
using-declaration. This also lets the hash distinguish differently
qualified
uses without canonicalizing away meaningful spelling differences.
The normalization exposes an existing assertion in the enum ODR
diagnostic
path: `AddEnumDecl` hashes canonical underlying integer types, but the
diagnostic emitter compares hashes of their spelled types. Compare the
actual
underlying integer types instead, while retaining the original spelling
in the
diagnostic. The extended `pr76638.cppm` regression also reproduces the
assertion
without the normalization change, when both underlying types are found
through
same-named using-declarations.
Use `EnumDecl::getIntegerType()` for this comparison so ignored cv
qualifiers
in the enum-base do not incorrectly take precedence over an actual
difference
in enumerator initializers. A regression checks that diagnostic as well.
Regression coverage includes both lookup directions, typedefs and
aliases,
record and enum types, chained using-declarations, templates, and
negative
tests for qualification, elaborated keywords, and cv qualification.
Remove the
now-fixed #78850 example from the modules documentation.
## Validation
Built from main at `44a4dbf32a6b54de32e4d064756d7a6ba5b9e808` plus this
patch,
in Release mode with assertions enabled on Windows x86-64 (X86 backend,
Clang 23.1.0 bootstrap, VS 2022 SDK).
| Suite | Passed | Unsupported | Expected Failures |
| :------------ | -----: | ----------: | ----------------: |
| Clang Modules | 914 | 34 | 0 |
| Clang PCH | 289 | 6 | 2 |
| **Total** | 1,203 | 40 | 2 |
Unexpected failures: **0**.
- Removing both implementation changes and rebuilding on the same main
base
makes both affected regression tests fail: the new lookup test reports
false ODR errors, and the extended enum test asserts while diagnosing an
ODR
violation. Restoring the changes and rebuilding passes both complete
suites.
- The cv-qualifier regression also fails with the earlier comparison of
spelled underlying types, then passes with `getIntegerType()`.
- Changed implementation lines pass clang-format checks; `git diff
--check`
passes.
The original release/23.x patch was also tested: 1,180 passed, 39
unsupported,
2 expected failures, and no unexpected failures across Modules and PCH.
Its
unmodified implementation reproduced the false-positive diagnostics,
missed
qualification diagnostic, and enum assertion.
Other platforms and configurations have not been tested locally.
This is a targeted ODR fix, not a general resolution of Clang's
remaining C++
module limitations.
The fix is also relevant to release/23.x; a backport can follow upstream
review
and merge.
Assisted-by: OpenAI Codex Astra
Co-authored-by: Bjorn Schobben <bjorn.schobben at aimsport.com>
Commit: 80793a65f0c8cab368358d2ce3e3d92bc7a63fb8
https://github.com/llvm/llvm-project/commit/80793a65f0c8cab368358d2ce3e3d92bc7a63fb8
Author: jiang1997 <jieke at live.cn>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M libcxx/docs/Status/Cxx26Issues.csv
M libcxx/include/__ranges/lazy_split_view.h
M libcxx/test/std/ranges/range.adaptors/range.lazy.split/begin.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.lazy.split/end.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.lazy.split/view_interface.pass.cpp
Log Message:
-----------
[libc++][ranges] Implement LWG 3599 (#221573)
Implement [LWG 3599](https://wg21.link/LWG3599) by requiring
`forward_range<const Pattern>` for the `const` overloads of
`lazy_split_view::begin` and `end`.
This adds tests for disabled `begin()` and fallback `end()` on
non-const-forward patterns, as well as a regression test for
`view_interface::front()`.
Closes #189808
Commit: 0a50c218e000acee02b90f8a0f1f50f3da9059e8
https://github.com/llvm/llvm-project/commit/0a50c218e000acee02b90f8a0f1f50f3da9059e8
Author: yingopq <115543042+yingopq at users.noreply.github.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsInstrFPU.td
M llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
M llvm/lib/Target/Mips/MipsSEISelLowering.cpp
M llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
M llvm/lib/Target/Mips/MipsScheduleGeneric.td
M llvm/lib/Target/Mips/MipsScheduleP5600.td
M llvm/test/CodeGen/Mips/llvm-ir/load.ll
M llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
M llvm/test/CodeGen/Mips/mips1-load-in-delay-slot.ll
A llvm/test/CodeGen/Mips/mips1-not-support-ldc1-sdc1.ll
Log Message:
-----------
[MIPS] Support MIPS I hard-float double loads/stores with LWC1/SWC1 (#209362)
MIPS I lacks LDC1/SDC1. This patch implements double precision
loads/stores using LWC1/SWC1 instructions.
* Add BuildPairF64_FPR and ExtractElementF64_FPR nodes
* Use them in lowerLOAD/lowerSTORE for MIPS I hard-float
* Avoid redundant mtc1/mfc1 instructions
Matches GCC behavior for MIPS I hard-float.
Fix #62190.
Commit: 7d04e28c7cee23af6a33cebdfecdaa7d43d1d4fe
https://github.com/llvm/llvm-project/commit/7d04e28c7cee23af6a33cebdfecdaa7d43d1d4fe
Author: AZero13 <gfunni234 at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/apx/adc.ll
M llvm/test/CodeGen/X86/apx/flags-copy-lowering.ll
M llvm/test/CodeGen/X86/overflow-intrinsic-setcc-fold.ll
M llvm/test/CodeGen/X86/select-lea.ll
M llvm/test/CodeGen/X86/smul-with-overflow.ll
M llvm/test/CodeGen/X86/smul_fix_sat.ll
M llvm/test/CodeGen/X86/smul_fix_sat_constants.ll
M llvm/test/CodeGen/X86/umul-with-carry.ll
M llvm/test/CodeGen/X86/umul-with-overflow.ll
M llvm/test/CodeGen/X86/umul_fix_sat.ll
M llvm/test/CodeGen/X86/umulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/X86/umulo-64-legalisation-lowering.ll
M llvm/test/CodeGen/X86/vec_smulo.ll
M llvm/test/CodeGen/X86/vec_umulo.ll
M llvm/test/CodeGen/X86/xmulo.ll
Log Message:
-----------
[X86] Prefer carry to overflow flag when using multiplication (#221611)
For all possible MUL/IMUL it will always output CF==OF, and CF is better
folding, so there's absolutely no reason the x86 backend should be
checking OF instead of CF for any form of multiply.
Did the change in FastISel too for consistency.
Commit: 0513c32abe1eff329fd22b578f4995e59d6140a2
https://github.com/llvm/llvm-project/commit/0513c32abe1eff329fd22b578f4995e59d6140a2
Author: LU-JOHN <John.Lu at amd.com>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll
Log Message:
-----------
[GlobalISel] When folding to fma correctly find fpext(fmul) with fewer uses (#218013)
When folding: `(fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext
y), z)` and both addends are candidates, correctly pick the side with
fewer uses. Previously the code looked for a `fmul` with the fewest uses
rather than a `fpext(fmul)`.
---------
Signed-off-by: John Lu <John.Lu at amd.com>
Commit: 2edc68ceee32011f8f2d28fb97b64bc9e3a3b521
https://github.com/llvm/llvm-project/commit/2edc68ceee32011f8f2d28fb97b64bc9e3a3b521
Author: AZero13 <gfunni234 at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Parse/ParseExprCXX.cpp
M clang/test/Parser/recovery.cpp
M clang/test/SemaCXX/MicrosoftSuper.cpp
Log Message:
-----------
[clang] Reject __super when preceded by a scope specifier (#221492)
The `__super` keyword is an MSVC extension that refers to the base class
of the current class context. It is fundamentally invalid for `__super`
to be qualified by another scope specifier (e.g. `::__super` or
`N::__super`).
Fixes #212988
---------
Co-authored-by: Shengxin Pei <TPPPP72 at outlook.com>
Co-authored-by: Corentin Jabot <corentinjabot at gmail.com>
Commit: 7efd21ff7aceefcec79adced0dcc99bf121e9696
https://github.com/llvm/llvm-project/commit/7efd21ff7aceefcec79adced0dcc99bf121e9696
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-07 (Mon, 07 Sep 2026)
Changed paths:
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/AST/TypeBase.h
M clang/lib/AST/ASTContext.cpp
Log Message:
-----------
[clang] Unique the QualType-keyed type pools in a UniquingSet. NFC (#221850)
Eight of the ASTContext type pools key on a QualType, or on a QualType
and a bool. The `get*Type()` functions incur the FoldingSetNodeID
serialization overhead before probing the hash table.
Switch to UniquingSet. Define `QualTypeBoolInfo` for three pools that
key on a QualType and a bool, because DenseMapInfo has no bool
specialization.
After the canonical type is built, these getters re-probe to refresh the
insert token. A token is now a hash (#218190), not a bucket, so nothing
invalidates it; fold the re-probe into the assertion it feeds.
Aided by Opus 5
Commit: 49ce9d0aac2117edc0d50e5a7a838f934c99dd61
https://github.com/llvm/llvm-project/commit/49ce9d0aac2117edc0d50e5a7a838f934c99dd61
Author: Dharuni R Acharya <125176188+DharuniRAcharya at users.noreply.github.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/test/Target/LLVMIR/nvvm/tcgen05-alloc.mlir
Log Message:
-----------
[MLIR][NVVM] Add "exclusive" support in tcgen05 alloc/dealloc Ops (#219451)
This patch adds `exclusive` support in `tcgen05.alloc/dealloc` MLIR ops.
Lit tests are added to verify the lowering to the intrinsics.
PTX ISA Reference:
https://docs.nvidia.com/cuda/developer-preview/13.4/parallel-thread-execution/index.html#tcgen05-instructions-tcgen05-alloc-dealloc-relinquish-alloc-permit
---------
Signed-off-by: DharuniRAcharya <dharunira at nvidia.com>
Commit: 62397f8b3c3986f54187ce08f00b3448ea1f8880
https://github.com/llvm/llvm-project/commit/62397f8b3c3986f54187ce08f00b3448ea1f8880
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/lib/Sema/SemaAttr.cpp
M llvm/lib/Bitcode/Reader/MetadataLoader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/RegisterUsageInfo.cpp
M llvm/lib/CodeGen/StackColoring.cpp
M llvm/lib/MC/StringTableBuilder.cpp
M llvm/lib/MCA/HardwareUnits/LSUnit.cpp
M llvm/lib/MCA/HardwareUnits/ResourceManager.cpp
M llvm/lib/Transforms/IPO/SampleProfile.cpp
M llvm/lib/Transforms/Scalar/GVNHoist.cpp
M llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M mlir/lib/Conversion/SCFToGPU/SCFToGPU.cpp
M mlir/lib/IR/PDL/PDLPatternMatch.cpp
Log Message:
-----------
Iterate DenseMaps with auto and structured bindings. NFC (#221869)
Avoid naming `std::pair` directly. The DenseMap bucket is subject to
change (#221853).
Commit: 131e31016ff94c8782d726baa3ed0160a480f3f3
https://github.com/llvm/llvm-project/commit/131e31016ff94c8782d726baa3ed0160a480f3f3
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.h
Log Message:
-----------
[SLP][modularisation][NFC] Move createInsertVector, createExtractVector (#221785)
Move the following BoUpSLP-independent shuffle helpers out of
SLPVectorizer.cpp into SLPVectorizer/SLPUtils.{h,cpp}:
createInsertVector
createExtractVector
They sit with the existing shuffle helpers. Behavior is unchanged.
Part of the SLPVectorizer.cpp modularization effort:
https://discourse.llvm.org/t/modularizing-slpvectorizer-cpp/90922
Commit: 6a183b8853b79a134402332cf4a776a8090d1b88
https://github.com/llvm/llvm-project/commit/6a183b8853b79a134402332cf4a776a8090d1b88
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/docs/ProgrammersManual.md
M llvm/unittests/ADT/FoldingSet.cpp
Log Message:
-----------
[ADT] Document the UniquingSet contracts. NFC (#221860)
#220195 added an isEqual hook, so an Info can now override the
comparison as well as the key and the hash. Name the three hooks, and
correct the guidance on when to prefer UniquingSet over FoldingSet.
Cover getOrInsert, which UniquingSet had no test for: an absent key
inserts, an equal key returns the node already in the set.
Aided by Opus 5
Co-authored-by: Kazu Hirata <kazu at google.com>
Commit: 08eb5edcafcc21faa841a75a29d0c2f2090535f3
https://github.com/llvm/llvm-project/commit/08eb5edcafcc21faa841a75a29d0c2f2090535f3
Author: GabrielWu2004 <101153587+GabrielWu2004 at users.noreply.github.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/test/Dialect/LLVMIR/canonicalize.mlir
Log Message:
-----------
[MLIR] AllocaOp canonicalization for array allocation in LLVM dialect (#221508)
Add the following canonicalization pattern to AllocaOp in MLIR's LLVM
dialect:
```
%n = constant(N)
%alloca = llvm.alloca %n x Ty
```
->
```
%one = constant(1)
%alloca = llvm.alloca %one x !llvm.array<N x Ty>
```
Here N is a constant representable with 64-bits. With this
canonicalization, the AllocaOp will be translated to `alloca [N x Ty]`
in LLVM IR. Without this canonicalization, the AllocaOp was translated
to `alloca Ty, N`. We prefer `alloca [N x Ty]` over `alloca Ty, N` for
fixed-size array allocation.
See [this
RFC](https://discourse.llvm.org/t/rfc-allocaop-canonicalization-in-mlirs-llvm-dialect/91734)
for more detailed problem motivation and description.
Assisted by: Codex
Commit: d34720a9ca4492dbb65af8b652e60dbb5f60ca55
https://github.com/llvm/llvm-project/commit/d34720a9ca4492dbb65af8b652e60dbb5f60ca55
Author: A. Jiang <de34 at live.cn>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M libcxx/test/std/utilities/optional/optional.comp_with_t/equal.pass.cpp
M libcxx/test/std/utilities/optional/optional.comp_with_t/greater.pass.cpp
M libcxx/test/std/utilities/optional/optional.comp_with_t/greater_equal.pass.cpp
M libcxx/test/std/utilities/optional/optional.comp_with_t/less_equal.pass.cpp
M libcxx/test/std/utilities/optional/optional.comp_with_t/less_than.pass.cpp
M libcxx/test/std/utilities/optional/optional.comp_with_t/not_equal.pass.cpp
M libcxx/test/std/utilities/optional/optional.relops/equal.pass.cpp
M libcxx/test/std/utilities/optional/optional.relops/greater_equal.pass.cpp
M libcxx/test/std/utilities/optional/optional.relops/greater_than.pass.cpp
M libcxx/test/std/utilities/optional/optional.relops/less_equal.pass.cpp
M libcxx/test/std/utilities/optional/optional.relops/less_than.pass.cpp
M libcxx/test/std/utilities/optional/optional.relops/not_equal.pass.cpp
M libcxx/test/support/test_comparisons.h
Log Message:
-----------
[libc++][test] Test SFINAE for `optional`'s operators in C++17 (#221643)
We have been intentionally constraining `optional`'s comparison
operators since C++17, so it is probably better to test the constraints
in C++17 mode. Given the constraints are standardized only since C++26
(via P2944R3), `LIBCPP_STATIC_ASSERT` is used in old modes.
In order to do this, `test_comparisons.h` is reworked to expose
`NonComparable` and `EqualityComparable` in pre-C++20 modes, and a new
type `TotallyOrdered` is invented as a replacement of
`ThreeWayComparable` in old modes.
As drive-by, also switches to use `// REQUIRES: std-at-least-c++17` in
touched test files, and adds previously missed includes of
`<type_traits>`.
Commit: cc798fb63ca1a08f43cdcd314b66a96fa973e584
https://github.com/llvm/llvm-project/commit/cc798fb63ca1a08f43cdcd314b66a96fa973e584
Author: Rajat Bajpai <rbajpai at nvidia.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/docs/NVPTXUsage.md
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/NVVMIntrinsicUtils.h
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/NVVMIntrinsicUtils.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-1cta.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-2cta.ll
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-override.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm100.ll
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-validate-data.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-gather4.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-im2colw.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-im2colw128.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-invalid.ll
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-mc32.ll
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-override.ll
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-validate-data.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g-im2colw.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g-scatter4.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g.ll
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/test/Target/LLVMIR/nvvm/tma_load_cluster_im2col.mlir
M mlir/test/Target/LLVMIR/nvvm/tma_load_cluster_tile.mlir
M mlir/test/Target/LLVMIR/nvvm/tma_load_cta_im2col.mlir
M mlir/test/Target/LLVMIR/nvvm/tma_load_cta_tile.mlir
Log Message:
-----------
[LLVM][NVPTX] Add Rubin extensions for G2S Tensor intrinsics (#220029)
This change adds support for the Rubin-extended Global-to-Shared tensor
copy intrinsics for both the Cluster and CTA variants:
1. 32-bit multicast mask support: the G2S Cluster intrinsics are now
overloaded on the multicast mask type (i16/i32); an i32 mask lowers to
`.multicast::cluster::32b`.
2. Data-validity reporting through the mbarrier: all G2S Cluster and CTA
intrinsics, including the property-override forms, take a trailing `i32
%validate_pattern` immediate (range [0, 6)) that selects a
`.mbarrier::report::validity` qualifier. It defaults to 0 (disabled).
3. Override tensor map properties: the G2S Cluster and CTA intrinsics
now support `.override::global_address`, optionally followed by
`.override::global_dim` / `.override::global_dim_stride`, across all
load modes. The dim/stride overrides apply to tile mode only; im2col and
gather4 support the global-address override only.
The new `validate_pattern` argument changes the IR signatures of all G2S
intrinsics; legacy declarations are auto-upgraded with the missing
trailing arguments defaulted to 0, and the multicast mask type selects
the overload. The MLIR NVVM `CpAsyncBulkTensorGlobalToSharedClusterOp`
is updated to build the new signature.
Commit: df3c1f712828dda66fe7efa0d2957629d60f8df8
https://github.com/llvm/llvm-project/commit/df3c1f712828dda66fe7efa0d2957629d60f8df8
Author: Vikram Hegde <Vikram.Hegde at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
Log Message:
-----------
[AMDGPU][GIsel][NPM] Port "AMDGPURegBankLegalize" to NPM (#217322)
Probably doesn't require all tests to be updated.
Assisted-by: Opus-4.8,
Commit: 05fa66e6624e6b14346e559cd7b692aaf48f3ca7
https://github.com/llvm/llvm-project/commit/05fa66e6624e6b14346e559cd7b692aaf48f3ca7
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/test/CodeGen/X86/huge-stack.ll
M llvm/test/CodeGen/X86/llvm.sincos.vec.ll
M llvm/test/CodeGen/X86/pr1505b.ll
M llvm/test/CodeGen/X86/stack-align.ll
M llvm/test/CodeGen/X86/subcarry.ll
M llvm/test/CodeGen/X86/swifterror.ll
M llvm/test/CodeGen/X86/var-permute-128.ll
M llvm/utils/UpdateTestChecks/asm.py
Log Message:
-----------
[UpdateTestChecks][X86] Allow --no_x86_scrub_sp to disable folded stack spill/restore stack math scrubing (#221788)
We were handling cases to show general load/store stack math, but had
missed the r/w/rmw folded cases
Commit: d402c6191ad4051a3cb534dae125dfdf1f304889
https://github.com/llvm/llvm-project/commit/d402c6191ad4051a3cb534dae125dfdf1f304889
Author: Andrew Gaul <andrew at gaul.org>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/test/CodeGen/X86/PR40322.ll
A llvm/test/CodeGen/X86/atomic-cmp-fold.ll
M llvm/test/CodeGen/X86/atomic-unordered.ll
Log Message:
-----------
[X86] Fold atomic loads into compares (#221290)
A compare of an atomic load kept the load in a register (mov + cmp/test)
where a compare of a regular load folds the load into the compare's
memory operand. The folded form performs a single full-width load, and
on x86 an ordinary load already provides every ordering up to seq_cst,
so folding is legal for any non-extending atomic load.
Add isel patterns folding an atomic load into CMP (mi/mr/rm forms across
i8/i16/i32/i64). Compare-to-zero already reaches these via EmitTest;
nonzero and register compares are emitted as a flag-only X86ISD::SUB (to
enable CSE with a real subtract) whose load the peephole then folds. The
peephole cannot move an ordered access, so those never folded for atomic
loads. Emit X86ISD::CMP instead when an operand is a foldable atomic
load: it has no non-atomic sibling to CSE with anyway.
x86lint reports 5854 "load foldable into compare" sites in a release
build of Firefox's libxul.so; sampling shows the majority are
atomic-load compares of the kind this folds -- mozilla::Atomic and
std::atomic loads, MOZ_LOG level checks (an Atomic<LogLevel>), and Rust
core::sync::atomic and log-crate level checks.
---------
Co-authored-by: Claude Fable 5 <noreply at anthropic.com>
Commit: 1e679c028b30b6542c8712ef2023911673e55c7c
https://github.com/llvm/llvm-project/commit/1e679c028b30b6542c8712ef2023911673e55c7c
Author: Martin Storsjö <martin at martin.st>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/cmake/modules/HandleLLVMOptions.cmake
M mlir/CMakeLists.txt
Log Message:
-----------
[CMake] Move -Wno-unused-but-set-parameter from MLIR up to LLVM (#221824)
This warning is known to have false positives with GCC versions before
14.
Since 3aec6a40bb4e49f9ea181ac5c949b6c7c20a5465, this warning appears
when building LLVMSupport as well - thus move the disabling of the
warning up from MLIR to all of LLVM.
In HandleLLVMOptions, the common procedure is to not check for whether
the options are supported or not, but to just hardcode the version
ranges where the options are supported, per compiler.
This option (and -Wunused-but-set-parameter) is available in GCC since
long before our minimum required version.
Commit: 011005fecf846e40dad1941f6cbbd6653ae37460
https://github.com/llvm/llvm-project/commit/011005fecf846e40dad1941f6cbbd6653ae37460
Author: Rohan Shenoy <RohanRadhesh.Shenoy at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86InstrSNP.td
M llvm/test/MC/Disassembler/X86/x86-64.txt
M llvm/test/MC/X86/SNP-64.s
Log Message:
-----------
[X86] Support further Zen5 and Zen6 instructions (#221659)
Support the following system instructions,
RMPREAD: https://docs.amd.com/v/u/en-US/24594_3.38_APM_Vol3_PUB
RMPOPT: https://docs.amd.com/search/all?query=69201
RMPCHKD (RMP Dirty) : https://docs.amd.com/search/all?query=69203
Commit: 0c098ae4518902f8f30abae5a620bf57fa84895a
https://github.com/llvm/llvm-project/commit/0c098ae4518902f8f30abae5a620bf57fa84895a
Author: Martin Storsjö <martin at martin.st>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Support/CMakeLists.txt
Log Message:
-----------
[Support] [CMake] Only pass -Wno-c99-extensions to Clang, not GCC (#221822)
GCC doesn't support this option, only Clang.
GCC doesn't warn if an unrecognized `-Wno-<foo>` option is passed, but
if GCC produces other warnings, it also adds a note about `-Wno-<foo>`
not being recognized, and that it may have been intended to silence the
warning that was produced.
Commit: 2c2ff263a437efccf074a07cb2906025252153d0
https://github.com/llvm/llvm-project/commit/2c2ff263a437efccf074a07cb2906025252153d0
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
Log Message:
-----------
[GlobalISel] Avoid copying complex pattern renderers (NFC) (#221657)
They're immediately destroyed after being copied, move them instead.
Improves aarch64-O0-g CTMark geomean -0.10%.
https://llvm-compile-time-tracker.com/compare.php?from=97cbc1e404b980edc58bfbcabb6f1c61793b624b&to=69a2cfb9a265b7c4a18ef7121a7afb239c886d13&stat=instructions:u
Assisted-by: codex
Commit: 2a9266ce8524af516426835bff1c06fb78d5280d
https://github.com/llvm/llvm-project/commit/2a9266ce8524af516426835bff1c06fb78d5280d
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
Log Message:
-----------
[AArch64][GlobalISel] Avoid duplicate register-bank queries in selectCopy (NFC) (#221655)
selectCopy redundantly queried both register banks through a single-use
helper. Inline the helper to reuse the existing results.
Small -0.04% geomean improvement on CTMark aarch64-O0-g.
https://llvm-compile-time-tracker.com/compare.php?from=97cbc1e404b980edc58bfbcabb6f1c61793b624b&to=ca7c3e1d88a6ca20b104b0fb62ce79897b61afc8&stat=instructions:u
Assisted-by: codex
Commit: 16df25d03f5a5becf9dbe994ef6b6d4546b357d9
https://github.com/llvm/llvm-project/commit/16df25d03f5a5becf9dbe994ef6b6d4546b357d9
Author: Steffen Larsen <sholstla at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/include/llvm/ADT/APInt.h
M llvm/lib/Support/APInt.cpp
Log Message:
-----------
[APInt][NFC] Add branch hints to APInt single-word (#219437)
The fast-path for APInt is generally done with for "single word"
integers, i.e. ones that can be represented in a single 64-bit word.
This commit adds branch hints to the single-word branching to help
indicate to the compilers prioritize branch-prediction towards the
fast-path. The trade-off of this is that the >64-bit APInt case will be
slower.
---------
Signed-off-by: Steffen Holst Larsen <sholstla at amd.com>
Commit: e91092685eab2ab0348ea06df2c3446001b480d4
https://github.com/llvm/llvm-project/commit/e91092685eab2ab0348ea06df2c3446001b480d4
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Mangling.h
A llvm/include/llvm/ExecutionEngine/Orc/Shared/Mangler.h
A llvm/include/llvm/ExecutionEngine/Orc/Shared/SymbolNameSpec.h
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/ExecutionEngine/Orc/Mangling.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/CMakeLists.txt
A llvm/lib/ExecutionEngine/Orc/Shared/Mangler.cpp
M llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
R llvm/unittests/ExecutionEngine/Orc/MangleAndInternerTest.cpp
A llvm/unittests/ExecutionEngine/Orc/ManglerTest.cpp
Log Message:
-----------
[ORC] Add SymbolNameSpec, hoist name mangling into Shared.
Introduce two Shared, ExecutionSession-independent pieces:
- SymbolNameSpec (Shared/SymbolNameSpec.h): a StringRef paired with a
SymbolNameKind (Verbatim, Linker, IR, C) describing the naming level
a symbol name is expressed in. A lightweight, dependency-free value
type, so it can describe interface-name constants in Shared headers.
- Mangler (Shared/Mangler.h, Shared/Mangler.cpp): the linker
name-mangling logic factored out of MangleAndInterner. It holds only
a ManglingMode (no ExecutionSession or SymbolStringPool), so names
can be mangled on the executor side as well as the controller
side. It exposes withMangledNameDo (which avoids allocating when
mangling is a no-op) and a mangledCopy convenience, both dispatching
on the spec's SymbolNameKind.
MangleAndInterner becomes a thin wrapper: it derives a ManglingMode
(from an ABIName / ManglingMode / DataLayout), holds a Mangler, and
interns whatever the Mangler produces. Behavior is unchanged.
This lets lookup utilities eventually accept C / IR source names and
mangle them to linker level on the caller's behalf, rather than
requiring pre-mangled names. The MangleAndInternerTest unit tests are
renamed to ManglerTest and now exercise Mangler directly;
MangleAndInterner is left untested since it is slated for removal.
Commit: 03474869170f49bd676f92ab86d15063a68d3ea0
https://github.com/llvm/llvm-project/commit/03474869170f49bd676f92ab86d15063a68d3ea0
Author: David Green <david.green at arm.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SchedNeoverseV3AE.td
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-sve-instructions.s
Log Message:
-----------
[AArch64] Correct the throughput of reductions on Neoverse V3ae (#221151)
This tightens up the throughput of sve saddv, sminv, smaxv, along with
the unsigned variants. They were a bit high due to the use of too many
micro ops.
Commit: d6a6de09cce9d0e08821a9aa15a0cbcb0889bb37
https://github.com/llvm/llvm-project/commit/d6a6de09cce9d0e08821a9aa15a0cbcb0889bb37
Author: Ketan Roy <145851442+MrRoy09 at users.noreply.github.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/DSInstructions.td
Log Message:
-----------
[AMDGPU] Use AMDGPUMnemonicAlias in DS_Real_gfx13 (NFC) (#217912)
Emit an AMDGPUMnemonicAlias in DS_Real_gfx13 so it carries the
PredicateControl fields.
NFC: 46 gfx13 aliases gain the PredicateControl fields at their
defaults; Predicates is unchanged on all of them.
Commit: a9cbac7d954efa6ac591fa099ea299a5add14188
https://github.com/llvm/llvm-project/commit/a9cbac7d954efa6ac591fa099ea299a5add14188
Author: David Green <david.green at arm.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
A llvm/test/CodeGen/Thumb2/LowOverheadLoops/dbg-verify.ll
Log Message:
-----------
[ARM] Handle debug instructions in LowOverheadLoop (#221699)
The last instruction in the block might be a debug instruction, in which
case we should get the last non-debug instruction.
Fixes #221633.
Commit: 586cfbcd9d59af33894e79192fdcad6057467465
https://github.com/llvm/llvm-project/commit/586cfbcd9d59af33894e79192fdcad6057467465
Author: Oscar Priego <oscar.priegov at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86CompressEVEX.cpp
M llvm/test/CodeGen/X86/avx512-icmp-sle-zero.ll
A llvm/test/CodeGen/X86/bitcast-sign-mask.ll
A llvm/test/CodeGen/X86/compress-evex-sign-mask.mir
M llvm/test/CodeGen/X86/compress-evex-vpmov-kill.mir
Log Message:
-----------
[X86] X86CompressEVEX - Fold AVX-512 sign-mask compares to MOVMSK (#216884)
## Summary
Fold AVX-512 complementary signed sign-test masks to the corresponding
MOVMSK instructions in `X86CompressEVEX`.
AVX-512 lowers comparisons such as:
- `X >= 0`
- `X > -1`
to `VPCMP*` producing a k-mask followed by `KMOV`.
For 128-bit and 256-bit B/D/Q forms, these masks can instead be obtained
from the source sign bits using:
- `VPCMPB` -> `VPMOVMSKB`
- `VPCMPD` -> `VMOVMSKPS`
- `VPCMPQ` -> `VMOVMSKPD`
followed by the appropriate complement.
## Details
The complement is restricted to the meaningful lane-mask bits so that
unused upper bits retain the zero-extension semantics of `KMOV`.
For the 32-lane byte case, all 32 bits are meaningful, so `NOT32r` can
be used directly without clobbering EFLAGS.
The transformation is limited to 128-bit and 256-bit B/D/Q forms with a
single non-narrowing `KMOV` consumer.
The matcher also verifies the expected zero/all-ones producer for the
comparison constant and avoids the fold when required register or
EFLAGS liveness constraints are not satisfied.
## Tests
Added:
- end-to-end CodeGen coverage for the affected sign-mask cases;
- dedicated MIR coverage for `X86CompressEVEX`;
- negative MIR cases covering:
- multiple mask uses;
- source clobbers;
- unsupported predicates/constants;
- narrowing `KMOV`;
- 512-bit vectors;
- extended registers;
- live EFLAGS;
- masked-move consumers with incompatible mask polarity;
- incorrect all-ones producer width;
- dead `KMOV` destinations.
Existing `VPMOV*2M + KMOV -> MOVMSK` coverage is preserved.
Fixes #216774
Signed-off-by: Oscar Priego Verdugo <oscar.priegov at gmail.com>
AI-assisted development tools were used during this contribution; I
personally modified, reviewed, and validated the final patch
Commit: 5700f6fefdc532bb6fa6e30f780a5a553253722e
https://github.com/llvm/llvm-project/commit/5700f6fefdc532bb6fa6e30f780a5a553253722e
Author: Vlad Sytchenko <vsytch at hotmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/test/CodeGenCoroutines/coro-destructor-of-final_suspend.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/test/Transforms/Coroutines/ArgAddr.ll
M llvm/test/Transforms/Coroutines/coro-align16.ll
M llvm/test/Transforms/Coroutines/coro-align32.ll
M llvm/test/Transforms/Coroutines/coro-align64-02.ll
M llvm/test/Transforms/Coroutines/coro-align64.ll
M llvm/test/Transforms/Coroutines/coro-align8-02.ll
M llvm/test/Transforms/Coroutines/coro-align8.ll
M llvm/test/Transforms/Coroutines/coro-alloca-01.ll
M llvm/test/Transforms/Coroutines/coro-alloca-02.ll
M llvm/test/Transforms/Coroutines/coro-alloca-03.ll
M llvm/test/Transforms/Coroutines/coro-alloca-04.ll
M llvm/test/Transforms/Coroutines/coro-alloca-06.ll
M llvm/test/Transforms/Coroutines/coro-alloca-08.ll
M llvm/test/Transforms/Coroutines/coro-byval-param.ll
M llvm/test/Transforms/Coroutines/coro-catchswitch.ll
M llvm/test/Transforms/Coroutines/coro-eh-aware-edge-split-01.ll
M llvm/test/Transforms/Coroutines/coro-eh-aware-edge-split-02.ll
M llvm/test/Transforms/Coroutines/coro-frame-arrayalloca.ll
M llvm/test/Transforms/Coroutines/coro-frame-reuse-alloca-01.ll
M llvm/test/Transforms/Coroutines/coro-frame-reuse-alloca-02.ll
M llvm/test/Transforms/Coroutines/coro-frame-reuse-alloca-04.ll
M llvm/test/Transforms/Coroutines/coro-frame-reuse-alloca-05.ll
M llvm/test/Transforms/Coroutines/coro-param-copy.ll
M llvm/test/Transforms/Coroutines/coro-spill-defs-before-corobegin.ll
A llvm/test/Transforms/Coroutines/coro-split-index-datalayout.ll
M llvm/test/Transforms/Coroutines/coro-split-sink-lifetime-01.ll
M llvm/test/Transforms/Coroutines/coro-split-sink-lifetime-02.ll
M llvm/test/Transforms/Coroutines/coro-split-sink-lifetime-03.ll
M llvm/test/Transforms/Coroutines/coro-split-sink-lifetime-04.ll
M llvm/test/Transforms/Coroutines/coro-split-tbaa-md.ll
Log Message:
-----------
[CoroSplit] Don't go sub-word for suspend index (#221374)
Currently, `CoroFrame` selects the coroutine suspend index type
(`SwitchIndexType`) using `Type::getIntNTy(Context, IndexBits)`. For
coroutines with fewer than 256 suspend points, this produces
sub-byte/sub-word integer types (such as `i1`, `i2`, or `i8`) in the
coroutine frame struct.
On targets whose `DataLayout` specifies `-n32` (no legal sub-32-bit
integer types), storing and loading sub-word integer fields in memory
forces the backend to emit read-modify-write sequences on every
coroutine suspend and zero-extension masks on every resume.
Use `DataLayout::getSmallestLegalIntType(Context, IndexBits)` when
selecting `SwitchIndexType` so that targets respect their legal native
integer width.
Commit: 4b11439e535eb820d2f4cc5ac9694bf539d8213f
https://github.com/llvm/llvm-project/commit/4b11439e535eb820d2f4cc5ac9694bf539d8213f
Author: David Green <david.green at arm.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/arm64-build-vector.ll
M llvm/test/CodeGen/AArch64/arm64-tbl.ll
M llvm/test/CodeGen/AArch64/neon-anyof-splat.ll
M llvm/test/CodeGen/AArch64/pdep.ll
M llvm/test/CodeGen/AArch64/pext.ll
Log Message:
-----------
[AArch64] Combine scalar_to_vector(C) -> buildvector (#220948)
This helps keep a single canonical form of a constant vector, helping a
number of the existing buildvector combines trigger.
Commit: 296d80836bb77f9a8b5e159ef615a9965171cfba
https://github.com/llvm/llvm-project/commit/296d80836bb77f9a8b5e159ef615a9965171cfba
Author: Vikram Hegde <Vikram.Hegde at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-merge-readanylane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir
Log Message:
-----------
[AMDGPU][GIsel][NPM] Port "AMDGPURegBankCombiner" to NPM (#217323)
Assisted-by: Opus-4.8
Commit: 5886c703eb2d205656811d78db82b76524c47da9
https://github.com/llvm/llvm-project/commit/5886c703eb2d205656811d78db82b76524c47da9
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/AST/TypeBase.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/Type.cpp
Log Message:
-----------
[clang] Unique more ASTContext type pools in a UniquingSet. NFC (#221898)
Similar to #221850.
Eight pools key on a small tuple of types, integers and pointers, yet
each get*Type() serializes that into a FoldingSetNodeID and hashes it
out of line before probing. Switch to UniquingSet.
These getters re-probe after building the canonical type. A token is a
hash (#218190), not a bucket, so nothing invalidates it. Drop unneeded
assertions.
Commit: bd5c005a780ced31e3a4b7717474638be825cb15
https://github.com/llvm/llvm-project/commit/bd5c005a780ced31e3a4b7717474638be825cb15
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes e910926 (#221908)
This fixes e91092685eab2ab0348ea06df2c3446001b480d4.
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=e91092685eab2ab0348ea06df2c3446001b480d4
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 9f5548da33ffdb282225bc03e17c0702c4c31884
https://github.com/llvm/llvm-project/commit/9f5548da33ffdb282225bc03e17c0702c4c31884
Author: Manuel Carrasco <Manuel.Carrasco at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
Log Message:
-----------
[SPIRV] Preserve DebugGlobalVariable emission order. (#221759)
Iterate GlobalVariableDebugInfoMap with MapVector so OpString and
DebugGlobalVariable follow insertion order.
The following tests had non-deterministic output, although didn't fail
due to the use of CHECK-DAG:
- llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable-multi-gve.ll
- llvm/test/CodeGen/SPIRV/debug-info/debug-lexical-block-namespace.ll
- llvm/test/CodeGen/SPIRV/debug-info/debug-type-pointer.ll
Commit: 478f9da04672855854811d5bca7f1fd05c52ed90
https://github.com/llvm/llvm-project/commit/478f9da04672855854811d5bca7f1fd05c52ed90
Author: Mattéo Rizza Murgier <matteo.rizza-murgier at sipearl.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/test/CodeGen/AArch64/fp-veclib-expansion.ll
Log Message:
-----------
[SelectionDAG] Widen vector math libcalls when no routine is available (#218948)
`tryExpandVecMathCall` currently only checks for a vector math routine
matching the node's exact vector type, unrolling when none is found.
This is suboptimal, and can lead to crashes for scalable types (which
cannot be unrolled).
This PR implements widening to first check if a routine with a wider vec
type exists before falling back to unrolling.
Example:
```
; llc -mtriple=aarch64 -mattr=+sve -vector-library=sleefgnuabi crash.ll
define <vscale x 2 x float> @frem_nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b) {
%res = frem <vscale x 2 x float> %a, %b
ret <vscale x 2 x float> %res
}
```
NOTE: When the routines take a mask (e.g. if they're scalable variants),
only relevant lanes are activated. Vectors are padded with copies of the
operand to avoid running on poison.
Commit: fc884a467025ef3ed81cf62aacc1f97bc0ca9f1b
https://github.com/llvm/llvm-project/commit/fc884a467025ef3ed81cf62aacc1f97bc0ca9f1b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
M llvm/test/CodeGen/AMDGPU/fdot2.ll
M llvm/test/CodeGen/AMDGPU/prevent-fmul-hoist-ir.ll
Log Message:
-----------
AMDGPU: Rename stale CONTRACT check prefixes in fp-contract tests (#221709)
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 87c39e6dce0a6a4106927c9284258d49924a80de
https://github.com/llvm/llvm-project/commit/87c39e6dce0a6a4106927c9284258d49924a80de
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/ConstantFolding.h
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
Log Message:
-----------
[ConstantFolding] Implement canConstantFoldCallTo() using TLI (#221903)
This did some odd matching on string names. Use TLI instead, matching
the actual constant folding logic.
I've adjusted callers to pass TLI to canConstantFoldCallTo() if they
also pass TLI to the later constant folding call.
Commit: 698dd11893fca65681f8cd84b39ff49d29ddcd1e
https://github.com/llvm/llvm-project/commit/698dd11893fca65681f8cd84b39ff49d29ddcd1e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/MachineInstr.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/lib/CodeGen/MIRParser/MILexer.cpp
M llvm/lib/CodeGen/MIRParser/MILexer.h
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/addrspacecast-nonnull.ll
A llvm/test/CodeGen/MIR/AMDGPU/addrspacecast-nonnull.mir
M llvm/utils/UpdateTestChecks/mir.py
Log Message:
-----------
AMDGPU: Use the addrspacecast nonnull flag in codegen (#220926)
Plumb the nonnull flag through to the backend so a flagged addrspacecast
lowers without the runtime null check, matching what
llvm.amdgcn.addrspacecast.nonnull already provides.
Add the NonNull MIFlag with MIR printer/parser support (including the
MIRPrinter path and update_mir_test_checks) so it round-trips on
G_ADDRSPACE_CAST, and preserve it through SelectionDAG vector
scalarization and splitting.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 7bf85cae41005e0394abf224a7bcfd465319c6d7
https://github.com/llvm/llvm-project/commit/7bf85cae41005e0394abf224a7bcfd465319c6d7
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/include/clang/Basic/BuiltinsX86_64.td
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/CodeGen/TargetBuiltins/X86.cpp
M clang/lib/Headers/bmi2intrin.h
M compiler-rt/lib/msan/tests/msan_test.cpp
Log Message:
-----------
[X86] Remove x86 PDEP/PEXT clang intrinsics and rely on generic elementwise implementations (#204969)
The clang frontend already converted the x86 builtins to generics, this just moves to using the elementwise builtins directly.
Commit: b182b415d9b2447cf1fd7231ebe28a96cfd1f9af
https://github.com/llvm/llvm-project/commit/b182b415d9b2447cf1fd7231ebe28a96cfd1f9af
Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/RegisterPressure.h
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/RegisterPressure.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/unittests/CodeGen/CMakeLists.txt
A llvm/unittests/CodeGen/RegisterPressureTest.cpp
Log Message:
-----------
[CodeGen] Correctly classify/mark dead defs when adjusting lane liveness (#215595)
Despite what the documentation of `adjustLaneLiveness` states, the
method never sets dead flags on dead def operands, even when missing
dead flags can later lead to machine verifier errors.
This makes the method identify dead definitions from definitions that
are initially thought to be alive, and makes it add a dead flag on the
last definition of a virtual register, matching the behavior expected by
the machine verifier (ref. "Instruction ending live segment on dead slot
has no dead flag").
`adjustLaneLiveness` and `detectDeadDefs` now also use the same
mechanism to identify dead definitions. It relies on comparing the
defined lanes of a definition with those that stay alive after it.
Commit: b3071f2b0db631e8fb0d4b47f5e46d0c8297879a
https://github.com/llvm/llvm-project/commit/b3071f2b0db631e8fb0d4b47f5e46d0c8297879a
Author: Ayokunle Amodu <ayokunle321 at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-vi-f16.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
Log Message:
-----------
[CIR][AMDGPU] Add support for AMDGCN class builtins (#213496)
Adds codegen for the following AMDGCN class builtins:
- __builtin_amdgcn_class (double)
- __builtin_amdgcn_classf (float)
- __builtin_amdgcn_classh (half)
These are lowered to the corresponding `llvm.amdgcn.class` intrinsics.
Commit: 97ad26d9bfdb0c83bc6edc3de016fb7bc7b3d5b3
https://github.com/llvm/llvm-project/commit/97ad26d9bfdb0c83bc6edc3de016fb7bc7b3d5b3
Author: Arda Serdar Pektezol <arda at pektezol.dev>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopFlatten.cpp
A llvm/test/Transforms/LoopFlatten/invalidate-scev-pr203176.ll
Log Message:
-----------
[LoopFlatten] Invalidate SCEV on each widening (#211819)
LoopFlatten can update a loop before deciding on not to flatten it due
to profitability. SCEV has cached loop information during the checks and
the widening, where it can lead to stale data if the pass bails at
flattening. Invalidate it after each successful widening.
Fixes #203176
Co-authored-by: Steve Gustaman <stevegustaman at kaist.ac.kr>
Commit: 803252a70e326051a340e1a80b79cd10ed633e7f
https://github.com/llvm/llvm-project/commit/803252a70e326051a340e1a80b79cd10ed633e7f
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGenTypes/LowLevelType.h
M llvm/include/llvm/IR/DerivedTypes.h
M llvm/include/llvm/Support/TypeSize.h
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/unittests/Support/TypeSizeTest.cpp
Log Message:
-----------
[NFC][LLVM] Remove TypeSize::multiplyCoefficientBy(). (#221215)
TypeSize implements operator*() that performs the same operation.
Commit: 1f15665245afc1b303ed2cad0c5ea610f499f666
https://github.com/llvm/llvm-project/commit/1f15665245afc1b303ed2cad0c5ea610f499f666
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
Log Message:
-----------
[AArch64] Add a fast-path for AArch64InstrInfo::getInstSizeInBytes (NFC) (#221894)
Improves CTMark geomean -0.07% on aarch64-O0-g.
https://llvm-compile-time-tracker.com/compare.php?from=97cbc1e404b980edc58bfbcabb6f1c61793b624b&to=be1403a1f2db85c9443fa8300fa8522561bea90a&stat=instructions:u
Assisted-by: codex
Commit: 283b9b565ea8093fd5d04d0435d6594624c58ddb
https://github.com/llvm/llvm-project/commit/283b9b565ea8093fd5d04d0435d6594624c58ddb
Author: David Spickett <david.spickett at arm.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M lldb/docs/resources/test.md
Log Message:
-----------
[lldb][docs] Remove duplicate title in test doc (#221944)
Commit: a1a2d57627695fb86438229340cba87560ab2c9b
https://github.com/llvm/llvm-project/commit/a1a2d57627695fb86438229340cba87560ab2c9b
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/docs/CMakeLists.txt
M clang/include/clang/Options/ClangOptionDocs.td
M clang/include/clang/Options/Options.td
M clang/utils/TableGen/ClangOptionDocEmitter.cpp
Log Message:
-----------
Revert "[clang][docs] Generate command line reference as Markdown" (#221937)
Reverts llvm/llvm-project#220385
This has broken several flang pipelines:
-
https://github.com/llvm/llvm-project/actions/runs/34051600098/job/101536096902?pr=218746
- https://github.com/llvm/llvm-project/actions/runs/34200642862
Commit: eb96d6530255aaaa00e156803b2fc224c80678ba
https://github.com/llvm/llvm-project/commit/eb96d6530255aaaa00e156803b2fc224c80678ba
Author: Mikołaj Piróg <mikolaj.maciej.pirog at intel.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/test/CodeGen/target-builtin-noerror.c
Log Message:
-----------
[X86] Make target-builtin-noerror.c fail on warning (#221796)
As in title. Also removed deleted features. The test was previously
accepting any string
Commit: 6755672f7a2bdf286b1a53fd44d07cad26e40afe
https://github.com/llvm/llvm-project/commit/6755672f7a2bdf286b1a53fd44d07cad26e40afe
Author: Henrich Lauko <xlauko at mail.muni.cz>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/test/CIR/CodeGen/callsite-inline-attributes.cpp
M clang/test/CIR/IR/inline-attrs.cir
M clang/test/CIR/IR/invalid-call.cir
M clang/test/CodeGen/AArch64/sme-inline-callees-streaming-attrs.c
Log Message:
-----------
[CIR] Drop the redundant suffix from the inline kind mnemonic (#220892)
inline_kind was the one CIR enum attribute mnemonic still repeating what
its
C++ enum class name says. The attribute now spells
`#cir.inline<always_inline>`. The operation argument keeps the name
inline_kind, since that is the accessor name, so the printed form reads
`inline_kind = #cir.inline<always_inline>`.
The enum's summary also becomes "inline kind" rather than the camelCase
"inlineKind", which is what generated docs show now that
CIR_InlineKindAttr
no longer overrides it.
25 CHECK lines change across four test files. Nine are in an
aarch64-registered-target test, unsupported in an X86-only build, but
the
substitution matches the two CIR tests that do run.
Commit: 8badd964149235ea91c2d98f02e1f39a78f117f5
https://github.com/llvm/llvm-project/commit/8badd964149235ea91c2d98f02e1f39a78f117f5
Author: Rohit Aggarwal <Rohit.Aggarwal at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/test/Transforms/LoopVectorize/X86/amdlibm-calls.ll
Log Message:
-----------
[AMDLIBM] Add VF8 mapping for cbrtf (amd_vrs8_cbrtf) (#220815)
Map cbrtf loops at VF=8 to amd_vrs8_cbrtf so -vector-library=AMDLIBM
matches the vector entry exported by AOCL-LibM.
AOCL repo : [AOCL-LibM](https://github.com/amd/aocl-libm-ose)
As per the latest external supported call in
[amdlibm_vec.h](https://github.com/amd/aocl-libm-ose/blob/master/include/external/amdlibm_vec.h)
Commit: fa0638edc6628ce2c386519ffdcbdcf35513e67e
https://github.com/llvm/llvm-project/commit/fa0638edc6628ce2c386519ffdcbdcf35513e67e
Author: Mariya Podchishchaeva <Mariya.Podchishchaeva at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
A clang/test/CIR/CodeGenHIP/ternary-struct-addrspace.hip
M clang/test/CIR/CodeGenOpenMP/target-map.c
Log Message:
-----------
[CIR] Cast alloca for function parameter to the right address space (#220836)
Function parameters are stored into temporary allocas and for
address-space aware targets allocas may yield pointers to address spaces
that are different from default address space or the address space of
the parameter type. Do a cast to avoid mismatch. The address space
mismatch was reproduced using cir.ternary op returning a function
parameter and a local variable. For local variables and return
temporaries we already cast alloca address space to temporary address
space but not for function parameter allocas.
Commit: aab03a357abe175a4f9042b8fb8255c63fbd4c8e
https://github.com/llvm/llvm-project/commit/aab03a357abe175a4f9042b8fb8255c63fbd4c8e
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/AArch64/scalar-steps-cost.ll
Log Message:
-----------
[VPlan] Add IV steps cost tests for small trip counts and regions (NFC). (#221948)
Add 2 tests covering missing cases: scalar-iv steps cost in single
iteration loops, and cost in replicate regions.
Commit: fc44546b1bf7cd2048dd079e9f69c3b384162d56
https://github.com/llvm/llvm-project/commit/fc44546b1bf7cd2048dd079e9f69c3b384162d56
Author: Vlad Sytchenko <vsytch at hotmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Add missing targets for CIR (#220753)
[bazel] Add missing targets for CIR
Commit: f0e67ea7d15c44b252f46388fecac396382e1a16
https://github.com/llvm/llvm-project/commit/f0e67ea7d15c44b252f46388fecac396382e1a16
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/concurrent_base.py
M lldb/test/API/functionalities/thread/concurrent_events/main.cpp
Log Message:
-----------
[lldb] Fix flaky TestConcurrentTwoWatchpointsOneSignal (#221697)
`g_watchme` was declared right next to `g_sigusr1_count`. Hardware
watchpoints round the watched address/size to an alignment boundary, so
a watchpoint on `g_watchme` could also end up covering
`g_sigusr1_count`. When the signal thread's handler touches
`g_sigusr1_count` while the watchpoint threads write `g_watchme`, that
overlap causes a spurious hit and lldb can attribute the stop to the
wrong thread.
See llvm.org/PR35228.
Fix: group the watched field and its padding into a single aligned
struct (`WatchMePadding`), so the compiler is guaranteed to lay out the
data and padding together.
Assisted by Claude.
Commit: e93a9e0d9936dce610967bb9be3d42f0f3d1493a
https://github.com/llvm/llvm-project/commit/e93a9e0d9936dce610967bb9be3d42f0f3d1493a
Author: Jan Schultke <me at eisenwave.net>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/CodeGen/X86/clmul-vector.ll
M llvm/test/CodeGen/X86/clmul.ll
Log Message:
-----------
[SelectionDAG] Expand CLMUL of zero-extended all-ones operand via parallel prefix XOR (#207339)
Fixes #204870
Commit: 09f54c2e2d9b78929089fed41275b0ed987538ff
https://github.com/llvm/llvm-project/commit/09f54c2e2d9b78929089fed41275b0ed987538ff
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/Program.cpp
M clang/lib/AST/ByteCode/Record.h
Log Message:
-----------
[clang][bytecode] Save Record::Field PrimType (#221945)
This does not increase the size of `Record::Field` but lets us avoid
classifying fields all the time.
Commit: b90c062f3f03f2c2311644845790252aa6e5237e
https://github.com/llvm/llvm-project/commit/b90c062f3f03f2c2311644845790252aa6e5237e
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
A llvm/lib/ExecutionEngine/Orc/Mangler.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/CMakeLists.txt
R llvm/lib/ExecutionEngine/Orc/Shared/Mangler.cpp
Log Message:
-----------
[ORC] Move Mangler implementation from OrcShared to OrcJIT (#221942)
Many OrcJIT clients don't directly depend on OrcSupport, and so broke
when e91092685eab moved mangling from OrcJIT to OrcSupport.
We want to reorganize these libraries in the not too distant future.
Rather than forcing clients to update dependencies that may change again
soon, move the code (but not the header) back into the OrcJIT library.
We can address the mismatch between the header's and implementation's
home during the library reorganization.
Commit: 2dfc0140a0385d063a7b336549a4055778febb1a
https://github.com/llvm/llvm-project/commit/2dfc0140a0385d063a7b336549a4055778febb1a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.h
A llvm/test/TableGen/RuntimeLibcallEmitter-library-dispatch.td
M llvm/test/TableGen/RuntimeLibcallEmitter-library-grouping.td
M llvm/test/TableGen/RuntimeLibcallEmitter-library-name-merge.td
M llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp
Log Message:
-----------
RuntimeLibcalls: Dispatch to library functions from SystemRuntimeLibrary (#217593)
When a SystemRuntimeLibrary names LibcallLibrary defs,
setTargetRuntimeLibcallSets now dispatches each under an isLibraryAvailable
guard, so an impl can be homed into a library without dropping it from the target.
Non-library members keep the inline path. No target names a library yet, so output
is unchanged.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 188842344ace5e1cc0cc84eec02d4a746213277a
https://github.com/llvm/llvm-project/commit/188842344ace5e1cc0cc84eec02d4a746213277a
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M lldb/source/Plugins/ABI/X86/ABIWindows_x86_64.cpp
Log Message:
-----------
[lldb][Windows] Mark unwind plan as valid at all instructions (#215514)
This is a follow up to https://github.com/llvm/llvm-project/pull/210076.
The unwind plan is now valid at every location.
Commit: 9bc8df6b880ef04a90e5b9ff05afd07f6fbdf562
https://github.com/llvm/llvm-project/commit/9bc8df6b880ef04a90e5b9ff05afd07f6fbdf562
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
Log Message:
-----------
[lldb][windows] print an error if Python fails to initialize (#181160)
Add checks around the `Py_init*` calls to check if Python was
initialized correctly. If any of the calls fails, print an error and
return early.
Python will fail to initialize if `%SystemRoot%` is not defined which
causes lldb to crash. This patch prints an error if the initialization
fails and returns early. lldb still crashes but gives a clue as to why
that's the case.
rdar://168004280
Commit: 6940519208db433dfffc408392344245129e4050
https://github.com/llvm/llvm-project/commit/6940519208db433dfffc408392344245129e4050
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M libc/shared/rpc.h
Log Message:
-----------
[libc] Simplify RPC lock handling to be scalar on the GPU (#221805)
Summary:
This interface was originally written in a complicated way as a
pessimistic bet against NVIDIA's independent thread scheduling. The idea
was that it would work regardless of which set actually executed the
function. The problem is that this forces the operation to be an
expensive vector operation.
This should be safe, we already have other safeguards against ITS in the
main loop. When this function is called, we know that the index and lane
mask are convergent in the set. ITS says the true threads executing this
could be greater than returned. But in this case the 'locked' value
would not be shuffled in, it would not see that it got the lock, and
loop again in a different mask set.
The complicated thing about ITS is mostly that any lanes that share a PC
will report convergent, but that should not bite us here as we already
guard against that before calling this.
Commit: 51eedac31577e2394d240aa9267374183a42b231
https://github.com/llvm/llvm-project/commit/51eedac31577e2394d240aa9267374183a42b231
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/test/CodeGenCUDA/fp-contract.cu
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
Log Message:
-----------
AMDGPU: Set the addrspacecast nonnull flag instead of the intrinsic (#220927)
AMDGPUCodeGenPrepare proved the source of certain flat<->local/private
addrspacecasts non-null and rewrote them to
llvm.amdgcn.addrspacecast.nonnull. Now that the flag is honored in
codegen, set it in place on the existing instruction instead.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 5e3af02eddc71b7e7c352b29783b3cf395f51330
https://github.com/llvm/llvm-project/commit/5e3af02eddc71b7e7c352b29783b3cf395f51330
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/addrspacecast.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/addrspacecast.ll
A llvm/test/Bitcode/amdgcn-addrspacecast-nonnull.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-gas.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll
R llvm/test/CodeGen/AMDGPU/llvm.amdgcn.addrspacecast.nonnull.ll
Log Message:
-----------
AMDGPU: Remove llvm.amdgcn.addrspacecast.nonnull (#220928)
The intrinsic is fully replaced by the nonnull flag on addrspacecast,
so remove it.
Old bitcode/IR is autoupgraded, though this is very conservative. This
intrinsic was only inserted by the backend, and hopefully nobody was
directly emitting it.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: c40a02b6da9291e33c53fc19c37f2d3bf35c06d0
https://github.com/llvm/llvm-project/commit/c40a02b6da9291e33c53fc19c37f2d3bf35c06d0
Author: David Spickett <david.spickett at arm.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M lldb/include/lldb/Breakpoint/StopPointSiteList.h
M lldb/source/Target/Process.cpp
Log Message:
-----------
[lldb] Small changes to StopPointSiteList::FindInRange (#221975)
1. Make the return value indicate an empty list or not. (I would return
a list, but you cannot copy this list and I don't want to make a larger
change right now)
2. Remove a redundant write at one of the call sites.
Commit: 2aa1dd5d9c56cde7f828cb78017c150e8c11629f
https://github.com/llvm/llvm-project/commit/2aa1dd5d9c56cde7f828cb78017c150e8c11629f
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/test/CodeGen/X86/vector-compress.ll
Log Message:
-----------
[LLVM][SelectionDAG] Fix incorrect splitting of VECTOR_COMPRESS when passthrough operand is not undef. (#215772)
When splitting VECTOR_COMPRESS the original mask is used for the final
step when inactive elements are set to their passthrough value. This is
incorrect because only the inactive lanes of the result should be set to
their passthrough value.
Commit: 6c8467d3f917e84ebc1bd7c10fb8bd69ded6040e
https://github.com/llvm/llvm-project/commit/6c8467d3f917e84ebc1bd7c10fb8bd69ded6040e
Author: Henrich Lauko <xlauko at mail.muni.cz>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRCUDAAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIREnumAttr.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
Log Message:
-----------
[CIR] Use the modern enum case classes (#220935)
The `I32EnumAttrCase` family carries an `Attr` half, and an
`IntegerAttr`
predicate with it, that a CIR enum has no use for now that the enums
derive
from `EnumInfo`. Upstream says of those forms that they "are not needed
when
using the newer `EnumCase` form".
Rename all of them to `I32EnumCase`, `I32BitEnumCaseNone`,
`I32BitEnumCaseBit` and `BitEnumCaseGroup`. The group class drops its
width
prefix because the modern spelling takes the width from its cases.
Commit: 991c62626638056a85c7af56e211344f8bdd36dc
https://github.com/llvm/llvm-project/commit/991c62626638056a85c7af56e211344f8bdd36dc
Author: Tomáš Slanina <itzexpoexpo at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/cmake/modules/HandleLLVMOptions.cmake
Log Message:
-----------
Set correct stack reserve when built by Clang on Windows (#221263)
Currently it's handled correctly for MSVC's LINK and MinGW (i.e.
distributed builds of LLVM work correctly), but not lld-link, causing
such builds to crash in certain scenarios.
Commit: 3741dacd195a961f996f357a3b753dd9432a7941
https://github.com/llvm/llvm-project/commit/3741dacd195a961f996f357a3b753dd9432a7941
Author: Vikash Gupta <Vikash.Gupta at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir
M llvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-and.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-crash.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-commute-shift.mir
M llvm/test/CodeGen/AArch64/neon-shuffle-vector-tbl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/merge-values-s16-true16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-opt.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/workitem-intrinsic-opts.ll
Log Message:
-----------
[GlobalISel] Migrate various generic wip_match_opcode combines to MIR-pattern. (#220213)
This patch converts a batch of GlobalISel combine rules from
hand-written C++ matchers to declarative MIR patterns preserving the
behavior. It also along with adds two functional changes (a
rule-ordering fix and an out-of-bounds bug fix) are described below.
- `select_same_val` → `select_same_val_trivial` +
`select_same_val_equiv` group
- `select_constant_cmp` → `_false` / `_true` / `_general` group
- `simplify_add_to_sub`, `add_p2i_to_ptradd` → `GICombinePatFrag`s
- `commute_shift` → `commute_shift_frags` (C++ residue reduced to
`isDesirableToCommuteWithShift`)
- `combine_i2p_to_p2i`, `ptr_add_zero`, `sext_trunc_sext_load` →
patterns.
- funnel-shift / rotate / `ashr_lshr` / `constant_fold_fma` /
`constant_fold_cast_op` / `combine_minmax_nan` → pattern fragments
- **`select_zero_true` / `select_zero_false`:** skip a constant
condition as they fold it to an arm instead strictly better and avoids a
`G_FREEZE` that post-legalization can't clean up.
- **`match_bitfield_extract_from_and`:** mask the AND immediate to the
operand width and reject fields where `lsb + width > size`, preventing
an out-of-bounds `G_UBFX` (fixes an AMDGPU `knownBitsForSBFE` crash).
28 CodeGen tests updated. All diffs are semantically equivalent.
Commit: a3b12f0cd5337230199fc9c6319cc2c4614f75b8
https://github.com/llvm/llvm-project/commit/a3b12f0cd5337230199fc9c6319cc2c4614f75b8
Author: Oscar Priego <oscar.priegov at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Analysis/MemoryDependenceAnalysis.cpp
M llvm/test/Transforms/GVN/pr46054-md-nonlocaldefcache-cleanup.ll
Log Message:
-----------
[MemDep] Remove cached non-local defs referencing deleted instructions (#219929)
MemoryDependenceResults::removeInstruction() removed entries from
NonLocalDefsCache when the removed non-pointer instruction was itself a
cache key, but did not remove entries where that instruction was the cached
dependency result.
This could leave a stale instruction reachable through NonLocalDefsCache
after GVN erased it. A later non-local load query could then consume the
dangling dependency and crash in GVN::analyzeLoadAvailability().
Use ReverseNonLocalDefsCache to remove forward cache entries whose
dependency result references the removed instruction, keeping both maps
consistent.
Related removal paths now use the existing reverse-map helper, with
consistency assertions to catch future map divergence.
Fixes #219885.
A downstream Mono integration has also hit #219885 in practice when
tagging non-pointer array-header loads with !invariant.group. They
currently gate those tags off as a temporary workaround pending the
upstream fix in this PR:
Phantomical/mono at 7e44c68
Commit: 651d01e873c6fce3c8d300362585b1a5f98bb883
https://github.com/llvm/llvm-project/commit/651d01e873c6fce3c8d300362585b1a5f98bb883
Author: AZero13 <gfunni234 at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/lib/AST/StmtPrinter.cpp
M clang/unittests/AST/TypePrinterTest.cpp
Log Message:
-----------
[clang][AST] Fix infinite recursion when printing fully qualified template parameters (#219044)
This fixes an infinite recursion crash that was introduced in #206041.
When printing a `DeclRefExpr` using
`PrintingPolicy::FullyQualifiedName`, we were previously trying to print
the fully qualified name of all decls. However, when the decl is a
template parameter, its `DeclContext` is the template specialization
itself. If a template specialization's arguments depend on that same
template parameter (e.g., `template<int Count> struct
View<int[Count]>`), attempting to print the qualified name forces Clang
to recursively evaluate the enclosing context. This led to unbounded
recursion (`View<int[Count]>::Count` ->
`View<int[View<int[Count]>::Count]>::Count` and so on). Since template
parameters are inherently scoped to their template declarations and do
not require a fully qualified name, this patch resolves the issue by
skipping `printQualifiedName` if the decl is a template parameter
(`!VD->isTemplateParameter()`).
Fixes #218076.
Commit: f20b6e56a866c49522737364de6a5ab4bedbd43e
https://github.com/llvm/llvm-project/commit/f20b6e56a866c49522737364de6a5ab4bedbd43e
Author: David Spickett <david.spickett at arm.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M lldb/include/lldb/Target/Process.h
M lldb/source/Target/Process.cpp
Log Message:
-----------
[lldb] Remove return value from RemoveBreakpointOpcodesFromBuffer (#221979)
It was never set to anything and the one caller ignored it.
Commit: 08a32ba66e9c01320a6ab13edfc5f332af8d47ed
https://github.com/llvm/llvm-project/commit/08a32ba66e9c01320a6ab13edfc5f332af8d47ed
Author: Kane Wang <wangqiang1 at kylinos.cn>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
A llvm/test/CodeGen/RISCV/GlobalISel/load-store.ll
Log Message:
-----------
[RISCV][GlobalISel] Fold large constant offsets in selectAddrRegImm (#219161)
Fold ADDI adjustment (AddiPair) for offsets in [-4096, 4094] and split
larger constants into materialized Hi + Lo12 offset, matching SDAG. Add
isWorthFoldingAdd to guard the split and extract the shared ADDI
renderer into renderAddiPair.
Assisted-by: Claude
Commit: c4babfb3128b9b167e469003028dbaf4e14a6167
https://github.com/llvm/llvm-project/commit/c4babfb3128b9b167e469003028dbaf4e14a6167
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
[Docs] Document persistent metadata printing (#220967)
Document how persistent metadata IDs affect intermediate and standalone
textual output. Final assembly output remains canonically renumbered.
Follow-up to #220390.
Commit: 27bb4d2432d9e5643c7f4f5df495c1580fe07da8
https://github.com/llvm/llvm-project/commit/27bb4d2432d9e5643c7f4f5df495c1580fe07da8
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorDropLeadUnitDim.cpp
M mlir/test/Dialect/Vector/vector-dropleadunitdim-transforms.mlir
Log Message:
-----------
[mlir][vector] Update `CastAwayTransfer{Read|Write}LeadingOneDim` (#219499)
Updates `CastAwayTransfer{Read|Write}LeadingOneDim` to use
`vector.shape_cast`, rather than `vector.extract`, as the canonical form
for stripping unit dimensions.
This change was originally implemented by @krzysz00 in #196206, but was
subsequently reverted in #199546. This PR intentionally restores only a
subset of #196206, making it easier to identify and triage any potential
regressions.
Co-authored-by: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Commit: fdffea81bc29094eb11eddf85309a6615c4f0049
https://github.com/llvm/llvm-project/commit/fdffea81bc29094eb11eddf85309a6615c4f0049
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.v2f16.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.v2f16.ll
Log Message:
-----------
[AMDGPU] Prefer packed minimum/maximum ops for two-input ops (#215449)
A two-input f16 fminimum or fmaximum operation should translate to a
packed two-input minimum/maximum instruction when the target supports
one.
It currently can be selected through the minimum3/maximum3 fallback
pattern instead. That emits a three-input instruction with one input
operand duplicated.
Keep the fallback for nested min/max expressions that can use the real
three-input instruction. Add a higher-priority direct pattern for
non-nested two-input operations on targets with packed IEEE
minimum/maximum opcodes.
Commit: a4e8604a2da580de80debb6a15c9c6d7379a68d5
https://github.com/llvm/llvm-project/commit/a4e8604a2da580de80debb6a15c9c6d7379a68d5
Author: sstwcw <su3e8a96kzlver at posteo.net>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/FormatTestVerilog.cpp
Log Message:
-----------
[clang-format] Recognize the signed modifier for Verilog struct (#219694)
after
```SystemVerilog
struct packed signed {
int a;
} pack1;
```
before
```SystemVerilog
struct packed signed { int a; }
pack1;
```
Commit: 09f1a51bf3a1cdd751379e0ccb9753419f4a14e9
https://github.com/llvm/llvm-project/commit/09f1a51bf3a1cdd751379e0ccb9753419f4a14e9
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
A llvm/test/CodeGen/X86/active_lane_mask.ll
Log Message:
-----------
[X86] Add basic llvm.get.active.lane.mask test coverage (#221978)
Commit: cb0e50003dc09853b390eca67a13b05b3d691fc4
https://github.com/llvm/llvm-project/commit/cb0e50003dc09853b390eca67a13b05b3d691fc4
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/acos_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/asin_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/atan_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/ceil_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cos_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cosh_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp2_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/floor_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log10_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log2_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/roundeven_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sin_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sinh_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sqrt_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tan_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tanh_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/trunc_mat.ll
Log Message:
-----------
[SPIRV] Add matrix type legalization for many float global opcodes (#220782)
fixes #220723
The issue in #220723 is that the global opcodes can not deduce the
element type when the input is a shuffle vector. This is the same issue
as #213783. All we have to do to fix this is to have deduceTypeFromUses
in the SPIRVPostLegalizer know that we need to look up the type from the
results register for these opcodes.
The secondary issue is that there were no matrix tests for any of these
global opcodes so I added them. I did not follow the template started by
the atan2 tests because those are overkill and testing way to much stuff
not related to opcode legalization.
Assisted on the tests by MAI-Code-1.1-Flash
Commit: 52d922aa153b1232813470e014635419ce006023
https://github.com/llvm/llvm-project/commit/52d922aa153b1232813470e014635419ce006023
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/CMakeLists.txt
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVOps.h
M mlir/lib/Dialect/SPIRV/IR/CMakeLists.txt
M mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVOpDefinition.cpp
A mlir/lib/Dialect/SPIRV/IR/SPIRVOpDefinition.h
A mlir/lib/Dialect/SPIRV/IR/SPIRVOpDefinitions.cpp
Log Message:
-----------
[MLIR][spirv] Shard generated operation definitions (NFC) (#221811)
Generate SPIR-V operation definitions in eight shards and use the
generated registration hook. Keep parser, printer, and verification
helpers in the existing implementation TU and expose them through a
private header.
Assisted-by: Codex
Commit: c4d8bd10c14a6902da83306270e836ef6fa5bb76
https://github.com/llvm/llvm-project/commit/c4d8bd10c14a6902da83306270e836ef6fa5bb76
Author: Benjamin Chetioui <3920784+bchetioui at users.noreply.github.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp
M mlir/lib/Dialect/LLVMIR/IR/BasicPtxBuilderInterface.cpp
M mlir/lib/Dialect/X86/Transforms/AVXTranspose.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
M mlir/test/Target/LLVMIR/Import/instructions.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[mlir][llvm] Add convergent attribute to llvm.inline_asm. (#221990)
Expose LLVM's convergent call-site attribute on the LLVM dialect
inline_asm op. This allows marking an inline asm block as convergent so
that divergence-aware passes do not move it relative to divergent
control flow.
Commit: 15359d3801d68f93aaf06d7c9647501211f620a1
https://github.com/llvm/llvm-project/commit/15359d3801d68f93aaf06d7c9647501211f620a1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
A llvm/test/CodeGen/Hexagon/const-prop-undef.mir
Log Message:
-----------
Hexagon: Fix constant propagation crash on a use with no reaching definition (#220297)
Commit: a76045040a1297217256d917bec9e02f9723804c
https://github.com/llvm/llvm-project/commit/a76045040a1297217256d917bec9e02f9723804c
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/CMakeLists.txt
M mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.h
M mlir/lib/Dialect/LLVMIR/CMakeLists.txt
M mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp
A mlir/lib/Dialect/LLVMIR/IR/ROCDLOps.cpp
A mlir/lib/Dialect/LLVMIR/IR/ROCDLOps.h
Log Message:
-----------
[MLIR][ROCDL] Shard generated operation definitions (NFC) (#221729)
ROCDL generated operation definitions is amongst the slowest MLIR
translation unit. Generate eight definition shards, compile them as
separate sources, and use the generated sharded registration hook while
keeping custom parser and printer helpers in one implementation unit.
Assisted-by: Codex
Commit: 8c8aa74533a841a7f61dac5e80c8241799458dd6
https://github.com/llvm/llvm-project/commit/8c8aa74533a841a7f61dac5e80c8241799458dd6
Author: Letu Ren <fantasquex at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
Log Message:
-----------
[mlir][LLVM] Add pdep and pext intrinsics (#220768)
Assisted-by: grok-4.6
Signed-off-by: Letu Ren <fantasquex at gmail.com>
Commit: 35fe7e14ecb4e50182fe93123e1876824d14bb94
https://github.com/llvm/llvm-project/commit/35fe7e14ecb4e50182fe93123e1876824d14bb94
Author: Alex Strelnikov <strel at google.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M libc/src/__support/printf_core/char_converter.h
M libc/src/__support/printf_core/converter.h
M libc/src/__support/printf_core/fixed_converter.h
M libc/src/__support/printf_core/float_dec_converter.h
M libc/src/__support/printf_core/float_dec_converter_limited.h
M libc/src/__support/printf_core/float_hex_converter.h
M libc/src/__support/printf_core/float_inf_nan_converter.h
M libc/src/__support/printf_core/int_converter.h
A libc/src/__support/printf_core/overflow_modes.def
M libc/src/__support/printf_core/printf_main.h
M libc/src/__support/printf_core/ptr_converter.h
M libc/src/__support/printf_core/strerror_converter.h
M libc/src/__support/printf_core/string_converter.h
M libc/src/__support/printf_core/vasprintf_internal.h
M libc/src/__support/printf_core/vfprintf_internal.h
M libc/src/__support/printf_core/write_int_converter.h
R libc/src/__support/printf_core/write_modes.def
M libc/src/__support/printf_core/writer.h
M libc/src/err/report.cpp
M libc/src/stdio/baremetal/vfprintf_internal.h
M libc/src/stdio/snprintf.cpp
M libc/src/stdio/snprintf_modular.cpp
M libc/src/stdio/sprintf.cpp
M libc/src/stdio/sprintf_modular.cpp
M libc/src/stdio/vsnprintf.cpp
M libc/src/stdio/vsnprintf_modular.cpp
M libc/src/stdio/vsprintf.cpp
M libc/src/stdio/vsprintf_modular.cpp
M libc/src/stdlib/str_from_util.h
M libc/src/stdlib/strfromd.cpp
M libc/src/stdlib/strfromf.cpp
M libc/src/stdlib/strfroml.cpp
M libc/src/time/asctime_utils.h
M libc/src/time/strftime.cpp
M libc/src/time/strftime_core/composite_converter.h
M libc/src/time/strftime_core/converter.h
M libc/src/time/strftime_core/num_converter.h
M libc/src/time/strftime_core/str_converter.h
M libc/src/time/strftime_core/strftime_main.h
M libc/src/time/strftime_l.cpp
M libc/test/src/__support/printf_core/converter_test.cpp
M libc/test/src/__support/printf_core/writer_test.cpp
Log Message:
-----------
[libc] Update printf_core::Writer to template on character type. (#220669)
This is motivated by working toward `swprintf`.
The primary goal is to enable a `CharT` template type parameter on
`printf_core::Writer`. This requires refactoring how the "overflow
write" logic is set up to get around the limitation on function template
partial specialization.
Key changes to `printf_core::Writer` and friends:
* Separate the overflow write logic from `WriteBuffer` into an
`OverflowWriter` template where specializations handle dispatch, and
remove the `WriteBuffer` subclasses.
* Rename from `WriteMode` to `OverflowMode` to try and shorten the
enumerators with minimal loss to clarity, and reduce the number of modes
to only two: `DROP_OVERFLOW` and `CALLBACK`.
* The number of dynamic function calls for flushing and resizing use
cases stays the same by templating the callback on a `WriteSink`.
At this stage the extra `CharT` template type parameter is added in this
PR mainly to ensure the setup works without running into function
template partial specializations. Fully expanding `Writer` with
`wchar_t` will be done in follow-up PRs.
Commit: cb180d50a81674b467887eab836f563607ae89e8
https://github.com/llvm/llvm-project/commit/cb180d50a81674b467887eab836f563607ae89e8
Author: Ryan VanderMeulen <ryanvm at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/cmake/modules/FindLibXml2.cmake
Log Message:
-----------
[cmake] FindLibXml2: keep user-provided LIBXML2_DEFINITIONS (#221294)
LLVM's `FindLibXml2.cmake` (added in #166867) unconditionally does
`set(LIBXML2_DEFINITIONS ${PC_LIBXML_CFLAGS_OTHER})` and puts
`PC_LIBXML_CFLAGS_OTHER` on the imported targets. CMake's own
`FindLibXml2` module only takes pkg-config's flags when the library it
found is the one pkg-config describes; otherwise it keeps whatever
`LIBXML2_DEFINITIONS` the user passed and exposes it through
`INTERFACE_COMPILE_OPTIONS`.
This matters when cross-compiling against a static libxml2 on Windows.
Passing `-DLIBXML2_DEFINITIONS=-DLIBXML_STATIC
-DLIBXML2_LIBRARIES=.../libxml2s.lib` worked with LLVM 22 (CMake's
module): the define reached both the `xmlReadMemory` configure check and
the consumers of `LibXml2::LibXml2`. With LLVM 23 it is silently
dropped, `xmlexports.h` declares the API `__declspec(dllimport)`, the
check fails to link against the static library and
`LLVM_ENABLE_LIBXML2=FORCE_ON` aborts with `Failed to configure
libxml2`. (pkg-config on the Linux host finds the host's libxml2, so
`PC_LIBXML_CFLAGS_OTHER` is empty and unrelated to the library actually
being used.)
Mirror CMake's behaviour: keep the user's definitions unless pkg-config
found the same library, and attach them to both `LibXml2::LibXml2` and
`LibXml2::LibXml2Static`.
Seen while building the Firefox clang 23 toolchains (x86_64 and aarch64
`-pc-windows-msvc`, cross-compiled from Linux with
`LLVM_EXPORT_SYMBOLS_FOR_PLUGINS=ON`).
---
**AI tool use disclosure** (per the [LLVM AI Tool Use
Policy](https://llvm.org/docs/AIToolPolicy.html)): this change was
developed with Claude Code assisting in the analysis and drafting. The
root cause was established against real 23.1.0 binaries; this cmake
change itself has so far only been verified to apply to 23.1.0 and main
and by code reading, while Firefox's CI validated the equivalent
workaround of passing -DLIBXML_STATIC via the compiler flags. The author
reviewed the change and is accountable for and able to answer questions
about it. Commits carry an `Assisted-by:` trailer.
Commit: 2ca09022430e88ab53cbf0f09d6ec8b3d6deb138
https://github.com/llvm/llvm-project/commit/2ca09022430e88ab53cbf0f09d6ec8b3d6deb138
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
Log Message:
-----------
[GlobalISel] Avoid double DenseMap lookups in ValueToVRegInfo (NFC) (#221741)
Improves CTMark geomean -0.06% on aarch64-O0-g.
https://llvm-compile-time-tracker.com/compare.php?from=97cbc1e404b980edc58bfbcabb6f1c61793b624b&to=fbf62152c51f2327cb2f4a382df90b3f345a8866&stat=instructions:u
Assisted-by: codex
Commit: 0650d53db287b22908ca2c76d21defbec209be44
https://github.com/llvm/llvm-project/commit/0650d53db287b22908ca2c76d21defbec209be44
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86CompressEVEX.cpp
M llvm/test/CodeGen/X86/avx512fp16-frem.ll
M llvm/test/CodeGen/X86/bfloat.ll
M llvm/test/CodeGen/X86/ucmp.ll
M llvm/test/CodeGen/X86/vector-fshl-128.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll
M llvm/test/CodeGen/X86/vector-shuffle-avx512.ll
M llvm/test/CodeGen/X86/vector-shuffle-v192.ll
Log Message:
-----------
[X86][X86CompressEVEX] Do not compress when there is a compressed disp8 (#221923)
Fixes: #206963
Assisted-by: Claude Opus 4.8
Commit: bb6f7fcb46cdbe258b0cba12506fe1f344cd2d45
https://github.com/llvm/llvm-project/commit/bb6f7fcb46cdbe258b0cba12506fe1f344cd2d45
Author: Risan Gnanasegaram <risan888 at hotmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
M mlir/test/Dialect/LLVMIR/layout.mlir
Log Message:
-----------
[mlir][LLVM] Use element allocation sizes when computing struct size (#221742)
`LLVMStructType::getTypeSizeInBits` currently advances by each element's
store size. With the data layout from #221665, this reports 11 bytes for
`!llvm.struct<packed (f80, i8)>`, while LLVM uses the 16-byte allocation
size of `f80` and reports a 17-byte struct.
Round each element's size up to its ABI alignment before adding it to
the
struct size, matching LLVM's `getTypeAllocSize` behavior. Packed structs
continue to suppress alignment gaps before elements, while each element
still consumes its allocation size.
Add regression coverage for packed, unpacked, nested, and array layouts.
Fixes #221665.
Testing: 99 relevant MLIR tests passed; 3 x86-only tests were
unsupported
on the ARM host.
Assisted by: OpenAI Codex
Commit: a25235064367ee356ceddf5064a4d14fca0f8567
https://github.com/llvm/llvm-project/commit/a25235064367ee356ceddf5064a4d14fca0f8567
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.h
Log Message:
-----------
[SLP][NFC] Fix createExtractVector comment missed in #221785 (#221999)
createExtractVector has no Generator; drop it from the doxygen comment.
Commit: 2e8a9d833739a7e3be91c700793b00594c3b745f
https://github.com/llvm/llvm-project/commit/2e8a9d833739a7e3be91c700793b00594c3b745f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/include/llvm/Target/TargetOptions.h
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
Log Message:
-----------
CodeGen: Remove TargetOptions::PPCGenScalarMASSEntries (#221424)
This was PPC specific and wasn't directly written by a generic cl::opt.
It also was inappropriately written based based on a check of the flag
in the TargetPassConfig, which is only likely to be the first use.
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: 1c5ed251750754befcfb619adf6452bc39ecf958
https://github.com/llvm/llvm-project/commit/1c5ed251750754befcfb619adf6452bc39ecf958
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/clmul-vector-256.ll
M llvm/test/CodeGen/X86/clmul-vector-512.ll
M llvm/test/CodeGen/X86/clmul-vector.ll
M llvm/test/CodeGen/X86/pdep-vector-128.ll
M llvm/test/CodeGen/X86/pdep-vector-256.ll
M llvm/test/CodeGen/X86/pdep-vector-512.ll
M llvm/test/CodeGen/X86/pext-vector-128.ll
M llvm/test/CodeGen/X86/pext-vector-256.ll
M llvm/test/CodeGen/X86/pext-vector-512.ll
M llvm/test/CodeGen/X86/znver-pdep.ll
M llvm/test/CodeGen/X86/znver-pext.ll
Log Message:
-----------
[X86] LowerCLMUL - fix unpack order of vXi32 CLMUL/CLMULH codegen (#222001)
Fix typo in the unpack order for vXi32 CLMUL/CLMULH codegen from #221289
and #221668 - I'd gotten the variable names right, but failed to
actually use the right variables!
Fixes #221964
Commit: cec101b15dd27fb1c51b6c87cb6e9d78517d2b09
https://github.com/llvm/llvm-project/commit/cec101b15dd27fb1c51b6c87cb6e9d78517d2b09
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 52d922a (#222005)
This fixes 52d922aa153b1232813470e014635419ce006023 (#221811).
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=52d922aa153b1232813470e014635419ce006023
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 8a3d6f8ca2970c31c21a90f90eb7fe0de0fb0f99
https://github.com/llvm/llvm-project/commit/8a3d6f8ca2970c31c21a90f90eb7fe0de0fb0f99
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M lldb/docs/resources/test.md
M lldb/packages/Python/lldbsuite/test/decorators.py
M lldb/test/API/commands/expression/import-std-module/array/TestArrayFromStdModule.py
M lldb/test/API/commands/expression/import-std-module/basic/TestImportStdModule.py
M lldb/test/API/commands/expression/import-std-module/conflicts/TestStdModuleWithConflicts.py
M lldb/test/API/commands/expression/import-std-module/deque-basic/TestDequeFromStdModule.py
M lldb/test/API/commands/expression/import-std-module/empty-module/TestEmptyStdModule.py
M lldb/test/API/commands/expression/import-std-module/forward_decl_from_module/TestForwardDeclFromStdModule.py
M lldb/test/API/commands/expression/import-std-module/forward_list-dbg-info-content/TestDbgInfoContentForwardListFromStdModule.py
M lldb/test/API/commands/expression/import-std-module/forward_list/TestForwardListFromStdModule.py
M lldb/test/API/commands/expression/import-std-module/iterator/TestIteratorFromStdModule.py
M lldb/test/API/commands/expression/import-std-module/list/TestListFromStdModule.py
M lldb/test/API/commands/expression/import-std-module/missing-module-sources/TestStdModuleSourcesMissing.py
M lldb/test/API/commands/expression/import-std-module/module-build-errors/TestStdModuleBuildErrors.py
M lldb/test/API/commands/expression/import-std-module/no-std-module/TestMissingStdModule.py
M lldb/test/API/commands/expression/import-std-module/non-module-type-separation/TestNonModuleTypeSeparation.py
M lldb/test/API/commands/expression/import-std-module/pair/TestPairFromStdModule.py
M lldb/test/API/commands/expression/import-std-module/queue/TestQueueFromStdModule.py
M lldb/test/API/commands/expression/import-std-module/retry-with-std-module/TestRetryWithStdModule.py
M lldb/test/API/commands/expression/import-std-module/shared_ptr-dbg-info-content/TestSharedPtrDbgInfoContentFromStdModule.py
M lldb/test/API/commands/expression/import-std-module/stack/TestStackFromStdModule.py
M lldb/test/API/commands/expression/import-std-module/sysroot/TestStdModuleSysroot.py
M lldb/test/API/commands/expression/import-std-module/vector-bool/TestVectorBoolFromStdModule.py
M lldb/test/API/commands/expression/import-std-module/vector-of-vectors/TestVectorOfVectorsFromStdModule.py
M lldb/test/API/commands/expression/import-std-module/vector/TestVectorFromStdModule.py
M lldb/test/API/commands/frame/var/TestFrameVar.py
M lldb/test/API/functionalities/breakpoint/jit_loader_rtdyld_elf/TestJitBreakPoint.py
M lldb/test/API/lang/cpp/abi_tag_structors/TestAbiTagStructors.py
M lldb/test/API/lang/cpp/forward/TestCPPForwardDeclaration.py
Log Message:
-----------
[lldb] Add requireClang decorator (#222007)
- Add requireClang, marking Clang-only tests as UNSUPPORTED elsewhere
instead of SKIPPED, following the existing require* convention.
- Replace the ~30 standalone @skipIf(compiler=no_match("clang")) uses
with @requireClang; leave the cases paired with a compiler_version check
as-is, since those are more complex than a simple compiler check.
- Remove the now-unused skipUnlessCompilerIsClang in favor of
requireClang.
- Update the testing docs to mention requireClang.
Follow-up to #214197.
Commit: ee89c01e6ad49aeefc918e08bc27f6b50c5407ba
https://github.com/llvm/llvm-project/commit/ee89c01e6ad49aeefc918e08bc27f6b50c5407ba
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/XCore/XCoreISelLowering.cpp
Log Message:
-----------
[XCore] Use getPtrAdd() instead of getGetElementPtr() (NFC) (#222017)
This was creating an i8 getelementptr, which is exactly what
ptradd is.
Commit: f1f0f21a51d64d9c0272959f18ece36e3247083e
https://github.com/llvm/llvm-project/commit/f1f0f21a51d64d9c0272959f18ece36e3247083e
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/CMakeLists.txt
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPMemoryUtils.cpp
A llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPMemoryUtils.h
M llvm/utils/gn/secondary/llvm/lib/Transforms/Vectorize/BUILD.gn
Log Message:
-----------
[SLP][modularisation][NFC] Move pointer/stride helpers to SLPMemoryUtils (#221786)
Move the following BoUpSLP-independent pointer/stride helpers out of
SLPVectorizer.cpp into a new SLPVectorizer/SLPMemoryUtils.{h,cpp}:
arePointersCompatible
computeCommonAlignment
calculateRtStride
arePointersCompatible reads the file-local RecursionMaxDepth cl::opt.
The option stays static in SLPVectorizer.cpp; the moved helper takes its
value as an explicit unsigned parameter. Behavior is unchanged.
Part of the SLPVectorizer.cpp modularization effort:
https://discourse.llvm.org/t/modularizing-slpvectorizer-cpp/90922
Assisted by AI.
Commit: fe65dbf7e9ad196d8b67aebab8a38936c9c14056
https://github.com/llvm/llvm-project/commit/fe65dbf7e9ad196d8b67aebab8a38936c9c14056
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMInstrInfo.cpp
M llvm/lib/Target/M68k/M68kInstrInfo.cpp
Log Message:
-----------
CodeGen: Remove stale LiveVariables.h includes from ARM and M68k InstrInfo (#222000)
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: 07af01c0f9e55599c4b8e11ad14851d2ef5d01fe
https://github.com/llvm/llvm-project/commit/07af01c0f9e55599c4b8e11ad14851d2ef5d01fe
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/IPO/Attributor.h
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
Log Message:
-----------
[Attributor] Remove dead function getKnownConstantRange (#221897)
getKnownConstantRange was added on January 15, 2020 in commit
188f9a348dc545bf9a420d998ad37761bddd7285 without any callers and has
been unused since.
Commit: b5395ed14ee6d3bc7a98c0abc9e592a1675e0bcc
https://github.com/llvm/llvm-project/commit/b5395ed14ee6d3bc7a98c0abc9e592a1675e0bcc
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/WindowsSecureHotPatching.cpp
Log Message:
-----------
[WindowsSecureHotPatching] Remove redundant getGetElementPtr() (NFC) (#222019)
This was creating a degenerate getelementptr without any indices,
which is equivalent to the base pointer and will fold away.
Commit: bbf7b8439d526de7a696bad82c7f8cc8696e39f7
https://github.com/llvm/llvm-project/commit/bbf7b8439d526de7a696bad82c7f8cc8696e39f7
Author: Ayokunle Amodu <ayokunle321 at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinNVPTX.cpp
A clang/test/CIR/CodeGenCUDA/builtins-nvvm-fma-oob.cu
A clang/test/CIR/CodeGenCUDA/builtins-nvvm-half.cu
Log Message:
-----------
[CIR][NVPTX] Add support for NVVM half type builtins (#221859)
Adds codegen for the following NVVM half type builtins:
- `__nvvm_ex2_approx_{f16,f16x2}`
- `__nvvm_fmin{_ftz,}{_nan,}{_xorsign_abs,}_{f16,f16x2}`
- `__nvvm_fmax{_ftz,}{_nan,}{_xorsign_abs,}_{f16,f16x2}`
- `__nvvm_fma_rn{_ftz,}{_relu,_sat,}_{f16,f16x2}`
- `__nvvm_fma_rn_oob{_relu,}_{f16,bf16,f16x2,bf16x2}`
These are lowered to the corresponding llvm.nvvm.* intrinsics.
This diverges a bit from OG, as no half-type helper is needed here. OG
routes these through `MakeHalfType`, which coerces each argument to the
intrinsic's declared parameter type, appends the intrinsic's defaulted
arguments, and
asserts that no argument is an integer constant expression. None of that
is needed for the builtins in this patch as each already agrees with its
intrinsic on operand and result types, and none has defaulted
parameters. The existing
`emitUnaryNVVMIntrinsic` and `emitBuiltinWithOneOverloadedType<N>`
helpers are therefore sufficient.
More generally, nothing `MakeHalfType` does is half-specific.
Assisted by Claude.
Commit: d5d12741de992606a7f045b744bdbce53538e196
https://github.com/llvm/llvm-project/commit/d5d12741de992606a7f045b744bdbce53538e196
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/lib/CodeGen/CGObjCMac.cpp
Log Message:
-----------
[CGObjCMac] Remove unnecssary zero-index GEPs (#222023)
getConstantGEP() was always called with two zero indices. However,
with opaque pointers, zero-index GEPs are redundant and will fold
away.
Commit: 3bd526b27ffe43b86d1550c79c085697434fb787
https://github.com/llvm/llvm-project/commit/3bd526b27ffe43b86d1550c79c085697434fb787
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Transforms/LoopUnroll/RISCV/runtime-unroll-max-trip-count.ll
M llvm/test/Transforms/LoopUnroll/RISCV/unroll.ll
Log Message:
-----------
[RISCV] Stop ignoring intrinsics in costing for force unrolling (#221107)
All intrinsic calls were hitting the "continue" for !isLoweredToCall
and bypassing the getInstructionCost.
I've modified runtime-unroll-max-trip-count.ll to override unrolling
costs and remove the bswap intrinsics that were previously not counted.
Test case written by Claude.
Commit: 0117d8ca5e8c37e3a14647875095cc422ee9a686
https://github.com/llvm/llvm-project/commit/0117d8ca5e8c37e3a14647875095cc422ee9a686
Author: Kirill Vedernikov <kvedernikov at nvidia.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-shared-collector-b.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-shared-decompress-b.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-shared-ti16.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-shared.mlir
M mlir/test/lit.cfg.py
Log Message:
-----------
[MLIR][NVVM] Add optional llc verification for NVVM dialect tests (#219980)
The motivation is to verify that MLIR NVVM dialect operations lower to
LLVM IR that is accepted by the NVPTX backend. Running llc gives these
tests an extra end-to-end check beyond textual IR matching and helps
catch mismatches between MLIR lowering, NVVM intrinsics, and backend
expectations.
A valid LLVM intrinsic call isn't necessarily selectable for every
combination of its immargs and target features. There is a concrete
NVPTX example in
`llvm/test/CodeGen/NVPTX/tcgen05-mma-collector-b-i8-invalid.ll`. The
intrinsic has a valid signature and individually valid immediate values,
but the combination `kind=i8` and `collector_b=lastuse` is not
supported. LLVM IR verification accepts it, while `llc` rejects it with
Cannot select.
The corresponding MLIR verifier does not duplicate every NVPTX
instruction-selection predicate. It currently checks MLIR-level
properties such as the `disable_output_lane size` and the interaction
between `a_shift` and `collector_a` (the examples are from
`tcgen05.mma`), while the backend owns the complete target-dependent
selection rules. We should improve the MLIR verifier whenever an invalid
MLIR operation can be rejected early, but a targeted integration check
also detects disagreement or drift between those two independently
maintained layers.
Another case is target-version drift. A translation test can be extended
with a new intrinsic variant requiring a newer SM or PTX ISA while
continuing to pass its textual `FileCheck`. Since the existing command
has no target contract, the test does not tell us whether all the
generated intrinsics are lowerable for one coherent target. An `llc`
invocation with explicit `-mcpu` and `-mattr` makes that contract
visible. If a test intended for sm_100a/PTX 8.6 starts using
functionality available only for sm_107f/PTX 9.4, the integration check
reports it immediately.
```
// RUN: %if has_llc_binary && host-supports-nvptx %{ mlir-translate --mlir-to-llvmir %s | %llc-verify -march=nvptx64 -mcpu=sm_<version> -mattr=+ptx<version> %}
```
`%llc-verify` finds `llc` as `lit.util.which("llc",
config.llvm_tools_dir)`.
Commit: 03fd869d69394b404698cda7cc1621f2be4121c2
https://github.com/llvm/llvm-project/commit/03fd869d69394b404698cda7cc1621f2be4121c2
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/lib/CodeGen/MicrosoftCXXABI.cpp
Log Message:
-----------
[MicrosoftCXXABI] Remove unnecessary zero-index GEP (#222025)
This was creating a zero-index GEP constant expression, which is
equivalent to the base pointer, and will be folded away.
Commit: 46c912344a6bc59acd5a396f1c4d921eb54a2c57
https://github.com/llvm/llvm-project/commit/46c912344a6bc59acd5a396f1c4d921eb54a2c57
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M flang/include/flang/Optimizer/OpenACC/Passes.td
M flang/include/flang/Semantics/runtime-type-info.h
M flang/lib/Optimizer/Dialect/FIRType.cpp
M flang/lib/Optimizer/OpenACC/Analysis/FIROpenACCSupportAnalysis.cpp
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCTypeInterfaces.cpp
A flang/lib/Optimizer/OpenACC/Transforms/ACCMapInfoPrep.cpp
M flang/lib/Optimizer/OpenACC/Transforms/CMakeLists.txt
M flang/lib/Semantics/runtime-type-info.cpp
A flang/test/Fir/OpenACC/acc-fir-map-info-prep-attach.mlir
A flang/test/Fir/OpenACC/acc-fir-map-info-prep-clauses.mlir
A flang/test/Fir/OpenACC/acc-fir-map-info-prep-declare-global.mlir
A flang/test/Fir/OpenACC/acc-fir-map-info-prep-exit.mlir
A flang/test/Fir/OpenACC/acc-fir-map-info-prep-implicit-present.mlir
A flang/test/Fir/OpenACC/acc-fir-map-info-prep-privatize.mlir
A flang/test/Fir/OpenACC/acc-fir-map-info-prep-types.mlir
A flang/test/Fir/OpenACC/acc-fir-map-info-prep.mlir
M flang/unittests/Optimizer/OpenACC/FIROpenACCSupportAnalysisTest.cpp
A mlir/include/mlir/Dialect/OpenACC/OpenACCCGEnums.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCCGOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsCG.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsType.h
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACCCG.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsCG.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsType.cpp
A mlir/test/Dialect/OpenACC/invalid-cg-mapinfo.mlir
A mlir/test/Dialect/OpenACC/ops-cg-mapinfo.mlir
M mlir/test/Dialect/OpenACC/ops.mlir
Log Message:
-----------
[acc] Pre-cg pass for handling flang data mapping to offload runtime (#221282)
Introduce acc.map_info as the acc dialect operation that captures a
single mapped object's offload facts (attach point, descriptor kind,
bounds, map flags, and size) so later codegen can lower data clauses to
the offload runtime from one representation.
Add a Flang pre-codegen pass, ACCMapInfoPrep, that materializes
acc.map_info for FIR-typed operands: it infers Fortran descriptor attach
and CFI facts, sizes mapped and privatized storage, and folds paired
enter/exit clause effects into map flags. This keeps FIR-specific
mapping logic out of ACCToLLVM and leaves that conversion to consume
map_info verbatim.
Commit: d3960386544aa370053b110610c8e7f30c850c0e
https://github.com/llvm/llvm-project/commit/d3960386544aa370053b110610c8e7f30c850c0e
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M libcxx/include/tuple
M libcxx/test/std/utilities/tuple/tuple.tuple/tuple.apply/make_from_tuple.pass.cpp
Log Message:
-----------
[libc++] Fix make_from_tuple for reference types (#220966)
#215067 refactored `make_from_tuple`, which introduced a regression when
trying to construct reference types with it.
Commit: 50766c94c42ea6bd4a9424a5a63a905765d5c172
https://github.com/llvm/llvm-project/commit/50766c94c42ea6bd4a9424a5a63a905765d5c172
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/pthread_attr_t.h
M libc/src/__support/threads/linux/thread.cpp
M libc/src/pthread/CMakeLists.txt
A libc/src/pthread/pthread_getattr_np.cpp
M libc/src/pthread/pthread_getattr_np.h
M libc/test/integration/src/pthread/CMakeLists.txt
A libc/test/integration/src/pthread/pthread_getattr_np_test.cpp
Log Message:
-----------
[libc] Implement pthread_getattr_np (#221231)
Implement the GNU extension pthread_getattr_np.
For the stack address and size, the function returns the same value as
pthread_getstack_np. Specifically, this means returning
PTHREAD_STACK_DYNAMIC_NP for the main thread. Since we're not promising
async-signal-safety of this function, we could parse /proc/self/maps
(like glibc does), to get the actual stack VMA, but:
- that's a lot of code
- I'm not particularly fond of relying on /proc for libc features
- the consistency with pthread_getattr_np is nice
For these reasons, I'm not implementing this (or other alternatives like
RLIMIT_STACK) right now. This incidentally means that the current
implementation of this function is async-signal-safe, but that is likely
to change once we add support for additional attributes.
For consistency with glibc, I report the guard size of newly created
threads as zero, regardless of what was present in the thread creation
attributes. I zero the attribute directly during thread creation as it
is not used for managed stacks.
Assisted-by: Gemini
Commit: 3eb8494f6d0e40bf6e7fc3e5ec0196c5b2726bd6
https://github.com/llvm/llvm-project/commit/3eb8494f6d0e40bf6e7fc3e5ec0196c5b2726bd6
Author: Chinmay Deshpande <chdeshpa at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[AMDGPU] Add APIs `getTotalNumVGPRs` and `getAddressableNumVGPRs` to TargetParser (#220695)
These align with `getTotalNumSGPRs` and `getAddressableNumSGPRs` that
already exist.
Commit: 12b2a6767a17e6450a3e844359afa30440bdd9ba
https://github.com/llvm/llvm-project/commit/12b2a6767a17e6450a3e844359afa30440bdd9ba
Author: Laxman Gupta <laxman.gupta1006 at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
M llvm/test/Transforms/AggressiveInstCombine/trunc_vector_instrs.ll
Log Message:
-----------
[AggressiveInstCombine] Add shufflevector support to TruncInstCombine (#220218)
Previously, expression graphs containing shufflevector could not be
reduced to a smaller bit-width. This change adds support for traversing
and rebuilding shufflevector operations during the transformation,
allowing truncation to propagate through shuffle operations.
The shuffle mask and vector shape are preserved while the operands are
rebuilt with the reduced element type.
This removes the corresponding TODO in TruncInstCombine.cpp.
AI Tool Used: GitHub Copilot
Commit: 1dac88b2aad1af472a4f4d5b7d87930e6e557d1f
https://github.com/llvm/llvm-project/commit/1dac88b2aad1af472a4f4d5b7d87930e6e557d1f
Author: Akash Dutta <137309513+akadutta at users.noreply.github.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHazardLatency.cpp
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp
M llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
A llvm/test/CodeGen/AMDGPU/insert-delay-alu-ldsdma.mir
A llvm/test/CodeGen/AMDGPU/ldsdma-not-coexec-valu.mir
A llvm/test/CodeGen/AMDGPU/ldsdma-not-valu-wait-sgpr.mir
Log Message:
-----------
[AMDGPU] Do not treat LDSDMA as VALU in several passes (#212866)
Use AllowLDSDMA=false (and producer/consumer split in InsertDelayAlu)
where LDSDMA was incorrectly classified as VALU.
Partially addresses https://github.com/llvm/llvm-project/issues/204488
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
Commit: 3199f80203b3981f87a915bc045cc6d43b850cea
https://github.com/llvm/llvm-project/commit/3199f80203b3981f87a915bc045cc6d43b850cea
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
A flang/test/Transforms/debug-line-table-no-types.fir
M flang/test/Transforms/debug-omp-target-op-1.fir
Log Message:
-----------
[flang][debug] Don't build signature types for minimal debug levels. (#221967)
AddDebugInfo converted the result and argument types of every function
before it checked the requested debug level, so -gline-tables-only or a
-gline-directives-only ended up with the full type graph of each
signature: derived types, array types, string types and the basic types
they are built from.
Leave the type list empty at those levels which is also what clang emits
for -gline-tables-only or -gline-directives-only. The subprogram of an
omp.target region gets the same treatment.
A single variable is now used to decide this so parameter for the
`addTargetOpDISP` lambda was removed.
Fixes #217343
Co-authored-by: Cursor <cursoragent at cursor.com>
Commit: af35312797b0be96be7b2f155542911df3693a2b
https://github.com/llvm/llvm-project/commit/af35312797b0be96be7b2f155542911df3693a2b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/MachinePipeliner.cpp
Log Message:
-----------
MachinePipeliner: Fix using getUniqueVRegDef on a physical register (#216793)
Currently this is permissive and doesn't assert when called with
a physical register, but I'm working on changing this edge case.
No current observable change.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: f40474d53bc0e780d7d3653248d5a241d36fe07a
https://github.com/llvm/llvm-project/commit/f40474d53bc0e780d7d3653248d5a241d36fe07a
Author: Ruoyu Qiu <cabbaken at outlook.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/DependenceAnalysis.h
M llvm/lib/Analysis/DependenceAnalysis.cpp
Log Message:
-----------
[DA] Refactor dependence analysis (NFC) (#221653)
Remove some unnecessary part of DA.
- Remove unused `GroupLoops` and `Group` subscript state.
- Reuse the already-computed source and destination loops.
- Simplify `APInt` initialization and zero SCEV construction.
- Replace redundant casts with direct typed accessors.
Commit: 5bf9caeaa485f1720db8cfbe92012710c2fad36c
https://github.com/llvm/llvm-project/commit/5bf9caeaa485f1720db8cfbe92012710c2fad36c
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/docs/CommandGuide/llubi.md
A llvm/test/tools/llubi/alloca_large_size_crash.ll
M llvm/tools/llubi/lib/Context.cpp
M llvm/tools/llubi/llubi.cpp
Log Message:
-----------
[llubi] Limit max-mem to 4 GiB (#221765)
Closes https://github.com/llvm/llvm-project/issues/220952.
Commit: dc49aeb509940d32415ce420a608fc8d4ca3b01e
https://github.com/llvm/llvm-project/commit/dc49aeb509940d32415ce420a608fc8d4ca3b01e
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M flang/lib/Optimizer/OpenACC/Transforms/CMakeLists.txt
Log Message:
-----------
[flang][acc] Add missing dependencies for ACCMapInfoPrep pass (#222028)
To resolve linking failures for:
cuf::hasDataAttr and loadRecordTypeSizeFromTypeDesc
after: https://github.com/llvm/llvm-project/pull/221282
Commit: b12d510875d4d3b56a34bb425757a1b488ba3e4b
https://github.com/llvm/llvm-project/commit/b12d510875d4d3b56a34bb425757a1b488ba3e4b
Author: Akash Manna <akash.manna.mymail at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaChecking.cpp
M clang/test/SemaCXX/warn-implicit-unicode-conversions.cpp
Log Message:
-----------
[Clang] Fix assertion when a Unicode character is splatted to a vector of its own type (#219987)
Fixes #202317
Comparing an `ext_vector_type` of `char32_t` against one of its own
elements (`V.xyzw < V.x`) splats the scalar to the vector type, and
`-Wconversion` checking then trips `Source != Target` in
`DiagnoseMixedUnicodeImplicitConversion`. `CheckImplicitConversion` does
reject `Source == Target` at the top, but only on the outer types; when
it later strips the vector wrapper off the target it ends up with
`char32_t` on both sides and nothing re-checks that. Every other element
check just happened to tolerate identical types silently, the Unicode
one is the first to assert, which is why this only showed up as a Clang
21 regression.
The fix is at the call site rather than in the diagnostic: once the
vector, matrix and SVE wrappers have been stripped, return early if the
element types are the same. That covers matrix splats and HLSL
truncation to the same element type too, not just this one warning, and
leaves the assertion and the warning's behaviour alone. A genuine
mismatch such as `V.xyzw < u8` still warns as before. Added a test with
the reproducer.
LLM tools were used for this contribution. I've reviewed, built, and
tested the change myself before pushing to GitHub.
Commit: 00a81e0a19da74292a84c0b5fcdae85f0646cc02
https://github.com/llvm/llvm-project/commit/00a81e0a19da74292a84c0b5fcdae85f0646cc02
Author: Zhen Wang <zhenw at nvidia.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M flang/include/flang/Optimizer/HLFIR/Passes.td
M flang/include/flang/Tools/CrossToolHelpers.h
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRAssign.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
A flang/test/Lower/CUDA/scalar-to-array-assign-device-O0.cuf
Log Message:
-----------
[flang][cuda] Inline scalar-to-array assignments in CUDA Fortran device code at -O0 (#221333)
At -O0, `arr = 11` lowers to a `_FortranAAssign` call. In device code
the runtime function's callees join the kernel's call graph, so the
device linker reserves a worst-case stack frame for every kernel
reaching it: `65,720` bytes per thread for a kernel with one such
assignment, versus `0` at -O1.
`InlineHLFIRAssign` already runs at -O0 with `onlyScalarRHS` for OpenMP
target device compilations. This extends that carve-out to CUDA Fortran.
Since a CUDA Fortran module holds both host and device code, the
decision is per-operation via `cuf::isCUDADeviceContext`, and host code
keeps the runtime call.
Only scalar-to-array broadcast is covered.
Commit: 443d419e798b37a3733b12db7859c5155407c6d8
https://github.com/llvm/llvm-project/commit/443d419e798b37a3733b12db7859c5155407c6d8
Author: David Spickett <david.spickett at arm.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M lldb/source/Plugins/ObjectFile/COFF/ObjectFileCOFF.cpp
Log Message:
-----------
[lldb] Fix switch case for i386 in COFF GetModuleSpecifications (#222030)
08c94c0ac3b503dd4971da8935001aba01918688 / #188276 accidentally removed
the "case:" for i386.
Commit: b674d2c82401631326305ce0d8e624b448daf8a5
https://github.com/llvm/llvm-project/commit/b674d2c82401631326305ce0d8e624b448daf8a5
Author: Sean Perry <perry at ca.ibm.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/include/clang/Options/Options.td
M clang/lib/Driver/ToolChains/ZOS.cpp
A clang/test/Driver/nodefaultrtlibs.c
Log Message:
-----------
[Driver][Clang] Add -nodefaultrtlibs (#219496)
On z/OS testing compiler-rt does not work with the -nodefaultlibs since
that option remove both the standard libraries like libc and the
compiler-rt library. On other platforms adding an argument like `-lc`
back to the command line in the test scripts works because the path for
libc (eg. `-L<path>`) hadn't been removed. On z/OS, the standard
libraries are located in data sets and you need to specify them by
complete name (eg. `<HLQ>.SCEELIB(CELQS003)`).
This is adding the option `-nodefaultrtlibs` so the compiler-rt tests
can remove just the compiler-rt libs from the link step.
Commit: d34b9a8dbb9e3fe3a894af0ecd381683dd95e693
https://github.com/llvm/llvm-project/commit/d34b9a8dbb9e3fe3a894af0ecd381683dd95e693
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/CodeGen/MachineBasicBlock.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.h
M llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
Log Message:
-----------
[CodeGen] Add const MBB overload to analyzeBranch (#221847)
Commit: 91ee3ddf53d996153f80193b350df013eb068803
https://github.com/llvm/llvm-project/commit/91ee3ddf53d996153f80193b350df013eb068803
Author: vporpo <vasileios.porpodas at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Scheduler.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Scheduler.cpp
Log Message:
-----------
[SandboxVec][Scheduler][NFC] Rename ScheduleTopItOpt to ScheduleFrontier (#220409)
We now have an actual class `SchedulingPoint` for pointing to the top of
schedule, so it is no longer an iteraterator as `ScheduleTopItOpt` would
imply. We also support both bottom-up and top-down directions so "Top"
is no longer a good name.
This patch renames the iterator to ScheduleFrontier.
Commit: f0bcda36c9f50c3bac7fb1b1dd06686166da155b
https://github.com/llvm/llvm-project/commit/f0bcda36c9f50c3bac7fb1b1dd06686166da155b
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
M mlir/test/Dialect/Linalg/elementwise/roundtrip.mlir
M mlir/test/lib/Dialect/Linalg/TestLinalgElementwiseFusion.cpp
Log Message:
-----------
[MLIR][linalg] Handle invalid elementwise kind safely (#221835)
The generic elementwise builder accepts an attribute list. Avoid passing
an uninitialized kind to region construction if a caller omits the
required kind, and reject attributes of the wrong type rather than
relying on an assertion.
Found by Coverity.
Assisted-by: Codex
Commit: 86a649acfded74042e2cec07df4fc2e70a02a74d
https://github.com/llvm/llvm-project/commit/86a649acfded74042e2cec07df4fc2e70a02a74d
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/TilingInterfaceImpl.cpp
Log Message:
-----------
[MLIR][linalg] Share external interface implementations to reduce build time (NFC) (#221814)
The Linalg tiling and partial-reduction external models instantiate
their operation-independent implementations for every registered
structured op. Keep thin operation-specific external models, but inherit
the implementations from non-template bases so the compiler emits and
optimizes them only once.
Assisted-by: Codex
Commit: 4f22c50a5bebe5b76c3d3d45c5db2a5a769727f6
https://github.com/llvm/llvm-project/commit/4f22c50a5bebe5b76c3d3d45c5db2a5a769727f6
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/test/Sema/assign.c
Log Message:
-----------
Add a regression test; NFC (#221981)
There was a request for a regression test in #50193; this was fixed
initially by 9eef4d1c5fa6b1bcbbe675c14ca8301d5d346f7b
Commit: 6dd22919138af830711ed4fb5b792482139b8eb0
https://github.com/llvm/llvm-project/commit/6dd22919138af830711ed4fb5b792482139b8eb0
Author: Domenic Nutile <domenic.nutile at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/test/CodeGen/AMDGPU/dpp_combine.mir
M llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
A llvm/test/CodeGen/AMDGPU/dpp_combine_rev_opcode.ll
A llvm/test/CodeGen/AMDGPU/dpp_combine_rev_opcode.mir
Log Message:
-----------
[AMDGPU] Restrict DPP combine from performing bad transformations when handling certain REV insts that use Src1 as the DPP operand (#216835)
This issue was originally discovered due to a benchmark failure in the
downstream. The REV subtractions have always worked this way, and the
REV shift operands worked this way before GFX11
Commit: 67b8998d404ad633c9ec377598c8c1077b312365
https://github.com/llvm/llvm-project/commit/67b8998d404ad633c9ec377598c8c1077b312365
Author: carlobertolli <carlo.bertolli at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/test/CodeGen/AMDGPU/promote-alloca-proper-value-replacement.ll
Log Message:
-----------
[AMDGPU] Avoid dangling SSAUpdater reference in PromoteAlloca full-vector store (#215686)
promoteAllocaToVector walks alloca users in use-list order across
blocks. A full-vector store forwards its value operand to the
SSAUpdater, and that operand can be a load from the same alloca in a
dominating block. If the store is visited first, the SSAUpdater holds a
raw pointer to the load; the load is later RAUW'd and deleted, leaving a
dangling reference that causes a crash.
Fix by sorting blocks in reverse post-order before visiting them, so a
forwarded load is always replaced before any store hands it to the
SSAUpdater.
Assisted-By: Cursor (Claude)
---------
Co-authored-by: Cursor <cursoragent at cursor.com>
Commit: 793137b8a9f92ad09f08701fd297aead07515a50
https://github.com/llvm/llvm-project/commit/793137b8a9f92ad09f08701fd297aead07515a50
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M mlir/include/mlir/ExecutionEngine/SparseTensor/File.h
M mlir/lib/ExecutionEngine/SparseTensor/File.cpp
A mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_file_rank.mlir
A mlir/test/Integration/data/rank_511.tns
Log Message:
-----------
[mlir][sparse] Reject tensor files with unsupported ranks (#220709)
Commit: 098c15fc1c119807ff61a16441c9903d9faefb0a
https://github.com/llvm/llvm-project/commit/098c15fc1c119807ff61a16441c9903d9faefb0a
Author: Hongyu Chen <xxs_chy at outlook.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/lib/Headers/riscv_packed_simd.h
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
A clang/test/Sema/riscv-pget-index-out-of-range.c
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
Log Message:
-----------
[RISCV][P-ext] Support Packed Element Extract (#221565)
See also
https://github.com/riscv/riscv-p-spec/blob/master/P-ext-intrinsics.adoc#packed-element-extract.
Commit: 16bcb2727f98f366ca9e28b98b83654cdb150b89
https://github.com/llvm/llvm-project/commit/16bcb2727f98f366ca9e28b98b83654cdb150b89
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M mlir/include/mlir/ExecutionEngine/SparseTensor/File.h
A mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_file_coordinates.mlir
A mlir/test/Integration/data/coordinate_above_dimension.tns
A mlir/test/Integration/data/coordinate_narrow.tns
A mlir/test/Integration/data/coordinate_negative.tns
A mlir/test/Integration/data/coordinate_overflow.tns
A mlir/test/Integration/data/coordinate_zero.tns
Log Message:
-----------
[mlir][sparse] Reject invalid tensor coordinates (#220708)
Commit: 6e1cb51ab9dc2de34f8161b27cf24345b4c4ccbb
https://github.com/llvm/llvm-project/commit/6e1cb51ab9dc2de34f8161b27cf24345b4c4ccbb
Author: Szymon Piotr Milczek <szymon.milczek at intel.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
Log Message:
-----------
[GlobalISel] Drop redundant scalable-dest check in G_EXTRACT_SUBVECTOR lowering (NFC) (#221934)
The scalarizing lowering of G_EXTRACT_SUBVECTOR bails out for both a
scalable source and a scalable destination.
According to llvm/docs/GlobalISel/GenericOpcode.md, G_EXTRACT_SUBVECTOR
only supports extracting a fixed vector from a scalable vector, never a
scalable vector from a fixed one.
This means that a fixed source implies a fixed destination, making the
DstTy.isScalable() check redundant.
Remove it. NFC.
Commit: 5d5365323003edd1f1c0fbc1e631ae5a2c49d176
https://github.com/llvm/llvm-project/commit/5d5365323003edd1f1c0fbc1e631ae5a2c49d176
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/include/clang/Options/FlangOptions.td
M flang/docs/ReleaseNotes.md
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/test/Driver/driver-help.f90
M flang/test/Lower/math-lowering/exponentiation.f90
M flang/test/Lower/split-sum-expression-tree-lowering.f90
M flang/tools/bbc/bbc.cpp
Log Message:
-----------
[flang] Enable FP sum reassociation by default (#218746)
Enable Fortran-standard-compliant reassociation within individual REAL
and COMPLEX sum expressions by default at all optimisation levels.
Preserve the explicit positive and negative Flang override flags.
Also enable by default on bbc to match flang.
RFC:
https://discourse.llvm.org/t/rfc-flang-reasssociate-within-real-and-complex-expressions-by-default/91626
Assisted-by: Codex
Commit: 841d4ad6b315ab92c2a37e6484a3b7963b50060c
https://github.com/llvm/llvm-project/commit/841d4ad6b315ab92c2a37e6484a3b7963b50060c
Author: Larry Meadows <Lawrence.Meadows at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/test/OpenMP/amdgcn_target_device_vla.cpp
M clang/test/OpenMP/amdgpu_target_with_aligned_attribute.c
M clang/test/OpenMP/bug60602.cpp
M clang/test/OpenMP/distribute_parallel_for_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_if_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_num_threads_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_private_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_proc_bind_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_if_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_lastprivate_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_num_threads_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_proc_bind_codegen.cpp
M clang/test/OpenMP/nvptx_SPMD_codegen.cpp
M clang/test/OpenMP/nvptx_distribute_parallel_generic_mode_codegen.cpp
M clang/test/OpenMP/nvptx_lambda_capturing.cpp
M clang/test/OpenMP/nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp
M clang/test/OpenMP/nvptx_target_teams_codegen.cpp
M clang/test/OpenMP/nvptx_target_teams_distribute_codegen.cpp
M clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp
M clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_generic_mode_codegen.cpp
M clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp
M clang/test/OpenMP/nvptx_target_teams_generic_loop_codegen.cpp
M clang/test/OpenMP/parallel_if_codegen_PR51349.cpp
M clang/test/OpenMP/reduction_complex.c
M clang/test/OpenMP/reduction_implicit_map.cpp
M clang/test/OpenMP/scope_codegen.cpp
M clang/test/OpenMP/target_codegen_global_capture.cpp
M clang/test/OpenMP/target_default_codegen.cpp
M clang/test/OpenMP/target_dyn_groupprivate_codegen.cpp
M clang/test/OpenMP/target_map_codegen_03.cpp
M clang/test/OpenMP/target_ompx_dyn_cgroup_mem_codegen.cpp
M clang/test/OpenMP/target_parallel_codegen.cpp
M clang/test/OpenMP/target_parallel_for_codegen.cpp
M clang/test/OpenMP/target_parallel_for_reduction_task_codegen.cpp
M clang/test/OpenMP/target_parallel_for_simd_codegen.cpp
M clang/test/OpenMP/target_parallel_for_simd_tl_codegen.cpp
M clang/test/OpenMP/target_parallel_for_tl_codegen.cpp
M clang/test/OpenMP/target_parallel_generic_loop_codegen-1.cpp
M clang/test/OpenMP/target_parallel_generic_loop_codegen-2.cpp
M clang/test/OpenMP/target_parallel_generic_loop_codegen.cpp
M clang/test/OpenMP/target_parallel_generic_loop_tl_codegen.cpp
M clang/test/OpenMP/target_parallel_generic_loop_uses_allocators_codegen.cpp
M clang/test/OpenMP/target_parallel_if_codegen.cpp
M clang/test/OpenMP/target_parallel_num_threads_codegen.cpp
M clang/test/OpenMP/target_parallel_num_threads_strict_codegen.cpp
M clang/test/OpenMP/target_parallel_reduction_task_codegen.cpp
M clang/test/OpenMP/target_parallel_tl_codegen.cpp
M clang/test/OpenMP/target_teams_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_if_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_order_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_proc_bind_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_task_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_openmp52_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_lastprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_proc_bind_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_reduction_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_codegen-1.cpp
M clang/test/OpenMP/target_teams_generic_loop_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_codegen_as_parallel_for.cpp
M clang/test/OpenMP/target_teams_generic_loop_collapse_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_if_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_order_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_reduction_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_uses_allocators_codegen.cpp
M clang/test/OpenMP/target_teams_reduction_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_copyin_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_if_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_lastprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_private_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_proc_bind_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_reduction_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_reduction_task_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_collapse_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_if_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_if_openmp52_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_lastprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_num_threads_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_private_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_proc_bind_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_reduction_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp
M clang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c.generated.all.expected
M clang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c.no-generated.all.expected
A offload/test/offloading/nested_parallel_reduction.c
Log Message:
-----------
[Clang][OpenMP] Don't mark outlined parallel region functions norecurse (#218862)
Clang marks every outlined OpenMP region function `norecurse`, in both
`emitOutlinedFunctionPrologue` and
`emitOutlinedFunctionPrologueAggregate`, and
does the same for the GPU parallel wrapper. For a `parallel` region that
is not
true: the body is reached through the function pointer the runtime is
handed, and
if the body opens another parallel region the runtime's parallel entry
is
re-entered while the first call is still live, so the entry and the body
sit in a
call graph cycle. `rpo-function-attrs` propagates the annotation off the
body and
onto the device runtime's parallel entry once internalization makes it
internal,
and a nested parallel region can then be folded away.
This drops the annotation where the runtime can re-enter the function —
the
parallel bodies and the GPU data sharing wrapper — and keeps it where it
holds by
setting it on the teams and target bodies, which are entered once and
never
handed back to the runtime as a callback. Task bodies never carried it,
as they
are emitted through `GenerateCapturedStmtFunction`.
Where the attribute is true `function-attrs` still infers it, so a
program whose
parallel regions do not nest loses nothing. Splitting one attribute
group into
two renumbers the groups in the combined-construct codegen tests, and
that
accounts for all of the test churn.
The new offload test covers the nested case that motivated this.
Commit: 121656d9360bcfc80c62c72f90cc1a28795b826e
https://github.com/llvm/llvm-project/commit/121656d9360bcfc80c62c72f90cc1a28795b826e
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M flang/test/Fir/OpenACC/acc-declare-gpu-module-insertion.fir
M mlir/lib/Dialect/OpenACC/Transforms/ACCDeclareGPUModuleInsertion.cpp
Log Message:
-----------
[mlir][openacc] Handle compiler generated global for unified mode (#221136)
Treat compiler generated global the same way as other global in unified
mode. This avoid having a host and device copy for runtime information
like type descriptors.
Commit: 888c6dc3c076077973e8998659caf5a8a081bb25
https://github.com/llvm/llvm-project/commit/888c6dc3c076077973e8998659caf5a8a081bb25
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFDeviceGlobal.cpp
M flang/test/Fir/CUDA/cuda-device-global.f90
Log Message:
-----------
[flang][cuda] Add compiler generated global to unified register global (#221135)
Treat compiler generated global the same way as other in unified mode.
Host has the initializer body and the device side is just a declaration.
Commit: 028cdb4b9ec090ef6eadea47a0223f9a3ab5845c
https://github.com/llvm/llvm-project/commit/028cdb4b9ec090ef6eadea47a0223f9a3ab5845c
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M .github/workflows/libcxx-pr-conformance-tests.yaml
M .github/workflows/libcxx-pr-test-tools.yml
Log Message:
-----------
[libcxx] Move premerge jobs to k8s mode runner set (#221395)
This allows setting the container image in the workflow definition which
should vastly simplify maintenance. The issues that we were running into
previously with jobs randomly aborting (and getting marked as passed)
have been fixed with some cluster-side config changes.
Commit: 00d831fd85c0fca31a72dec32ebcd417f007b66c
https://github.com/llvm/llvm-project/commit/00d831fd85c0fca31a72dec32ebcd417f007b66c
Author: Amr Hesham <amr96 at programmer.net>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
Log Message:
-----------
[CIR][NFC] Fix build issue after Inlineasm convergent attr (#222041)
Fix build error after introducing InlineAsm convergent attribute in
https://github.com/llvm/llvm-project/pull/221990
Commit: 97195b284954aac357b9732df2a7a6ed6ca446c9
https://github.com/llvm/llvm-project/commit/97195b284954aac357b9732df2a7a6ed6ca446c9
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Vector/canonicalize.mlir
Log Message:
-----------
[mlir][vector] Extend `ShapeCastCreateMaskFolderTrailingOneDim` (#219494)
Extends `ShapeCastCreateMaskFolderTrailingOneDim` so that it also works
for leading unit dims. For example,
```mlir
%1 = vector.create_mask %c1, %c1, %dim, %c1 : vector<1x1x[4]x1xi1>
%2 = vector.shape_cast %1 : vector<1x1x[4]x1xi1> to vector<[4]x1xi1>
```
is folded as:
```mlir
%0 = vector.create_mask %c1, %dim : vector<[4]xi1>
```
To better reflect the extended functionality, the updated pattern is
renamed as:
* `ShapeCastCreateMaskFolderBoundaryUnitDim`.
It takes a template parameter to specify whether to consider
the leading or the trailing unit dims.
Commit: 14e941a0566ae06e982c5d8ddd085697c48fd413
https://github.com/llvm/llvm-project/commit/14e941a0566ae06e982c5d8ddd085697c48fd413
Author: Amit Tiwari <Amit.Tiwari at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M openmp/libompd/gdb-plugin/CMakeLists.txt
M openmp/libompd/gdb-plugin/ompd/ompd.py
M openmp/libompd/gdb-plugin/ompdAPITests.c
A openmp/libompd/gdb-plugin/ompdDLService.c
A openmp/libompd/gdb-plugin/ompdDLService.h
M openmp/libompd/gdb-plugin/ompdModule.c
M openmp/libompd/test/lit.cfg
A openmp/libompd/test/ompd_dl_service.c
Log Message:
-----------
[OpenMP][OMPD] Add symbol lookup helper for GDB plugin (#221956)
On LLVM today, `libompd.so` exists with `dlopen`, finds each API with
`dlsym` and checks error with `dlerror`.
**Missing piece**: There is no single place that:
load this library
look up this name
give me a real error string
**Issues**:
A later change would have to edit 30+ calls sites,
`dlerror()` is easy to misuse,
failures often drop the OS error string.
**Fix**: Add these helpers:
`ompd_load_library(path)` – load `libompd.so`
`ompd_get_symbol(name)` – look up one function
`ompd_get_dl_error()` – last error text or NULL
The plugin still uses `dlopen/dlsym` inside that helper. No LLVM
Support. No `setup.py`.
Commit: ae78759605ffc4b1b58727acb023e47cfb4157e2
https://github.com/llvm/llvm-project/commit/ae78759605ffc4b1b58727acb023e47cfb4157e2
Author: David Green <david.green at arm.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/arm64-xaluo.ll
M llvm/test/CodeGen/AArch64/i128-math.ll
M llvm/test/CodeGen/AArch64/i256-math.ll
M llvm/test/CodeGen/AArch64/mul-i128-overflow.ll
A llvm/test/CodeGen/AArch64/overflow-vec.ll
M llvm/test/CodeGen/AArch64/overflow.ll
M llvm/test/CodeGen/AArch64/pr55644.ll
Log Message:
-----------
[AArch64][GlobalISel] Update and extend the test coverage for overflow intrinsics. NFC (#222059)
Commit: df595667da70f2c90fe6bf2942d7d3939a41322e
https://github.com/llvm/llvm-project/commit/df595667da70f2c90fe6bf2942d7d3939a41322e
Author: Baranov Victor <bar.victor.2002 at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp
M clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.h
M clang-tools-extra/docs/ReleaseNotes.md
M clang-tools-extra/docs/clang-tidy/checks/readability/identifier-naming.rst
A clang-tools-extra/test/clang-tidy/checkers/readability/identifier-naming-allow-trailing-underscore.cpp
Log Message:
-----------
[clang-tidy] Add TrailingUnderscore option for naming-check (#221452)
Fixes https://github.com/llvm/llvm-project/issues/154756.
Commit: a22313e92ef003a70c1c54dac82ccf1f5ade2e2f
https://github.com/llvm/llvm-project/commit/a22313e92ef003a70c1c54dac82ccf1f5ade2e2f
Author: Valery Pykhtin <valery.pykhtin at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/test/MC/AMDGPU/gfx1250_asm_vopd_errs.s
M llvm/test/MC/AMDGPU/misaligned-vgpr-tuples-err.s
Log Message:
-----------
[AMDGPU] Add AsmParser tests for misaligned VGPR tuples in custom-predicate operands (#221986)
MFMA VGPR sources, DP-ALU DPP, v_pk_mov_b32 and VOPD3 f64 take VGPR tuple
operands validated by custom AsmParser predicates. Odd-aligned tuples are
currently only caught late by validateVGPRAlign, so the error points at the
whole instruction (column 1). A follow-up moves the diagnostic to the
offending operand.
Commit: 3e3965fa48ce7f8945202a8cd9ba7ea37faba0b6
https://github.com/llvm/llvm-project/commit/3e3965fa48ce7f8945202a8cd9ba7ea37faba0b6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/CommandFlags.h
M llvm/include/llvm/Target/Target.td
M llvm/include/llvm/Target/TargetOptions.h
M llvm/lib/CodeGen/CommandFlags.cpp
M llvm/lib/CodeGen/TargetOptionsImpl.cpp
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMInstrVFP.td
M llvm/test/CodeGen/ARM/build-attributes.ll
A llvm/test/CodeGen/ARM/eabi-attribute-fp-rounding-strictfp.ll
M llvm/test/CodeGen/ARM/fnmul.ll
Log Message:
-----------
CodeGen: Remove TargetOptions::HonorSignDependentRoundingFPMathOption (#222027)
This option was only settable through the hidden -enable-sign-dependent-
rounding-fp-math flag and was never set by the in-tree frontends. Its
documentation describes honoring a dynamically-changeable rounding mode,
which is what strictfp is for; this relic predates any design for FP
mode controls.
Replace the one ARM consumer with strictfp checks, and remove the
predicate from the patterns which checked it. There were also no tests
for the pattern, so add those.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 1ca6698be7708121f987d0acf896c7dc4cf63a51
https://github.com/llvm/llvm-project/commit/1ca6698be7708121f987d0acf896c7dc4cf63a51
Author: Nerixyz <nerixdev at outlook.de>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M lldb/include/lldb/API/SBFile.h
M lldb/source/API/SBFile.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/PythonDataObjects.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/PythonDataObjects.h
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
M lldb/tools/lldb-dap/DAP.cpp
Log Message:
-----------
[lldb][Windows] Translate file descriptors between CRT instances (#217126)
The official LLVM and lldb builds use `LLVM_ENABLE_RPMALLOC`. This
changes the default CRT allocator to rpmalloc for performance reasons.
In doing so, it also changes the CRT linkage from dynamic (`/MD`) to
static (`/MT`).
Since the CRT is the one managing file descriptors on Windows, its
universe is now scoped to a module. For lldb, this means we have three
fd-spaces: the driver (lldb/lldb-dap), liblldb, and Python.
We usually pass files around as file descriptors. This breaks when we do
it between modules.
Fortunately, the C runtime provides us with helpers to translate between
the process scoped HANDLEs and file descriptors. This way, we can
allocate an fd for a handle passed across modules. For Python, there's
the [`msvcrt`](https://docs.python.org/3/library/msvcrt.html) library we
can use to translate.
Fixes #216679.
Commit: f6c89fda0ae3a08b83a19f7b67aaad3aff027b0a
https://github.com/llvm/llvm-project/commit/f6c89fda0ae3a08b83a19f7b67aaad3aff027b0a
Author: Eli Friedman <efriedma at qti.qualcomm.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/include/llvm/IR/Instruction.h
M llvm/include/llvm/IR/Value.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
Log Message:
-----------
Add Instruction::user_iterator. (#220391)
Users of an Instruction have a special property: they're guaranteed to
be Instructions themselves. Add a specialized iterator to take advantage
of this property.
See the change to IVDescriptors.cpp for an example of how this
simplifies code.
Commit: 9301f0b17193ff139f77c6ed69e4b9793b584bb3
https://github.com/llvm/llvm-project/commit/9301f0b17193ff139f77c6ed69e4b9793b584bb3
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/AArch64/hor-fp-reduction-instcount.ll
Log Message:
-----------
[SLP][NFC]Add a test with non-profitable vectorization, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/222080
Commit: e85a62955715c5ff38b685303379313ac81a0bbf
https://github.com/llvm/llvm-project/commit/e85a62955715c5ff38b685303379313ac81a0bbf
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/include/clang/CIR/Interfaces/CIROpInterfaces.td
Log Message:
-----------
[NFCI][CIR] Add in 2 missing returns- (#222061)
I discovered these two were missing thanks to a warning diagnostic on a
downstream. It isn't clear why this doesn't cause problems anywhere (we
must just not really use these?), but fix it anyway.
Commit: b290e9efa6b991bb61887de29924a3c979de0376
https://github.com/llvm/llvm-project/commit/b290e9efa6b991bb61887de29924a3c979de0376
Author: Larry Meadows <Lawrence.Meadows at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
M llvm/lib/Transforms/IPO/OpenMPOpt.cpp
A llvm/test/Transforms/OpenMP/callback_parallel_regions.ll
A offload/test/offloading/fortran/target-teams-distribute-nested-parallel-do.f90
Log Message:
-----------
[OpenMPOpt] Look inside the callbacks the loop runtime functions are handed (#221449)
The `__kmpc_{distribute_,for_,distribute_for_}static_loop_*` functions
take the
loop body as a callback, so a parallel region written inside that body
is
reachable from the kernel only through the runtime call. `AAKernelInfo`
could not
see it: it recorded an unknown reaching region, and every kernel using
those
functions got a worker state machine whose only option was an indirect
call to
whatever it was handed.
Describe each function's callback argument in `OMPKinds.def`, attach
`!callback`
metadata, and fold the callback's `AAKernelInfo` state into the
caller's, so the
state machine can dispatch directly to the regions the body reaches. The
two
"more than one callee means give up" checks are relaxed for functions
carrying
`!callback`, since that edge is analyzable by construction; the
conservative
unknown-region record is kept for the case that motivated it, a callback
we only
see a declaration of.
These calls still block SPMD-ization, and the `TODO` saying they need
not is
replaced with the obstacles that actually remain. A plain `distribute`
spreads
iterations over teams, so the runtime runs it with TId 0 and a team size
of one;
SPMD-izing has every thread run its block's whole share. The
thread-indexed
families are stopped by the transform rather than the analysis: guarding
puts
single-threaded code behind a block-wide barrier, and a barrier inside a
body
only some threads run is divergent.
Ported from AMD's ROCm fork, `8176194f36b9`, which also used the
analysis to
SPMD-ize these kernels; that part is left out because it is disabled by
default
downstream after regressing applications.
Tested on gfx90a: `llvm/test/Transforms/{OpenMP,Attributor}` 260 passed,
1
unsupported. `offload/test/amdgpu-amd-amdhsa` 516 passed, including the
new
Fortran reproducer. No kernel in the AOMP smoke and smoke-fort suites
changes
execution mode.
Commit: 824137c10506050554cf15ef30e02ece7f0a9c75
https://github.com/llvm/llvm-project/commit/824137c10506050554cf15ef30e02ece7f0a9c75
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/CUDA/CUFLaunchAttachAttr.cpp
Log Message:
-----------
[flang][cuda][NFC] Switch to a simple walk for CUFLaunchAttachAttr pass (#222073)
CUFLaunchAttachAttr only sets cuf.proc_attr on outlined CUF kernel
launches (names containing _cufk_). It did that with
applyPartialConversion on the whole module, so the conversion driver
walked host and GPU IR to touch a handful of ops.
Walk gpu.launch_func instead and apply the same filter. I
Commit: 866a738a0357106ce668543eeeb8314c0a0efeed
https://github.com/llvm/llvm-project/commit/866a738a0357106ce668543eeeb8314c0a0efeed
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
A llvm/test/CodeGen/AMDGPU/early-lis-two-address-regsequence-undef.mir
Log Message:
-----------
TwoAddressInstruction: Don't repair the unchanged def of a degenerate REG_SEQUENCE (#222053)
When every source operand of a REG_SEQUENCE is undef,
eliminateRegSequence rewrites the instruction in place to IMPLICIT_DEF.
The dead def of DstReg is left untouched, so its live range is already correct.
Passing DstReg to repairIntervalsInRange then makes it re-add an overlapping
segment with a fresh value for the unchanged def, asserting in
LiveInterval::addSegment. Drop DstReg from the repaired set in this case.
Exposed by -early-live-intervals
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: 37cc0cae36a5d2231f331b7180c0a141c1b91cac
https://github.com/llvm/llvm-project/commit/37cc0cae36a5d2231f331b7180c0a141c1b91cac
Author: Mircea Trofin <mtrofin at google.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/IR/Constants.cpp
M llvm/unittests/IR/ConstantsTest.cpp
Log Message:
-----------
Reapply "[IR] `replaceUsesWith` when aliasing a GV and the use is `dso_local_equivalent`" (#220450) (#222036)
This reverts commit 751ed7b16433d2279286d0765f51cd36edc6d771.
The patch is quite indepdendent from PR #203171, which uncovered the
issue. We decouple them. The fix is tested in the unittest introduced
here. When we reland #203171, we'll add the cfi_dso_local_equivalent.ll
test.
Commit: ebd4778190106a84a583db8310054ff8b09dccf4
https://github.com/llvm/llvm-project/commit/ebd4778190106a84a583db8310054ff8b09dccf4
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
[ProfCheck] Exclude new OpenMP test (#222090)
Introduced in #221449. We haven't gotten around to fixing OpenMP yet, so
exclude it for now.
Commit: 5caed2fb0161f35e15cfdaa392dfb046cd037750
https://github.com/llvm/llvm-project/commit/5caed2fb0161f35e15cfdaa392dfb046cd037750
Author: Michael Jones <michaelrj at google.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/unistd.yaml
M libc/src/unistd/CMakeLists.txt
A libc/src/unistd/execl.h
M libc/src/unistd/linux/CMakeLists.txt
A libc/src/unistd/linux/execl.cpp
M libc/src/unistd/linux/execle.cpp
M libc/test/integration/src/unistd/CMakeLists.txt
A libc/test/integration/src/unistd/execl_test.cpp
A libc/test/integration/src/unistd/execl_test_normal_exit.cpp
Log Message:
-----------
[libc] Implement execl (#220326)
Basically the same as execle, but passes the global env pointer. POSIX
standard here:
https://pubs.opengroup.org/onlinepubs/9799919799/functions/exec.html
Assisted-by: Automated tooling, human reviewed
Commit: 9f51fa4e9ead0da931c1f7b5d2aa3fdbc62c845e
https://github.com/llvm/llvm-project/commit/9f51fa4e9ead0da931c1f7b5d2aa3fdbc62c845e
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M .github/workflows/release-binaries.yml
Log Message:
-----------
workflows/release-binaries: Fix zstd compression (#219587)
23.1.0 was the first e2e release with zstd archives. I noticed that once
it shipped they didn't have a meaningful size improvement over the
pre-existing archives. Turns out this is because by default zstd
compresses over a 128MB window which wasn't large enough to get
meaningful savings. We now use 1GB for this which uses more memory but
should take the archive from the 1.8GB that the xz release is, to ~1gb.
I played around with a few options and this was the best time vs
compress vs memory usage ratio.
Assisted-By: codex
Commit: 49d09aaac230988c61fa700c7ace90e4e2376c51
https://github.com/llvm/llvm-project/commit/49d09aaac230988c61fa700c7ace90e4e2376c51
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
[SelectionDAG][NFC] Move EmitStackConvert from LegalizeDAG to SelectionDAG (#221357)
I've ran into multiple instances, include #221358 , where I need to
effectively "bitcast" an integer value to a floating point value with
different width (and vice versa). To my best understandings storing into
stack and loading back is the only feasible way. LegalizeDAG already has
this routine, so I thought it might be a good idea to extract it out and
put inside SelectionDAG.
NFC.
Commit: 1a4e4cbd2317320e5432664bbd709feb03bb1067
https://github.com/llvm/llvm-project/commit/1a4e4cbd2317320e5432664bbd709feb03bb1067
Author: jinge90 <ge.jin at intel.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/runtimes/CMakeLists.txt
Log Message:
-----------
[compiler-rt] Add llvm-link deps when building compiler-rt builtins for spirv64 targets (#221906)
https://github.com/llvm/llvm-project/pull/214149 uses llvm-link to
create libclang_rt.builtins.bc from static archive library. It is better
to follow libclc approach to add llvm-link dependency for
builtin-spirv64* in llvm runtime CMakeLists.txt.
Signed-off-by: jinge90 <ge.jin at intel.com>
Commit: 3ba57d142cc3b70ee49798d47d5da9fd99b482dd
https://github.com/llvm/llvm-project/commit/3ba57d142cc3b70ee49798d47d5da9fd99b482dd
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/header-induction-start-bounds.ll
M llvm/test/Transforms/ConstraintElimination/induction-condition-in-loop-exit-postinc.ll
M llvm/test/Transforms/PhaseOrdering/constraint-eliminiation-interactions.ll
Log Message:
-----------
[ConstraintElim] Support IV increments via [u|s]add.with.overflow. (#221771)
Treat [u|s]add.with.overflow like plain add when looking for increment
of an IV. We do not retrieve any wrap flags from the IR in that case, and
leave it to SCEV to determine them as needed.
This did not show any improvements on the workloads in
llvm-opt-benchmark-nightly, but helps to remove runtime checks for Swift
code end-to-end (see newly added PhaseOrdering test).
Alive2 Proof: https://alive2.llvm.org/ce/z/o2vMyw
PR: https://github.com/llvm/llvm-project/pull/221771
Commit: 30cfec3b4e6fc18c46d253028c52ee7bacaaf860
https://github.com/llvm/llvm-project/commit/30cfec3b4e6fc18c46d253028c52ee7bacaaf860
Author: David Green <david.green at arm.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll
M llvm/test/CodeGen/AArch64/arm64-popcnt.ll
Log Message:
-----------
[AArch64] Regenerate and update arm64-big-endian-bitconverts.ll. NFC (#222107)
Commit: 37dd96fedb5973485b37d03ec7a1fdbf6d1e6dbc
https://github.com/llvm/llvm-project/commit/37dd96fedb5973485b37d03ec7a1fdbf6d1e6dbc
Author: Larry Meadows <Lawrence.Meadows at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
A llvm/test/Transforms/Attributor/indirect_call_program_address_space.ll
Log Message:
-----------
[Attributor] Compare an indirect call's callee in the program address space (#222097)
Specializing an indirect call emits, for each candidate callee, an
`icmp` between
the call's callee operand and the candidate. The operand was first
normalized to
address space 0, but the candidates are functions, and functions live in
the
target's program address space. Where that is not 0 the two sides of the
comparison had different types and the `icmp` asserted:
```
Instructions.h:1266: void llvm::ICmpInst::AssertOK(): Assertion
`getOperand(0)->getType() == getOperand(1)->getType() &&
"Both operands to ICmp instruction are not of the same type!"' failed.
```
Normalize to the program address space instead. It is 0 unless a target
says
otherwise, so nothing changes for those; for `spirv64`, whose data
layout sets
`P9`, it is the difference between comparing a `ptr` with a `ptr
addrspace(9)`
and comparing two `ptr addrspace(9)`.
This was found on the `intel-sycl-gpu` builder, which crashed compiling
`offload/test/offloading/nested_parallel_reduction.c` for
`spirv64-intel` once
841d4ad6b315 let that call site reach the specialization path: before,
it took
the single-callee promotion path, which emits no comparison. The bug it
reached
is older than that commit and is not specific to OpenMP, so the test
added here
is a plain Attributor one that needs only a data layout with a non-zero
program
address space.
Commit: 6a77c9113211f81804455102823b996e01283ffc
https://github.com/llvm/llvm-project/commit/6a77c9113211f81804455102823b996e01283ffc
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/scalar-steps-cost.ll
Log Message:
-----------
[VPlan] Don't cost scalar IV steps if the vector body runs at most once. (#221974)
If the vector loop executes exactly once, each scalar IV step folds to a
constant, and there's nothing to cost.
Similarly to BranchOnCount and VPRegionBlock::cost, treat
VPScalarIVSteps as free in that case.
This fixes a slight inaccuracy introduced when moving to computing
VPScalarIVSteps costs in VPlan directly.
PR: https://github.com/llvm/llvm-project/pull/221974
Commit: 4afa58e64810be046a9427d3cf7827a0dc2c235c
https://github.com/llvm/llvm-project/commit/4afa58e64810be046a9427d3cf7827a0dc2c235c
Author: Yao Qi <yao_qi at apple.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M lldb/source/Utility/ArchSpec.cpp
M lldb/unittests/Utility/ArchSpecTest.cpp
Log Message:
-----------
[lldb] Fix infinite recursion in ArchSpec's core matching (#221899)
`target create` never returns for a little-endian 32-bit MIPS ELF file,
on any host whose platform advertises `armv7m`/`armv7em` compatibility.
On Darwin that is every platform, since
`PlatformDarwin::GetCompatibleArchs()`
lists both for every arm64/arm64e host and falls through to that same
list
for any other host core. It is found by `lldb-target-fuzzer`.
Reproduce with a 52-byte ELF32 header (`ELFCLASS32`, `ELFDATA2LSB`,
`e_machine = EM_MIPS`, `e_flags = EF_MIPS_ARCH_32`, everything else
zero),
saved as `mips32el.elf`:
```
(lldb) target create mips32el.elf
```
This never returns. Attaching a debugger to the hung process shows the
same three frames looping forever, with the call stack never growing:
```
frame #1: cores_match(core1=eCore_arm_armv7m, core2=eCore_mips32el, try_inverse=false, ...) at ArchSpec.cpp:1575 [inlined]
frame #2: ArchSpec::IsMatch(rhs=..., match=CompatibleMatch) at ArchSpec.cpp:1449
frame #3: Platform::IsCompatibleArchitecture(...) at Platform.cpp:1193
```
`cores_match()` checks `core1` against `core2`. When nothing matches and
the caller did not ask for an exact match, it sets `try_inverse` and
retries once with the two cores swapped. It retries because the rule
tables are not symmetric: a core lists only what it accepts, not
everything
that accepts it.
Every case that reaches this fallback must leave `try_inverse` false on
the
way out, so the swap happens at most once. Three cases,
`eCore_arm_armv7em`, `eCore_arm_armv7m`, and `eCore_mips32el`, instead
set
it back to true unconditionally. When both sides of a comparison are one
of these three, the swapped call re-arms `try_inverse`, and the tail
call
back into `cores_match()` recurses forever.
This is a tail call, so an optimizing compiler turns the recursion into
a
loop instead of a growing stack. That is why the process spins instead
of
crashing with a stack overflow.
The three cases cannot simply leave `try_inverse` false like their
siblings. `ArchSpec("mipsel").IsCompatibleMatch(ArchSpec("mips64el"))`
is
true today only because of this same swap: `eCore_mips32el`'s own rule
says
nothing about 64-bit MIPS, but `eCore_mips64el`'s rule accepts any
32-bit
MIPS core with the same endianness, and only the inverted comparison
reaches that rule.
Instead, split the switch into a one-directional helper that never
recurses, and try both directions from a plain, non-recursive wrapper:
```
cores_match(A, B) := cores_match_one_direction(A, B) ||
cores_match_one_direction(B, A)
```
This keeps every existing one-directional rule exactly as it was,
including
the mips32el/mips64el rule above, and makes a second retry impossible no
matter what any case does.
Adds two regression tests to ArchSpecTest.cpp. One asserts that the
previously-hanging pairs now return false right away. The other locks in
the two relationships that depend on checking both directions, so a
future
change cannot bring the recursion back by "fixing" the three cases the
naive way.
Assisted-by: claude
Commit: 220294cbf949a487daed4739701d82dfee4054f3
https://github.com/llvm/llvm-project/commit/220294cbf949a487daed4739701d82dfee4054f3
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Remove VPWidenInductionRecipe::getStartValue (NFC). (#222015)
It now shadows VPHeaderPHIRecipe::getStartValue, which returns the same
VPValue and, as the base class accessor, also has a non-const overload.
Narrowing the return type to VPIRValue * was its only purpose.
Commit: ede01decbcb34bd2f04b9102ab96664cc6d5aa4b
https://github.com/llvm/llvm-project/commit/ede01decbcb34bd2f04b9102ab96664cc6d5aa4b
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M libc/lib/CMakeLists.txt
Log Message:
-----------
[libc] Generate a stub for libdl.a (#222098)
Avoid link errors when build rules explicitly add `-ldl` to the linker
invocation -
create an empty `libdl.a` static archive on Linux. It's necessary, for
example,
to build Clang (https://github.com/llvm/llvm-project/issues/97191)
Follow the approach from f88e9de37a52abf9b269a7232bf4d4028bc4ace8
which added a similar stub for `libpthread.a`. Like pthread, dynamic
loader
functions (although they are mostly unimplemented in LLVM-libc as of
today)
are residing in the main `libc.a` archive instead.
Commit: f91b6a0319fd900cb6e665fc8f8dcc5c1a801e4c
https://github.com/llvm/llvm-project/commit/f91b6a0319fd900cb6e665fc8f8dcc5c1a801e4c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
A llvm/test/CodeGen/PowerPC/vsx-swap-removal-undef.mir
Log Message:
-----------
PowerPC: Fix VSX swap removal crash on an undef register (#216714)
formWebs walks each vector-register use and unions its equivalence class
with that of its defining instruction, which it requires to be present
in the swap map. A use of an undef register has no defining instruction, so
the web formation crashed. Treat it like a physical-register mention so the
web is conservatively rejected.
Found by AI while working on something else.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Commit: 7024b9e1b423b3c3c6ac76ab6a73cb2c9e4ef842
https://github.com/llvm/llvm-project/commit/7024b9e1b423b3c3c6ac76ab6a73cb2c9e4ef842
Author: Amr Hesham <amr96 at programmer.net>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/test/CIR/CodeGen/vector-strict-fp.cpp
Log Message:
-----------
[CIR] Support fp strict for vector logical and, or ops (#221808)
Support fp strict for vector logical `cir.or` and `cir.and` ops
Commit: de2a0dd540f714f5e5ae2d3017fe22e2aa6de002
https://github.com/llvm/llvm-project/commit/de2a0dd540f714f5e5ae2d3017fe22e2aa6de002
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/CodeGen/BUILD.gn
A llvm/utils/gn/secondary/clang/lib/CodeGenUtils/BUILD.gn
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/CodeGen/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/Orc/BUILD.gn
Log Message:
-----------
[gn build] Port commits (#222125)
9853cb54d9d2
b182b415d9b2
b90c062f3f03
e91092685eab
4c986c23921d
Commit: 43e82f2b4570c9f5be05ae7113260775bd8773a4
https://github.com/llvm/llvm-project/commit/43e82f2b4570c9f5be05ae7113260775bd8773a4
Author: Alex Langford <alangford at apple.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M lldb/source/Commands/CommandObjectType.cpp
Log Message:
-----------
[lldb] Remove ConstString from CommandObjectType interfaces (#218811)
CommandObjectType was creating ConstStrings type names, function names,
etc. before they needed to be. I'd like to remove ConstString from the
DataFormatter code entirely, so pushing the creation down as far as
possible first is a good first step.
The only remaining use (outside of function arguments) is
ScriptAddOptions. I need to understand it more before I can really
remove it.
Commit: 733c1ec3a313db0e1b5162ff3b2b4438de6cc45c
https://github.com/llvm/llvm-project/commit/733c1ec3a313db0e1b5162ff3b2b4438de6cc45c
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M libc/src/__support/CMakeLists.txt
A libc/src/__support/pwd/CMakeLists.txt
A libc/src/__support/pwd/field_tokenizer.h
A libc/src/__support/pwd/flat_file_db.h
M libc/src/pwd/CMakeLists.txt
R libc/src/pwd/field_tokenizer.h
R libc/src/pwd/flat_file_db.h
M libc/src/pwd/pwd_utils.cpp
M libc/src/pwd/pwd_utils.h
M libc/test/src/__support/CMakeLists.txt
A libc/test/src/__support/pwd/CMakeLists.txt
A libc/test/src/__support/pwd/field_tokenizer_test.cpp
A libc/test/src/__support/pwd/flat_file_db_test.cpp
M libc/test/src/pwd/CMakeLists.txt
R libc/test/src/pwd/field_tokenizer_test.cpp
R libc/test/src/pwd/flat_file_db_test.cpp
Log Message:
-----------
[libc][NFC] Move flat-file database to src/__support/pwd (#221778)
Move FieldTokenizer and FlatFileDatabase from libc/src/pwd to
libc/src/__support/pwd so they can be reused across subsystems (such as
grp) without cross-directory dependencies.
* Move headers to libc/src/__support/pwd/
* Move unit tests to libc/test/src/__support/pwd/
* Update include paths and CMake dependencies in libc/src/pwd/
Assisted-by: Automated tooling, human reviewed.
Commit: d4816e76ca0d005880fa9b581232f0b905a85bb0
https://github.com/llvm/llvm-project/commit/d4816e76ca0d005880fa9b581232f0b905a85bb0
Author: Mattéo Rizza Murgier <matteo.rizza-murgier at sipearl.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M flang/lib/Semantics/check-data.cpp
A flang/test/Semantics/data27.f90
Log Message:
-----------
[flang] Fix crash with legacy DATA initializer for an invalid declaration (#221170)
For legacy DATA /initialization/, declarations weren't checked for
errors before construction, resulting in an assert crash. This PR fixes
this by adding a check.
Fixes #220846
Commit: d298cac180f6c68a89458aaf450c9d84af8f56cc
https://github.com/llvm/llvm-project/commit/d298cac180f6c68a89458aaf450c9d84af8f56cc
Author: Dave Lee <davelee.com at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/include/llvm/Support/DataExtractor.h
M llvm/lib/Support/DataExtractor.cpp
M llvm/unittests/Support/DataExtractorTest.cpp
Log Message:
-----------
[Support] Add DataExtractor::getSLEB128APSInt (#218801)
Add a APSInt variant of `getSLEB128`, supporting values greater than
int64_t.
The new `getSLEB128APSInt` can support values greater than `INT64_MAX`.
This functionality will be used by LLDB formatter bytecode.
Assisted-by: claude
Commit: 9f5246879112eb81a925e02beb1822a4287e81df
https://github.com/llvm/llvm-project/commit/9f5246879112eb81a925e02beb1822a4287e81df
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/docs/CMakeLists.txt
M clang/include/clang/Basic/DiagnosticDocs.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/test/TableGen/DiagnosticDocs.inc
A clang/test/TableGen/diag-docs-determinism.td
M clang/test/TableGen/emit-diag-docs.td
M clang/utils/TableGen/ClangDiagnosticsEmitter.cpp
Log Message:
-----------
[clang][docs] Generate diagnostics reference as Markdown (#221361)
Generate Clang's diagnostics reference from MyST Markdown rather than
reStructuredText. Update diagnostic-group documentation to use native MyST
roles and references, and have the TableGen emitter produce MyST list tables
for diagnostic alternatives.
The new list-table emission code is more verbose, but it is conceptually
simpler, since it's just tracking nested indentation as it emits table cells.
Here's a sample of the table markdown output:
```
* - {warning}`warning:` {diagtext}`They say`
- :::{list-table}
:widths: auto
* - {diagtext}`good`
* - {diagtext}`bad`
:::
-
- :::{list-table}
:widths: auto
* - {diagtext}`food`
* - {diagtext}`forests`
:::
- {diagtext}`are`
- :::{list-table}
:widths: auto
* - {diagtext}`good`
* - {diagtext}`bad`
:::
- {diagtext}`according to` {placeholder}`D`
```
See clang/test/TableGen/emit-diag-docs.td for examples of how it looks.
Tracking issue: #201242
Assisted-By: Codex & Claude
Commit: 540f5aca4a2cbd88b998e155db5b85a6a95ef024
https://github.com/llvm/llvm-project/commit/540f5aca4a2cbd88b998e155db5b85a6a95ef024
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h
M clang/test/CodeGenHLSL/builtins/select.hlsl
Log Message:
-----------
[HLSL] Fix float type promotion to double of the select intrinsic (#222056)
fixes #222055
A previous pr replaced per vector 2-4 overloads with an all inclusive
vector template overload. These vector overloads needed to be guarded so
that vec1s go down the scalar overload path.
Assisted by Copilot MA-code-1.1-flash
Commit: accc84148aae88d54c11403d04929afaccecf4d6
https://github.com/llvm/llvm-project/commit/accc84148aae88d54c11403d04929afaccecf4d6
Author: Michael Halkenhäuser <MichaelGerald.Halkenhauser at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUReserveWWMRegs.cpp
A llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-reserved-wwm-vgpr.ll
Log Message:
-----------
[AMDGPU] Refresh RegisterClassInfo after reserving WWM registers (#221849)
AMDGPUReserveWWMRegs reserves the VGPRs the WWM allocator picked for SGPR
spill lanes and clears the per-lane VGPR mask, but updates neither
MachineRegisterInfo nor the shared RegisterClassInfo. RegAllocBase
re-freezes the reserved set, but owns its RegisterClassInfo by value, so
only its private copy is refreshed, and a later user of the analysis is
offered an allocation order that still lists the reserved register.
AMDGPURewriteAGPRCopyMFMA became such a user in #216510: its spill slot
elimination assigned that register, which asserts in VirtRegMap and, in a
build without assertions, silently clobbers the spilled SGPRs. #216510 was
reverted in #221749; this is a prerequisite for relanding it.
Update MRI and the analysis at the end of the pass, as SIPreAllocateWWMRegs
already does, after clearPerLaneVGPRAllocMask() since the mask is itself an
input to getReservedRegs().
AI-assisted.
Commit: cc5c51457347547dbac6edcfe9887ca5aeee1b3d
https://github.com/llvm/llvm-project/commit/cc5c51457347547dbac6edcfe9887ca5aeee1b3d
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M lldb/unittests/Protocol/ProtocolMCPServerTest.cpp
M lldb/unittests/TestingSupport/TestUtilities.h
Log Message:
-----------
[lldb] Fix -Wunused-template (#221815)
This warning was enabled by default in clang 23.1.0 (although reverted
for 23.1.1). These fixes still make sense to perform though. Template
definitions in headers should not use static, and others are completely
unused.
Commit: 1f388eaf27616aceced0dd292af066ea8dbcd066
https://github.com/llvm/llvm-project/commit/1f388eaf27616aceced0dd292af066ea8dbcd066
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-drop.ll
Log Message:
-----------
[SLP][NFC]Add a test with missed vectorization, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/222141
Commit: 8fdbba5073a6fe2ae16be0117f8f473eea27dc2a
https://github.com/llvm/llvm-project/commit/8fdbba5073a6fe2ae16be0117f8f473eea27dc2a
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M libc/include/llvm-libc-macros/linux/unistd-macros.h
M libc/include/unistd.yaml
M libc/src/unistd/linux/sysconf.cpp
M libc/test/src/unistd/CMakeLists.txt
M libc/test/src/unistd/sysconf_test.cpp
Log Message:
-----------
[libc][unistd] Support _SC_GET(GR|PW)_R_SIZE_MAX in sysconf. (#222135)
* Add support for POSIX-specified `_SC_GETGR_R_SIZE_MAX` and
`_SC_GETPW_R_SIZE_MAX`
constants used as arguments to `sysconf` function;
* Return -1 for these values - they provide "initial size" for
user-supplied buffers passed to `getgr*` and `getpw*`
functions, but there's no real maximum limit imposed by the LLVM-libc
implementation, and user might provide a
size they can, and rely on `ERANGE` return values if the chosen size
ended up being too small for pwd/group entries.
* Add unit test coverage, and update the unit test to use proxy headers
instead of system-provided `<unistd.h>`.
Also, properly test errno values returned by `sysconf`.
This fixes one of the remaining blockers for building Clang against
LLVM-libc (https://github.com/llvm/llvm-project/issues/97191)
Commit: 915c3497042d7cbbaa01128c0c044e46caae69da
https://github.com/llvm/llvm-project/commit/915c3497042d7cbbaa01128c0c044e46caae69da
Author: Ayokunle Amodu <ayokunle321 at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M .github/new-prs-labeler.yml
Log Message:
-----------
[Github] Match backend:NVPTX files outside llvm/ (#221968)
The backend:NVPTX labeler rules are anchored to the llvm/ subtree (every
glob starts with llvm/**), so NVPTX/NVVM-related files elsewhere in the
tree never get the label. In particular, ClangIR's lowering under clang/
touches NVPTX code but the PR is not tagged backend:NVPTX.
This drops the llvm/ prefix so the patterns match anywhere in the tree.
Commit: c0a6b4bee96cc2c81716c5238c453ca68fee8042
https://github.com/llvm/llvm-project/commit/c0a6b4bee96cc2c81716c5238c453ca68fee8042
Author: 简 <32090825+LittleJianCH at users.noreply.github.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/MachineInstr.cpp
Log Message:
-----------
[CodeGen] Avoid quadratic operand removal in MachineInstr::insert (#220165)
This optimizes MachineInstr::insert by copying trailing operands
first and then removing them from the end. This avoids repeatedly
shifting the remaining operands, reducing the operation from quadratic
to linear time without changing behavior.
Commit: 1936b4a95dadcdeddefce26facb208413a9b3b86
https://github.com/llvm/llvm-project/commit/1936b4a95dadcdeddefce26facb208413a9b3b86
Author: Valery Pykhtin <valery.pykhtin at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
Log Message:
-----------
[AMDGPU] Factor the AsmParser match-specificity comparison into a helper, NFC (#221987)
Extract the "keep the most specific match status" comparison in
matchAndEmitInstruction into an atLeastAsSpecific() lambda ranking
Match_MnemonicFail < Match_InvalidOperand < Match_MissingFeature. No
functional change.
Commit: 15034a76b21551f0e62c7c40f0878e8eeb0deebc
https://github.com/llvm/llvm-project/commit/15034a76b21551f0e62c7c40f0878e8eeb0deebc
Author: Raghu Maddhipatla <raghu.maddhipatla at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/test/Lower/OpenMP/omp-declarative-allocate-align.f90
A flang/test/Lower/OpenMP/omp-declarative-allocate-derived-warning.f90
A flang/test/Lower/OpenMP/omp-declarative-allocate-save-warning.f90
M mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Target/LLVMIR/openmp-allocate-directive.mlir
Log Message:
-----------
[OpenMP] [MLIR] [Flang] Replace all uses of variables in ALLOCATE directive to use new value which is created. (#212361)
Limitation:
Right now, added a TODO warning about lowering of variable with SAVE
attribute or named COMMON block are not completely supported end to end.
So a warning is emitted.
Commit: fa4d413ea4cfd0ab00c4d7b6d3f27087a3fc46bc
https://github.com/llvm/llvm-project/commit/fa4d413ea4cfd0ab00c4d7b6d3f27087a3fc46bc
Author: Jackson Stogel <jtstogel at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[bazel] Port 35fe7e14ec (#222150)
Commit: e94e2be5be17bb3221c622bb3c638f4a1d9cd1c8
https://github.com/llvm/llvm-project/commit/e94e2be5be17bb3221c622bb3c638f4a1d9cd1c8
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
Log Message:
-----------
[VPlan] Collect predecessors/successors up front (NFC) (#222145)
Collect predecessors and successors up front in reassociateBlocks.
Currently NFC, but makes it more robust in the future, because it also
correctly handles self-edges.
Commit: 9a6ba310ff3d2ed4a88352dd164bfd94518e3cff
https://github.com/llvm/llvm-project/commit/9a6ba310ff3d2ed4a88352dd164bfd94518e3cff
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
Log Message:
-----------
[VPlan] Add helper to add incoming values for last predecessor (NFC). (#222149)
Factor logic to helper function, so it can be re-used in follow-up
changes.
Commit: 6d53e28d51d931eaa50f832cac81b3da4afc779d
https://github.com/llvm/llvm-project/commit/6d53e28d51d931eaa50f832cac81b3da4afc779d
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/Affine/TransformOps/AffineTransformOps.td
M mlir/include/mlir/Dialect/Bufferization/TransformOps/BufferizationTransformOps.td
M mlir/include/mlir/Dialect/Func/TransformOps/FuncTransformOps.td
M mlir/include/mlir/Dialect/GPU/TransformOps/GPUTransformOps.td
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgMatchOps.td
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td
M mlir/include/mlir/Dialect/MemRef/TransformOps/MemRefTransformOps.td
M mlir/include/mlir/Dialect/NVGPU/TransformOps/NVGPUTransformOps.td
M mlir/include/mlir/Dialect/SCF/TransformOps/SCFTransformOps.td
M mlir/include/mlir/Dialect/Tensor/TransformOps/TensorTransformOps.td
M mlir/include/mlir/Dialect/Transform/IR/TransformDialect.td
M mlir/include/mlir/Dialect/Transform/IR/TransformOps.td
M mlir/include/mlir/Dialect/Transform/TuneExtension/TuneExtensionOps.td
M mlir/include/mlir/Dialect/Vector/TransformOps/VectorTransformOps.td
M mlir/include/mlir/Dialect/XeGPU/TransformOps/XeGPUTransformOps.td
M mlir/lib/Dialect/MemRef/TransformOps/MemRefTransformOps.cpp
M mlir/test/CAPI/transform_interpreter.c
M mlir/test/Conversion/FuncToLLVM/func-memref-return.mlir
M mlir/test/Conversion/FuncToLLVM/func-to-llvm.mlir
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm-32b.mlir
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
M mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm.mlir
M mlir/test/Dialect/Bufferization/Transforms/transform-ops.mlir
M mlir/test/Dialect/Func/func-transform.mlir
M mlir/test/Dialect/GPU/transform-gpu-failing.mlir
M mlir/test/Dialect/GPU/transform-gpu.mlir
M mlir/test/Dialect/LLVM/lower-to-llvm-transform-symbol-def.mlir
M mlir/test/Dialect/LLVM/transform-e2e.mlir
M mlir/test/Dialect/Linalg/continuous-tiling-full.mlir
M mlir/test/Dialect/Linalg/continuous-tiling-multiway-split.mlir
M mlir/test/Dialect/Linalg/convert-conv2d-to-img2col.mlir
M mlir/test/Dialect/Linalg/hoisting.mlir
M mlir/test/Dialect/Linalg/match-ops-interpreter.mlir
M mlir/test/Dialect/Linalg/match-ops-invalid.mlir
M mlir/test/Dialect/Linalg/matmul-shared-memory-padding.mlir
M mlir/test/Dialect/Linalg/multisize-tiling-full.mlir
M mlir/test/Dialect/Linalg/pad-to-specific-memory-space.mlir
M mlir/test/Dialect/Linalg/promote.mlir
M mlir/test/Dialect/Linalg/promotion_options.mlir
M mlir/test/Dialect/Linalg/td/decompose-pack.mlir
M mlir/test/Dialect/Linalg/td/decompose-unpack.mlir
M mlir/test/Dialect/Linalg/td/propagate-data-layout.mlir
M mlir/test/Dialect/Linalg/td/vectorize-with-patterns.mlir
M mlir/test/Dialect/Linalg/transform-lower-pack.mlir
M mlir/test/Dialect/Linalg/transform-op-bufferize-to-allocation.mlir
M mlir/test/Dialect/Linalg/transform-op-fuse.mlir
M mlir/test/Dialect/Linalg/transform-op-hoist-pad-build-packing-loop-nest.mlir
M mlir/test/Dialect/Linalg/transform-op-hoist-pad.mlir
M mlir/test/Dialect/Linalg/transform-op-multitile-sizes.mlir
M mlir/test/Dialect/Linalg/transform-op-pad-tiling-interface-multiple-of.mlir
M mlir/test/Dialect/Linalg/transform-op-pad-tiling-interface.mlir
M mlir/test/Dialect/Linalg/transform-op-pad.mlir
M mlir/test/Dialect/Linalg/transform-op-rewrite-in-destination-passing-style.mlir
M mlir/test/Dialect/Linalg/transform-op-specialize-matmul.mlir
M mlir/test/Dialect/Linalg/transform-op-split-reduction-by-scaling.mlir
M mlir/test/Dialect/Linalg/transform-op-split-reduction.mlir
M mlir/test/Dialect/Linalg/transform-op-split.mlir
M mlir/test/Dialect/Linalg/transform-op-vectorize.mlir
M mlir/test/Dialect/Linalg/transform-ops-invalid.mlir
M mlir/test/Dialect/Linalg/transform-ops.mlir
M mlir/test/Dialect/Linalg/transform-promotion.mlir
M mlir/test/Dialect/Linalg/transform-tile-and-fuse-pack-unpack.mlir
M mlir/test/Dialect/Linalg/transform-winograd-conv2d.mlir
M mlir/test/Dialect/Linalg/vectorization/contraction-interface.mlir
M mlir/test/Dialect/Linalg/vectorization/convolution-with-patterns-flatten.mlir
M mlir/test/Dialect/Linalg/vectorization/convolution-with-patterns.mlir
M mlir/test/Dialect/Linalg/vectorization/extract.mlir
M mlir/test/Dialect/Linalg/vectorization/insert-slice-with-patterns.mlir
M mlir/test/Dialect/Linalg/vectorization/linalg-ops-with-patterns.mlir
M mlir/test/Dialect/Linalg/vectorization/linalg-ops.mlir
M mlir/test/Dialect/Linalg/vectorization/pad-with-patterns.mlir
M mlir/test/Dialect/Linalg/vectorization/unsupported.mlir
M mlir/test/Dialect/MemRef/make-loop-independent.mlir
A mlir/test/Dialect/MemRef/transform-ops-assembly-invalid.mlir
A mlir/test/Dialect/MemRef/transform-ops-assembly.mlir
M mlir/test/Dialect/MemRef/transform-ops.mlir
M mlir/test/Dialect/NVGPU/transform-create-async-groups.mlir
M mlir/test/Dialect/NVGPU/transform-pipeline-shared.mlir
M mlir/test/Dialect/SCF/transform-op-coalesce.mlir
M mlir/test/Dialect/SCF/transform-ops-invalid.mlir
M mlir/test/Dialect/SCF/transform-ops.mlir
M mlir/test/Dialect/Tensor/fold-empty-op.mlir
M mlir/test/Dialect/Tensor/transform-op-make-loop-independent.mlir
M mlir/test/Dialect/Transform/Library/lower-to-llvm-transform-symbol-def.mlir
M mlir/test/Dialect/Transform/check-use-after-free.mlir
M mlir/test/Dialect/Transform/expensive-checks.mlir
M mlir/test/Dialect/Transform/include/Library/lower-to-llvm.mlir
M mlir/test/Dialect/Transform/interpreter-entry-point-2.mlir
M mlir/test/Dialect/Transform/normal-forms.mlir
M mlir/test/Dialect/Transform/ops-invalid.mlir
M mlir/test/Dialect/Transform/ops.mlir
M mlir/test/Dialect/Transform/selective-targeting.mlir
M mlir/test/Dialect/Transform/test-dialect-injection.mlir
M mlir/test/Dialect/Transform/test-interpreter-printing.mlir
M mlir/test/Dialect/Transform/test-interpreter.mlir
M mlir/test/Dialect/Transform/test-loop-transforms.mlir
M mlir/test/Dialect/Transform/test-pass-application.mlir
M mlir/test/Dialect/Transform/test-pattern-application.mlir
M mlir/test/Dialect/Transform/test-tune-extension.mlir
M mlir/test/Dialect/Vector/transform-op-vector-to-llvm.mlir
M mlir/test/Dialect/Vector/transform-vector.mlir
M mlir/test/Dialect/Vector/vector-transfer-drop-unit-dims-patterns.mlir
M mlir/test/Examples/transform-opt/external-def.mlir
M mlir/test/Examples/transform-opt/self-contained.mlir
M mlir/test/Examples/transform/Ch1/invalidation-2.mlir
M mlir/test/Examples/transform/Ch1/sequence.mlir
M mlir/test/Examples/transform/Ch2/sequence.mlir
M mlir/test/Examples/transform/Ch3/sequence.mlir
M mlir/test/Examples/transform/Ch4/features.mlir
M mlir/test/Examples/transform/ChH/full.mlir
M mlir/test/Integration/Dialect/EmitC/td.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmNeon/matmul-i8.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul-mixed-types.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/pack-unpack-mmt4d.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/pack-scalable-inner-tile.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/pack-unpack-mmt4d.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/td/pack-unpack.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/mmt4d.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/pack-dynamic-inner-tile.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/pack-unpack-mmt4d.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/unpack-dynamic-inner-tile.mlir
M mlir/test/Integration/Dialect/Transform/match_matmul_common.mlir
M mlir/test/Integration/Dialect/Transform/match_reduction.mlir
M mlir/test/Interfaces/TilingInterface/tile-and-fuse-using-interface.mlir
M mlir/test/Transforms/test-block-legalization.mlir
M mlir/test/lib/Dialect/Transform/TestTransformDialectExtension.td
M mlir/test/lib/Interfaces/TilingInterface/TestTilingInterfaceTransformOps.td
M mlir/test/python/dialects/transform.py
M mlir/test/python/dialects/transform_bufferization_ext.py
M mlir/test/python/dialects/transform_extras.py
M mlir/test/python/dialects/transform_interpreter.py
M mlir/test/python/dialects/transform_loop_ext.py
M mlir/test/python/dialects/transform_memref_ext.py
M mlir/test/python/dialects/transform_structured_ext.py
M mlir/test/python/dialects/transform_tensor_ext.py
M mlir/test/python/integration/dialects/transform.py
Log Message:
-----------
[MLIR][Transform] Enable strict property assembly format (#217290)
Enable strict property assembly format mode for the Transform dialect
and its extensions. Bind transform operation options directly in
declarative assembly formats so strict parsing does not rely on fallback
handling.
Update transform dialect, extension, and transform-driven tests to use
the direct property spelling.
Assisted-by: Codex
Commit: 4e12d4bc6b5fc33f0e556f8f282cf97d2843c39b
https://github.com/llvm/llvm-project/commit/4e12d4bc6b5fc33f0e556f8f282cf97d2843c39b
Author: Addmisol <addmisol9 at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/lib/Sema/SemaExpr.cpp
M clang/test/CodeGenOpenCL/address-spaces-conversions.cl
M clang/test/CodeGenOpenCL/size_t.cl
Log Message:
-----------
[Clang][Sema] Promote pointers to common address space in pointer subtraction (#217341)
fixes #216804
## Summary
This PR fixes pointer subtraction between pointers with different but
overlapping address spaces (e.g., `private` and `generic` in
OpenCL).
Previously, when subtracting a private pointer from a generic pointer on
AMDGPU:
- The private pointer (AS5, 32-bit) was converted directly to i32 via
`ptrtoaddr`
- The generic pointer (AS0, 64-bit) was converted to i64 via `ptrtoaddr`
- This resulted in incorrect comparison of 32-bit vs 64-bit values
Now, pointers are first promoted to the composite (superset) address
space using `addrspacecast` before the subtraction. This
mirrors how the conditional operator (`?:`) already handles mixed
address space pointers.
## Test plan
- `clang/test/CodeGenOpenCL/size_t.cl` updated and passes
- Verified generated IR shows correct `addrspacecast` before `ptrtoaddr`
for AMDGCN and SPIR targets
---------
Signed-off-by: addmisol <addmisol9 at gmail.com>
Commit: 19a128ca460284d1274581dd6fedbc6e5f0f1a7d
https://github.com/llvm/llvm-project/commit/19a128ca460284d1274581dd6fedbc6e5f0f1a7d
Author: vporpo <vasileios.porpodas at amd.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Scheduler.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Scheduler.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/SchedulerTest.cpp
Log Message:
-----------
[SandboxVec][Scheduler] Reinsert deferred ready nodes to the ready list (#222054)
Up until now if trySchedule() failed, the ready instructions would be
removed from the ready list for no good reason.
This patch fixes this and reinserts the deferred nodes to the ready
list.
This also helps reduce the scan for ready instructions in trySchedule().
Commit: 644f006fba2b52f0cc0fd58917f2a3ad7d67e6c6
https://github.com/llvm/llvm-project/commit/644f006fba2b52f0cc0fd58917f2a3ad7d67e6c6
Author: Jackson Stogel <jtstogel at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M utils/bazel/MODULE.bazel
M utils/bazel/MODULE.bazel.lock
M utils/bazel/extensions.bzl
A utils/bazel/linux_uapi.bzl
Log Message:
-----------
[libc][bazel] Add a repo with linux kernel UAPI headers (#216867)
This PR exposes a target `@linux_uapi//:linux_uapi_headers` that points
to a local directory configured by the `LINUX_UAPI_INCLUDE_DIR`
environment variable. Linux UAPI headers are required to support libc's
`FULL_BUILD` configuration, which uses `-nostdlibinc` and thus requires
a copy of linux kernel headers.
Commit: b586da6cd57c3e8f4abfc46bc08af52e2f68f25a
https://github.com/llvm/llvm-project/commit/b586da6cd57c3e8f4abfc46bc08af52e2f68f25a
Author: Jackson Stogel <jtstogel at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/libc_build_rules.bzl
M utils/bazel/llvm-project-overlay/libc/libc_configure_options.bzl
Log Message:
-----------
[libc][bazel] Allow building with -DLIBC_FULL_BUILD (#218992)
This PR defines a flag `-- at llvm-project//libc:build_mode` that
configures LLVM-libc to build with full-build flags. This is only
compatible with clang at the moment, since it relies on the
`-nostdlibinc` flag.
This PR contains the logic for LLVM-libc full build in Bazel. A largely
AI generated follow-on PR has `libc/BUILD.bazel` changes for building
libc targets in full-build mode:
https://github.com/llvm/llvm-project/pull/218993.
Commit: 4a78f273acba2f3bc10b683df252b20f5a8198b0
https://github.com/llvm/llvm-project/commit/4a78f273acba2f3bc10b683df252b20f5a8198b0
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/Maintainers.md
M clang/docs/AMDGPUSupport.md
M clang/docs/AddressSanitizer.md
M clang/docs/AllocToken.md
M clang/docs/AutomaticReferenceCounting.md
M clang/docs/Block-ABI-Apple.md
M clang/docs/BlockLanguageSpec.md
M clang/docs/BoundsSafety.md
M clang/docs/BoundsSafetyAdoptionGuide.md
M clang/docs/BoundsSafetyImplPlans.md
M clang/docs/CIR/ABILowering.md
M clang/docs/CIR/CleanupAndEHDesign.md
M clang/docs/CIR/CodeDuplication.md
M clang/docs/CXXTypeAwareAllocators.md
M clang/docs/ClangLinkerWrapper.md
M clang/docs/ClangNVLinkWrapper.md
M clang/docs/ClangOffloadBundler.md
M clang/docs/ClangSYCLLinker.md
M clang/docs/ClangTransformerTutorial.md
M clang/docs/ConstantInterpreter.md
M clang/docs/ControlFlowIntegrity.md
M clang/docs/DataFlowSanitizer.md
M clang/docs/DebuggingCoroutines.md
M clang/docs/DriverInternals.md
M clang/docs/FAQ.md
M clang/docs/FunctionEffectAnalysis.md
M clang/docs/HIPSupport.md
M clang/docs/HLSL/AvailabilityDiagnostics.md
M clang/docs/HLSL/EntryFunctions.md
M clang/docs/HLSL/ExpectedDifferences.md
M clang/docs/HLSL/FunctionCalls.md
M clang/docs/HLSL/HLSLIRReference.md
M clang/docs/HLSL/HLSLSupport.md
M clang/docs/HLSL/ResourceTypes.md
M clang/docs/HardwareAssistedAddressSanitizer.md
M clang/docs/InternalsManual.md
M clang/docs/LLVMExceptionHandlingCodeGen.md
M clang/docs/LanguageExtensions.md
M clang/docs/LeakSanitizer.md
M clang/docs/LibASTImporter.md
M clang/docs/LifetimeSafety.md
M clang/docs/MatrixTypes.md
M clang/docs/MemorySanitizer.md
M clang/docs/MisExpect.md
M clang/docs/Modules.md
M clang/docs/OffloadingDesign.md
M clang/docs/OpenCLSupport.md
M clang/docs/OpenMPSupport.md
M clang/docs/OverflowBehaviorTypes.md
M clang/docs/PCHInternals.md
M clang/docs/PointerAuthentication.md
M clang/docs/RISCVSupport.md
M clang/docs/RealtimeSanitizer.md
M clang/docs/ReleaseNotes.md
M clang/docs/SYCLSupport.md
M clang/docs/SafeBuffers.md
M clang/docs/SafeStack.md
M clang/docs/SanitizerCoverage.md
M clang/docs/SanitizerSpecialCaseList.md
M clang/docs/SanitizerStats.md
M clang/docs/ShadowCallStack.md
M clang/docs/SourceBasedCodeCoverage.md
M clang/docs/StandardCPlusPlusModules.md
M clang/docs/StructureProtection.md
M clang/docs/ThinLTO.md
M clang/docs/Toolchain.md
M clang/docs/TypeSanitizer.md
M clang/docs/UndefinedBehaviorSanitizer.md
M clang/docs/UsersManual.md
M clang/docs/WarningSuppressionMappings.md
M clang/docs/analyzer/checkers.md
M clang/docs/analyzer/developer-docs/DebugChecks.md
M clang/docs/analyzer/user-docs/Annotations.md
M clang/docs/analyzer/user-docs/CrossTranslationUnit.md
M clang/docs/analyzer/user-docs/FAQ.md
M clang/docs/analyzer/user-docs/TaintAnalysisConfiguration.md
M clang/docs/analyzer/user-docs/UsingWithXCode.md
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/BuiltinsAMDGPUDocs.td
M clang/include/clang/Basic/DiagnosticDocs.td
M clang/include/clang/Options/ClangOptionDocs.td
Log Message:
-----------
[docs] Remove TOCs from Clang docs to prepare for Furo migration (#214868)
This is a mechanical change generated by
`utils/docs/remove_page_tocs.py`. In case of conflicts, which are
likely, due to the ongoing markdown migration (#201242), this script can
be re-run to regenerate the change. I'm creating a separate PR for it to
minimize the diff on the functional changes for the furo PR.
Commit: 600241fd49f1d5d5a9aac608da8b2872d23fa082
https://github.com/llvm/llvm-project/commit/600241fd49f1d5d5a9aac608da8b2872d23fa082
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/docs/DataFlowAnalysisIntro.md
M clang/docs/LifetimeSafety.md
M clang/docs/UsersManual.md
A clang/docs/_static/custom.css
M clang/docs/analyzer/conf.py
M clang/docs/conf.py
R libc/docs/_static/copybutton.css
R libc/docs/_static/copybutton.js
M libc/docs/conf.py
R llvm/docs/_static/LLVMWyvernSmall.png
R llvm/docs/_static/copybutton.css
R llvm/docs/_static/copybutton.js
M llvm/docs/conf.py
M utils/docs/llvm_sphinx/__init__.py
A utils/docs/llvm_sphinx/_static/LLVMWyvernSmall.png
A utils/docs/llvm_sphinx/_static/copybutton.css
A utils/docs/llvm_sphinx/_static/copybutton.js
A utils/docs/llvm_sphinx/ext/furo.py
Log Message:
-----------
[clang][docs] Adopt the furo theme used by llvm and libc (#214869)
This change moves the static assets into utils/docs/llvm_sphinx, and
centralizes some of the furo theme logic there.
It then configures furo from clang/docs/conf.py and
clang/analyzer/docs/conf.py.
The temporary preview for the site is here:
https://clangdocs.staging.reidkleckner.dev/after/clang/docs/
The RFC is here:
https://discourse.llvm.org/t/rfc-use-furo-theme-for-clang-docs/91505/7
I plan to wait until at least Aug 13 before merging to gather more
feedback.
Commit: 1977a8b9130e9d0af669feba15d5641f9740ec9d
https://github.com/llvm/llvm-project/commit/1977a8b9130e9d0af669feba15d5641f9740ec9d
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M libc/include/llvm-libc-macros/linux/netdb-macros.h
M libc/include/netdb.yaml
M libc/test/src/netdb/CMakeLists.txt
A libc/test/src/netdb/getaddrinfo_test.cpp
R libc/test/src/netdb/netdb_test.cpp
Log Message:
-----------
[libc][netdb] Add AI_* family of constants. (#221360)
* Provide the values for `AI_*` flags that are passed in `ai_flags`
field of `addrinfo`
structure to `getaddrinfo` calls.
* Reference some of those constant in a placeholder unittest. Rename it
to `getaddrinfo_test`
to clarify its scope (we'll likely be using different test files for
other netdb.h functions).
Commit: b249fd3c6e3dd0e9f9617e57a5cf64fa42d1b486
https://github.com/llvm/llvm-project/commit/b249fd3c6e3dd0e9f9617e57a5cf64fa42d1b486
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M mlir/test/Dialect/Linalg/vectorization/contraction-interface.mlir
M mlir/test/Dialect/Linalg/vectorization/convolution-with-patterns.mlir
Log Message:
-----------
[MLIR][Linalg] Update transform tests for strict properties (#222184)
Update recently added vectorization tests to use the custom assembly
syntax.
Strict Transform dialect properties no longer parse inherent attributes
from the generic attribute dictionary.
These tests landed concurrently with the strict-properties migration.
Assisted-by: Codex
Commit: 66462afa7e4a33f0d720877f2228589d5b43de81
https://github.com/llvm/llvm-project/commit/66462afa7e4a33f0d720877f2228589d5b43de81
Author: David Tellenbach <dtellenbach at apple.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/test/CodeGen/AArch64/cmpbr-early-ifcvt.mir
Log Message:
-----------
[AArch64][CMPBR] Fix splitting of CBB/CBH instructions into ext + cmp (#221112)
We falsely split CBB/CBH instructions by explicitly extending the
second register operand instead of the first one, leading to the
following, wrong codegen:
cbh $wn, $wm, cc, trgt => sxth $wt, $wm
cmp $wn, $wt, cc, sxth
Correct is
cbh $wn, $wm, cc, trgt => sxth $wt, $wn
cmp $wt, $wm, cc, sxth
since cmp with extended register extends it's second, not its first
operand.
Commit: df55ebfbe36ec8c6e19fd5b06f218a56cc6f5e23
https://github.com/llvm/llvm-project/commit/df55ebfbe36ec8c6e19fd5b06f218a56cc6f5e23
Author: jiel-nv <37816794+jiel-nv at users.noreply.github.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/CUDA/CUFPredefinedVarToGPU.cpp
M flang/test/Fir/CUDA/predefined-variables.mlir
Log Message:
-----------
[flang][cuda] Create predefined variable reads at the location of use (#222058)
Commit: 1462d6f99a0cdf8c99108cb32eb020efe6ba5f89
https://github.com/llvm/llvm-project/commit/1462d6f99a0cdf8c99108cb32eb020efe6ba5f89
Author: A. Jiang <de34 at live.cn>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M libcxx/include/__optional/optional.h
M libcxx/include/__optional/optional_ref.h
Log Message:
-----------
[libc++][NFC] Remove `optional::__get` (#217218)
Internal communicating functions `optional::__get` can be superseded by
either `value`, `operator*()`, or direct use of data member. Even though
`value()` is checked, checks are already performed before internal calls
to it, so compilers should be able to remove duplicated checks.
It is intended to use `opt.value()` instead of `*opt` to avoid undesired
argument-dependent lookup.
Commit: 58d0cb5a6e50748b4e577da18b1ce34c3418119b
https://github.com/llvm/llvm-project/commit/58d0cb5a6e50748b4e577da18b1ce34c3418119b
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/include/mlir/Dialect/EmitC/IR/EmitCBase.td
M mlir/test/Dialect/EmitC/canonicalize.mlir
M mlir/test/Dialect/EmitC/form-expressions.mlir
M mlir/test/Dialect/EmitC/invalid_ops.mlir
M mlir/test/Dialect/EmitC/invalid_types.mlir
M mlir/test/Dialect/EmitC/ops.mlir
M mlir/test/Dialect/EmitC/types.mlir
M mlir/test/Target/Cpp/attrs.mlir
M mlir/test/Target/Cpp/call.mlir
M mlir/test/Target/Cpp/common-cpp.mlir
M mlir/test/Target/Cpp/const.mlir
M mlir/test/Target/Cpp/expressions.mlir
M mlir/test/Target/Cpp/invalid.mlir
M mlir/test/Target/Cpp/literal_call_operand.mlir
M mlir/test/Target/Cpp/lvalue.mlir
M mlir/test/Target/Cpp/member.mlir
M mlir/test/Target/Cpp/subscript.mlir
M mlir/test/Target/Cpp/switch.mlir
M mlir/test/Target/Cpp/types.mlir
M mlir/test/Target/Cpp/variable.mlir
M mlir/test/Target/Cpp/verbatim.mlir
M mlir/test/Transforms/sccp.mlir
Log Message:
-----------
[MLIR][EmitC] Enable strict property assembly format (#217271)
Enable strict property assembly format mode for the EmitC dialect. Spell
call metadata directly in the affected declarative assembly formats and
drop unneeded property dictionaries from formats that already cover
their inherent attributes.
Refresh EmitC tests and related C++ target checks so call properties use
direct syntax while ordinary attributes remain in attr-dict.
Assisted-by: Codex
Commit: 68622e02c9e51d8202a82aca96421662a06eaa18
https://github.com/llvm/llvm-project/commit/68622e02c9e51d8202a82aca96421662a06eaa18
Author: Douglas Yung <douglas.yung at sony.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M compiler-rt/test/fuzzer/fork.test
M compiler-rt/test/fuzzer/fork_corpus_groups.test
Log Message:
-----------
[Fuzzer] Bump rss_limit again. (#222187)
The two tests libFuzzer-x86-64-default-Linux::fork_corpus_groups.test
and libFuzzer-x86-64-default-Linux::fork.test have started being flaky
again on two of my bots, so bumping up the rss limit in the test which
temporarily solved the issue back in #204701.
See comment in #222187 for links to the bots and recent failures.
Commit: 5e282718a88c5e19dfe3524dee0bc91a5fa1e224
https://github.com/llvm/llvm-project/commit/5e282718a88c5e19dfe3524dee0bc91a5fa1e224
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/Func/IR/FuncOps.td
M mlir/lib/Dialect/Func/IR/FuncOps.cpp
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize.mlir
M mlir/test/IR/core-ops.mlir
M mlir/test/Transforms/canonicalize.mlir
M mlir/test/Transforms/inlining.mlir
Log Message:
-----------
[MLIR][Func] Enable strict property assembly format (#217300)
Enable the strict properties assembly format mode for the Func dialect.
Spell inherent call attributes directly in the call formats so they are
no longer parsed from attr-dict in strict mode.
Assisted-by: Codex
Commit: bbd998f0186f5362d3c9c1cc575bf6ce20007685
https://github.com/llvm/llvm-project/commit/bbd998f0186f5362d3c9c1cc575bf6ce20007685
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M flang/test/Semantics/data27.f90
Log Message:
-----------
[flang][test] Expand test for legacy DATA initializer on invalid declarations (#222171)
Follow-up to #221170. Expands `flang/test/Semantics/data27.f90` with the
other shapes that crashed the same way before that fix and now produce
the expected error
Assisted-by: AI
Commit: 9851e4f8979b8b57557d03cd98b54f57287a128f
https://github.com/llvm/llvm-project/commit/9851e4f8979b8b57557d03cd98b54f57287a128f
Author: Jackson Stogel <jtstogel at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[libc][bazel] Make a large swath of targets full-build compatible (#218993)
After this PR, all compatible targets in `@llvm-project//libc:all` are
buildable under full-build mode.
```
bazel build @llvm-project//libc:all -- at llvm-project//libc:build_mode=full --config=generic_clang --keep_going
```
Assited-by: Gemini 3.5
Commit: a953c8466be3dc855f99bf0433386fcae4ef2627
https://github.com/llvm/llvm-project/commit/a953c8466be3dc855f99bf0433386fcae4ef2627
Author: Liao Chunyu <chunyu at iscas.ac.cn>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/MC/RISCV/rv32p-invalid.s
M llvm/test/MC/RISCV/rv32p-valid.s
Log Message:
-----------
[RISCV][MC]Fix encoding for psati.dw/dh (#221889)
psati.dh: the width is specified by uimm4+1.
psati.dw: the width is specified by uimm5+1.
https://github.com/riscv/riscv-p-spec/blob/master/P-ext-proposal.adoc#psati-dh-rv32
Commit: ea3f107a84eaa2459f6eb5d1c8dbeefea7576689
https://github.com/llvm/llvm-project/commit/ea3f107a84eaa2459f6eb5d1c8dbeefea7576689
Author: Larry Meadows <Lawrence.Meadows at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/test/OpenMP/amdgcn-attributes.cpp
M clang/test/OpenMP/amdgcn_target_device_vla.cpp
M clang/test/OpenMP/nvptx_SPMD_codegen.cpp
M clang/test/OpenMP/nvptx_target_teams_codegen.cpp
M clang/test/OpenMP/ompx_attributes_codegen.cpp
M clang/test/OpenMP/target_num_teams_num_threads_attributes.cpp
M clang/test/OpenMP/target_teams_reduction_codegen.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M mlir/test/Target/LLVMIR/omptarget-region-device-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-target-launch-device.mlir
M offload/plugins-nextgen/common/src/RecordReplay.cpp
A offload/test/offloading/thread_limit_below_wavefront.c
Log Message:
-----------
[OpenMP] Reserve the main thread's warp for generic mode kernels (#218790)
In generic mode one warp of the block runs the main thread and the rest
run the
user's threads, so everything needing the team size computes
`BlockSize - WarpSize`: the device runtime's `getMaxTeamThreads`, and
the state
machine OpenMPOpt builds. The bound written into the kernel was the
program's
`thread_limit` exactly, so on gfx90a `thread_limit(4)` launched a block
of 4
threads and the team size came out as `4 - 64`. That subtraction is
unsigned, so
the runtime saw four billion workers rather than none: the parallel
region never
ran, and on current trunk the launch dies with a memory access fault.
Any
`thread_limit` below one warp was affected, so anything under 64 on a
wave64
target.
Add the warp where the bound is written, in `createTargetInit`, for
generic mode
only, so `thread_limit(4)` writes 68 and the team gets its 4, clamped to
the
target's maximum work group size because an out-of-range bound is
dropped rather
than clamped. A fixed 64 is reserved rather than the target's own
wavefront: the
bound is only a ceiling, and the runtime still adds the real warp size
and
clamps to it, so the block that launches is unchanged. Where the warp is
narrower the ceiling is 32 too high, which costs the backend some
register
budget and nothing else; NVPTX with `thread_limit(20)` now gets
`maxntid=84`
where it would have got 52, and still launches 52.
The record-replay recorder, which wrote `thread_limit` as the largest
launch a
replay would accept, now records the larger block that was actually
launched.
`thread_limit_below_wavefront.c` is the reproducer, and the remaining
files are
regenerated clang and MLIR expectations.
## Testing
Tested on `main` at 68622e02c9e5: `clang/test/OpenMP`,
`mlir/test/Target/LLVMIR`
and `llvm/test/Transforms/OpenMP` give 2114 passed, 14 unsupported, 4
failed.
The four are `mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-shared*`, which
fail on
`main` independently of this change: their RUN lines hand `llc` an
`-mxcoff-roptr` it only accepts on AIX.
`check-offload` on an MI210 has nothing failing: 1134 passed, 4
expectedly
failed, 363 unsupported, 12 skipped. That covers the new test,
`thread_limit_below_wavefront.c`, and the six `omp-kernel-replay` tests.
Commit: d1c0cc5e760f9cbb68e2acec80a476c4b8b898b7
https://github.com/llvm/llvm-project/commit/d1c0cc5e760f9cbb68e2acec80a476c4b8b898b7
Author: Michael Halkenhäuser <MichaelGerald.Halkenhauser at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUReserveWWMRegs.cpp
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
Log Message:
-----------
[AMDGPU] Do not freeze reserved registers in AMDGPUReserveWWMRegs (#222193)
Refreshing the shared RegisterClassInfo needs an up-to-date reserved set, but
freezing it into MachineRegisterInfo, as #221849 did, publishes it too early:
clearing the per-lane VGPR mask unreserves those registers, and LiveIntervals
does not extend a reserved register's unit ranges to its uses, so those uses
fail verification.
Take the set from TargetRegisterInfo instead. It is the same set, and the
register allocator still freezes it into MachineRegisterInfo itself.
AI-assisted.
Commit: d7da49ea2bbc11a93f162ab2ef9755e57843075d
https://github.com/llvm/llvm-project/commit/d7da49ea2bbc11a93f162ab2ef9755e57843075d
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/docs/CMakeLists.txt
M clang/include/clang/Options/ClangOptionDocs.td
M clang/include/clang/Options/FlangOptions.td
M clang/include/clang/Options/Options.td
M clang/utils/TableGen/ClangOptionDocEmitter.cpp
M flang/docs/CMakeLists.txt
M flang/docs/FlangOptionsDocs.td
M flang/docs/FlangOptionsMan.td
Log Message:
-----------
[clang][flang][docs] Re-land Markdown CLI ref generator (#222147)
Reverts llvm/llvm-project#221937
Relands llvm/llvm-project#220385
This time, the migration includes flang command line reference
documentation, so the change passes `ninja docs-flang-html/man`.
Tracking issue: #201242
Assisted-By: Codex
Commit: 4383c7f120edc4e31294eb148a57c762d7d53170
https://github.com/llvm/llvm-project/commit/4383c7f120edc4e31294eb148a57c762d7d53170
Author: Shanzhi Chen <chenshanzhi at huawei.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
Log Message:
-----------
[BOLT][AArch64] Fix relocation type for `LDRSW` (#221939)
Fix the incorrect relocation type for `LDRSW`. It should be
`ELF::R_AARCH64_LDST32_ABS_LO12_NC`, but it was mistakenly set to
`ELF::R_AARCH64_LDST64_ABS_LO12_NC` in PR #196051.
Commit: 7209c7af3323615c632a3409a2a776b29fbac528
https://github.com/llvm/llvm-project/commit/7209c7af3323615c632a3409a2a776b29fbac528
Author: Vy Nguyen <1762963+oontvoo at users.noreply.github.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M clang/test/Driver/modules-driver-depscan-log.cpp
Log Message:
-----------
[clang][Driver][test] Specify output path in modules-driver-depscan-log.cpp (#222209)
In `clang/test/Driver/modules-driver-depscan-log.cpp`, `%clang -c` is
invoked on `%t/A.cppm` without an explicit output file (`-o`). By
default, Clang writes the resulting object file (`A.o`) to the current
working directory.
In sandboxed or hermetic test environments where the test runner
executes with a read-only working directory (e.g., Bazel, Nix, or remote
build executors), the test fails with:
```text
error: unable to open output file 'A.o': 'Permission denied'
1 error generated.
Commit: dea8e298844a7721d6db80e2474c178d454b148c
https://github.com/llvm/llvm-project/commit/dea8e298844a7721d6db80e2474c178d454b148c
Author: Shengxin Pei <TPPPP72 at outlook.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/test/SemaCXX/cxx20-default-compare.cpp
R clang/test/SemaCXX/gh147127.cpp
Log Message:
-----------
[clang][test] Move test `gh147127.cpp` to `cxx20-default-compare.cpp` NFC (#222208)
Follow-up #198830
Commit: e1683efa7ce0c77dbd2f3b04e05e18313aee4338
https://github.com/llvm/llvm-project/commit/e1683efa7ce0c77dbd2f3b04e05e18313aee4338
Author: Justin Bogner <mail at justinbogner.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/IR/Type.cpp
M llvm/test/CodeGen/DirectX/ResourceAccess/handle-cases.ll
M llvm/test/CodeGen/DirectX/ResourceAccess/handle-to-index.ll
M llvm/test/CodeGen/DirectX/ResourceAccess/looped-phi-nodes-resolved.ll
M llvm/test/CodeGen/DirectX/ResourceAccess/looped-phi-nodes.ll
M llvm/test/Transforms/GVN/PRE/no-phi-translate.ll
M llvm/test/Transforms/GVN/PRE/no-pre-load-for-token-like.ll
M llvm/test/Transforms/LCSSA/token-like-live-out.ll
M llvm/test/Transforms/SimpleLoopUnswitch/token-uses.ll
R llvm/test/Transforms/SimplifyCFG/token_like_type.ll
M llvm/test/Verifier/tokenlike1.ll
M llvm/test/Verifier/tokenlike5.ll
M llvm/test/Verifier/tokenlike6.ll
M llvm/test/Verifier/tokenlike7.ll
M llvm/unittests/Transforms/Utils/LocalTest.cpp
Log Message:
-----------
[IR][DirectX] Drop IsTokenLike from `dx.*` target types (#222130)
We made the DirectX resource types "token-like" a while ago in order to
prevent transforms from moving them into PHIs and the like in ways that
made determining their provenance more difficult. However, there are
patterns in HLSL that can generate the problematic IR directly and we've
since implemented logic in `DXILResourceAccess` to handle such cases
anyway. Because of this, we aren't really getting any benefit from the
types being `IsTokenLike`, and in some cases we're working with
intermediate IR that doesn't actually pass the verifier.
Drop `IsTokenLike` from the `dx.*` types since it's no longer correct or
useful. I've updated the tests to use `amdgpu.stridemark` instead, and
slightly abused `llvm.ssa.copy` in order to manufacture SSA values of
that type. I had to drop the test that actually needed a load from a
value depending on the token-like type, as there just isn't really a way
for that to come up without the resource types.
Commit: 33898fffd3c09eba75e4199749117923bc1beee2
https://github.com/llvm/llvm-project/commit/33898fffd3c09eba75e4199749117923bc1beee2
Author: Shengxin Pei <TPPPP72 at outlook.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/test/SemaCXX/ms-ctor-closure.cpp
Log Message:
-----------
[clang][test] Add test for #67685 NFC (#222212)
Commit: 8c7d76bfc1b5c75effc7bd8ecc4892be9970ea5d
https://github.com/llvm/llvm-project/commit/8c7d76bfc1b5c75effc7bd8ecc4892be9970ea5d
Author: Teresa Johnson <tejohnson at google.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/test/ThinLTO/X86/memprof-funcassigncloning.ll
M llvm/test/ThinLTO/X86/memprof-funcassigncloning2.ll
M llvm/test/Transforms/MemProfContextDisambiguation/duplicate-context-ids.ll
M llvm/test/Transforms/MemProfContextDisambiguation/funcassigncloning.ll
M llvm/test/Transforms/MemProfContextDisambiguation/funcassigncloning2.ll
M llvm/test/Transforms/MemProfContextDisambiguation/funcassigncloningrecursion.ll
M llvm/test/Transforms/MemProfContextDisambiguation/inlined3.ll
Log Message:
-----------
[MemProf] Use NodeId to break ties deterministically in identifyClones (#222126)
In identifyClones(), ties between caller edges with identical allocation
types and matching clone candidates were previously broken by comparing
the first element of ContextIds (*A->ContextIds.begin() <
*B->ContextIds.begin()).
Because ContextIds is a DenseSet, its iteration order depends on hash
table
layout and bucket distribution, introducing non-determinism across
different
runs or architectures.
Replace this tie-breaker with caller NodeId (A->Caller->NodeId <
B->Caller->NodeId),
which provides a deterministic and stable ordering. Also apply
Callee->NodeId
in CalleeCallerEdgeLessThan for consistency.
Update tests whose remark or dump order depended on the previous
tie-breaker.
For tests that verify multi-clone greedy assignment behavior
(funcassigncloning*.ll),
reorder the input MIB contexts so caller NodeIds reproduce the visit
order
exercising the extra clone creation.
Assisted-by: Gemini
Commit: b113e2640849cd75a39efeae6256d5aecc3f1446
https://github.com/llvm/llvm-project/commit/b113e2640849cd75a39efeae6256d5aecc3f1446
Author: Anshul Nigham <nigham at google.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
Log Message:
-----------
Fix Bazel build for 52d922a (#222219)
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=52d922aa153b1232813470e014635419ce006023
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 5503fa587536afa2624971224dbfc6e25d762d37
https://github.com/llvm/llvm-project/commit/5503fa587536afa2624971224dbfc6e25d762d37
Author: Thrrreeee <shijinrui at bytedance.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M bolt/lib/Passes/FixRISCVCallsPass.cpp
M bolt/test/RISCV/call-link-register.s
M bolt/test/RISCV/relax.s
Log Message:
-----------
[BOLT][RISCV] Remove redundant AUIPCs when rewriting call pairs (#221965)
`FixRISCVCallsPass` replaces the AUIPC instruction with a Noop when
converting an AUIPC/JALR pair into a call or tail-call pseudo. Add the
`NOP` annotation so the existing RemoveNops pass can remove it, avoiding
an unnecessary instruction in the output.
Commit: 7caac9be9a7f9ecda3f31802ef451a25f2b61658
https://github.com/llvm/llvm-project/commit/7caac9be9a7f9ecda3f31802ef451a25f2b61658
Author: Thrrreeee <shijinrui at bytedance.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/include/bolt/Passes/LivenessAnalysis.h
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
M bolt/lib/Target/X86/X86MCPlusBuilder.cpp
M bolt/unittests/Core/MCPlusBuilder.cpp
Log Message:
-----------
[BOLT][RISCV] Implement register analysis hooks (#220581)
This patch implements the RISC-V register-analysis hooks in
`RISCVMCPlusBuilder` that previously fell back to the unimplemented
base-class methods.
The `MCPlusBuilder` unittests fixture is also extended to create a
RISC-V binary context. New tests cover the flags-register result,
zeroing-XOR recognition, ABI register masks, general-purpose register
masks, and non-scavengeable registers. These hooks provide the
target-specific register information required by BOLT analyses and
transformations on RISC-V.
BTW, this is split out as a prerequisite fo LongJump pass implement for
RISCV.
Commit: 6ef30f15d71bab018de258496f83b8dee529ce60
https://github.com/llvm/llvm-project/commit/6ef30f15d71bab018de258496f83b8dee529ce60
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
Log Message:
-----------
[GlobalISel] Use getTypeFromIdx instead of direct table indexing in GIR_AddCImm (#222114)
Commit: 83728c8a9fe27b1427cf0125e5a7896bbb55b6ae
https://github.com/llvm/llvm-project/commit/83728c8a9fe27b1427cf0125e5a7896bbb55b6ae
Author: Dave Lee <davelee.com at gmail.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M lldb/docs/resources/formatterbytecode.md
M lldb/include/lldb/DataFormatters/FormatterBytecode.def
M lldb/include/lldb/DataFormatters/FormatterBytecode.h
M lldb/source/DataFormatters/FormatterBytecode.cpp
M lldb/source/DataFormatters/TypeSummary.cpp
M lldb/source/DataFormatters/TypeSynthetic.cpp
M lldb/unittests/DataFormatter/FormatterBytecodeTest.cpp
Log Message:
-----------
[lldb] Add APSInt representation to formatter bytecode (#220665)
Adopt a single representation for integers in the formatter bytecode
interpreter. This simplifies code generation, where the (now deprecated)
distinction of `uint64_t` and `int64_t` types could make conditionals
and other operations more complicated, by having to have code paths for
signed and unsigned.
Depends on https://github.com/llvm/llvm-project/pull/218801
Assisted-by: claude
Commit: 1261f5003d93e83295b93782b871be06db2564c4
https://github.com/llvm/llvm-project/commit/1261f5003d93e83295b93782b871be06db2564c4
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-print-before-after-all.ll
M llvm/test/Transforms/LoopVectorize/X86/funclet.ll
M llvm/test/Transforms/LoopVectorize/vplan-print-before-after.ll
Log Message:
-----------
[VPlan] Split simplifyRecipes into simplifyRecipes and combineRecipes (#221924)
Bringing it in line with InstSimplify and InstCombine, split up
simplifyRecipe into a function that modifies and creates recipes
(combineRecipe), and one that is analysis-only (simplifyRecipe).
This allows us to avoid adding simplficiation only folds to the worklist
in #213899.
The funclet.ll test no longer erases the constant-folded intrinsic call
because vputils::isDeadRecipe returns false.
Commit: bcef85f08355c76d1e7e98604ed68fa1d93c2022
https://github.com/llvm/llvm-project/commit/bcef85f08355c76d1e7e98604ed68fa1d93c2022
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPMemoryUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPMemoryUtils.h
Log Message:
-----------
[SLP][modularisation][NFC] Move compress load/store helpers to SLPMemoryUtils (#222038)
Move the following BoUpSLP-independent masked-load/store compress
helpers out of SLPVectorizer.cpp into
SLPVectorizer/SLPMemoryUtils.{h,cpp}:
isMaskedLoadCompress (both overloads)
isMaskedStoreCompress
buildCompressMask, used only by isMaskedLoadCompress, moves alongside
them and stays file-local. isMaskedLoadCompress reads the file-local
SLPReVec cl::opt; the option stays static in SLPVectorizer.cpp and the
moved helper takes its value as an explicit bool parameter. Behavior is
unchanged.
Part of the SLPVectorizer.cpp modularization effort:
https://discourse.llvm.org/t/modularizing-slpvectorizer-cpp/90922
Assisted by AI
Commit: 4f45ae199557874671659bf59b2875e06ec2a0ff
https://github.com/llvm/llvm-project/commit/4f45ae199557874671659bf59b2875e06ec2a0ff
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/CMakeLists.txt
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPReductionUtils.cpp
A llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPReductionUtils.h
M llvm/utils/gn/secondary/llvm/lib/Transforms/Vectorize/BUILD.gn
Log Message:
-----------
[SLP][modularisation][NFC] Move reduction match helpers to SLPReductionUtils (#222052)
Move the following BoUpSLP-independent reduction pattern-match helpers
out of SLPVectorizer.cpp into a new
SLPVectorizer/SLPReductionUtils.{h,cpp}:
getNonPhiOperand
isReductionCandidate
matchRdxBop, used only by these two, moves alongside them and stays
file-local. Behavior is unchanged.
Part of the SLPVectorizer.cpp modularization effort:
https://discourse.llvm.org/t/modularizing-slpvectorizer-cpp/90922
Assisted by AI
Commit: 90e4efa54ff95f7895522fbe152a8da86bf4e446
https://github.com/llvm/llvm-project/commit/90e4efa54ff95f7895522fbe152a8da86bf4e446
Author: Thrrreeee <shijinrui at bytedance.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M bolt/unittests/Core/CMakeLists.txt
Log Message:
-----------
[BOLT][NFC] Fix CoreTests linking with shared libraries (#222225)
`CoreTests` directly uses `Triple` and `SubtargetFeatures` constructors
from `LLVMTargetParser` but does not declare the dependency. This causes
undefined-symbol errors with BUILD_SHARED_LIBS=ON.
https://github.com/llvm/llvm-project/pull/220581
Fix https://lab.llvm.org/buildbot/#/builders/218/builds/6464.
Commit: 7c4aac7e60f9f813df5693dcc735bda7873594f7
https://github.com/llvm/llvm-project/commit/7c4aac7e60f9f813df5693dcc735bda7873594f7
Author: Jason Molenda <jmolenda at apple.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M lldb/unittests/API/CMakeLists.txt
Log Message:
-----------
[lldb] Link API unit tests against LLVMTestingSupport. (#222206)
Changes to lldb have added a dependency on llvm::detail::TakeError, this
fails to link on my desktop without the dependency. Most other unittests
already link to LLVMTestingSupport.
Commit: 23074079b992a232aabca0d982ee15d818a5b4a7
https://github.com/llvm/llvm-project/commit/23074079b992a232aabca0d982ee15d818a5b4a7
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/bedrock/Session.h
M orc-rt/test/unit/bedrock/SessionTest.cpp
Log Message:
-----------
[orc-rt] Add Session::attach for pre-mode ControllerAccesses. (#222227)
Allow clients to attach a session using a pre-constructed
ControllerAccess object. This allows clients to use non-trivial
construction methods (e.g. factories) to build ControllerAccess objects.
Commit: 786ba30e072e92648840ddbb5bc3f76e0af35b07
https://github.com/llvm/llvm-project/commit/786ba30e072e92648840ddbb5bc3f76e0af35b07
Author: Dharuni R Acharya <125176188+DharuniRAcharya at users.noreply.github.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/include/llvm/IR/Intrinsics.td
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
M llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
Log Message:
-----------
[LLVM][AutoUpgrade] Support default args on undeclared multi-call upgrades (#216246)
When an `.ll` file contains multiple calls to an intrinsic without an explicit
declaration, only the first call is upgraded successfully, and the remaining
subsequent calls fail.
`LLParser` builds one temporary Function per call, so after the first
upgrade occupies the canonical name the later functions are uniquified
(eg. `llvm.foo.1`). The intrinsic ID was previously looked up using `F->getName()`,
which requires an exact name match. So, the uniquified names resolved to `not_intrinsic`,
causing the upgrade to return and the default arguments were not applied.
This patch fixes this issue by using the cached `F->getIntrinsicID()`,
which is set when the temporary function is created from the original name.
It also `rename(F)` before inserting the full declaration, so the temporary
function no longer occupies the canonical name.
---------
Signed-off-by: DharuniRAcharya <dharunira at nvidia.com>
Commit: 1fddb91bf4ad2c3012c107f0cf792e2b2a5a9b67
https://github.com/llvm/llvm-project/commit/1fddb91bf4ad2c3012c107f0cf792e2b2a5a9b67
Author: ShashwathiNavada <shashwathinavada at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Semantics/modfile86.f90
A flang/test/Semantics/modfile87.f90
A flang/test/Semantics/resolve132.f90
Log Message:
-----------
[Flang][Semantics] Diagnose missing MODULE prefix in submodule procedures (#197173)
Add a portability warning when a submodule procedure is missing the
MODULE prefix required by a MODULE PROCEDURE interface in its parent
module.
Commit: b53c11f42061e7e020af1a0e2a54f53b4a2dde3f
https://github.com/llvm/llvm-project/commit/b53c11f42061e7e020af1a0e2a54f53b4a2dde3f
Author: Anshul Nigham <nigham at google.com>
Date: 2026-09-08 (Tue, 08 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/OpenACC/Support/BUILD.bazel
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/OpenACC/Transforms/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Fix Bazel build (#222232)
Add missing deps and update sharding for ROCDLDialect
Commit: 8d4c923371a73b9f60bee93d91c1cc0c3b49b89e
https://github.com/llvm/llvm-project/commit/8d4c923371a73b9f60bee93d91c1cc0c3b49b89e
Author: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
A clang-tools-extra/docs/clang-tidy/checks/readability/function-cognitive-complexity.md
R clang-tools-extra/docs/clang-tidy/checks/readability/function-cognitive-complexity.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/function-size.md
R clang-tools-extra/docs/clang-tidy/checks/readability/function-size.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/identifier-length.md
R clang-tools-extra/docs/clang-tidy/checks/readability/identifier-length.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/identifier-naming.md
R clang-tools-extra/docs/clang-tidy/checks/readability/identifier-naming.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/implicit-bool-conversion.md
R clang-tools-extra/docs/clang-tidy/checks/readability/implicit-bool-conversion.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/inconsistent-declaration-parameter-name.md
R clang-tools-extra/docs/clang-tidy/checks/readability/inconsistent-declaration-parameter-name.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/inconsistent-ifelse-braces.md
R clang-tools-extra/docs/clang-tidy/checks/readability/inconsistent-ifelse-braces.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/isolate-declaration.md
R clang-tools-extra/docs/clang-tidy/checks/readability/isolate-declaration.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/magic-numbers.md
R clang-tools-extra/docs/clang-tidy/checks/readability/magic-numbers.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/make-member-function-const.md
R clang-tools-extra/docs/clang-tidy/checks/readability/make-member-function-const.rst
Log Message:
-----------
[clang-tidy][docs] Rename readability check docs to Markdown [2/5] (#221528)
Tracking issue: #201242
See the [migration guide] for more information.
[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
This is the second part of the mechanical rename of the check
documentations in readability module.
The rewrite is provided by the next PR in this stack.
Commit: 30e244ed348addbc4611466404dd717d5906a1a7
https://github.com/llvm/llvm-project/commit/30e244ed348addbc4611466404dd717d5906a1a7
Author: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang-tools-extra/docs/clang-tidy/checks/readability/function-cognitive-complexity.md
M clang-tools-extra/docs/clang-tidy/checks/readability/function-size.md
M clang-tools-extra/docs/clang-tidy/checks/readability/identifier-length.md
M clang-tools-extra/docs/clang-tidy/checks/readability/identifier-naming.md
M clang-tools-extra/docs/clang-tidy/checks/readability/implicit-bool-conversion.md
M clang-tools-extra/docs/clang-tidy/checks/readability/inconsistent-declaration-parameter-name.md
M clang-tools-extra/docs/clang-tidy/checks/readability/inconsistent-ifelse-braces.md
M clang-tools-extra/docs/clang-tidy/checks/readability/isolate-declaration.md
M clang-tools-extra/docs/clang-tidy/checks/readability/magic-numbers.md
M clang-tools-extra/docs/clang-tidy/checks/readability/make-member-function-const.md
Log Message:
-----------
[clang-tidy][docs] Rewrite readability check docs to Markdown [2/5] (#221529)
Tracking issue: #201242
See the [migration guide] for more information.
[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
This is the second part of rewriting check documentations in readability
module from reST to MyST Markdown.
AI Usage: This was prepared with rnk's fork of rst2myst and
GPT5.6-assisted cleanup.
I manually verified that the documentation renders as expected.
Preview site:
https://broken.life/llvm-staging/readability-markdown-port/index.html
---------
Co-authored-by: EugeneZelenko <eugene.zelenko at gmail.com>
Commit: c1872e7fd3307679a2da53f9d83de0ccf234b4ad
https://github.com/llvm/llvm-project/commit/c1872e7fd3307679a2da53f9d83de0ccf234b4ad
Author: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M .mailmap
Log Message:
-----------
[mailmap] Add entry for Zeyi Xu (#222237)
Commit: 5e973ba5721412c7d31349e56172ed9086f4c5e2
https://github.com/llvm/llvm-project/commit/5e973ba5721412c7d31349e56172ed9086f4c5e2
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/test/AST/absurdly_big_struct.cpp
Log Message:
-----------
[clang][test] Make new absurdly_big_struct test more targeted (#219897)
The previous version of `y()` used `c2[i]`, which can't be evaluated at
compile-time.
The emitted diagnostic depends on something calling
`ASTContext::getASTRecordLayout()` for `b`, which currently happens in
the constant evaluator. If the evaluator decides to evaluate `c2[i]`
before calling `getASTRecordLayout()`, the test fails since the
diagnostic is never emitted.
Fix this by simply using `c2[0]` instead.
Commit: 60969adcbc2fca5779580ca93ba00a7b06cc0e40
https://github.com/llvm/llvm-project/commit/60969adcbc2fca5779580ca93ba00a7b06cc0e40
Author: Steven Wu <stevenwu at apple.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/include/llvm/Support/FileSystem.h
Log Message:
-----------
[Support][FileSystem] Prefer `status` with `file_t` parameter. NFC. (#157581)
When searching the documentation for LLVM for `llvm::sys::fs::status`,
only the version with file descriptor can be found because the
documentation is built on the UNIX host and the file handle version is
defined out.
In reality, file handle version is more portable and should be displayed
instead. On UNIX, these two functions have the same underlying type,
thus it shouldn't matter which one is declared, and both versions are
still available on Windows for compatibility.
Commit: bf1d0038c9715c93e8d3ec95bf5923d57acd2b39
https://github.com/llvm/llvm-project/commit/bf1d0038c9715c93e8d3ec95bf5923d57acd2b39
Author: Letu Ren <fantasquex at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
Log Message:
-----------
[mlir][LLVM] Add clmul intrinsics (#222113)
Assisted-by: gpt-5.6-sol
Signed-off-by: Letu Ren <fantasquex at gmail.com>
Commit: 79f1047ae03783dbcf7506b99d265e5a803fbd3c
https://github.com/llvm/llvm-project/commit/79f1047ae03783dbcf7506b99d265e5a803fbd3c
Author: Wenju He <wenju.he at intel.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/include/llvm/Passes/PassBuilder.h
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/test/Other/new-pm-O0-ep-callbacks.ll
M llvm/test/Other/new-pm-thinlto-postlink-defaults.ll
M llvm/tools/opt/NewPMDriver.cpp
Log Message:
-----------
[PassBuilder] Add ThinLTO EP callbacks mirroring FullLinkTimeOptimizationEarly/Last (#221857)
Our downstream has a request to add customization pass into
ThinLinkTimeOptimizationEarlyEPCallback, but buildThinLTODefaultPipeline
has no equivalent EPCallback like buildLTODefaultPipeline does. This PR
add it and ThinLinkTimeOptimizationLastEPCallback as well.
Co-authored-by: Claude <noreply at anthropic.com>
Commit: b61bc342396753be2c56dc6abb7d06cfc6be6b25
https://github.com/llvm/llvm-project/commit/b61bc342396753be2c56dc6abb7d06cfc6be6b25
Author: David Green <david.green at arm.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/arm64-vmul.ll
M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
Log Message:
-----------
[AArch64] Update and regenerate vec-combine-compare-to-bitmask.ll. NFC (#222242)
Commit: b4b7775cfa79d7e3382657037eb037f8c7cb2428
https://github.com/llvm/llvm-project/commit/b4b7775cfa79d7e3382657037eb037f8c7cb2428
Author: Steffen Larsen <sholstla at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/test/CIR/CodeGen/atomic-scoped.c
M clang/test/CIR/CodeGen/atomic.c
Log Message:
-----------
[CIR] Preserve volatile semantics for atomic operations (#220874)
This commit fixes the preservation of volatile semantics for atomic RMW
operations in CIR CodeGen.
Signed-off-by: Steffen Holst Larsen <sholstla at amd.com>
Commit: e3a60a700dfa488adebd546705424aae7c8b3a35
https://github.com/llvm/llvm-project/commit/e3a60a700dfa488adebd546705424aae7c8b3a35
Author: Vishank Singh <vishanksinghh at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M libcxx/docs/Status/Cxx26Issues.csv
M libcxx/include/__ranges/lazy_split_view.h
A libcxx/test/std/ranges/range.adaptors/range.lazy.split/range.lazy.split.outer.value/ctor.compile.pass.cpp
R libcxx/test/std/ranges/range.adaptors/range.lazy.split/range.lazy.split.outer.value/ctor.default.pass.cpp
R libcxx/test/std/ranges/range.adaptors/range.lazy.split/range.lazy.split.outer.value/ctor.iter.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.lazy.split/range.lazy.split.outer/deref.pass.cpp
Log Message:
-----------
[libc++][ranges] Implement LWG4013: Make `lazy_split_view::outer-iterator::value_type` non-default-constructible (#221919)
Remove the default constructor of `outer-iterator::value_type` and make
the remaining constructor private (exposition-only), as required by LWG
4013.
Update the corresponding tests:
- `ctor.default.pass.cpp` and `ctor.iter.pass.cpp` are now deleted.
- `ctor.compile.pass.cpp` is added to verify `value_type` is not
default-constructible and its construction from iterator is not
available.
- Cases testing construction of `value_type` via `operator*` are moved
to `range.lazy.split.outer/deref.pass.cpp`.
Closes #105321
Commit: 580484b5032d55cf6adac0fe1274a4ee8eaa0c2a
https://github.com/llvm/llvm-project/commit/580484b5032d55cf6adac0fe1274a4ee8eaa0c2a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/test/TableGen/AMDGPUTargetDefSubArchSpelling.td
M llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
Log Message:
-----------
AMDGPU: Remove unused getBaseArchNameAMDGCN (#222157)
This ended up unused for gfx1250-strict
Co-authored-by: Claude <noreply at anthropic.com>
Commit: 1e744320ff27ee748c1a2a121fe226984efddc1b
https://github.com/llvm/llvm-project/commit/1e744320ff27ee748c1a2a121fe226984efddc1b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
Log Message:
-----------
GlobalISel: Drop AllowFPOpFusion from CombinerHelper FMA formation (#221918)
Only rely on the contract flags.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 27e964eceb2f15fb99618e73bd92f02f4a938816
https://github.com/llvm/llvm-project/commit/27e964eceb2f15fb99618e73bd92f02f4a938816
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Shared/SymbolNameSpec.h
Log Message:
-----------
[ORC] Require symbol name kind in SymbolNameSpec constructor. (#222238)
Require clients to spell out the naming level that SymbolNameSpecs are
expressed in. (An implicit default is a footgun, and adds limited
convenience)
Commit: 7bb9b13816ef9616425525651ea629f2138b194f
https://github.com/llvm/llvm-project/commit/7bb9b13816ef9616425525651ea629f2138b194f
Author: Frederik Harwath <frederik.harwath at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
M llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
M llvm/test/MC/AMDGPU/gfx13_asm_vop3.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
Log Message:
-----------
[AMDGPU] Rework pseudo-scalar transcendental inline constant restriction handling (#208459)
The f16 pseudo-scalar transcendental instructions do not support inline
constants on gfx12. The existing handling of this restriction is
incomplete. It involves checking the
hasNoF16PseudoScalarTransInlineConstants function in the right places.
For the SIInstrInfo::isInlineConstant function, for instance, this has
led to a situation where some overloads respect the restriction and
others do not. This approach also relies on completely disabling the
folding of constant operands. The machine code emission does still use
the inline constant encoding if it encounters a suitable operand.
Introduce a new "noinline" operand type and use it for the instruction
variant that is used on gfx12. This does also enable the use of literal
constants.
Commit: f4b84aa292909aa0e737cc0cdfa9eda7ef4bd4f2
https://github.com/llvm/llvm-project/commit/f4b84aa292909aa0e737cc0cdfa9eda7ef4bd4f2
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanValue.h
A llvm/test/Transforms/LoopVectorize/RISCV/scatter-type-mismatch.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-flags.ll
A llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-intrinsic.ll
M llvm/unittests/Transforms/Vectorize/VPDomTreeTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Log Message:
-----------
[VPlan] Consolidate VPIWithType and VPI (NFC) (#203019)
The extra ResultType has been absorbed into VPInstruction, and the
recipe classes can now be consolidated. The patch also fixes missing
flags-printing in the case of WideIVStep, and includes a test to guard
against bad changes, discovered during the review process.
Commit: 962a202be1f642f119921413293e8325e2e06757
https://github.com/llvm/llvm-project/commit/962a202be1f642f119921413293e8325e2e06757
Author: Machillka <machillka2007 at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang-tools-extra/clangd/InlayHints.cpp
M clang-tools-extra/clangd/unittests/InlayHintTests.cpp
Log Message:
-----------
[clangd] Place deduced return type hints after noexcept (#219829)
Deduced return type hints for functions and lambdas could appear before
a `noexcept` specifier, even though a trailing return type belongs after
the exception specification.
Use the end of the function type's local source range when it is
available. For lambdas without a function type location, keep the end of
the lambda introducer as a fallback.
Fixes clangd/clangd#2696
Assisted-by: Codex
Commit: a1f878adc64fee90fca87382a01013eca7e19b2b
https://github.com/llvm/llvm-project/commit/a1f878adc64fee90fca87382a01013eca7e19b2b
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/lib/Serialization/ASTWriter.cpp
A clang/test/Modules/pr222002.cppm
Log Message:
-----------
[C++20] [Modules] Keep DeductionGuideDecl in the general lookup table (#222246)
Close https://github.com/llvm/llvm-project/issues/222002
The root cause of the problem is, the deduction guide was not in the
general lookup table. The fix is to move them into the general lookup
table. This should be fine as the DeductionGuide may not pollute the
name lookup results.
Commit: 6dc6c67b786260486641eb62546c34b48143e131
https://github.com/llvm/llvm-project/commit/6dc6c67b786260486641eb62546c34b48143e131
Author: David Spickett <david.spickett at arm.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M libcxx/CMakeLists.txt
M libcxxabi/CMakeLists.txt
A runtimes/cmake/Modules/GetSanitizerFlags.cmake
Log Message:
-----------
[libcxx][libcxxabi][cmake] Deduplicate sanitizer flags function (#221757)
While experimenting with flang-rt builds I realised there were two
copies of this function.
We don't need it in flang-rt right now but I figure reducing duplication
is good anyway.
Commit: 3a8bd232cfa8c08a6c7e88801696af65ed1562ea
https://github.com/llvm/llvm-project/commit/3a8bd232cfa8c08a6c7e88801696af65ed1562ea
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper-image.c
M llvm/lib/Frontend/Offloading/OffloadWrapper.cpp
M llvm/test/tools/llvm-offload-wrapper/offload-wrapper.ll
Log Message:
-----------
[OffloadWrapper] Use getPtrAdd() instead of getGetElementPtr() (#222014)
One case has a redundant zero-offset GEP. The other two just add
a byte offset in a convoluted way.
Commit: 1c1ea3793471775c5dc1bb2a4757a5ea32097967
https://github.com/llvm/llvm-project/commit/1c1ea3793471775c5dc1bb2a4757a5ea32097967
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/MustExecute.h
M llvm/lib/Analysis/MustExecute.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
Log Message:
-----------
[LoopSafetyInfo] Compute block colors lazily (NFC) (#221954)
Computing the block colors is fairly expensive, but only rarely actually
needed. We can delay computation to first use.
Fixes https://github.com/llvm/llvm-project/issues/221162.
Commit: 590a3b87dba125069e962956d562802a8173dc38
https://github.com/llvm/llvm-project/commit/590a3b87dba125069e962956d562802a8173dc38
Author: Steffen Larsen <sholstla at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/lib/CIR/Dialect/Transforms/HoistAllocas.cpp
M clang/test/CIR/Transforms/hoist-allocas.cir
Log Message:
-----------
[CIR] Reposition entry-block allocas ahead of control flow (#220496)
HoistAllocas returns early when an alloca was already in the entry
block, but being in the block is not the same as being ahead of the
control flow in it. The pass runs before FlattenCFG, which splits the
body at each structured control-flow op, so an alloca sitting after one
is left in a block that is no longer the entry block.
That matters because SROA only collects allocas from the entry block. An
alloca stranded behind a scope is invisible to it and never promoted, so
anything whose address it holds stays in memory.
Commit: ddf2077559587500f47e3666c696b7366bb36af0
https://github.com/llvm/llvm-project/commit/ddf2077559587500f47e3666c696b7366bb36af0
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/FinalizeISel.cpp
M llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
Log Message:
-----------
[GlobalISel] Fix duplicate finalizeLowering calls (NFC) (#221902)
Improves CTMark geomean -0.07% on aarch64-O0-g.
https://llvm-compile-time-tracker.com/compare.php?from=97cbc1e404b980edc58bfbcabb6f1c61793b624b&to=d8b1a78ba013d5e687acc0e8bf00d3d77749f3db&stat=instructions:u
Assisted-by: codex
Commit: cdd1900816f625eb1f38a6e755c49ccadec56209
https://github.com/llvm/llvm-project/commit/cdd1900816f625eb1f38a6e755c49ccadec56209
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/FastISel.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/IR/Attributes.h
M llvm/include/llvm/IR/Attributes.td
M llvm/include/llvm/IR/InstrTypes.h
M llvm/lib/Analysis/Lint.cpp
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TypePromotion.cpp
M llvm/lib/IR/Attributes.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/IR/VerifierAMDGPU.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Transforms/IPO/ExpandVariadics.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
M llvm/test/Analysis/BasicAA/call-attrs.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
M llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll
M llvm/test/CodeGen/AArch64/GlobalISel/swiftself.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
M llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll
M llvm/test/CodeGen/AMDGPU/waterfall-call-inreg-agpr.ll
M llvm/test/CodeGen/ARM/returned-ext.ll
M llvm/test/CodeGen/ARM/struct-byval-loop.ll
M llvm/test/CodeGen/M68k/multiple-return.ll
M llvm/test/CodeGen/NVPTX/forward-ld-param.ll
M llvm/test/CodeGen/RISCV/rvv/shrinkwrap.ll
M llvm/test/CodeGen/RISCV/shrinkwrap.ll
M llvm/test/CodeGen/SPARC/64abi.ll
M llvm/test/CodeGen/SystemZ/args-14.ll
M llvm/test/CodeGen/SystemZ/call-zos-01.ll
M llvm/test/CodeGen/VE/Scalar/call.ll
M llvm/test/CodeGen/VE/Scalar/va_callee.ll
M llvm/test/CodeGen/VE/Vector/fastcc_caller.ll
M llvm/test/CodeGen/WebAssembly/signext-zeroext-callsite.ll
M llvm/test/CodeGen/X86/bool-zext.ll
M llvm/test/CodeGen/X86/return-ext.ll
M llvm/test/Instrumentation/ThreadSanitizer/tsan_basic.ll
M llvm/test/Transforms/DeadArgElim/deadexternal.ll
M llvm/test/Transforms/Inline/access-attributes-prop.ll
M llvm/test/Transforms/PhaseOrdering/pr64289-tce.ll
M llvm/test/Transforms/SROA/readonlynocapture.ll
M llvm/test/Transforms/SimplifyCFG/hoist-sink-swifterror-store.ll
M llvm/unittests/IR/AttributesTest.cpp
Log Message:
-----------
[IR] Do not inherit ABI attributes from the callee (#207173)
Usually attributes that are missing on the call-site are inherited form
the callee instead. This is fine for optional optimization attributes,
but problematic for ABI-affecting attributes.
ABI attributes generally must be placed at the call-site as well,
because there is no callee to inherit from for indirect calls. Failing
to specify ABI attributes at the call-site generally indicates a bug.
The motivation for being stricter about this (apart from just being the
right thing to do) is to properly support cases where the attributes at
the call-site and the callee actually differ. Two examples I'm aware of
are:
* During cross-language LTO, it's possible to have one side use a `ptr`
argument and the other a `ptr byval(ptr)` argument. Both represent the
same ABI using different IR encodings, but you can't just inherit the
`byval` attribute from one to the other (because the byval case requires
an additional level of indirection in use of the argument).
* To fix our incompatibility with the x86-64 psABI, I believe we'll want
to do something like emit zeroext/signext at function returns and
call-site arguments only, so that we both don't assume incoming values
are zero/sign-extended, but still zero/sign-extend outgoing values. This
makes sure we still remain compatible with old Clang-generated object
files.
We've attempted to make a change like this previously, but ran into
substantial issues with missing call-site attributes on
compiler-inserted calls. The issue was particularly severe on s390x,
which requires zeroext/signext on more values than other architectures.
I believe that the situation here has improved a lot in the meantime,
with libcalls now inferring mandatory ABI attributes, and s390x also
using a noext attribute plus validation logic in the backend to detect
cases where the necessary attributes are missing.
-----
ABI attributes on call-sites must be queried using `hasABIParamAttr()`
and `hasABIRetAttr()` instead of `paramHasAttr()` and `hasRetAttr()`
now. Passing an ABI attribute to the latter two will result in an
assertion failure.
Commit: 8c3cb9c166e8f5ade26bc90a4a4cf5ec628f894f
https://github.com/llvm/llvm-project/commit/8c3cb9c166e8f5ade26bc90a4a4cf5ec628f894f
Author: Vikram Hegde <Vikram.Hegde at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-epilog-phi.mir
M llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-gen-structure.mir
M llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-loop-carried-mem.mir
Log Message:
-----------
[CodeGen][NPM] Port MachinePipeliner to NPM (#221676)
changes of note,
1. registers the pass with AMDGPUCodeGenPassBuilder::addPreRegAlloc()
2. Changes the core MachinePipeliner::run() method to return actual
"Changed" state
Commit: d0a59913f8cfc3041c9d284e36858aedbf8dfa0e
https://github.com/llvm/llvm-project/commit/d0a59913f8cfc3041c9d284e36858aedbf8dfa0e
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/include/llvm/IR/DerivedTypes.h
M llvm/include/llvm/IR/Type.h
M llvm/include/llvm/SandboxIR/Type.h
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/IR/Type.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/unittests/SandboxIR/TypesTest.cpp
Log Message:
-----------
[IR] Remove obsolete visited sets from type queries (NFC) (#221743)
Recursive types have been rejected since 2024 (#114799), making the
visited sets in type queries unnecessary.
Improves CTMark geomean -0.08% on aarch64-O0-g. Also improves
compile-time slightly for several other targets.
https://llvm-compile-time-tracker.com/compare.php?from=97cbc1e404b980edc58bfbcabb6f1c61793b624b&to=45c1423e7e38b6950ae760fc159ecb69cafdd691&stat=instructions%3Au
Assisted-by: codex
Commit: 531a8ac4c959dbdabcb4fea4a31beecde36bcdd9
https://github.com/llvm/llvm-project/commit/531a8ac4c959dbdabcb4fea4a31beecde36bcdd9
Author: Manuel Carrasco <Manuel.Carrasco at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
M llvm/test/CodeGen/SPIRV/debug-info/debug-function-definition-call-before-alloca.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-function-definition-calls.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-function-definition-external-call.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-inlined-at-recursive.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-inlined-at.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-block.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-calls.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-if-phi.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-loop-merge.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-loop.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-selection-merge.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-shared.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-no-line.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-scope-block.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-scope-no-scope-block.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-scope-no-scope.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-scope-same-line.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-scope-shared.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-scope.ll
Log Message:
-----------
Add support for NSDI DebugScope, DebugNoScope and DebugInlinedAt (#218959)
Add support for NSDI
[DebugScope](https://github.khronos.org/SPIRV-Registry/nonsemantic/NonSemantic.Shader.DebugInfo.html#DebugScope),
[DebugNoScope](https://github.khronos.org/SPIRV-Registry/nonsemantic/NonSemantic.Shader.DebugInfo.html#DebugNoScope)
and
[DebugInlinedAt](https://github.khronos.org/SPIRV-Registry/nonsemantic/NonSemantic.Shader.DebugInfo.html#DebugInlinedAt).
DebugScope/DebugNoScope are region delimiters following the same region
rule as DebugLine/DebugNoLine. The two regions are tracked separately
because a DebugScope region could span several DebugLine regions, and
either can skip emission on a cache miss at different times.
DebugInlinedAt is not an region instruction, so it is emitted at module
scope. We allow recursive traversal when building them to support
chains.
The PR also adds a test showing a limitation in the DebugLine
deduplication that is at the DILocation pointer level which may lead to
duplicate opcodes.
Commit: c4cd7b73e27839103badad11e4eff9baf3d53d84
https://github.com/llvm/llvm-project/commit/c4cd7b73e27839103badad11e4eff9baf3d53d84
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M lldb/source/Plugins/ExpressionParser/Clang/ClangASTImporter.cpp
M llvm/include/llvm/ADT/DenseMap.h
M llvm/lib/MCA/InstrBuilder.cpp
M llvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Transforms/Scalar/GVNSink.cpp
M llvm/unittests/ADT/DenseMapTest.cpp
M llvm/utils/lldbDataFormatters.py
M third-party/unittest/googletest/include/gtest/internal/custom/gtest-printers.h
Log Message:
-----------
[ADT] Give DenseMapPair its own members instead of a std::pair base. NFC (#221853)
std::pair declares a copy assignment operator, so it is not trivially
copyable. destroyAll and copyFrom therefore ask about KeyT and ValueT
separately. Hold first and second directly.
Conversion to std::pair is explicit; insert also takes a bucket, and a
converting constructor keeps range insert working across pair types.
Co-authored-by: Kazu Hirata <kazu at google.com>
Commit: 5bf967cb132bf6700474813f961f657af6ef83ea
https://github.com/llvm/llvm-project/commit/5bf967cb132bf6700474813f961f657af6ef83ea
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/test/CodeGen/target-data.c
M clang/test/CodeGenHIP/amdgpu-barrier-type.hip
M clang/test/CodeGenOpenCL/amdgpu-env-amdgcn.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
M lld/test/ELF/lto/amdgcn-oses.ll
M lld/test/ELF/lto/amdgcn.ll
M lld/test/ELF/lto/amdgpu.ll
M llvm/docs/AMDGPUUsage.rst
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/Support/AMDGPUAddrSpace.h
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/Type.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerExecSync.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/TargetParser/TargetDataLayout.cpp
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/always_uniform.ll
A llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync-and-module-lds.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync-and-sw-lds.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll
M llvm/test/CodeGen/AMDGPU/attributor-noalias-addrspace.ll
A llvm/test/CodeGen/AMDGPU/barrier-addrspace-dereference.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-named-barrier.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-named-barrier.ll
A llvm/test/CodeGen/AMDGPU/null-named-barrier-gv.ll
M llvm/test/CodeGen/AMDGPU/s-barrier-id-allocation.ll
A llvm/test/CodeGen/AMDGPU/s-barrier-lowering-bad-absolute-symbol.ll
A llvm/test/CodeGen/AMDGPU/s-barrier-lowering-wrong-gv-signature.ll
M llvm/test/CodeGen/AMDGPU/s-barrier-lowering.ll
M llvm/test/CodeGen/AMDGPU/s-barrier-signal-var-gep.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
M mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-barriers-gfx12.mlir
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
Log Message:
-----------
[RFC][AMDGPU] Add BARRIER address space (#209746)
Add a new BARRIER address space that is used for global variables that
are used to represent the barrier IDs in GFX12.5.
These barrier addresses just have values corresponding 1-1 to barrier
IDs. They are still implemented on top of LDS, but the offsetting
happens during an addrspacecast to generic, not whenever the barrier GV
is used.
The motivation for this is to make the relation between LDS and barrier
GVs explicit in the compiler. It does add a bit more complexity, but
that complexity was already there, just hidden by pretending barrier GVs
were actual LDS.
Commit: 59c5d5efb7343424d243e4a3972f7b24a07b115d
https://github.com/llvm/llvm-project/commit/59c5d5efb7343424d243e4a3972f7b24a07b115d
Author: Hans Wennborg <hans at hanshq.net>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
A llvm/test/CodeGen/X86/branch-on-zero.ll
Log Message:
-----------
[X86] Enable preferZeroCompareBranch() (#219919)
This makes CodeGenPrepare reorganize code such as:
```
%c = icmp eq i32 %x, 10
br %c, then, else
%a = add i32 %x, -10
```
into
```
%a = add i32 %x, -10
%cmp = icmp eq %a, 0
%br %cmp, then, else
```
so that the zero-compare and branch gets lowered to a JCC based on the
flags from the arithmetic instruction.
This was already enabled for ARM, SystemZ and RISC-V, but seems a good
fit for X86 too, as mentioned in Issue #58636.
Commit: cdab5d7b28a38112cf91784ea7d404d2d4c6a68e
https://github.com/llvm/llvm-project/commit/cdab5d7b28a38112cf91784ea7d404d2d4c6a68e
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/include/llvm/Support/AMDGPUAddrSpace.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
Log Message:
-----------
[AMDGPU] Add synthetic apertures and use them for barriers (#209748)
Define what a synthetic aperture is, and adjust the barrier AS
to use this new system. This makes the barrier AS even safer to
use as now we can use all 32 bits of it without ever risking
hitting a valid address of any kind (LDS or outside LDS).
Commit: 1770693262b32d2216d7224fd412d78ab07e1bfa
https://github.com/llvm/llvm-project/commit/1770693262b32d2216d7224fd412d78ab07e1bfa
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Add scalar-type-infer assert for casts (NFC) (#222258)
Casts require the ResultTy to be passed: add an assert to
computeScalarTypeForInstruction to guard against incorrect usage.
Commit: 39ffb93f2cc8b24d0b8a588dc042a4d931273ada
https://github.com/llvm/llvm-project/commit/39ffb93f2cc8b24d0b8a588dc042a4d931273ada
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/arm64-abi_align.ll
M llvm/test/CodeGen/AMDGPU/loop-address.ll
M llvm/test/CodeGen/Hexagon/insert4.ll
M llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll
M llvm/test/CodeGen/Hexagon/vect/vect-xor.ll
M llvm/test/Transforms/LoopVectorize/dbg.value.ll
M llvm/test/Transforms/LoopVectorize/vectorize-once.ll
M llvm/test/Transforms/SimplifyCFG/volatile-phioper.ll
Log Message:
-----------
llvm: Remove phantom fp-contract-model attributes from tests (#221925)
This attribute has never been consumed by upstream llvm,
or emitted by upstream clang. I can only guess this existed in
at least one downstream fork.
Commit: f796b25647e378a02482ef383f2db45804d8fb72
https://github.com/llvm/llvm-project/commit/f796b25647e378a02482ef383f2db45804d8fb72
Author: yingopq <115543042+yingopq at users.noreply.github.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.h
A llvm/test/CodeGen/Mips/jalr-no-mangle.ll
Log Message:
-----------
[Mips] Strip \x01 no-mangle prefix from R_MIPS_JALR symbol name (#219427)
R_MIPS_JALR relocation did not strip the \x01 no-mangle prefix, causing
linker to see two different symbols: my_target_sym and
\x01my_target_sym.
Use Mangler::getNameWithPrefix() to process the symbol name.
Fix #207470.
Commit: 68a77b6106d375eabb8a7ec2585a0f3e0382c4a2
https://github.com/llvm/llvm-project/commit/68a77b6106d375eabb8a7ec2585a0f3e0382c4a2
Author: Steffen Larsen <sholstla at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-wave32.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-wave64.hip
Log Message:
-----------
[CIR][AMDGPU] Implement inverse_ballot and read_exec codegen (#221661)
This commit implements the CIR codegen for the following AMDGPU
builtins:
- __builtin_amdgcn_inverse_ballot_w32
- __builtin_amdgcn_inverse_ballot_w64
- __builtin_amdgcn_read_exec
- __builtin_amdgcn_read_exec_lo
- __builtin_amdgcn_read_exec_hi
inverse_ballot_w32/w64 map to llvm.amdgcn.inverse.ballot. read_exec,
read_exec_lo and read_exec_hi read the exec mask as a ballot over an
all-true predicate, at least as wide as the wavefront.
Commit: 411a8eea0c269fff79700da1b3a9e71914718d4b
https://github.com/llvm/llvm-project/commit/411a8eea0c269fff79700da1b3a9e71914718d4b
Author: Robert Imschweiler <robert.imschweiler at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M openmp/runtime/src/i18n/en_US.txt
M openmp/runtime/src/kmp_settings.cpp
M openmp/runtime/src/kmp_traits.cpp
M openmp/runtime/src/kmp_traits.h
M openmp/runtime/unittests/Traits/TestOMPTraitParser.cpp
Log Message:
-----------
[libomp] Parse OMP_DEFAULT_DEVICE with new device trait parser (#176166)
... but do not yet expose the new functionalities to the user. This is a
backward compatible update that is going to be followed by the step to
the OpenMP 6.0 semantics as defined in 4.3.8.
Commit: 9a14832f08551e15620440391910bc6919904775
https://github.com/llvm/llvm-project/commit/9a14832f08551e15620440391910bc6919904775
Author: Valery Pykhtin <valery.pykhtin at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Log Message:
-----------
[AMDGPU] Check a wide copy dst reg against the dst operand's regclass (#221789)
The wide-copy check added in #214561 tested the destination against the
source operand's class. No test change: V_MOV_B64's source class VS_64
also accepts a VGPR destination, which is why it currently works. Adding
@robertvirany.
Co-authored-by: Claude <noreply at anthropic.com>
Commit: cd2f66534d425b3db62fea6df9703ffb87c6c3c5
https://github.com/llvm/llvm-project/commit/cd2f66534d425b3db62fea6df9703ffb87c6c3c5
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/GISelWorkList.h
Log Message:
-----------
[GlobalISel] Lazily reserve worklist maps (NFC) (#221900)
Small -0.03% geomean improvement on CTMark aarch64-O0-g, but consistent
little improvements across the board.
https://llvm-compile-time-tracker.com/compare.php?from=97cbc1e404b980edc58bfbcabb6f1c61793b624b&to=1729db67721b79fcb72469111d543e6df28c1185&stat=instructions:u
Assisted-by: codex
Commit: d6a334df0889026e0d91d3fc5adf452e0bbf0682
https://github.com/llvm/llvm-project/commit/d6a334df0889026e0d91d3fc5adf452e0bbf0682
Author: Petr Kurapov <petr.kurapov at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
A llvm/test/MC/AMDGPU/buffer-op-lds-operand.s
A llvm/test/tools/llvm-mca/AMDGPU/buffer-op-lds-operand.s
Log Message:
-----------
[AMDGPU][AsmParser]: Use dummy operand for parsing buffer LDS isAsync… (#219459)
… operand.
After the introduction of .async for LDS buffer ops variants, there a
similar mca crash addressed in
https://github.com/llvm/llvm-project/pull/165305. This parses a dummy
operand as a placeholder.
Commit: 4b8b168e8b6897fe3816949a316002ee8aff2e98
https://github.com/llvm/llvm-project/commit/4b8b168e8b6897fe3816949a316002ee8aff2e98
Author: Andreas Leitner <leitner.andi at googlemail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/read-register-src-flat-scratch-base.ll
A llvm/test/CodeGen/AMDGPU/read-write-register-src-flat-scratch-base-invalid-subtarget.ll
A llvm/test/CodeGen/AMDGPU/type-mismatch-src-flat-scratch-base.ll
A llvm/test/CodeGen/AMDGPU/write-register-src-flat-scratch-base.ll
Log Message:
-----------
[AMDGPU] Add getRegisterByName support for src_flat_scratch_base (#220560)
Expose `src_flat_scratch_base`, `src_flat_scratch_base_lo`, and
`src_flat_scratch_base_hi` through `llvm.read_register` /
`llvm.write_register`.
The implementation is basically the same as the existing named-register
support for `flat_scratch`
It errors out on targets without `FeatureGloballyAddressableScratch`
(pre-gfx1250).
Commit: 0c62d834abff9b180def1b32d3cf9c225d504994
https://github.com/llvm/llvm-project/commit/0c62d834abff9b180def1b32d3cf9c225d504994
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/LoopVectorize.h
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
M llvm/test/Transforms/LoopVectorize/replicate-region-cost-probability.ll
M llvm/unittests/Transforms/Vectorize/VPlanTestBase.h
Log Message:
-----------
[VPlan] Record estimated branch probabilities on VPlan0 for cost modeling (#216172)
Update execution frequency/probability tracking in VPlan to also include
estimates from BFI, and use the information in VPlan for VPlan-based
cost computations, removing another remaining IR-based lookup.
We need to differentiate between estimated and concrete profile
information when annotating branches with information from BFI (using
custom !vplan.prof.estimated metadata instead of !prof) and track if a
computed frequency contains any estimates using an extra bool which is
also encoded in the metadata (so we do not synthesize !prof
for such frequencies during codegen).
The new code should only request BFI if needed, and compile-time impact
should be in the noise:
https://llvm-compile-time-tracker.com/compare.php?from=8436dd4a2bfe57d0b3fb6c9c11c69d75c1d1bccb&to=4d60694fed5e5765d4f5a2a72aac7b8674e512e2&stat=instructions:u
PR: https://github.com/llvm/llvm-project/pull/216172
Commit: 17b659b8444a957ea2b42cb4e91d65897fee7558
https://github.com/llvm/llvm-project/commit/17b659b8444a957ea2b42cb4e91d65897fee7558
Author: Yao Qi <yao_qi at apple.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M lldb/unittests/Target/MemoryTest.cpp
Log Message:
-----------
[lldb] [unittests] Cover what the memory cache reads from the inferior (#221015)
`MemoryCache`'s tests checked how many bytes a read returned, never
which requests the cache made to get them, so a change to the request
shape could not fail a test. Add four tests over the request log
`DummyProcess` now keeps.
Two assert what the cache sends: `TestReadRequestShape` checks the
address and size of every request, and `TestReadRangesFromCaches` checks
that a range the cache already holds is served without reaching the
inferior.
`TestFlushAtTheTopOfTheAddressSpace` pins `Flush`'s current behavior at
the wrap, not correct behavior. When a flushed range wraps past
`UINT64_MAX`, `Flush` counts cache lines only from the start of the
range to the top of the address space, never the lines the wrapped
portion covers between address 0 and the range's end. This bug predates
this change; the following cache-partition change fixes it, and this
test's assertion that address 0 survives the flush will need to flip
once
that lands.
`TesetMemoryCacheRead` gains one assertion, that a line whose reply
falls short leaves the error alone, next to the two requests it already
checks.
Also add a `CacheTestProcess` helper and use it in the seven cache
tests, so each states its setup in two lines rather than thirteen, and
expose the L2 map next to L1 for assertions.
---------
Co-authored-by: Jonas Devlieghere <jonas at devlieghere.com>
Commit: 7f0421be7f82a64796fa002b85bedbd6eaacc57f
https://github.com/llvm/llvm-project/commit/7f0421be7f82a64796fa002b85bedbd6eaacc57f
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/test/CodeGen/AMDGPU/idemponent-atomics.ll
M llvm/test/CodeGen/AMDGPU/mmra.ll
Log Message:
-----------
[AMDGPU] Remove unsound idempotent atomicrmw to atomic load lowering (#218377)
An idempotent atomicrmw still holds a slot in the modification order, so
folding it to a plain load can drop synchronization the memory model
requires
Commit: 8e84c4a901a7fe6ba80b3c305b200c3e9bbc4606
https://github.com/llvm/llvm-project/commit/8e84c4a901a7fe6ba80b3c305b200c3e9bbc4606
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/arm64-abi_align.ll
M llvm/test/CodeGen/AMDGPU/loop-address.ll
M llvm/test/CodeGen/Hexagon/insert4.ll
M llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll
M llvm/test/CodeGen/Hexagon/vect/vect-xor.ll
M llvm/test/Transforms/LoopVectorize/dbg.value.ll
M llvm/test/Transforms/LoopVectorize/vectorize-once.ll
M llvm/test/Transforms/SimplifyCFG/volatile-phioper.ll
Log Message:
-----------
llvm: Remove phantom ssp-buffers-size attributes from tests (#221928)
"ssp-buffers-size" was never a real function attribute. There is
"stack-protector-buffer-size". This may have existed in a downstream
fork, but it's also irrelevant for these tests.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 4af454042b636fc6f7b1b99e178247989863b8e5
https://github.com/llvm/llvm-project/commit/4af454042b636fc6f7b1b99e178247989863b8e5
Author: Guray Ozen <guray.ozen at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M mlir/docs/Remarks.md
M mlir/include/mlir/IR/Remarks.h
M mlir/lib/IR/Remarks.cpp
M mlir/unittests/IR/RemarkTest.cpp
Log Message:
-----------
[MLIR][Remark] Expose RemarkEngine filter queries (#222262)
Expose following filter APIs publicly:
```
| Query | Answers |
|----------------------------------------------|------------------------------------------------------|
| `isAnyRemarkEnabled()` | At least one category filter is active |
| `isAnyRemarkEnabled(category)` | Some kind of remark is enabled for the category |
| `isRemarkEnabled(kind, category)` | Remarks of `kind` are enabled for the category |
| `is{Passed,Missed,Analysis,Failed}OptRemarkEnabled(category)` | Per-kind query |
```
Assisted by Claude Fable 5.1
Commit: 468a7300de067ec0581f51cbfb56421f4b13eaf0
https://github.com/llvm/llvm-project/commit/468a7300de067ec0581f51cbfb56421f4b13eaf0
Author: David Spickett <david.spickett at arm.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M lldb/source/Host/common/NativeProcessProtocol.cpp
Log Message:
-----------
[lldb][lldb-server] Log possible breakpoint PC in hex (#222285)
Commit: e87fb92a9719c1f1f0112e108f9444bb5b99ac49
https://github.com/llvm/llvm-project/commit/e87fb92a9719c1f1f0112e108f9444bb5b99ac49
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
A llvm/test/CodeGen/AArch64/fp-intrinsics-bf16.ll
Log Message:
-----------
[NFC][LLVM][AArch64] Add test coverage for scalar bfloat constrained intrinsics. (#222076)
Tests are a clone of fp-intrinsics-fp16.ll with s/half/bfloat/ applied
and failing tests (fcmp and i128 variants) removed.
Commit: 4e7628708d6d09c4051fd1fa54cb6b517db326fe
https://github.com/llvm/llvm-project/commit/4e7628708d6d09c4051fd1fa54cb6b517db326fe
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
Log Message:
-----------
[GlobalISel] Restrict value offset tracking to aggregates (NFC) (#221287)
The single-vreg fast path added in d30d5fe8dd5d3 still populated an
offset list, even though offsets are only necessary for aggregate
values.
This wasn't the only place doing so. Avoid creating or updating offset
lists for non-aggregate values and add an assertion to enforce this
invariant.
Small -0.04% geomean improvement on CTMark aarch64-O0-g.
https://llvm-compile-time-tracker.com/compare.php?from=97cbc1e404b980edc58bfbcabb6f1c61793b624b&to=2aeb9d236a2cacf8ab93722b8b629243384bae68&stat=instructions:u
Assisted-by: codex
Commit: cc38b29781cbc0a2b525a18833adf61c51375af2
https://github.com/llvm/llvm-project/commit/cc38b29781cbc0a2b525a18833adf61c51375af2
Author: Tianyi Chen <diannaaav at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/test/Misc/cc1as-darwin-target-variant-sdk-version.s
M clang/test/Misc/cc1as-darwin-target-variant-triple.s
M llvm/test/MC/MachO/diff-with-two-sections.s
M llvm/test/MC/MachO/weakdef.s
M llvm/test/MC/MachO/zero-space.s
A llvm/test/tools/llvm-readobj/MachO/cpu-capabilities.yaml
M llvm/test/tools/llvm-readobj/MachO/file-headers-arm64.test
M llvm/test/tools/llvm-readobj/MachO/file-headers.test
M llvm/tools/llvm-readobj/MachODumper.cpp
Log Message:
-----------
[llvm-readobj] Display Mach-O CPU capability bits (#221617)
The Mach-O file header output masks the capability bits out of
`cpusubtype`
without printing them separately, so this information is missing from
the
output.
Add a `CpuCapabilities` field to print the high byte in hexadecimal,
matching the numeric representation used by `llvm-objdump`.
Fixes #80198.
Assisted-by: OpenAI Codex (implementation, tests, and initial
description).
Commit: 6a20cac62912114cbc9208b565cf88fd73f21377
https://github.com/llvm/llvm-project/commit/6a20cac62912114cbc9208b565cf88fd73f21377
Author: Tianyi Chen <diannaaav at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/docs/CommandGuide/llvm-objdump.md
M llvm/tools/llvm-objdump/ObjdumpOpts.td
Log Message:
-----------
[llvm-objdump] Document selecting symbols containing commas (#221619)
The documentation does not clearly distinguish how
`--disassemble-symbols=`
and `--disassemble=<symbol>` handle their arguments, making it easy to
overlook how to select symbols whose names contain commas.
Update the command guide and help text to explain that the former
accepts
a comma-separated list of symbols, while the latter accepts a single
symbol
name and may be specified multiple times.
Assisted-by: OpenAI Codex
Commit: 95dfce1739bf2719f89a9f6673eb5b23f2d32b09
https://github.com/llvm/llvm-project/commit/95dfce1739bf2719f89a9f6673eb5b23f2d32b09
Author: David Green <david.green at arm.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SchedNeoverseV3.td
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-neon-instructions.s
Log Message:
-----------
[AArch64] Add Neoverse V3 scheduling info for v264 frecpe (#221917)
This was missing, falling back to the default information. It should be
like the others.
This is the Neoverse V3 equivalent of #219115
Commit: 3d2f88da6e15645080d852d52c32435b62aca97b
https://github.com/llvm/llvm-project/commit/3d2f88da6e15645080d852d52c32435b62aca97b
Author: Timur Golubovich <timur.golubovich at intel.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/avx512-masked-op-fusion.ll
Log Message:
-----------
[X86] Fix commuteSelect miscompile with double-used condition value (#219436)
The multi-use loop iterated `Cond->users()` which yields duplicates when
a select uses the condition in multiple operand positions. This caused a
double-commute and iterator corruption, leaving other selects with an
inverted condition but unswapped operands.
Remove the in-place mutation loop and return a new select node. The DAG
combiner visits each select independently and `getSetCC` CSEs the
inverted condition so all commuted selects share it.
Commit: 4200a8e34e488aaf9c1b5b1966aa4c1bbec8b4d5
https://github.com/llvm/llvm-project/commit/4200a8e34e488aaf9c1b5b1966aa4c1bbec8b4d5
Author: Oscar Priego <oscar.priegov at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86CompressEVEX.cpp
M llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
M llvm/test/CodeGen/X86/compress-evex-vpmov-blendv.mir
M llvm/test/CodeGen/X86/compress-evex-vpmov-kill.mir
Log Message:
-----------
[X86] Compress masked VPBLENDM using VBLENDV (#221838)
Fixes #221678.
This extends the X86 EVEX compression pass to recognize compatible
`VPMOVD2M/VPMOVQ2M + VPBLENDMD/VPBLENDMQ` patterns and replace them with
the corresponding VEX `VBLENDVPS/VBLENDVPD` instruction when the mask
width and element granularity match.
For example, the reported AVX-512 sequence:
```asm
vpslld $31, %xmm0, %xmm0
vpmovd2m %xmm0, %k1
vpblendmd %xmm1, %xmm2, %xmm0 {%k1}
```
is reduced to:
```asm
vpslld $31, %xmm0, %xmm0
vblendvps %xmm0, %xmm1, %xmm2, %xmm0
```
The fold is restricted to compatible producer/consumer pairs.
Mixed-width or mixed-element-granularity cases such as
`VPMOVD2MZ128 + VPBLENDMQZ256` are intentionally left unchanged.
The MIR coverage includes:
- 128-bit and 256-bit dword/qword positive cases.
- An incompatible-width negative case.
- Kill/liveness preservation for the reused vector mask.
The existing `avx512-regcall-NoMask.ll` codegen checks are also updated
to reflect the optimized `VBLENDVPS` sequence produced by this fold.
Local validation includes:
- `compress-evex-vpmov-blendv.mir`
- `compress-evex-vpmov-kill.mir`
- `avx512-regcall-NoMask.ll`
- `compress-evex-sign-mask.mir`
- `evex-to-vex-compress.mir`
- `bitcast-sign-mask.ll`
AI-assisted tools were used during investigation and development.
The resulting changes were reviewed, modified, validated, and tested by
me.
Signed-off-by: Oscar Priego Verdugo <oscar.priegov at gmail.com>
Commit: 79230407a26e8d7de47e4c8e7b7f7b0d63bee00c
https://github.com/llvm/llvm-project/commit/79230407a26e8d7de47e4c8e7b7f7b0d63bee00c
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/include/clang/AST/ASTContext.h
M clang/lib/AST/ASTContext.cpp
Log Message:
-----------
[clang][AST][NFC] Make ASTContext::isPFPField() static (#220265)
Commit: 09520670fec80a117bb34307ef684cf8bafbe71b
https://github.com/llvm/llvm-project/commit/09520670fec80a117bb34307ef684cf8bafbe71b
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M lldb/source/Target/StackFrameRecognizer.cpp
M lldb/test/API/commands/frame/recognizer/step-through/TestFrameRecognizerStepThrough.py
Log Message:
-----------
[lldb] Match frame recognizers by function when the frame has no symbol (#222060)
A frame can have a function without having a symbol: a PE/COFF image
built with DWARF carries no symbol table at all, so `symctx.symbol` is
null on Windows while `symctx.function` resolves fine from the debug
info. `GetRecognizerForFrame` bailed out on `!symbol`, so no frame
recognizer ever matched there.
Fall back to the function's start address when there is no symbol. The
symbol still wins when both are present, so this is a no-op on
ELF/Mach-O.
This fixes `TestFrameRecognizerStepThrough.py`.
Commit: 48ae4d3b158042b4ad77a6b23aa412aedac7105a
https://github.com/llvm/llvm-project/commit/48ae4d3b158042b4ad77a6b23aa412aedac7105a
Author: William Tran-Viet <wtranviet at proton.me>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M libcxx/include/__optional/optional_ref.h
M libcxx/test/std/utilities/optional/optional.monadic/transform.pass.cpp
Log Message:
-----------
[libc++] Fix `optional<T>::transform` into `optional<T&>` (#221506)
Resolves #220332
- Make `optional<T>` a friend of `optional<T&>`, and add tests.
Commit: 6b728014512aefa838e3b1674355589c901cdde2
https://github.com/llvm/llvm-project/commit/6b728014512aefa838e3b1674355589c901cdde2
Author: Alexander Wilson <rdtscp at meta.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M bolt/lib/Core/Relocation.cpp
M bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
M bolt/lib/Target/RISCV/RISCVMCSymbolizer.cpp
M bolt/lib/Target/RISCV/RISCVMCSymbolizer.h
A bolt/test/RISCV/call-relocation-pair.s
A bolt/test/RISCV/unsymbolized-call-edge.s
A bolt/test/RISCV/unsymbolized-call-entry.s
A bolt/test/RISCV/unsymbolized-call.s
A bolt/test/RISCV/unsymbolized-long-jump.s
Log Message:
-----------
[BOLT][RISCV] Fix AUIPC/JALR call rewriting (#216882)
This builds on the RISC-V decoder support from #217550 and the BOLT
target symbolizer and GOT relocation handling from #217944, both of
which are now merged.
`R_RISCV_CALL` and `R_RISCV_CALL_PLT` cover an AUIPC/JALR pair, but BOLT
treated them as four-byte relocations and decoded only the AUIPC
immediate. Read both instructions and combine their signed high and low
immediates so relocated call targets retain the low 12 bits.
LTO can also leave linker-resolved intra-section AUIPC/JALR calls
without relocations. On RV64, recognize standard call and tail-call
pairs during disassembly, reconstruct the target (including JALR
target-bit clearing), and attach an exact entry-point symbol before
function reordering. Alternate link-register preservation is provided by
the merged #218408.
This follows the RISC-V Unprivileged ISA sections on AUIPC and JALR:
https://docs.riscv.org/reference/isa/v20260120/unpriv/rv32.html
It also follows the RISC-V ELF psABI procedure-call relocations:
https://riscv-non-isa.github.io/riscv-elf-psabi-doc/#_relocations
Tests cover relocation-backed calls, relocation-free RV64 calls and tail
calls, exact function entry points, signed offsets, JALR target-bit
clearing, and rejection of near matches.
Validation:
- Rebuilt `llvm-bolt`, `llvm-mc`, `llvm-objdump`, `llvm-readelf`, and
`lld`.
- All 658 tests in `bolt/test/RISCV` and `llvm/test/MC/RISCV` pass on
current `main`.
**Scope:** Relocation-free recovery is intentionally RV64-only. RV32
XLEN-wrapped target arithmetic remains out of scope. Symbolizer
infrastructure and GOT correctness are provided by #217944 rather than
this PR.
Assisted-by: Codex
Commit: accf16eec44ec81449fe8cbf0ddd53c1ff567247
https://github.com/llvm/llvm-project/commit/accf16eec44ec81449fe8cbf0ddd53c1ff567247
Author: Mariya Podchishchaeva <Mariya.Podchishchaeva at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/include/clang/Lex/Lexer.h
M clang/lib/Parse/ParseExprCXX.cpp
M clang/lib/Parse/ParseTentative.cpp
A clang/test/Parser/cuda-operator-lesslessless.cu
Log Message:
-----------
[clang][CUDA/HIP] Fix parsing of `operator<<<...>` (#218384)
In CUDA mode Lexer merges `<<<` into a single token and Parser fails to
recognize that it is actually a template specialization of `operator<<`
and not a CUDA kernel call expression. Split `<<<` following operator
token to `<<` and `<`.
Commit: be7f0c897238a2d4ae742d1b6db50283069bdeef
https://github.com/llvm/llvm-project/commit/be7f0c897238a2d4ae742d1b6db50283069bdeef
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/arm64-abi_align.ll
M llvm/test/CodeGen/AMDGPU/loop-address.ll
M llvm/test/CodeGen/Hexagon/insert4.ll
M llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll
M llvm/test/CodeGen/Hexagon/vect/vect-xor.ll
M llvm/test/Transforms/LoopVectorize/dbg.value.ll
M llvm/test/Transforms/LoopVectorize/vectorize-once.ll
M llvm/test/Transforms/SimplifyCFG/volatile-phioper.ll
Log Message:
-----------
llvm: Remove phantom relocation-model attributes from tests (#221931)
"relocation-model" was never a real function attribute.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: a86b58566a2581160938db41fa258ff84457b80c
https://github.com/llvm/llvm-project/commit/a86b58566a2581160938db41fa258ff84457b80c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M lld/test/ELF/amdgpu-tid.s
M llvm/docs/AMDGPUUsage.rst
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/test/MC/AMDGPU/amdgcn-target-directive-conflict.s
M llvm/test/MC/AMDGPU/amdgcn_target_directive_from_eflags.s
M llvm/test/MC/AMDGPU/hsa-diag-v4.s
M llvm/test/MC/AMDGPU/hsa-tg-split.s
M llvm/test/MC/AMDGPU/hsa-v4.s
M llvm/test/MC/AMDGPU/hsa-v5-uses-dynamic-stack.s
M llvm/test/MC/AMDGPU/user-sgpr-count.s
M llvm/test/MC/AMDGPU/xnack-mask.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-cov5.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx10.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx90a.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx950.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-sgpr.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-vgpr.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx10.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx9.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-raw.s
Log Message:
-----------
AMDGPU: Remove xnack and sramecc subtarget features (#212792)
Now that these are controlled by module flags, the subtarget
features were just used for assembler and disassembler controls.
Now that the assembler and disassembler can infer these from
the e_flags and target directives, they are no longer necessary.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Commit: ebeb871f9a5fd31f088b7fb952c99cc4da17eeb1
https://github.com/llvm/llvm-project/commit/ebeb871f9a5fd31f088b7fb952c99cc4da17eeb1
Author: Tuomas Kärnä <tuomas.karna at intel.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
Log Message:
-----------
[MLIR][XeGPU] Restrict XeGPUPropagateLayout analysis scope (#221793)
This PR prevents concurrent access to traversal and mutation of the
shared IR by restricting the walk scope to determine program order
within each gpu.module.
Previously, although the pass is scoped to a single gpu.module, this
walk climbs all the way up to the enclosing top-level builtin.module and
traverses the entire module — including sibling gpu.modules. When there
is multiple gpu.modules, it causes concurrent traversal and mutation of
the shared IR and eventually leads to a segfault.
Assisted-by: Claude
Commit: b3e641630cbe0c25022e6033bdfc1cbf1fc215b4
https://github.com/llvm/llvm-project/commit/b3e641630cbe0c25022e6033bdfc1cbf1fc215b4
Author: Tomohiro Kashiwada <kikairoya at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/test/SemaCXX/dllimport.cpp
Log Message:
-----------
[Clang](NFC) Rewrite test/SemaCXX/dllimport.cpp as done for dllexport.cpp (#191391)
Commit: 2189cea443f1bb69861af2a1994b11f5aaa5be68
https://github.com/llvm/llvm-project/commit/2189cea443f1bb69861af2a1994b11f5aaa5be68
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
A llvm/test/Transforms/LoopVectorize/AArch64/select-first-index-narrow.ll
A llvm/test/Transforms/LoopVectorize/find-last-ptr-induction.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
A llvm/test/Transforms/LoopVectorize/select-first-index-narrow.ll
Log Message:
-----------
[LV] Add tests for argmin/argmax with a narrow index and ptr IVs (NFC) (#222290)
Extend test coverage for argmin/argmax with truncated IVs and pointer
inductions.
Commit: ef208564acbfc9e8fef0d6c436bac1681f1a6778
https://github.com/llvm/llvm-project/commit/ef208564acbfc9e8fef0d6c436bac1681f1a6778
Author: Kareem Ergawy <kergawy at nvidia.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M flang/include/flang/Optimizer/Analysis/AliasAnalysis.h
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/lib/Optimizer/Transforms/LoopInvariantCodeMotion.cpp
A flang/unittests/Optimizer/AliasAnalysisRecursiveEffectsCacheTest.cpp
M flang/unittests/Optimizer/CMakeLists.txt
Log Message:
-----------
[fir][aa] Add opt-in cache for use by fir `AliasAnalysis` clients (#221973)
Adds `AliasAnalysisRecursiveEffectsCache`, an opt-in cache that memoizes
per-operation read/write summaries so that `getModRef` on an operation
with `HasRecursiveMemoryEffects` does not re-walk its nested regions on
every query.
This is independent of the `getSource()` memoization added separately:
that one is keyed on (value, flags) and answers "what memory does this
value refer to", while this one is keyed on the operation and answers
"what does this operation and everything nested in it read and write".
LICM enables both, since it only hoists pure-read ops and so invalidates
neither.
Commit: 5dc123502ac6ef7de22c67685fe3519e88c51ce4
https://github.com/llvm/llvm-project/commit/5dc123502ac6ef7de22c67685fe3519e88c51ce4
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Log Message:
-----------
PowerPC: Drop AllowFPOpFusion from isProfitableToHoist (#221347)
Commit: ad21971d92794a9488a17f7592c44da1ada9554c
https://github.com/llvm/llvm-project/commit/ad21971d92794a9488a17f7592c44da1ada9554c
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M .github/new-prs-labeler.yml
M .github/workflows/libcxx-pr-conformance-tests.yaml
M .github/workflows/libcxx-pr-test-tools.yml
M .github/workflows/release-binaries.yml
M .mailmap
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/include/bolt/Passes/LivenessAnalysis.h
M bolt/lib/Core/Relocation.cpp
M bolt/lib/Passes/FixRISCVCallsPass.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
M bolt/lib/Target/RISCV/RISCVMCSymbolizer.cpp
M bolt/lib/Target/RISCV/RISCVMCSymbolizer.h
M bolt/lib/Target/X86/X86MCPlusBuilder.cpp
M bolt/test/RISCV/call-link-register.s
A bolt/test/RISCV/call-relocation-pair.s
A bolt/test/RISCV/conditional-tail-call-relocs.s
M bolt/test/RISCV/relax.s
A bolt/test/RISCV/unsymbolized-call-edge.s
A bolt/test/RISCV/unsymbolized-call-entry.s
A bolt/test/RISCV/unsymbolized-call.s
A bolt/test/RISCV/unsymbolized-long-jump.s
M bolt/unittests/Core/CMakeLists.txt
M bolt/unittests/Core/MCPlusBuilder.cpp
M clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp
M clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.h
M clang-tools-extra/clangd/InlayHints.cpp
M clang-tools-extra/clangd/unittests/InlayHintTests.cpp
M clang-tools-extra/docs/ReleaseNotes.md
A clang-tools-extra/docs/clang-tidy/checks/readability/function-cognitive-complexity.md
R clang-tools-extra/docs/clang-tidy/checks/readability/function-cognitive-complexity.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/function-size.md
R clang-tools-extra/docs/clang-tidy/checks/readability/function-size.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/identifier-length.md
R clang-tools-extra/docs/clang-tidy/checks/readability/identifier-length.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/identifier-naming.md
R clang-tools-extra/docs/clang-tidy/checks/readability/identifier-naming.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/implicit-bool-conversion.md
R clang-tools-extra/docs/clang-tidy/checks/readability/implicit-bool-conversion.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/inconsistent-declaration-parameter-name.md
R clang-tools-extra/docs/clang-tidy/checks/readability/inconsistent-declaration-parameter-name.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/inconsistent-ifelse-braces.md
R clang-tools-extra/docs/clang-tidy/checks/readability/inconsistent-ifelse-braces.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/isolate-declaration.md
R clang-tools-extra/docs/clang-tidy/checks/readability/isolate-declaration.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/magic-numbers.md
R clang-tools-extra/docs/clang-tidy/checks/readability/magic-numbers.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/make-member-function-const.md
R clang-tools-extra/docs/clang-tidy/checks/readability/make-member-function-const.rst
A clang-tools-extra/test/clang-tidy/checkers/readability/identifier-naming-allow-trailing-underscore.cpp
M clang/Maintainers.md
M clang/docs/AMDGPUSupport.md
M clang/docs/AddressSanitizer.md
M clang/docs/AllocToken.md
M clang/docs/AutomaticReferenceCounting.md
M clang/docs/Block-ABI-Apple.md
M clang/docs/BlockLanguageSpec.md
M clang/docs/BoundsSafety.md
M clang/docs/BoundsSafetyAdoptionGuide.md
M clang/docs/BoundsSafetyImplPlans.md
M clang/docs/CIR/ABILowering.md
M clang/docs/CIR/CleanupAndEHDesign.md
M clang/docs/CIR/CodeDuplication.md
M clang/docs/CMakeLists.txt
M clang/docs/CXXTypeAwareAllocators.md
M clang/docs/ClangLinkerWrapper.md
M clang/docs/ClangNVLinkWrapper.md
M clang/docs/ClangOffloadBundler.md
M clang/docs/ClangSYCLLinker.md
M clang/docs/ClangTransformerTutorial.md
M clang/docs/ConstantInterpreter.md
M clang/docs/ControlFlowIntegrity.md
M clang/docs/DataFlowAnalysisIntro.md
M clang/docs/DataFlowSanitizer.md
M clang/docs/DebuggingCoroutines.md
M clang/docs/DriverInternals.md
M clang/docs/FAQ.md
M clang/docs/FunctionEffectAnalysis.md
M clang/docs/HIPSupport.md
M clang/docs/HLSL/AvailabilityDiagnostics.md
M clang/docs/HLSL/EntryFunctions.md
M clang/docs/HLSL/ExpectedDifferences.md
M clang/docs/HLSL/FunctionCalls.md
M clang/docs/HLSL/HLSLIRReference.md
M clang/docs/HLSL/HLSLSupport.md
M clang/docs/HLSL/ResourceTypes.md
M clang/docs/HardwareAssistedAddressSanitizer.md
M clang/docs/InternalsManual.md
M clang/docs/LLVMExceptionHandlingCodeGen.md
M clang/docs/LanguageExtensions.md
M clang/docs/LeakSanitizer.md
M clang/docs/LibASTImporter.md
M clang/docs/LifetimeSafety.md
M clang/docs/MatrixTypes.md
M clang/docs/MemorySanitizer.md
M clang/docs/MisExpect.md
M clang/docs/Modules.md
M clang/docs/OffloadingDesign.md
M clang/docs/OpenCLSupport.md
M clang/docs/OpenMPSupport.md
M clang/docs/OverflowBehaviorTypes.md
M clang/docs/PCHInternals.md
M clang/docs/PointerAuthentication.md
M clang/docs/RISCVSupport.md
M clang/docs/RealtimeSanitizer.md
M clang/docs/ReleaseNotes.md
M clang/docs/SYCLSupport.md
M clang/docs/SafeBuffers.md
M clang/docs/SafeStack.md
M clang/docs/SanitizerCoverage.md
M clang/docs/SanitizerSpecialCaseList.md
M clang/docs/SanitizerStats.md
M clang/docs/ShadowCallStack.md
M clang/docs/SourceBasedCodeCoverage.md
M clang/docs/StandardCPlusPlusModules.md
M clang/docs/StructureProtection.md
M clang/docs/ThinLTO.md
M clang/docs/Toolchain.md
M clang/docs/TypeSanitizer.md
M clang/docs/UndefinedBehaviorSanitizer.md
M clang/docs/UsersManual.md
M clang/docs/WarningSuppressionMappings.md
A clang/docs/_static/custom.css
M clang/docs/analyzer/checkers.md
M clang/docs/analyzer/conf.py
M clang/docs/analyzer/developer-docs/DebugChecks.md
M clang/docs/analyzer/user-docs/Annotations.md
M clang/docs/analyzer/user-docs/CrossTranslationUnit.md
M clang/docs/analyzer/user-docs/FAQ.md
M clang/docs/analyzer/user-docs/TaintAnalysisConfiguration.md
M clang/docs/analyzer/user-docs/UsingWithXCode.md
M clang/docs/conf.py
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/AST/TypeBase.h
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/BuiltinsAMDGPUDocs.td
M clang/include/clang/Basic/BuiltinsX86.td
M clang/include/clang/Basic/BuiltinsX86_64.td
M clang/include/clang/Basic/DiagnosticDocs.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRCUDAAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIREnumAttr.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
M clang/include/clang/CIR/Interfaces/CIROpInterfaces.td
M clang/include/clang/Lex/Lexer.h
M clang/include/clang/Options/ClangOptionDocs.td
M clang/include/clang/Options/FlangOptions.td
M clang/include/clang/Options/Options.td
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/Program.cpp
M clang/lib/AST/ByteCode/Record.h
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/ODRDiagsEmitter.cpp
M clang/lib/AST/ODRHash.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/Type.cpp
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinNVPTX.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CMakeLists.txt
M clang/lib/CIR/Dialect/Transforms/HoistAllocas.cpp
M clang/lib/CIR/FrontendAction/CMakeLists.txt
M clang/lib/CIR/Interfaces/CMakeLists.txt
M clang/lib/CIR/Lowering/CMakeLists.txt
M clang/lib/CIR/Lowering/DirectToLLVM/CMakeLists.txt
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/CGObjCMac.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/CodeGen/MicrosoftCXXABI.cpp
M clang/lib/CodeGen/TargetBuiltins/X86.cpp
M clang/lib/Driver/ToolChains/ZOS.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Headers/bmi2intrin.h
M clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h
M clang/lib/Headers/riscv_packed_simd.h
M clang/lib/Parse/ParseExprCXX.cpp
M clang/lib/Parse/ParseTentative.cpp
M clang/lib/Sema/SemaAttr.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineCXX.cpp
M clang/test/AST/absurdly_big_struct.cpp
M clang/test/Analysis/dtor-array.cpp
M clang/test/CIR/CodeGen/atomic-scoped.c
M clang/test/CIR/CodeGen/atomic.c
M clang/test/CIR/CodeGen/callsite-inline-attributes.cpp
M clang/test/CIR/CodeGen/vector-strict-fp.cpp
A clang/test/CIR/CodeGenCUDA/builtins-nvvm-fma-oob.cu
A clang/test/CIR/CodeGenCUDA/builtins-nvvm-half.cu
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-vi-f16.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-wave32.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-wave64.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
A clang/test/CIR/CodeGenHIP/ternary-struct-addrspace.hip
M clang/test/CIR/CodeGenOpenMP/target-map.c
M clang/test/CIR/IR/inline-attrs.cir
M clang/test/CIR/IR/invalid-call.cir
M clang/test/CIR/Lowering/lifetime.cir
M clang/test/CIR/Lowering/stack-save-restore.cir
M clang/test/CIR/Transforms/abi-lowering/byval-sret-arg-attr-lowering.cir
M clang/test/CIR/Transforms/abi-lowering/extend-signed-arg.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-bitint.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-complex.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-empty-class.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-scalars.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-struct-direct.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-union-coerce-shapes.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-union.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-variadic-call.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-vector.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-vptr.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-wide-floats.cir
M clang/test/CIR/Transforms/hoist-allocas.cir
M clang/test/CMakeLists.txt
M clang/test/CodeGen/AArch64/sme-inline-callees-streaming-attrs.c
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M clang/test/CodeGen/target-builtin-noerror.c
M clang/test/CodeGen/target-data.c
M clang/test/CodeGenCUDA/fp-contract.cu
M clang/test/CodeGenCoroutines/coro-destructor-of-final_suspend.cpp
M clang/test/CodeGenHIP/amdgpu-barrier-type.hip
M clang/test/CodeGenHLSL/builtins/select.hlsl
M clang/test/CodeGenOpenCL/address-spaces-conversions.cl
M clang/test/CodeGenOpenCL/amdgpu-env-amdgcn.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
M clang/test/CodeGenOpenCL/size_t.cl
M clang/test/Driver/modules-driver-depscan-log.cpp
A clang/test/Driver/nodefaultrtlibs.c
M clang/test/Misc/cc1as-darwin-target-variant-sdk-version.s
M clang/test/Misc/cc1as-darwin-target-variant-triple.s
A clang/test/Modules/odr-hash-using-declarations.cppm
A clang/test/Modules/pr222002.cppm
M clang/test/Modules/pr76638.cppm
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper-image.c
M clang/test/OpenMP/amdgcn-attributes.cpp
M clang/test/OpenMP/amdgcn_target_device_vla.cpp
M clang/test/OpenMP/amdgpu_target_with_aligned_attribute.c
M clang/test/OpenMP/bug60602.cpp
M clang/test/OpenMP/distribute_parallel_for_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_if_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_num_threads_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_private_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_proc_bind_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_if_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_lastprivate_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_num_threads_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_proc_bind_codegen.cpp
M clang/test/OpenMP/nvptx_SPMD_codegen.cpp
M clang/test/OpenMP/nvptx_distribute_parallel_generic_mode_codegen.cpp
M clang/test/OpenMP/nvptx_lambda_capturing.cpp
M clang/test/OpenMP/nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp
M clang/test/OpenMP/nvptx_target_teams_codegen.cpp
M clang/test/OpenMP/nvptx_target_teams_distribute_codegen.cpp
M clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp
M clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_generic_mode_codegen.cpp
M clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp
M clang/test/OpenMP/nvptx_target_teams_generic_loop_codegen.cpp
M clang/test/OpenMP/ompx_attributes_codegen.cpp
M clang/test/OpenMP/parallel_if_codegen_PR51349.cpp
M clang/test/OpenMP/reduction_complex.c
M clang/test/OpenMP/reduction_implicit_map.cpp
M clang/test/OpenMP/scope_codegen.cpp
M clang/test/OpenMP/target_codegen_global_capture.cpp
M clang/test/OpenMP/target_default_codegen.cpp
M clang/test/OpenMP/target_dyn_groupprivate_codegen.cpp
M clang/test/OpenMP/target_map_codegen_03.cpp
M clang/test/OpenMP/target_num_teams_num_threads_attributes.cpp
M clang/test/OpenMP/target_ompx_dyn_cgroup_mem_codegen.cpp
M clang/test/OpenMP/target_parallel_codegen.cpp
M clang/test/OpenMP/target_parallel_for_codegen.cpp
M clang/test/OpenMP/target_parallel_for_reduction_task_codegen.cpp
M clang/test/OpenMP/target_parallel_for_simd_codegen.cpp
M clang/test/OpenMP/target_parallel_for_simd_tl_codegen.cpp
M clang/test/OpenMP/target_parallel_for_tl_codegen.cpp
M clang/test/OpenMP/target_parallel_generic_loop_codegen-1.cpp
M clang/test/OpenMP/target_parallel_generic_loop_codegen-2.cpp
M clang/test/OpenMP/target_parallel_generic_loop_codegen.cpp
M clang/test/OpenMP/target_parallel_generic_loop_tl_codegen.cpp
M clang/test/OpenMP/target_parallel_generic_loop_uses_allocators_codegen.cpp
M clang/test/OpenMP/target_parallel_if_codegen.cpp
M clang/test/OpenMP/target_parallel_num_threads_codegen.cpp
M clang/test/OpenMP/target_parallel_num_threads_strict_codegen.cpp
M clang/test/OpenMP/target_parallel_reduction_task_codegen.cpp
M clang/test/OpenMP/target_parallel_tl_codegen.cpp
M clang/test/OpenMP/target_teams_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_if_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_order_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_proc_bind_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_task_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_openmp52_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_lastprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_proc_bind_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_reduction_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_codegen-1.cpp
M clang/test/OpenMP/target_teams_generic_loop_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_codegen_as_parallel_for.cpp
M clang/test/OpenMP/target_teams_generic_loop_collapse_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_if_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_order_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_reduction_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_uses_allocators_codegen.cpp
M clang/test/OpenMP/target_teams_reduction_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_copyin_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_if_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_lastprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_private_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_proc_bind_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_reduction_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_reduction_task_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_collapse_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_if_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_if_openmp52_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_lastprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_num_threads_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_private_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_proc_bind_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_reduction_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp
A clang/test/Parser/cuda-operator-lesslessless.cu
M clang/test/Parser/recovery.cpp
M clang/test/Sema/assign.c
A clang/test/Sema/global-explicit-register-undefined-type.c
A clang/test/Sema/riscv-pget-index-out-of-range.c
M clang/test/SemaCXX/MicrosoftSuper.cpp
M clang/test/SemaCXX/cxx20-default-compare.cpp
M clang/test/SemaCXX/dllimport.cpp
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M llvm/lib/Support/CMakeLists.txt
M llvm/lib/Support/DataExtractor.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64SchedNeoverseV3.td
M llvm/lib/Target/AArch64/AArch64SchedNeoverseV3AE.td
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHazardLatency.cpp
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
M llvm/lib/Target/AMDGPU/AMDGPULowerExecSync.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
M llvm/lib/Target/AMDGPU/AMDGPUReserveWWMRegs.cpp
M llvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/ARM/ARMInstrInfo.cpp
M llvm/lib/Target/ARM/ARMInstrVFP.td
M llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
M llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp
M llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.h
M llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
M llvm/lib/Target/M68k/M68kInstrInfo.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.h
M llvm/lib/Target/Mips/MipsInstrFPU.td
M llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
M llvm/lib/Target/Mips/MipsSEISelLowering.cpp
M llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
M llvm/lib/Target/Mips/MipsScheduleGeneric.td
M llvm/lib/Target/Mips/MipsScheduleP5600.td
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
M llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
M llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
M llvm/lib/Target/X86/X86CompressEVEX.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86InstrSNP.td
M llvm/lib/Target/XCore/Disassembler/CMakeLists.txt
M llvm/lib/Target/XCore/XCoreISelLowering.cpp
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/lib/TargetParser/TargetDataLayout.cpp
M llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/IPO/ExpandVariadics.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/IPO/OpenMPOpt.cpp
M llvm/lib/Transforms/IPO/SampleProfile.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/GVNHoist.cpp
M llvm/lib/Transforms/Scalar/GVNSink.cpp
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/LoopFlatten.cpp
M llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
M llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
M llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/CMakeLists.txt
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPMemoryUtils.cpp
A llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPMemoryUtils.h
A llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPReductionUtils.cpp
A llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPReductionUtils.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Scheduler.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/lib/Transforms/Vectorize/VPlanValue.h
M llvm/runtimes/CMakeLists.txt
M llvm/test/Analysis/BasicAA/call-attrs.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/addrspacecast.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/addrspacecast.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/always_uniform.ll
M llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
A llvm/test/Bitcode/amdgcn-addrspacecast-nonnull.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
M llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir
M llvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-and.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-crash.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-commute-shift.mir
M llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll
M llvm/test/CodeGen/AArch64/GlobalISel/swiftself.ll
M llvm/test/CodeGen/AArch64/arm64-abi_align.ll
M llvm/test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll
M llvm/test/CodeGen/AArch64/arm64-build-vector.ll
M llvm/test/CodeGen/AArch64/arm64-popcnt.ll
M llvm/test/CodeGen/AArch64/arm64-tbl.ll
M llvm/test/CodeGen/AArch64/arm64-vmul.ll
M llvm/test/CodeGen/AArch64/arm64-xaluo.ll
M llvm/test/CodeGen/AArch64/cmpbr-early-ifcvt.mir
A llvm/test/CodeGen/AArch64/fp-intrinsics-bf16.ll
M llvm/test/CodeGen/AArch64/fp-veclib-expansion.ll
M llvm/test/CodeGen/AArch64/i128-math.ll
M llvm/test/CodeGen/AArch64/i256-math.ll
M llvm/test/CodeGen/AArch64/mul-i128-overflow.ll
M llvm/test/CodeGen/AArch64/neon-anyof-splat.ll
M llvm/test/CodeGen/AArch64/neon-shuffle-vector-tbl.ll
A llvm/test/CodeGen/AArch64/overflow-vec.ll
M llvm/test/CodeGen/AArch64/overflow.ll
M llvm/test/CodeGen/AArch64/pdep.ll
M llvm/test/CodeGen/AArch64/pext.ll
M llvm/test/CodeGen/AArch64/pr55644.ll
M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/merge-values-s16-true16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-merge-readanylane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
A llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-gas.ll
A llvm/test/CodeGen/AMDGPU/addrspacecast-nonnull.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync-and-module-lds.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync-and-sw-lds.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll
M llvm/test/CodeGen/AMDGPU/attributor-noalias-addrspace.ll
A llvm/test/CodeGen/AMDGPU/barrier-addrspace-dereference.ll
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
M llvm/test/CodeGen/AMDGPU/dpp_combine.mir
M llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
A llvm/test/CodeGen/AMDGPU/dpp_combine_rev_opcode.ll
A llvm/test/CodeGen/AMDGPU/dpp_combine_rev_opcode.mir
A llvm/test/CodeGen/AMDGPU/early-lis-two-address-regsequence-undef.mir
M llvm/test/CodeGen/AMDGPU/fdot2.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.v2f16.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.v2f16.ll
M llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
M llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
M llvm/test/CodeGen/AMDGPU/idemponent-atomics.ll
A llvm/test/CodeGen/AMDGPU/insert-delay-alu-ldsdma.mir
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-named-barrier.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-named-barrier.ll
A llvm/test/CodeGen/AMDGPU/ldsdma-not-coexec-valu.mir
A llvm/test/CodeGen/AMDGPU/ldsdma-not-valu-wait-sgpr.mir
R llvm/test/CodeGen/AMDGPU/llvm.amdgcn.addrspacecast.nonnull.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/loop-address.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-opt.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mmra.ll
A llvm/test/CodeGen/AMDGPU/null-named-barrier-gv.ll
M llvm/test/CodeGen/AMDGPU/prevent-fmul-hoist-ir.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-proper-value-replacement.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
A llvm/test/CodeGen/AMDGPU/read-register-src-flat-scratch-base.ll
A llvm/test/CodeGen/AMDGPU/read-write-register-src-flat-scratch-base-invalid-subtarget.ll
A llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-reserved-wwm-vgpr.ll
M llvm/test/CodeGen/AMDGPU/s-barrier-id-allocation.ll
A llvm/test/CodeGen/AMDGPU/s-barrier-lowering-bad-absolute-symbol.ll
A llvm/test/CodeGen/AMDGPU/s-barrier-lowering-wrong-gv-signature.ll
M llvm/test/CodeGen/AMDGPU/s-barrier-lowering.ll
M llvm/test/CodeGen/AMDGPU/s-barrier-signal-var-gep.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll
M llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-epilog-phi.mir
M llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-gen-structure.mir
M llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-loop-carried-mem.mir
M llvm/test/CodeGen/AMDGPU/true16-fold.mir
A llvm/test/CodeGen/AMDGPU/type-mismatch-src-flat-scratch-base.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
M llvm/test/CodeGen/AMDGPU/waterfall-call-inreg-agpr.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/workitem-intrinsic-opts.ll
A llvm/test/CodeGen/AMDGPU/write-register-src-flat-scratch-base.ll
M llvm/test/CodeGen/ARM/build-attributes.ll
A llvm/test/CodeGen/ARM/eabi-attribute-fp-rounding-strictfp.ll
M llvm/test/CodeGen/ARM/fnmul.ll
M llvm/test/CodeGen/ARM/returned-ext.ll
M llvm/test/CodeGen/ARM/struct-byval-loop.ll
M llvm/test/CodeGen/DirectX/ResourceAccess/handle-cases.ll
M llvm/test/CodeGen/DirectX/ResourceAccess/handle-to-index.ll
M llvm/test/CodeGen/DirectX/ResourceAccess/looped-phi-nodes-resolved.ll
M llvm/test/CodeGen/DirectX/ResourceAccess/looped-phi-nodes.ll
A llvm/test/CodeGen/Hexagon/const-prop-undef.mir
M llvm/test/CodeGen/Hexagon/insert4.ll
M llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll
M llvm/test/CodeGen/Hexagon/vect/vect-xor.ll
M llvm/test/CodeGen/M68k/multiple-return.ll
A llvm/test/CodeGen/MIR/AMDGPU/addrspacecast-nonnull.mir
A llvm/test/CodeGen/Mips/jalr-no-mangle.ll
M llvm/test/CodeGen/Mips/llvm-ir/load.ll
M llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
M llvm/test/CodeGen/Mips/mips1-load-in-delay-slot.ll
A llvm/test/CodeGen/Mips/mips1-not-support-ldc1-sdc1.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-1cta.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-2cta.ll
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-override.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm100.ll
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-validate-data.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-gather4.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-im2colw.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-im2colw128.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-invalid.ll
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-mc32.ll
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-override.ll
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-validate-data.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g-im2colw.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g-scatter4.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g.ll
M llvm/test/CodeGen/NVPTX/forward-ld-param.ll
A llvm/test/CodeGen/PowerPC/vsx-swap-removal-undef.mir
A llvm/test/CodeGen/RISCV/GlobalISel/load-store.ll
M llvm/test/CodeGen/RISCV/and-negpow2-cmp.ll
M llvm/test/CodeGen/RISCV/rvv/shrinkwrap.ll
M llvm/test/CodeGen/RISCV/shrinkwrap.ll
M llvm/test/CodeGen/SPARC/64abi.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-function-definition-call-before-alloca.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-function-definition-calls.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-function-definition-external-call.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-inlined-at-recursive.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-inlined-at.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-block.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-calls.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-if-phi.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-loop-merge.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-loop.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-selection-merge.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-shared.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-no-line.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-scope-block.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-scope-no-scope-block.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-scope-no-scope.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-scope-same-line.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-scope-shared.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-scope.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/acos_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/asin_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/atan_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/ceil_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cos_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cosh_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp2_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/floor_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log10_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log2_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/roundeven_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sin_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sinh_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sqrt_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tan_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tanh_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/trunc_mat.ll
M llvm/test/CodeGen/SystemZ/args-14.ll
M llvm/test/CodeGen/SystemZ/call-zos-01.ll
A llvm/test/CodeGen/Thumb2/LowOverheadLoops/dbg-verify.ll
M llvm/test/CodeGen/VE/Scalar/call.ll
M llvm/test/CodeGen/VE/Scalar/va_callee.ll
M llvm/test/CodeGen/VE/Vector/fastcc_caller.ll
M llvm/test/CodeGen/WebAssembly/signext-zeroext-callsite.ll
M llvm/test/CodeGen/X86/PR40322.ll
A llvm/test/CodeGen/X86/active_lane_mask.ll
M llvm/test/CodeGen/X86/apx/adc.ll
M llvm/test/CodeGen/X86/apx/flags-copy-lowering.ll
A llvm/test/CodeGen/X86/atomic-cmp-fold.ll
M llvm/test/CodeGen/X86/atomic-unordered.ll
M llvm/test/CodeGen/X86/avx512-icmp-sle-zero.ll
M llvm/test/CodeGen/X86/avx512-masked-op-fusion.ll
M llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
M llvm/test/CodeGen/X86/avx512fp16-frem.ll
M llvm/test/CodeGen/X86/bfloat.ll
A llvm/test/CodeGen/X86/bitcast-sign-mask.ll
M llvm/test/CodeGen/X86/bool-zext.ll
A llvm/test/CodeGen/X86/branch-on-zero.ll
M llvm/test/CodeGen/X86/clmul-vector-256.ll
M llvm/test/CodeGen/X86/clmul-vector-512.ll
M llvm/test/CodeGen/X86/clmul-vector.ll
M llvm/test/CodeGen/X86/clmul.ll
A llvm/test/CodeGen/X86/compress-evex-sign-mask.mir
M llvm/test/CodeGen/X86/compress-evex-vpmov-blendv.mir
M llvm/test/CodeGen/X86/compress-evex-vpmov-kill.mir
M llvm/test/CodeGen/X86/huge-stack.ll
M llvm/test/CodeGen/X86/llvm.sincos.vec.ll
M llvm/test/CodeGen/X86/overflow-intrinsic-setcc-fold.ll
M llvm/test/CodeGen/X86/pdep-vector-128.ll
M llvm/test/CodeGen/X86/pdep-vector-256.ll
M llvm/test/CodeGen/X86/pdep-vector-512.ll
M llvm/test/CodeGen/X86/pext-vector-128.ll
M llvm/test/CodeGen/X86/pext-vector-256.ll
M llvm/test/CodeGen/X86/pext-vector-512.ll
M llvm/test/CodeGen/X86/pr1505b.ll
M llvm/test/CodeGen/X86/return-ext.ll
M llvm/test/CodeGen/X86/select-lea.ll
M llvm/test/CodeGen/X86/smul-with-overflow.ll
M llvm/test/CodeGen/X86/smul_fix_sat.ll
M llvm/test/CodeGen/X86/smul_fix_sat_constants.ll
M llvm/test/CodeGen/X86/stack-align.ll
M llvm/test/CodeGen/X86/subcarry.ll
M llvm/test/CodeGen/X86/swifterror.ll
M llvm/test/CodeGen/X86/ucmp.ll
M llvm/test/CodeGen/X86/umul-with-carry.ll
M llvm/test/CodeGen/X86/umul-with-overflow.ll
M llvm/test/CodeGen/X86/umul_fix_sat.ll
M llvm/test/CodeGen/X86/umulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/X86/umulo-64-legalisation-lowering.ll
M llvm/test/CodeGen/X86/var-permute-128.ll
M llvm/test/CodeGen/X86/vec_smulo.ll
M llvm/test/CodeGen/X86/vec_umulo.ll
M llvm/test/CodeGen/X86/vector-compress.ll
M llvm/test/CodeGen/X86/vector-fshl-128.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll
M llvm/test/CodeGen/X86/vector-shuffle-avx512.ll
M llvm/test/CodeGen/X86/vector-shuffle-v192.ll
M llvm/test/CodeGen/X86/xmulo.ll
M llvm/test/CodeGen/X86/znver-pdep.ll
M llvm/test/CodeGen/X86/znver-pext.ll
M llvm/test/Instrumentation/ThreadSanitizer/tsan_basic.ll
M llvm/test/MC/AMDGPU/amdgcn-target-directive-conflict.s
M llvm/test/MC/AMDGPU/amdgcn_target_directive_from_eflags.s
A llvm/test/MC/AMDGPU/buffer-op-lds-operand.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vopd_errs.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
M llvm/test/MC/AMDGPU/gfx13_asm_vop3.s
M llvm/test/MC/AMDGPU/hsa-diag-v4.s
M llvm/test/MC/AMDGPU/hsa-tg-split.s
M llvm/test/MC/AMDGPU/hsa-v4.s
M llvm/test/MC/AMDGPU/hsa-v5-uses-dynamic-stack.s
M llvm/test/MC/AMDGPU/misaligned-vgpr-tuples-err.s
M llvm/test/MC/AMDGPU/user-sgpr-count.s
M llvm/test/MC/AMDGPU/xnack-mask.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
M llvm/test/MC/Disassembler/X86/x86-64.txt
M llvm/test/MC/MachO/diff-with-two-sections.s
M llvm/test/MC/MachO/weakdef.s
M llvm/test/MC/MachO/zero-space.s
M llvm/test/MC/RISCV/rv32p-invalid.s
M llvm/test/MC/RISCV/rv32p-valid.s
M llvm/test/MC/X86/SNP-64.s
M llvm/test/Other/new-pm-O0-ep-callbacks.ll
M llvm/test/Other/new-pm-thinlto-postlink-defaults.ll
M llvm/test/TableGen/AMDGPUTargetDefSubArchSpelling.td
A llvm/test/TableGen/RuntimeLibcallEmitter-library-dispatch.td
M llvm/test/TableGen/RuntimeLibcallEmitter-library-grouping.td
M llvm/test/TableGen/RuntimeLibcallEmitter-library-name-merge.td
M llvm/test/ThinLTO/X86/memprof-funcassigncloning.ll
M llvm/test/ThinLTO/X86/memprof-funcassigncloning2.ll
M llvm/test/Transforms/AggressiveInstCombine/trunc_vector_instrs.ll
A llvm/test/Transforms/Attributor/indirect_call_program_address_space.ll
M llvm/test/Transforms/ConstraintElimination/add-nsw.ll
M llvm/test/Transforms/ConstraintElimination/cond-used-in-phi.ll
M llvm/test/Transforms/ConstraintElimination/header-induction-start-bounds.ll
M llvm/test/Transforms/ConstraintElimination/induction-condition-in-loop-exit-postinc.ll
M llvm/test/Transforms/ConstraintElimination/induction-condition-in-loop-exit.ll
M llvm/test/Transforms/ConstraintElimination/induction-nowrap-from-scev-not-ir.ll
M llvm/test/Transforms/ConstraintElimination/loops.ll
M llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-cfg.ll
M llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-decrement.ll
M llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-wrapping.ll
M llvm/test/Transforms/ConstraintElimination/pr70510.ll
M llvm/test/Transforms/ConstraintElimination/transfer-signed-facts-to-unsigned-is-known-non-negative.ll
M llvm/test/Transforms/ConstraintElimination/wrapping-math.ll
M llvm/test/Transforms/Coroutines/ArgAddr.ll
M llvm/test/Transforms/Coroutines/coro-align16.ll
M llvm/test/Transforms/Coroutines/coro-align32.ll
M llvm/test/Transforms/Coroutines/coro-align64-02.ll
M llvm/test/Transforms/Coroutines/coro-align64.ll
M llvm/test/Transforms/Coroutines/coro-align8-02.ll
M llvm/test/Transforms/Coroutines/coro-align8.ll
M llvm/test/Transforms/Coroutines/coro-alloca-01.ll
M llvm/test/Transforms/Coroutines/coro-alloca-02.ll
M llvm/test/Transforms/Coroutines/coro-alloca-03.ll
M llvm/test/Transforms/Coroutines/coro-alloca-04.ll
M llvm/test/Transforms/Coroutines/coro-alloca-06.ll
M llvm/test/Transforms/Coroutines/coro-alloca-08.ll
M llvm/test/Transforms/Coroutines/coro-byval-param.ll
M llvm/test/Transforms/Coroutines/coro-catchswitch.ll
M llvm/test/Transforms/Coroutines/coro-eh-aware-edge-split-01.ll
M llvm/test/Transforms/Coroutines/coro-eh-aware-edge-split-02.ll
M llvm/test/Transforms/Coroutines/coro-frame-arrayalloca.ll
M llvm/test/Transforms/Coroutines/coro-frame-reuse-alloca-01.ll
M llvm/test/Transforms/Coroutines/coro-frame-reuse-alloca-02.ll
M llvm/test/Transforms/Coroutines/coro-frame-reuse-alloca-04.ll
M llvm/test/Transforms/Coroutines/coro-frame-reuse-alloca-05.ll
M llvm/test/Transforms/Coroutines/coro-param-copy.ll
M llvm/test/Transforms/Coroutines/coro-spill-defs-before-corobegin.ll
A llvm/test/Transforms/Coroutines/coro-split-index-datalayout.ll
M llvm/test/Transforms/Coroutines/coro-split-sink-lifetime-01.ll
M llvm/test/Transforms/Coroutines/coro-split-sink-lifetime-02.ll
M llvm/test/Transforms/Coroutines/coro-split-sink-lifetime-03.ll
M llvm/test/Transforms/Coroutines/coro-split-sink-lifetime-04.ll
M llvm/test/Transforms/Coroutines/coro-split-tbaa-md.ll
M llvm/test/Transforms/DeadArgElim/deadexternal.ll
M llvm/test/Transforms/GVN/PRE/no-phi-translate.ll
M llvm/test/Transforms/GVN/PRE/no-pre-load-for-token-like.ll
M llvm/test/Transforms/GVN/pr46054-md-nonlocaldefcache-cleanup.ll
M llvm/test/Transforms/Inline/access-attributes-prop.ll
M llvm/test/Transforms/InstCombine/trunc.ll
M llvm/test/Transforms/JumpThreading/update-bpi-bfi-unfold-select.ll
M llvm/test/Transforms/LCSSA/token-like-live-out.ll
A llvm/test/Transforms/LoopFlatten/invalidate-scev-pr203176.ll
M llvm/test/Transforms/LoopUnroll/RISCV/runtime-unroll-max-trip-count.ll
M llvm/test/Transforms/LoopUnroll/RISCV/unroll.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalar-steps-cost.ll
A llvm/test/Transforms/LoopVectorize/AArch64/select-first-index-narrow.ll
A llvm/test/Transforms/LoopVectorize/RISCV/scatter-type-mismatch.ll
M llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
M llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-print-before-after-all.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-flags.ll
A llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-intrinsic.ll
M llvm/test/Transforms/LoopVectorize/X86/amdlibm-calls.ll
M llvm/test/Transforms/LoopVectorize/X86/funclet.ll
M llvm/test/Transforms/LoopVectorize/dbg.value.ll
A llvm/test/Transforms/LoopVectorize/find-last-ptr-induction.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/replicate-region-cost-probability.ll
A llvm/test/Transforms/LoopVectorize/select-first-index-narrow.ll
M llvm/test/Transforms/LoopVectorize/vectorize-once.ll
M llvm/test/Transforms/LoopVectorize/vplan-print-before-after.ll
M llvm/test/Transforms/MemProfContextDisambiguation/duplicate-context-ids.ll
M llvm/test/Transforms/MemProfContextDisambiguation/funcassigncloning.ll
M llvm/test/Transforms/MemProfContextDisambiguation/funcassigncloning2.ll
M llvm/test/Transforms/MemProfContextDisambiguation/funcassigncloningrecursion.ll
M llvm/test/Transforms/MemProfContextDisambiguation/inlined3.ll
A llvm/test/Transforms/OpenMP/callback_parallel_regions.ll
A llvm/test/Transforms/OpenMP/indirect_call_specialization_cap.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/trunc-intrinsics.ll
M llvm/test/Transforms/PhaseOrdering/constraint-eliminiation-interactions.ll
M llvm/test/Transforms/PhaseOrdering/pr64289-tce.ll
A llvm/test/Transforms/SLPVectorizer/AArch64/hor-fp-reduction-instcount.ll
A llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-drop.ll
M llvm/test/Transforms/SROA/readonlynocapture.ll
M llvm/test/Transforms/SimpleLoopUnswitch/token-uses.ll
M llvm/test/Transforms/SimplifyCFG/hoist-sink-swifterror-store.ll
R llvm/test/Transforms/SimplifyCFG/token_like_type.ll
M llvm/test/Transforms/SimplifyCFG/volatile-phioper.ll
M llvm/test/Verifier/tokenlike1.ll
M llvm/test/Verifier/tokenlike5.ll
M llvm/test/Verifier/tokenlike6.ll
M llvm/test/Verifier/tokenlike7.ll
A llvm/test/tools/llubi/alloca_large_size_crash.ll
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-sve-instructions.s
A llvm/test/tools/llvm-mca/AMDGPU/buffer-op-lds-operand.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-cov5.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx10.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx90a.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx950.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-sgpr.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-vgpr.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx10.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx9.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-raw.s
M llvm/test/tools/llvm-offload-wrapper/offload-wrapper.ll
A llvm/test/tools/llvm-readobj/MachO/cpu-capabilities.yaml
M llvm/test/tools/llvm-readobj/MachO/file-headers-arm64.test
M llvm/test/tools/llvm-readobj/MachO/file-headers.test
M llvm/tools/llubi/lib/Context.cpp
M llvm/tools/llubi/llubi.cpp
M llvm/tools/llvm-objdump/ObjdumpOpts.td
M llvm/tools/llvm-readobj/MachODumper.cpp
M llvm/tools/opt/NewPMDriver.cpp
M llvm/unittests/ADT/DenseMapTest.cpp
M llvm/unittests/ADT/FoldingSet.cpp
M llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
M llvm/unittests/CodeGen/CMakeLists.txt
A llvm/unittests/CodeGen/RegisterPressureTest.cpp
M llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
R llvm/unittests/ExecutionEngine/Orc/MangleAndInternerTest.cpp
A llvm/unittests/ExecutionEngine/Orc/ManglerTest.cpp
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M llvm/unittests/IR/AttributesTest.cpp
M llvm/unittests/IR/ConstantsTest.cpp
M llvm/unittests/SandboxIR/TypesTest.cpp
M llvm/unittests/Support/DataExtractorTest.cpp
M llvm/unittests/Support/TypeSizeTest.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/unittests/Transforms/Utils/LocalTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/SchedulerTest.cpp
M llvm/unittests/Transforms/Vectorize/VPDomTreeTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTestBase.h
M llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
M llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
M llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
M llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp
M llvm/utils/UpdateTestChecks/asm.py
M llvm/utils/UpdateTestChecks/mir.py
M llvm/utils/gn/secondary/clang/lib/CodeGen/BUILD.gn
A llvm/utils/gn/secondary/clang/lib/CodeGenUtils/BUILD.gn
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Transforms/Vectorize/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/CodeGen/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/Orc/BUILD.gn
M llvm/utils/lldbDataFormatters.py
M llvm/utils/profcheck-xfail.txt
M mlir/CMakeLists.txt
M mlir/docs/Remarks.md
M mlir/include/mlir/Dialect/Affine/TransformOps/AffineTransformOps.td
M mlir/include/mlir/Dialect/Bufferization/TransformOps/BufferizationTransformOps.td
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/include/mlir/Dialect/EmitC/IR/EmitCBase.td
M mlir/include/mlir/Dialect/Func/IR/FuncOps.td
M mlir/include/mlir/Dialect/Func/TransformOps/FuncTransformOps.td
M mlir/include/mlir/Dialect/GPU/TransformOps/GPUTransformOps.td
M mlir/include/mlir/Dialect/LLVMIR/CMakeLists.txt
A mlir/include/mlir/Dialect/LLVMIR/LLVMAllOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMRequiresSMTraits.h
M mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.h
M mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td
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A mlir/include/mlir/Dialect/OpenACC/OpenACCCGEnums.td
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