[all-commits] [llvm/llvm-project] 7caac9: [BOLT][RISCV] Implement register analysis hooks (#...

[Thrrreeee via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7caac9be9a7f9ecda3f31802ef451a25f2b61658
      https://github.com/llvm/llvm-project/commit/7caac9be9a7f9ecda3f31802ef451a25f2b61658
  Author: Thrrreeee <shijinrui at bytedance.com>
  Date:   2026-09-09 (Wed, 09 Sep 2026)

  Changed paths:
    M bolt/include/bolt/Core/MCPlusBuilder.h
    M bolt/include/bolt/Passes/LivenessAnalysis.h
    M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
    M bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
    M bolt/lib/Target/X86/X86MCPlusBuilder.cpp
    M bolt/unittests/Core/MCPlusBuilder.cpp

  Log Message:
  -----------
  [BOLT][RISCV] Implement register analysis hooks (#220581)

This patch implements the RISC-V register-analysis hooks in
`RISCVMCPlusBuilder` that previously fell back to the unimplemented
base-class methods.

The `MCPlusBuilder` unittests fixture is also extended to create a
RISC-V binary context. New tests cover the flags-register result,
zeroing-XOR recognition, ABI register masks, general-purpose register
masks, and non-scavengeable registers. These hooks provide the
target-specific register information required by BOLT analyses and
transformations on RISC-V.
BTW, this is split out as a prerequisite fo LongJump pass implement for
RISCV.



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