[all-commits] [llvm/llvm-project] accc84: [AMDGPU] Refresh RegisterClassInfo after reserving...

[Michael Halkenhäuser via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: accc84148aae88d54c11403d04929afaccecf4d6
      https://github.com/llvm/llvm-project/commit/accc84148aae88d54c11403d04929afaccecf4d6
  Author: Michael Halkenhäuser <MichaelGerald.Halkenhauser at amd.com>
  Date:   2026-09-08 (Tue, 08 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUReserveWWMRegs.cpp
    A llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-reserved-wwm-vgpr.ll

  Log Message:
  -----------
  [AMDGPU] Refresh RegisterClassInfo after reserving WWM registers (#221849)

AMDGPUReserveWWMRegs reserves the VGPRs the WWM allocator picked for SGPR
spill lanes and clears the per-lane VGPR mask, but updates neither
MachineRegisterInfo nor the shared RegisterClassInfo. RegAllocBase
re-freezes the reserved set, but owns its RegisterClassInfo by value, so
only its private copy is refreshed, and a later user of the analysis is
offered an allocation order that still lists the reserved register.

AMDGPURewriteAGPRCopyMFMA became such a user in #216510: its spill slot
elimination assigned that register, which asserts in VirtRegMap and, in a
build without assertions, silently clobbers the spilled SGPRs. #216510 was
reverted in #221749; this is a prerequisite for relanding it.

Update MRI and the analysis at the end of the pass, as SIPreAllocateWWMRegs
already does, after clearPerLaneVGPRAllocMask() since the mask is itself an
input to getReservedRegs().

AI-assisted.



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