[all-commits] [llvm/llvm-project] bbf7b8: [CIR][NVPTX] Add support for NVVM half type builti...

[Ayokunle Amodu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bbf7b8439d526de7a696bad82c7f8cc8696e39f7
      https://github.com/llvm/llvm-project/commit/bbf7b8439d526de7a696bad82c7f8cc8696e39f7
  Author: Ayokunle Amodu <ayokunle321 at gmail.com>
  Date:   2026-09-08 (Tue, 08 Sep 2026)

  Changed paths:
    M clang/lib/CIR/CodeGen/CIRGenBuiltinNVPTX.cpp
    A clang/test/CIR/CodeGenCUDA/builtins-nvvm-fma-oob.cu
    A clang/test/CIR/CodeGenCUDA/builtins-nvvm-half.cu

  Log Message:
  -----------
  [CIR][NVPTX] Add support for NVVM half type builtins (#221859)

Adds codegen for the following NVVM half type builtins:

- `__nvvm_ex2_approx_{f16,f16x2}`
- `__nvvm_fmin{_ftz,}{_nan,}{_xorsign_abs,}_{f16,f16x2}`
- `__nvvm_fmax{_ftz,}{_nan,}{_xorsign_abs,}_{f16,f16x2}`
- `__nvvm_fma_rn{_ftz,}{_relu,_sat,}_{f16,f16x2}`
- `__nvvm_fma_rn_oob{_relu,}_{f16,bf16,f16x2,bf16x2}`

These are lowered to the corresponding llvm.nvvm.* intrinsics.

This diverges a bit from OG, as no half-type helper is needed here. OG
routes these through `MakeHalfType`, which coerces each argument to the
intrinsic's declared parameter type, appends the intrinsic's defaulted
arguments, and
asserts that no argument is an integer constant expression. None of that
is needed for the builtins in this patch as each already agrees with its
intrinsic on operand and result types, and none has defaulted
parameters. The existing
`emitUnaryNVVMIntrinsic` and `emitBuiltinWithOneOverloadedType<N>`
helpers are therefore sufficient.

More generally, nothing `MakeHalfType` does is half-specific.

Assisted by Claude.



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