[all-commits] [llvm/llvm-project] 0a50c2: [MIPS] Support MIPS I hard-float double loads/stor...

[yingopq via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0a50c218e000acee02b90f8a0f1f50f3da9059e8
      https://github.com/llvm/llvm-project/commit/0a50c218e000acee02b90f8a0f1f50f3da9059e8
  Author: yingopq <115543042+yingopq at users.noreply.github.com>
  Date:   2026-09-08 (Tue, 08 Sep 2026)

  Changed paths:
    M llvm/lib/Target/Mips/MipsInstrFPU.td
    M llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
    M llvm/lib/Target/Mips/MipsSEISelLowering.cpp
    M llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
    M llvm/lib/Target/Mips/MipsScheduleGeneric.td
    M llvm/lib/Target/Mips/MipsScheduleP5600.td
    M llvm/test/CodeGen/Mips/llvm-ir/load.ll
    M llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
    M llvm/test/CodeGen/Mips/mips1-load-in-delay-slot.ll
    A llvm/test/CodeGen/Mips/mips1-not-support-ldc1-sdc1.ll

  Log Message:
  -----------
  [MIPS] Support MIPS I hard-float double loads/stores with LWC1/SWC1 (#209362)

MIPS I lacks LDC1/SDC1. This patch implements double precision
loads/stores using LWC1/SWC1 instructions.

* Add BuildPairF64_FPR and ExtractElementF64_FPR nodes
* Use them in lowerLOAD/lowerSTORE for MIPS I hard-float
* Avoid redundant mtc1/mfc1 instructions

Matches GCC behavior for MIPS I hard-float.

Fix #62190.



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