[all-commits] [llvm/llvm-project] afb42a: [clang][NVPTX][MLIR][NVVM] Add overloaded fadd int...

[Srinivasa Ravi via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: afb42af9cc18d0dd08ccac3577310e049095700b
      https://github.com/llvm/llvm-project/commit/afb42af9cc18d0dd08ccac3577310e049095700b
  Author: Srinivasa Ravi <srinivasar at nvidia.com>
  Date:   2026-09-07 (Mon, 07 Sep 2026)

  Changed paths:
    M clang/lib/CIR/CodeGen/CIRGenBuiltinNVPTX.cpp
    M clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp
    M clang/test/CIR/CodeGenCUDA/builtins-nvvm-math.cu
    M clang/test/CodeGen/builtins-nvptx.c
    M llvm/docs/NVPTXUsage.md
    M llvm/include/llvm/IR/IntrinsicsNVVM.td
    M llvm/include/llvm/IR/NVVMIntrinsicUtils.h
    M llvm/lib/Analysis/ConstantFolding.cpp
    M llvm/lib/IR/AutoUpgrade.cpp
    M llvm/lib/IR/NVVMIntrinsicUtils.cpp
    M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
    M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
    M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
    M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
    M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
    M llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
    A llvm/test/CodeGen/NVPTX/bf16-add.ll
    A llvm/test/CodeGen/NVPTX/bf16-sub.ll
    R llvm/test/CodeGen/NVPTX/f16-add-sat.ll
    A llvm/test/CodeGen/NVPTX/f16-add.ll
    R llvm/test/CodeGen/NVPTX/f16-sub-sat.ll
    A llvm/test/CodeGen/NVPTX/f16-sub.ll
    A llvm/test/CodeGen/NVPTX/fp-add-f32x2.ll
    A llvm/test/CodeGen/NVPTX/fp-add-invalid.ll
    M llvm/test/CodeGen/NVPTX/fp-arith-sat.ll
    A llvm/test/CodeGen/NVPTX/fp-fold-sub-f32x2.ll
    M llvm/test/CodeGen/NVPTX/fp-fold-sub.ll
    M llvm/test/CodeGen/NVPTX/mixed-precision-fp.ll
    M llvm/test/Transforms/InstCombine/NVPTX/nvvm-intrins.ll
    M llvm/test/Transforms/InstSimplify/const-fold-nvvm-add.ll
    A llvm/test/Verifier/NVPTX/fadd.ll
    M llvm/unittests/IR/IntrinsicsTest.cpp
    M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
    M mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
    M mlir/test/Target/LLVMIR/nvvm/addf/addf.mlir
    M mlir/test/Target/LLVMIR/nvvm/addf/addf_invalid.mlir
    M mlir/test/Target/LLVMIR/nvvm/addf/addf_vector.mlir
    M mlir/test/Target/LLVMIR/nvvm/subf/subf.mlir
    M mlir/test/Target/LLVMIR/nvvm/subf/subf_invalid.mlir
    M mlir/test/Target/LLVMIR/nvvm/subf/subf_vector.mlir

  Log Message:
  -----------
  [clang][NVPTX][MLIR][NVVM] Add overloaded fadd intrinsics (#221681)

This change adds the following overloaded `fadd` intrinsics with
NVPTX codegen:

- `llvm.nvvm.fadd`
- `llvm.nvvm.fadd.ftz`
- `llvm.nvvm.fadd.sat`
- `llvm.nvvm.fadd.ftz.sat`

The rounding mode is passed in as an `i32` immediate operand.

Auto-upgrades the older non-overloaded intrinsics to the new
ones, and updates clang builtins, CIR codegen, and MLIR NVVM ops
to lower to the new intrinsics.

In the interest of completion, this also:
- Adds intrinsics support for lowering some half-precision additions 
that were omitted earlier (`f16/f16x2` without saturation, and
`bf16/bf16x2` additions), and support for the `f32x2` type.
- Extends the DAG combine pattern for lowering `fneg + add-intrinsic`
to `sub` instructions to all supported types.
- Adds tests for constant folding of these intrinsics with the newly
supported scalar types.

PTX Spec Reference:
https://docs.nvidia.com/cuda/developer-preview/13.4/parallel-thread-execution/index.html#floating-point-instructions-add

Assisted-by: Claude Opus 5



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