[all-commits] [llvm/llvm-project] bb577f: [AArch64][GlobalISel] Select i16/f16 cross-bank bi...

[Cullen Rhodes via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bb577f620571ce3bb97f2e717b53500574a9cf27
      https://github.com/llvm/llvm-project/commit/bb577f620571ce3bb97f2e717b53500574a9cf27
  Author: Cullen Rhodes <cullen.rhodes at arm.com>
  Date:   2026-09-07 (Mon, 07 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir

  Log Message:
  -----------
  [AArch64][GlobalISel] Select i16/f16 cross-bank bitcasts (#220612)

Test bitcast_to_half in
llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll crashes with

  H0 = COPY W8
  unimplemented reg-to-reg copy
  UNREACHABLE executed at

/home/culrho01/llvm-project/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp:6363!

when type-based RegBankSelect (#199040) is enabled. Normal RBS keeps
both operands on GPR and moves to FPR afterward. This extends
instruction select to support bitcasts where src/dst reg bank doens't
match.

Assisted-by: codex



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