[all-commits] [llvm/llvm-project] b966c7: [AMDGPU] Fix true16 high-half packing when the low...

[Barbara Mitic via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b966c71b74e498c3a9570c790a71a5a1a2fe0e2f
      https://github.com/llvm/llvm-project/commit/b966c71b74e498c3a9570c790a71a5a1a2fe0e2f
  Author: Barbara Mitic <Barbara.Mitic at amd.com>
  Date:   2026-09-07 (Mon, 07 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
    M llvm/test/CodeGen/AMDGPU/pack-half-to-lshl-or.ll

  Log Message:
  -----------
  [AMDGPU] Fix true16 high-half packing when the low operand is not a VGPR (#220843)

The true16 (hi << 16) | z pattern used v_or_b16 and EXTRACT_SUBREG hi16
on z. That is only valid when z is a VGPR. When z is an immediate (e.g.
0x3c00), EXTRACT_SUBREG hi16 does not isolate the high 16 bits, so the
whole constant is ORed into hi: we get (hi | 0x3c00) << 16 instead of hi
<< 16.

Select v_lshl_or_b32 instead, with z as VSrc_b32, matching the fake16
path.



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