[all-commits] [llvm/llvm-project] 8a1193: [clang][NFC] Bump the maximum number of Frontend d...
aokblast via All-commits
all-commits at lists.llvm.org
Sat Aug 8 04:44:00 PDT 2026
Branch: refs/heads/users/aokblast/lldb/mmap_fix_for_reexport
Home: https://github.com/llvm/llvm-project
Commit: 8a119310dae2fd67497c8611fc3208d16a36a2c3
https://github.com/llvm/llvm-project/commit/8a119310dae2fd67497c8611fc3208d16a36a2c3
Author: Tony Varghese <tonypalampalliyil at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticIDs.h
Log Message:
-----------
[clang][NFC] Bump the maximum number of Frontend diagnostics (#210345)
The number of Frontend diagnostics in DiagnosticFrontendKinds.td is
close to the DIAG_SIZE_FRONTEND limit of 200 (195 in use), and in-flight
PRs adding frontend diagnostics (e.g. #187986) run into the static
assert in DiagnosticIDs.cpp. Increase the limit to 300, following the
precedent of #200948 which did the same for Sema diagnostics.
Co-authored-by: Tony Varghese <tony.varghese at ibm.com>
Commit: a64f7412551ae63a49dd8617f93ab89878288879
https://github.com/llvm/llvm-project/commit/a64f7412551ae63a49dd8617f93ab89878288879
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp
M llvm/test/CodeGen/SPIRV/structurizer/HLSLControlFlowHint-pass-check.ll
Log Message:
-----------
[SPIR-V][NewPM] Register SPIRVStructurizer with the new pass manager (#209965)
Commit: 9d2e7e6836beadbe63380f64c716df2c086ff2ea
https://github.com/llvm/llvm-project/commit/9d2e7e6836beadbe63380f64c716df2c086ff2ea
Author: Lukas <43409484+hertelukas at users.noreply.github.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
M llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
M llvm/lib/Transforms/Utils/FixIrreducible.cpp
M llvm/lib/Transforms/Utils/UnifyLoopExits.cpp
M llvm/test/Transforms/FixIrreducible/bug45623.ll
M llvm/test/Transforms/FixIrreducible/multiedge.ll
M llvm/test/Transforms/FixIrreducible/nested.ll
M llvm/test/Transforms/FixIrreducible/switch.ll
M llvm/test/Transforms/FixIrreducible/unreachable.ll
M llvm/test/Transforms/FixIrreducible/unsupported-terminator.ll
M llvm/test/Transforms/UnifyLoopExits/basic.ll
M llvm/test/Transforms/UnifyLoopExits/integer_guards.ll
M llvm/test/Transforms/UnifyLoopExits/multiedge.ll
M llvm/test/Transforms/UnifyLoopExits/nested.ll
M llvm/test/Transforms/UnifyLoopExits/restore-ssa.ll
M llvm/test/Transforms/UnifyLoopExits/switch.ll
M llvm/test/Transforms/UnifyLoopExits/undef-phis.ll
Log Message:
-----------
[FixIrreducible][UnifyLoopExits] Support switch statements (#206567)
This builds on #149308, which implemented `callbr` support.
The same approach of splitting multi-branch edges entering irreducible
loops can be used for switches. It does not introduce any new switch
statements, but alleviates the requirement of having to run the
`LowerSwitch` pass first. This makes the pass usable for users other
than AMDGPU, which can handle switch statements (e.g., WebAssembly, see
[here](https://github.com/llvm/llvm-project/pull/181755#issuecomment-3936316307)).
I'm also implementing a flag into the `ControlFlowHub` to support
switches as well, for which I will open a separate PR. Currently the
`ControlFlowHub` creates a branch-sled, mimicking a `switch` (a series
of blocks consisting only of conditional branches, selectively entering
an irreducible loop at a certain point or continuing to the next
potential entry point). If the target can support switches, that should
be the clear goal here, as shown in the image below. This PR implements
the step from (a) to (b), whereas extending the `ControlFlowHub`
represents the step from (b) to (c). ((c) to (d) already exists through
`SwitchToLookup` and `SwitchToArithmetic`).
<img width="1055" height="432" alt="image"
src="https://github.com/user-attachments/assets/780b7894-1895-4137-8148-b2bbc7f73a8f"
/>
The test cases in `switch.ll` were adapted from the `callbr.ll` tests
using an LLM to ensure equivalent coverage. I've manually reviewed the
control flow and conditions for every case, and the final assertions
were generated using `update_test_checks.py`.
Commit: c34d2c30e86358bfe308558b5e0719e9f5305153
https://github.com/llvm/llvm-project/commit/c34d2c30e86358bfe308558b5e0719e9f5305153
Author: Aayush Shrivastava <iamaayushrivastava at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
M mlir/test/Dialect/LLVMIR/mem2reg.mlir
Log Message:
-----------
[mlir] Fix mem2reg crash on scalable vector store/load with matching type (#209426)
Fixes #209065
`createInsertAndCast/createExtractAndCast` in `LLVMMemorySlot.cpp`
queried the bit size of the source/target types before checking whether
they were already identical. For scalable vector types (e.g.
`vector<[4]xi1>`), this size query implicitly converts a scalable
TypeSize to a scalar, which aborts. `mem2reg` hits this path for any
store or load whose value type exactly matches the slot's element type,
since `getStored/removeBlockingUses` run even when no cast is needed.
This fix adds an early return when the types are already equal, skipping
the size query, consistent with the existing short-circuit in
`areConversionCompatible/castSameSizedTypes`.
Commit: e2572b883f0b2bc7a7a3808e484039f9382aa898
https://github.com/llvm/llvm-project/commit/e2572b883f0b2bc7a7a3808e484039f9382aa898
Author: Ming-Yi Lai <ming-yi.lai at mediatek.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M lld/ELF/Arch/RISCV.cpp
M lld/test/ELF/riscv-feature-zicfilp-unlabeled.s
Log Message:
-----------
[LLD][RISCV][Zicfilp] Generate unlabeled landing pad-style PLT (#145461)
To support dynamic linking when Zicfilp is enabled, lpad insns are
inserted into PLTs. This patch generates the unlabeled landing pad-style
PLT, in which all the lpads have label `0`, when ZICFILP-unlabeled is
enabled:
--- PLT Header:
```
1: auipc t3, %pcrel_hi(.got.plt)
sub t1, t1, t2
l[w|d] t2, %pcrel_lo(1b)(t3)
addi t1, t1, -(hdr size + 16)
addi t0, t3, %pcrel_lo(1b)
srli t1, t1, log2(16/PTRSIZE)
l[w|d] t0, PTRSIZE(t0)
jr t2
```
--- PLT Entry:
```
lpad 0
1: auipc t2, %pcrel_hi(function at .got.plt)
l[w|d] t2, %pcrel_lo(1b)(t2)
jalr t1, t2
```
(The PLT format is specified in the psABI draft at
<https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/417>)
---------
Co-authored-by: Piyou Chen <piyou.chen at sifive.com>
Co-authored-by: Kito Cheng <npickito at gmail.com>
Commit: 21d537e48677c6c9f3fe679694bba7bcaece90ce
https://github.com/llvm/llvm-project/commit/21d537e48677c6c9f3fe679694bba7bcaece90ce
Author: Mel Chen <mel.chen at sifive.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
Log Message:
-----------
[LV][Test] Rename conflicting IR values to avoid FileCheck conflicts. nfc (#210293)
Commit: 99789ca18a7982a0b8d63e681d957590f67455c4
https://github.com/llvm/llvm-project/commit/99789ca18a7982a0b8d63e681d957590f67455c4
Author: A. Jiang <de34 at live.cn>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M libcxx/docs/Status/Cxx23Issues.csv
M libcxx/test/std/ranges/range.adaptors/range.adjacent.transform/helpers.h
M libcxx/test/std/ranges/range.adaptors/range.adjacent.transform/iterator/member_types.compile.pass.cpp
Log Message:
-----------
[libc++] Add tests for LWG3798 and mark it as Complete (#210640)
Commit: 9e2e9b33e14808541c0470b92ade34bee6608bf6
https://github.com/llvm/llvm-project/commit/9e2e9b33e14808541c0470b92ade34bee6608bf6
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/test/UnitTest/CMakeLists.txt
M libc/test/UnitTest/ExecuteFunctionUnix.cpp
M libc/test/UnitTest/HermeticTestUtils.cpp
M libc/test/UnitTest/LibcDeathTestExecutors.cpp
M libc/test/src/stdlib/CMakeLists.txt
M utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel
Log Message:
-----------
[libc] Port process utilities to hermetic mode and enable some tests (#209999)
This is achieved by calling internal libc functions in hermetic mode. In
the overlay mode I keep calling the system functions so that the tests
work even on systems which don't have these implemented.
I also needed to implement the delete operators as both the libc proper
and the test framework uses them nowadays.
This is sufficient to enable all stdlib tests in hermetic mode, except
for one, which actually exposes a bug in the implementation. I'll deal
with that in a separate patch.
Commit: ba9a115e3ba30699cafe7815d851f89f02f821ea
https://github.com/llvm/llvm-project/commit/ba9a115e3ba30699cafe7815d851f89f02f821ea
Author: Adam Scott <adamscott200322 at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/vselect-masked-shift.ll
Log Message:
-----------
[AArch64] Fold vector shifts guarded against oversized amounts into USHL (#207628)
`select(icmp ult(amt, EltSize), shl(x, amt), 0)`, where EltSize is the
{8, 16, 32, 64} lane size, is the usual way to guard a variable vector
shift against shl poison. On AArch64 the guard is unnecessary because
USHL already returns zero once the shift amount reaches the lane size.
For v4i32:
Before:
```
movi v2.4s, #63
movi v3.4s, #32
and v1.16b, v1.16b, v2.16b
ushl v0.4s, v0.4s, v1.4s
cmhi v1.4s, v3.4s, v1.4s
and v0.16b, v1.16b, v0.16b
```
After:
```
movi v2.4s, #63
and v1.16b, v1.16b, v2.16b
ushl v0.4s, v0.4s, v1.4s
```
USHL reads each lane's shift amount as a signed value from its low byte
so amounts above 127 would be misread. The fold applies directly when
known bits can prove the amounts are at most 127 and otherwise the
amounts are clamped to EltSize with umin first, which is still one
instruction cheaper than the select.
NEON has no umin for 64-bit lanes so unbounded v2i64 amounts use the SVE
umin when available and otherwise keep the select.
lshr gets the same fold since it already lowers to ushl with a negated
amount.
This is the AArch64 counterpart of #86922, which added the same folds
for AVX2's variable shifts. This does the select(shift) half; the
shift(select) form will be a follow-up.
Closes #200698.
Commit: 92aded9ac802ed85971627bfa651697f960eefbf
https://github.com/llvm/llvm-project/commit/92aded9ac802ed85971627bfa651697f960eefbf
Author: Kareem Ergawy <kergawy at nvidia.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M flang/include/flang/Lower/PFTBuilder.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/PFTBuilder.cpp
M flang/lib/Lower/Runtime.cpp
M flang/test/HLFIR/assumed_shape_with_value_keyword.f90
M flang/test/HLFIR/optional_dummy.f90
M flang/test/Integration/OpenMP/parallel-private-reduction-worstcase.f90
M flang/test/Lower/HLFIR/intrinsic-subroutines.f90
M flang/test/Lower/MIF/change_team2.f90
M flang/test/Lower/OpenACC/Todo/acc-unstructured-combined-construct.f90
M flang/test/Lower/OpenACC/Todo/do-loops-to-acc-loops-todo.f90
M flang/test/Lower/OpenACC/acc-terminator.f90
M flang/test/Lower/OpenACC/acc-unstructured.f90
M flang/test/Lower/OpenMP/loop-compound.f90
M flang/test/Lower/OpenMP/parallel-reduction3.f90
M flang/test/Lower/OpenMP/stop-stmt-in-region.f90
M flang/test/Lower/OpenMP/unstructured.f90
M flang/test/Lower/OpenMP/wsloop-unstructured.f90
M flang/test/Lower/branching-directive.f90
A flang/test/Lower/do_loop_execute_region_wrap.f90
M flang/test/Lower/do_loop_unstructured.f90
M flang/test/Lower/fail_image.f90
A flang/test/Lower/if_construct_execute_region_wrap.f90
M flang/test/Lower/ifconvert.f90
M flang/test/Lower/mixed_loops.f90
M flang/test/Lower/nsw.f90
M flang/test/Lower/pre-fir-tree02.f90
M flang/test/Lower/while_loop.f90
Log Message:
-----------
[flang][PFT-to-MLIR] Wrap unstructured Fortran constructs in scf.execute_region (#208635)
Extend the PFT-to-MLIR (HLFIR/FIR) lowering so unstructured DO and IF
constructs are emitted inside scf.execute_region, hiding their
multi-block CFG behind a single op. OpenACC lowerings that reject
multi-block content (e.g. the "unstructured do loop in combined acc
construct" TODO in OpenACC.cpp) now see a structured op instead.
The main goal is to prevent propagating the "unstructured" property up
the evaluation tree just because one nested evaluation is unstructured;
which is the current behavior.
Flag: -mmlir --wrap-unstructured-constructs-in-execute-region (default
on).
An evaluation is wrappable iff all of the following hold:
* wrap flag on
* eval is parser::DoConstruct or parser::IfConstruct
* eval.isUnstructured
* branchesAreInternal(eval) -- every controlSuccessor in the subtree
targets a nested eval or the constructExit
* !hasIncomingBranch(eval) -- no outside eval branches into the body
(PFT's synthetic IfConstruct around `if(c) goto X` absorbs label targets
between the IF and X; the incoming-branch check excludes such wrappers
when an outer GOTO names one of those labels)
* does not contain a ReturnStmt -- its lowering creates the function's
final block in the current region, which would mis-parent func.return
* not an infinite DO and does not contain one (no LoopControl in any
nested DO): the wrap's yield is unreachable and the body has no
write-shaped side effects, so RegionDCE treats the wrap as trivially
dead and drops it. Excluding the whole enclosing construct keeps such
infinite loops visible in the parent CFG.
* not the body DO of an enclosing OpenACCLoopConstruct or
OpenACCCombinedConstruct -- nor one of the N collapsed iterator DOs
reached by walking down through `collapse(N)`. Such DOs are driven
directly into acc.loop by the OpenACC lowering, so wrapping them would
hide the iteration from the acc.loop op.
Diagnostics
-----------
Emit per-wrap and per-function diagnostics on stderr so the wrapping is
observable from a single compile invocation:
[wrap-unstructured] wrapped DO at <loc>
[wrap-unstructured] wrapped IF at <loc>
[wrap-unstructured] summary: N execute_region(s) wrapping unstructured
constructs at <loc>
The counter is reset per function and the summary is suppressed when no
wraps fire.
Co-authored-by: Claude Opus 4.7 <noreply at anthropic.com>
---------
Co-authored-by: Claude Opus 4.7 <noreply at anthropic.com>
Commit: 751fca6c06e4d29b8d2a62c307afce8ba6a0a101
https://github.com/llvm/llvm-project/commit/751fca6c06e4d29b8d2a62c307afce8ba6a0a101
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M clang/test/Driver/freebsd-mips-as.c
M clang/test/Driver/freebsd.c
Log Message:
-----------
[Driver][test] Unwrap freebsd-mips-as.c RUN lines (#210658)
Collapse 3-line RUN blocks to 2 lines and move -### immediately after
%clang, matching the prevailing style for new tests.
Commit: a4ca7f3a670c84196cad4c739114b316fed6d8f1
https://github.com/llvm/llvm-project/commit/a4ca7f3a670c84196cad4c739114b316fed6d8f1
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M libc/hdr/CMakeLists.txt
Log Message:
-----------
[libc][cmake] Remove proxy header XXX_macros -> XXX.h deps (#210008)
In the full build mode, these headers do not include the main XXX.h
header, which makes sense, because they exist to allow us only to expose
a part of it. They do include it in the overlay mode, but in this case,
they are referring to the header from the libc being overlaid, which
exists outside of the build system.
Also fix float_macros by moving
libc.include.llvm-libc-macros.float_macros from DEPENDS to
FULL_BUILD_DEPENDS, as llvm-libc-macros/float-macros.h is only included
under LIBC_FULL_BUILD.
Commit: f214ce6b0a9a6af9b1d899895e29cbba68ee2726
https://github.com/llvm/llvm-project/commit/f214ce6b0a9a6af9b1d899895e29cbba68ee2726
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/arpa/inet/BUILD.bazel
Log Message:
-----------
[libc][bazel] Add missing arpa/inet functions and tests (#210310)
Add bazel build targets for the remaining arpa/inet functions
(inet_addr, inet_aton, inet_ntoa, and inet_ntop) along with their unit
tests and supporting targets (__support_net_address, headers, and proxy
types).
Assisted by Gemini.
Commit: 72e0b55f9b1fd69030d7e9853a708bfd2fba36ec
https://github.com/llvm/llvm-project/commit/72e0b55f9b1fd69030d7e9853a708bfd2fba36ec
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/include/llvm/Analysis/ConstraintSystem.h
M llvm/lib/Analysis/ConstraintSystem.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/gep-arithmetic-signed-predicates.ll
Log Message:
-----------
[ConstraintSys] Solve sub-system with variables needed for query (#210432)
Update ConstraintSystem to only solve the sub-system containing all
variables relevant to a given query.
The sub-system contains the transitive closure of all variables in rows
involving the variables in the constraint to prove.
The iterative collection loop only needs very few iterations to
complete. The pruned system can significantly speed up Fourier–Motzkin
elimination and reduce the cost of copying the system.
This helps to notably decrease compile-time in cases when there are
larger numbers of variables & rows (especially during (Thin)LTO).
Highlights include
* stage1-ReleaseThinLTO: -0.16%
* stage1-ReleaseLTO-g: -0.19%
* stage1-aarch64-O3: -0.04%
https://llvm-compile-time-tracker.com/compare.php?from=1f2772f8e26beb909c2a559f1fb08697e3e06909&to=77fbe7926609da96a193254e44efd1d6f8a097de&stat=instructions%3Au
Note that we will now stop to simplify conditions in code we proved
dead/unreachable earlier; previously, unrelated constraints in the
system that form contradictions would allow proving any unrelated fact.
After pruning, unrelated facts will no longer contribute.
Commit: 4234ff65326237102157875f6ddf098355864178
https://github.com/llvm/llvm-project/commit/4234ff65326237102157875f6ddf098355864178
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M libcxx/include/__functional/function.h
Log Message:
-----------
Reapply "[libc++][NFC] Inline std::function members into the class body" (#209555) (#210260)
This caused LLDB to fail, which has been fixed now.
This reverts commit 7618426138aae95561da676a1d1e10ee0392bf78.
Commit: 1ad0e6989597f550e1a5b53abd889366b65aa6c7
https://github.com/llvm/llvm-project/commit/1ad0e6989597f550e1a5b53abd889366b65aa6c7
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M clang/lib/Driver/ToolChains/FreeBSD.cpp
M clang/lib/Driver/ToolChains/Serenity.cpp
M clang/test/Driver/freebsd.c
Log Message:
-----------
[Driver,FreeBSD] Fix -pie for -r and -no-pie links (#210663)
Port Gnu.cpp changes ae623d16d50c and cac82e26c642 to FreeBSD and
Serenity: -r should suppress -pie. -nopie, OpenBSD specific, should not
be used by other OSes.
Group the options selecting the link mode and place them after -m, as
gnutools::Linker does, so that -r suppresses -export-dynamic and
--hash-style as well, and -no-pie overrides the -fsanitize PIE default.
Drop --enable-new-dtags: default in modern linkers.
Change -Bstatic to -static to follow Gnu.cpp (identical in lld and older
GNU ld).
Commit: 37a2803740cc9df3d605431b2410c9d9c0bc5731
https://github.com/llvm/llvm-project/commit/37a2803740cc9df3d605431b2410c9d9c0bc5731
Author: Kamlesh Kumar <kamleshbhalui at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
M llvm/test/CodeGen/AArch64/scalable_masked_interleaved_stores.ll
M llvm/test/CodeGen/AArch64/sve-ldst-sext.ll
M llvm/test/CodeGen/AArch64/sve-ldst-zext.ll
A llvm/test/CodeGen/AArch64/vector-deinterleave-load.ll
A llvm/test/CodeGen/AArch64/vector-interleave-store.ll
Log Message:
-----------
[AArch64] Add combine for interleave deinterleave (#208414)
These combines now can emit ldN/stN without interleaved access pass.
Commit: 6fb8d5fd507d976cb8072a7aa245c225c25ee08a
https://github.com/llvm/llvm-project/commit/6fb8d5fd507d976cb8072a7aa245c225c25ee08a
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M lldb/source/Plugins/TraceExporter/docs/htr.md
Log Message:
-----------
[lldb][docs] Remove image links from trace doc (#210664)
The document was first added in https://reviews.llvm.org/D105741 but
that did not include the images (they were not in the RFC or discussions
either).
Commit: 03b5c5285eaf0acdc1dc30c5be6e0a7cefeab16f
https://github.com/llvm/llvm-project/commit/03b5c5285eaf0acdc1dc30c5be6e0a7cefeab16f
Author: Nathan Gauër <brioche at google.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/docs/LangRef.md
M llvm/include/llvm/IR/IntrinsicInst.h
M llvm/include/llvm/InitializePasses.h
A llvm/include/llvm/Transforms/Scalar/LogicalSROA.h
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Transforms/Scalar/CMakeLists.txt
A llvm/lib/Transforms/Scalar/LogicalSROA.cpp
A llvm/test/Transforms/LSROA/array.ll
A llvm/test/Transforms/LSROA/basictest.ll
A llvm/test/Transforms/LSROA/escaping.ll
A llvm/test/Transforms/LSROA/nesting.ll
A llvm/test/Transforms/LSROA/normal-gep.ll
A llvm/test/Transforms/LSROA/phi.ll
A llvm/test/Transforms/LSROA/select.ll
Log Message:
-----------
[LSROA] Add logical SROA pass (#192058)
This commit adds a logical-pointer compatible SROA pass. As-is, the pass
does not optimizes nested structs, arrays, or usages of structured
alloca with non-structured GEP instructions.
Adding support for both is not complex, but increase the size of the PR,
hence we can start with this.
Next step will be to allow mem2reg to apply on logical alloca/ptr, and
to add support for nesting/arrays.
---------
Co-authored-by: Nikita Popov <npopov at redhat.com>
Commit: b8300a76659d65fd9738de1c1e4bf5b71e9ef72b
https://github.com/llvm/llvm-project/commit/b8300a76659d65fd9738de1c1e4bf5b71e9ef72b
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/Scalar/GVN.h
M llvm/lib/Transforms/Scalar/GVN.cpp
Log Message:
-----------
[GVN] Remove the "private" `llvm::gvn` namespace (NFC) (#210323)
Move `AvailableValue` and `AvailableValueInBlock` into GVNPass, similar
to other helper types.
Retain `llvm::gvn::GVNLegacyPass` as just `llvm::GVNLegacyPass` -
"legacy" is already a sufficent hint and it is not going to become more
"private" by stacking "gvn" prefixes to the name.
Ideally, `GVNLegacyPass` should be defined in an anonymous namespace,
but that is not possible because it is declared as a friend of GVNPass.
Commit: b9b454166eaa92d2e6e129f6c21ad59639d8364e
https://github.com/llvm/llvm-project/commit/b9b454166eaa92d2e6e129f6c21ad59639d8364e
Author: Hongyu Chen <xxs_chy at outlook.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvp-zip.ll
Log Message:
-----------
[RISCV][P-ext] Generalize lowerVECTOR_SHUFFLEAsRV32PNarrowingShift (#210522)
The previous implementation only matches
`shuffle(extract_subvector(src), extract_subvector(src), mask)`.
This patch generalizes it to `shuffle(a, b, mask)`, so we can now lower
it to `PNSRL(concat(a,b), element_bits)` if it is a deinterleave
shuffle. And we use `foldConcatVector` to handle the original pattern
with `extract_subvector`.
Commit: 023361f8ef6aa47d10cd839515c58322890367c3
https://github.com/llvm/llvm-project/commit/023361f8ef6aa47d10cd839515c58322890367c3
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
Log Message:
-----------
[lldb][AArch64][Linux][NFC] Move RegisterSetType enum into header (#207145)
I will be using this later to replace all the register specific
functions this class has (WriteSVE/ReadSVE and so on) with single
functions that use RegisterSetType to decide what to do.
While I'm here, I've made some sizeof and casts use RegisterSetType in
case the underlying type changes later.
Commit: 975c8f5a7b25f84a257ddfaf9605c62147a0913d
https://github.com/llvm/llvm-project/commit/975c8f5a7b25f84a257ddfaf9605c62147a0913d
Author: Raphael Isemann <rise at apple.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M lldb/include/lldb/Core/ModuleSpec.h
M lldb/source/API/SBAddressRangeList.cpp
M lldb/source/API/SBMemoryRegionInfo.cpp
M lldb/source/Breakpoint/Breakpoint.cpp
M lldb/source/Breakpoint/BreakpointLocation.cpp
M lldb/source/Breakpoint/BreakpointLocationList.cpp
M lldb/source/Breakpoint/BreakpointOptions.cpp
M lldb/source/Breakpoint/BreakpointResolverName.cpp
M lldb/source/Breakpoint/Watchpoint.cpp
M lldb/source/Breakpoint/WatchpointList.cpp
M lldb/source/Core/Disassembler.cpp
M lldb/source/Core/DumpDataExtractor.cpp
M lldb/source/Core/DynamicLoader.cpp
M lldb/source/Core/FormatEntity.cpp
M lldb/source/Core/IOHandler.cpp
M lldb/source/Core/IOHandlerCursesGUI.cpp
M lldb/source/Core/Mangled.cpp
M lldb/source/Core/SearchFilter.cpp
M lldb/source/Core/SourceManager.cpp
M lldb/source/DataFormatters/FormattersHelpers.cpp
M lldb/source/DataFormatters/StringPrinter.cpp
M lldb/source/DataFormatters/TypeCategory.cpp
M lldb/source/DataFormatters/TypeSynthetic.cpp
M lldb/source/DataFormatters/ValueObjectPrinter.cpp
M lldb/source/DataFormatters/VectorType.cpp
M lldb/source/Expression/IRInterpreter.cpp
M lldb/source/Expression/Materializer.cpp
M lldb/source/Expression/REPL.cpp
M lldb/source/Host/common/ProcessLaunchInfo.cpp
M lldb/source/Symbol/SymbolContext.cpp
M lldb/source/Symbol/Type.cpp
M lldb/source/Symbol/UnwindPlan.cpp
M lldb/source/Utility/Event.cpp
M lldb/source/Utility/ProcessInfo.cpp
M lldb/source/Utility/StructuredData.cpp
M lldb/source/ValueObject/ValueObject.cpp
Log Message:
-----------
[lldb][NFC] Remove various Stream::Printf calls with constants (#210294)
`Stream::Printf` needs to call various other (variadic) functions, needs
to parse the input string and potentially handle too-long format
outputs. Calling in with a constant string is wasting a lot of
instruction on doing nothing.
assisted-by: claude
Commit: 1c1c0657f990b92d23067cb7367772f4c91ea32b
https://github.com/llvm/llvm-project/commit/1c1c0657f990b92d23067cb7367772f4c91ea32b
Author: Abhay Kanhere <a_kanhere at apple.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
A llvm/test/Transforms/ConstraintElimination/lshr.ll
Log Message:
-----------
[ConstraintElim] LSHR x, n <= x when n< bitwidth (#209583)
A logical right shift never increases an unsigned value:
for %r = lshr %x, %n, add the fact %r u<= %x when LSHR is not poison.
This extends the existing udiv/urem fact modeling to lshr.
https://alive2.llvm.org/ce/z/RUTMwe proof shown with constant value <
bit size
Commit: ead8fd8e29fbf3774b7a08bf7b991c2ada30112b
https://github.com/llvm/llvm-project/commit/ead8fd8e29fbf3774b7a08bf7b991c2ada30112b
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M libcxx/include/__ranges/lazy_split_view.h
Log Message:
-----------
[libc++][ranges][NFC] Format `lazy_split_view` (#210644)
Pre-requisite for: https://github.com/llvm/llvm-project/pull/193891
Commit: eec2f0916d44c33beac52f4396c7a9c98b0c9cf6
https://github.com/llvm/llvm-project/commit/eec2f0916d44c33beac52f4396c7a9c98b0c9cf6
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M libcxx/include/__configuration/availability.h
Log Message:
-----------
[libc++][NFC] Removed duplicated `_LIBCPP_INTRODUCED_IN_LLVM_23` macros (#210602)
Removed the redundant macros, which apparently were added by two
different patches.
Commit: 39a2c6a695f9d045b05fd5798a7cb99f3c7425a7
https://github.com/llvm/llvm-project/commit/39a2c6a695f9d045b05fd5798a7cb99f3c7425a7
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M libcxx/test/libcxx/atomics/builtin_clear_padding.pass.cpp
M libcxx/test/std/numerics/numeric.ops/numeric.ops.sat/saturating.bitint.pass.cpp
Log Message:
-----------
[libc++][test][NFC] Removed unsupported compilers from tests (#210413)
Commit: 9cb6db4e3814fba503389aa0af16960847295fd2
https://github.com/llvm/llvm-project/commit/9cb6db4e3814fba503389aa0af16960847295fd2
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/Scalar/GVN.h
M llvm/lib/Transforms/Scalar/GVN.cpp
Log Message:
-----------
Revert "[GVN] Remove the "private" `llvm::gvn` namespace (NFC)" (#210666)
Reverts llvm/llvm-project#210323
FAILED: lib/Transforms/Scalar/CMakeFiles/LLVMScalarOpts.dir/GVN.cpp.o
/var/llvm-compile-time-tracker/llvm-project/llvm/lib/Transforms/Scalar/GVN.cpp:4001:27:
error: qualified name does not name a class before ‘:’ token
4001 | class llvm::GVNLegacyPass : public FunctionPass {
Commit: ded79d9ddea47eb3a42da740353c16d21e890354
https://github.com/llvm/llvm-project/commit/ded79d9ddea47eb3a42da740353c16d21e890354
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
A llvm/test/CodeGen/SPIRV/constant/fp128-unsupported.ll
Log Message:
-----------
[SPIR-V] Reject fp128 and ppc_fp128 types with a diagnostic (#208397)
Introduced as a part of discussion in
https://github.com/llvm/llvm-project/pull/208219
Commit: 4caba63c698121203eea9280a392159dc6328e68
https://github.com/llvm/llvm-project/commit/4caba63c698121203eea9280a392159dc6328e68
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M lldb/test/API/commands/gui/spawn-threads/TestGuiSpawnThreads.py
Log Message:
-----------
[lldb][test] Double the timeout for TestGuiSpawnThreads.py (#210043)
If the host machine is overloaded, spawning threads may be delayed due
to lack of resources. I'm pretty sure this is the cause of failures in
GitHub CI reported in
https://github.com/llvm/llvm-project/issues/209874.
For what the test is doing, we unfortunately cannot get around needing
to wait on the test program.
We could perhaps come up with a lit mode that runs some tests in serial,
but this is a larger project than I want to get into now.
For now, let's try doubling the timeout. This test is unlikely to fail
for real, so if it's taking a long time, it'll be due to system
resources. In 99% of cases, it'll pass in a few seconds still.
Commit: 35c8e920cdd5b53dccfd669ebd92f3e06f534aae
https://github.com/llvm/llvm-project/commit/35c8e920cdd5b53dccfd669ebd92f3e06f534aae
Author: Valery Pykhtin <valery.pykhtin at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
Log Message:
-----------
[NFC][AMDGPU] Use SIInstrFlags predicates in SIMemoryLegalizer and AMDGPUBaseInfo. (#209821)
Part of a series following the introduction of SIInstrFlags predicates.
Commit: 195df3d4654b43ecf35927e574a8061bfaecbb78
https://github.com/llvm/llvm-project/commit/195df3d4654b43ecf35927e574a8061bfaecbb78
Author: Matsu <47756807+khaki3 at users.noreply.github.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsCG.cpp
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-worker-reduction-private.mlir
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsCGTest.cpp
Log Message:
-----------
[mlir][OpenACC] Privatize worker reduction accumulators per worker (#210456)
Example:
```fortran
!$acc parallel
!$acc loop gang reduction(+:sum)
do k = 1, p
!$acc loop worker reduction(+:sum)
do j = 1, n
!$acc loop vector reduction(+:sum)
do i = 1, m
sum = sum + a(i,j,k)
end do
end do
end do
```
In this code, the worker accumulator is both gang- and worker-scoped.
Shared
memory allocated only one copy, so workers raced while updating the same
value.
Fix: allocate one shared-memory accumulator per worker whenever worker
parallelism is present.
Commit: 91ad9f0ce9655eb3715c937f7d64d329bac63817
https://github.com/llvm/llvm-project/commit/91ad9f0ce9655eb3715c937f7d64d329bac63817
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fcmp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmad.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fract.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.frexp.mant.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.cd.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/add-max.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-sin-cos-f16-f32.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bitop3.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-return-types.ll
M llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll
M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll
M llvm/test/CodeGen/AMDGPU/float-sopc-vopc.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaxnum.ll
M llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminnum.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fsub-as-fneg-src-modifier.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/literal64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.flat.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.store.async.from.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.modf.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/lround.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/memset-pattern.ll
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-global.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-smem.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
Log Message:
-----------
AMDGPU/GlobalISel: Handle G_BITCAST for 16 bit extendedLLTs (#208750)
Handle bitcast between i16 and f16/bf16.
For true16 this was already legal, make it legal in regbanklegalize as well.
For non-true16 widen it using G_ANYEXT to i32 and G_TRUNC to dst.
The "i32 G_ANYEXT f16/bf16" and "f16/bf16 G_TRUNC i32" are already legal,
for example these are generated by common CallLowering argument lowering.
Commit: 5ec4a236305f18f2d2d8646902ab166655f1b7f1
https://github.com/llvm/llvm-project/commit/5ec4a236305f18f2d2d8646902ab166655f1b7f1
Author: Matsu <47756807+khaki3 at users.noreply.github.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M flang-rt/lib/cuda/allocator.cpp
M flang/include/flang/Lower/AbstractConverter.h
M flang/include/flang/Lower/Bridge.h
M flang/include/flang/Optimizer/Builder/Runtime/CUDA/Descriptor.h
M flang/include/flang/Runtime/CUDA/descriptor.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Optimizer/Builder/Runtime/CUDA/Descriptor.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/test/Fir/CUDA/cuda-code-gen.mlir
M flang/test/Lower/CUDA/cuda-allocatable.cuf
M flang/test/Lower/CUDA/cuda-derived.cuf
M flang/test/Lower/CUDA/cuda-return01.cuf
M flang/test/Lower/CUDA/cuda-return02.cuf
Log Message:
-----------
[flang][cuda] Fix device-variable leaks and reset-safe cleanup (#209865)
Example:
```fortran
program main
use cudafor
integer, allocatable, device :: b(:)
integer :: istat
allocate(b(1024))
b = 2
istat = cudaDeviceReset()
end program
```
Managed descriptors and main-program allocatable data could leak. After
`cudaDeviceReset()`, compiler-generated scope-exit cleanup could also
access
stale descriptors or recreate a CUDA context.
Fix: free device data and descriptors in the correct order, and avoid
unnecessary
managed temporary descriptors. Each routine’s CUDA scope-exit cleanup is
grouped
under one `CUFDeviceIsActive()` check using
`cuDevicePrimaryCtxGetState`.
Routines without CUDA cleanup—and individual runtime frees—incur no
query.
Commit: f6b1a575b4076281cd67cf3f3a626d70363f1b9b
https://github.com/llvm/llvm-project/commit/f6b1a575b4076281cd67cf3f3a626d70363f1b9b
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-legalize-range-metadata.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector-pointer-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-weird-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/trunc-brc.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll
Log Message:
-----------
AMDGPU/GlobalISel: Switch legalizer intrinsic lowering to extended LLTs (#209200)
Affects various buffer intrinsics.
Commit: 9428725fa09113905847decc48e8b5a731ad0ae6
https://github.com/llvm/llvm-project/commit/9428725fa09113905847decc48e8b5a731ad0ae6
Author: Ryan Thomas Lynch <me at ryanlyn.ch>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M mlir/test/mlir-tblgen/op-result.td
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
Log Message:
-----------
[mlir-tblgen] Emit named result indices (#210542)
similar to https://github.com/llvm/llvm-project/pull/146839
useful for cases such as being able to programmatically update the
result segment sizes or clone an operation via `OperationState` while
editing just a few results, programmatically
Commit: 085ecff1ecc69ad022b614cfa4dc020540b6296b
https://github.com/llvm/llvm-project/commit/085ecff1ecc69ad022b614cfa4dc020540b6296b
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlanValue.h
Log Message:
-----------
[VPlan] Assert VPRegionValues are not used in VPTransformState::get(NFC) (#199420)
VPRegionValues must be replaced with concrete VPValues before execute
and never passed to VPTransformState::get. Add assert to guard against
violations.
Commit: 79e05f4aff2e5b9f0513c0539d146e44cc80193c
https://github.com/llvm/llvm-project/commit/79e05f4aff2e5b9f0513c0539d146e44cc80193c
Author: Jacob Crawley <jacob.crawley at arm.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleave-low-vf-cost.ll
Log Message:
-----------
[AArch64][LV] Adjust costs for low-VF interleaved access (#209441)
Addressing regression introduced by #205844 in which a significantly
slower SVE tail loop is generated.
The cost model for the case where the interleave factor is larger than
the VF has been adjusted to more accurately reflect the cost of the uzp
instructions generated by the deinterleave tree, and the cost of
legalizing the type of each subvector.
Commit: d9fff42ccd58cb3d95cff60641011d72d38dc300
https://github.com/llvm/llvm-project/commit/d9fff42ccd58cb3d95cff60641011d72d38dc300
Author: Matsu <47756807+khaki3 at users.noreply.github.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Lower/Bridge.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Transforms/AffinePromotion.cpp
M flang/lib/Optimizer/Transforms/ControlFlowConverter.cpp
M flang/lib/Optimizer/Transforms/FIRToSCF.cpp
M flang/test/Fir/FirToSCF/do-loop.fir
M flang/test/Fir/loop01.fir
M flang/test/Integration/ivdep.f90
M flang/test/Lower/OpenACC/acc-cache.f90
M flang/test/Lower/OpenACC/acc-declare.f90
M flang/test/Lower/OpenMP/default-clause.f90
M flang/test/Lower/OpenMP/hlfir-seqloop-parallel.f90
M flang/test/Lower/OpenMP/parallel-private-clause-fixes.f90
M flang/test/Lower/OpenMP/sections-predetermined-private.f90
M flang/test/Lower/OpenMP/shared-loop.f90
M flang/test/Lower/OpenMP/unstructured.f90
M flang/test/Lower/OpenMP/wsloop-reduction-allocatable-array-minmax.f90
M flang/test/Lower/OpenMP/wsloop-variable.f90
M flang/test/Lower/allocatable-polymorphic.f90
M flang/test/Lower/dispatch.f90
M flang/test/Lower/do_concurrent_loop_in_nested_block.f90
M flang/test/Lower/do_loop.f90
M flang/test/Lower/do_loop_execute_region_wrap.f90
M flang/test/Lower/do_loop_unstructured.f90
M flang/test/Lower/infinite_loop.f90
M flang/test/Lower/inline_directive.f90
M flang/test/Lower/ivdep.f90
M flang/test/Lower/loops.f90
M flang/test/Lower/loops2.f90
M flang/test/Lower/mixed_loops.f90
M flang/test/Lower/nsw.f90
M flang/test/Transforms/DoConcurrent/skip_all_nested_loops.f90
Log Message:
-----------
[flang] Lower plain DO loops without a secondary-induction iter_arg (#207816)
Example:
```fortran
do i = lb, ub, step
...
end do
```
Flang lowers this with the DO variable as a redundant `iter_arg`, which
hides memory recurrences from later analyses. Simply removing it would
require converting the `index` IV to the source integer type each
iteration, potentially blocking vectorization.
Fix: allow `fir.do_loop` to use the DO variable’s integer type directly.
Trip-count and post-loop calculations remain in `index`. This removes
the redundant `iter_arg` without introducing per-iteration conversions.
`do concurrent` and unstructured loops are unaffected.
Commit: a3dac803338cabed2d18b840771fb6d83750f34e
https://github.com/llvm/llvm-project/commit/a3dac803338cabed2d18b840771fb6d83750f34e
Author: ShengYi Hung <aokblast at FreeBSD.org>
Date: 2026-08-08 (Sat, 08 Aug 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticIDs.h
M clang/lib/Driver/ToolChains/FreeBSD.cpp
M clang/lib/Driver/ToolChains/Serenity.cpp
M clang/test/Driver/freebsd-mips-as.c
M clang/test/Driver/freebsd.c
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M flang-rt/lib/cuda/allocator.cpp
M flang/include/flang/Lower/AbstractConverter.h
M flang/include/flang/Lower/Bridge.h
M flang/include/flang/Lower/PFTBuilder.h
M flang/include/flang/Optimizer/Builder/Runtime/CUDA/Descriptor.h
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/include/flang/Runtime/CUDA/descriptor.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/PFTBuilder.cpp
M flang/lib/Lower/Runtime.cpp
M flang/lib/Optimizer/Builder/Runtime/CUDA/Descriptor.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Transforms/AffinePromotion.cpp
M flang/lib/Optimizer/Transforms/ControlFlowConverter.cpp
M flang/lib/Optimizer/Transforms/FIRToSCF.cpp
M flang/test/Fir/CUDA/cuda-code-gen.mlir
M flang/test/Fir/FirToSCF/do-loop.fir
M flang/test/Fir/loop01.fir
M flang/test/HLFIR/assumed_shape_with_value_keyword.f90
M flang/test/HLFIR/optional_dummy.f90
M flang/test/Integration/OpenMP/parallel-private-reduction-worstcase.f90
M flang/test/Integration/ivdep.f90
M flang/test/Lower/CUDA/cuda-allocatable.cuf
M flang/test/Lower/CUDA/cuda-derived.cuf
M flang/test/Lower/CUDA/cuda-return01.cuf
M flang/test/Lower/CUDA/cuda-return02.cuf
M flang/test/Lower/HLFIR/intrinsic-subroutines.f90
M flang/test/Lower/MIF/change_team2.f90
M flang/test/Lower/OpenACC/Todo/acc-unstructured-combined-construct.f90
M flang/test/Lower/OpenACC/Todo/do-loops-to-acc-loops-todo.f90
M flang/test/Lower/OpenACC/acc-cache.f90
M flang/test/Lower/OpenACC/acc-declare.f90
M flang/test/Lower/OpenACC/acc-terminator.f90
M flang/test/Lower/OpenACC/acc-unstructured.f90
M flang/test/Lower/OpenMP/default-clause.f90
M flang/test/Lower/OpenMP/hlfir-seqloop-parallel.f90
M flang/test/Lower/OpenMP/loop-compound.f90
M flang/test/Lower/OpenMP/parallel-private-clause-fixes.f90
M flang/test/Lower/OpenMP/parallel-reduction3.f90
M flang/test/Lower/OpenMP/sections-predetermined-private.f90
M flang/test/Lower/OpenMP/shared-loop.f90
M flang/test/Lower/OpenMP/stop-stmt-in-region.f90
M flang/test/Lower/OpenMP/unstructured.f90
M flang/test/Lower/OpenMP/wsloop-reduction-allocatable-array-minmax.f90
M flang/test/Lower/OpenMP/wsloop-unstructured.f90
M flang/test/Lower/OpenMP/wsloop-variable.f90
M flang/test/Lower/allocatable-polymorphic.f90
M flang/test/Lower/branching-directive.f90
M flang/test/Lower/dispatch.f90
M flang/test/Lower/do_concurrent_loop_in_nested_block.f90
M flang/test/Lower/do_loop.f90
A flang/test/Lower/do_loop_execute_region_wrap.f90
M flang/test/Lower/do_loop_unstructured.f90
M flang/test/Lower/fail_image.f90
A flang/test/Lower/if_construct_execute_region_wrap.f90
M flang/test/Lower/ifconvert.f90
M flang/test/Lower/infinite_loop.f90
M flang/test/Lower/inline_directive.f90
M flang/test/Lower/ivdep.f90
M flang/test/Lower/loops.f90
M flang/test/Lower/loops2.f90
M flang/test/Lower/mixed_loops.f90
M flang/test/Lower/nsw.f90
M flang/test/Lower/pre-fir-tree02.f90
M flang/test/Lower/while_loop.f90
M flang/test/Transforms/DoConcurrent/skip_all_nested_loops.f90
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/hdr/CMakeLists.txt
M libc/test/UnitTest/CMakeLists.txt
M libc/test/UnitTest/ExecuteFunctionUnix.cpp
M libc/test/UnitTest/HermeticTestUtils.cpp
M libc/test/UnitTest/LibcDeathTestExecutors.cpp
M libc/test/src/stdlib/CMakeLists.txt
M libcxx/docs/Status/Cxx23Issues.csv
M libcxx/include/__configuration/availability.h
M libcxx/include/__functional/function.h
M libcxx/include/__ranges/lazy_split_view.h
M libcxx/test/libcxx/atomics/builtin_clear_padding.pass.cpp
M libcxx/test/std/numerics/numeric.ops/numeric.ops.sat/saturating.bitint.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.adjacent.transform/helpers.h
M libcxx/test/std/ranges/range.adaptors/range.adjacent.transform/iterator/member_types.compile.pass.cpp
M lld/ELF/Arch/RISCV.cpp
M lld/test/ELF/riscv-feature-zicfilp-unlabeled.s
M lldb/include/lldb/Core/ModuleSpec.h
M lldb/source/API/SBAddressRangeList.cpp
M lldb/source/API/SBMemoryRegionInfo.cpp
M lldb/source/Breakpoint/Breakpoint.cpp
M lldb/source/Breakpoint/BreakpointLocation.cpp
M lldb/source/Breakpoint/BreakpointLocationList.cpp
M lldb/source/Breakpoint/BreakpointOptions.cpp
M lldb/source/Breakpoint/BreakpointResolverName.cpp
M lldb/source/Breakpoint/Watchpoint.cpp
M lldb/source/Breakpoint/WatchpointList.cpp
M lldb/source/Core/Disassembler.cpp
M lldb/source/Core/DumpDataExtractor.cpp
M lldb/source/Core/DynamicLoader.cpp
M lldb/source/Core/FormatEntity.cpp
M lldb/source/Core/IOHandler.cpp
M lldb/source/Core/IOHandlerCursesGUI.cpp
M lldb/source/Core/Mangled.cpp
M lldb/source/Core/SearchFilter.cpp
M lldb/source/Core/SourceManager.cpp
M lldb/source/DataFormatters/FormattersHelpers.cpp
M lldb/source/DataFormatters/StringPrinter.cpp
M lldb/source/DataFormatters/TypeCategory.cpp
M lldb/source/DataFormatters/TypeSynthetic.cpp
M lldb/source/DataFormatters/ValueObjectPrinter.cpp
M lldb/source/DataFormatters/VectorType.cpp
M lldb/source/Expression/IRInterpreter.cpp
M lldb/source/Expression/Materializer.cpp
M lldb/source/Expression/REPL.cpp
M lldb/source/Host/common/ProcessLaunchInfo.cpp
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
M lldb/source/Plugins/TraceExporter/docs/htr.md
M lldb/source/Symbol/SymbolContext.cpp
M lldb/source/Symbol/Type.cpp
M lldb/source/Symbol/UnwindPlan.cpp
M lldb/source/Utility/Event.cpp
M lldb/source/Utility/ProcessInfo.cpp
M lldb/source/Utility/StructuredData.cpp
M lldb/source/ValueObject/ValueObject.cpp
M lldb/test/API/commands/gui/spawn-threads/TestGuiSpawnThreads.py
M llvm/docs/LangRef.md
M llvm/include/llvm/Analysis/ConstraintSystem.h
M llvm/include/llvm/IR/IntrinsicInst.h
M llvm/include/llvm/InitializePasses.h
A llvm/include/llvm/Transforms/Scalar/LogicalSROA.h
M llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
M llvm/lib/Analysis/ConstraintSystem.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp
M llvm/lib/Transforms/Scalar/CMakeLists.txt
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
A llvm/lib/Transforms/Scalar/LogicalSROA.cpp
M llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
M llvm/lib/Transforms/Utils/FixIrreducible.cpp
M llvm/lib/Transforms/Utils/UnifyLoopExits.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlanValue.h
M llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
M llvm/test/CodeGen/AArch64/scalable_masked_interleaved_stores.ll
M llvm/test/CodeGen/AArch64/sve-ldst-sext.ll
M llvm/test/CodeGen/AArch64/sve-ldst-zext.ll
A llvm/test/CodeGen/AArch64/vector-deinterleave-load.ll
A llvm/test/CodeGen/AArch64/vector-interleave-store.ll
A llvm/test/CodeGen/AArch64/vselect-masked-shift.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fcmp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmad.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fract.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.frexp.mant.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.cd.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-legalize-range-metadata.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector-pointer-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-weird-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/trunc-brc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/add-max.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-sin-cos-f16-f32.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bitop3.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-return-types.ll
M llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll
M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll
M llvm/test/CodeGen/AMDGPU/float-sopc-vopc.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaxnum.ll
M llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminnum.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/fsub-as-fneg-src-modifier.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/literal64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.flat.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.store.async.from.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.modf.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/lround.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/memset-pattern.ll
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-global.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-smem.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/RISCV/rvp-zip.ll
A llvm/test/CodeGen/SPIRV/constant/fp128-unsupported.ll
M llvm/test/CodeGen/SPIRV/structurizer/HLSLControlFlowHint-pass-check.ll
M llvm/test/Transforms/ConstraintElimination/gep-arithmetic-signed-predicates.ll
A llvm/test/Transforms/ConstraintElimination/lshr.ll
M llvm/test/Transforms/FixIrreducible/bug45623.ll
M llvm/test/Transforms/FixIrreducible/multiedge.ll
M llvm/test/Transforms/FixIrreducible/nested.ll
M llvm/test/Transforms/FixIrreducible/switch.ll
M llvm/test/Transforms/FixIrreducible/unreachable.ll
M llvm/test/Transforms/FixIrreducible/unsupported-terminator.ll
A llvm/test/Transforms/LSROA/array.ll
A llvm/test/Transforms/LSROA/basictest.ll
A llvm/test/Transforms/LSROA/escaping.ll
A llvm/test/Transforms/LSROA/nesting.ll
A llvm/test/Transforms/LSROA/normal-gep.ll
A llvm/test/Transforms/LSROA/phi.ll
A llvm/test/Transforms/LSROA/select.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleave-low-vf-cost.ll
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
M llvm/test/Transforms/UnifyLoopExits/basic.ll
M llvm/test/Transforms/UnifyLoopExits/integer_guards.ll
M llvm/test/Transforms/UnifyLoopExits/multiedge.ll
M llvm/test/Transforms/UnifyLoopExits/nested.ll
M llvm/test/Transforms/UnifyLoopExits/restore-ssa.ll
M llvm/test/Transforms/UnifyLoopExits/switch.ll
M llvm/test/Transforms/UnifyLoopExits/undef-phis.ll
M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsCG.cpp
M mlir/test/Dialect/LLVMIR/mem2reg.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-worker-reduction-private.mlir
M mlir/test/mlir-tblgen/op-result.td
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsCGTest.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/arpa/inet/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/aokblast/lldb/fix_auxilary_handle
Commit: c7ad68262ff4f5156d8bfe31cda849abda8e5b48
https://github.com/llvm/llvm-project/commit/c7ad68262ff4f5156d8bfe31cda849abda8e5b48
Author: aokblast <aokblast at FreeBSD.org>
Date: 2026-08-08 (Sat, 08 Aug 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticIDs.h
M clang/lib/Driver/ToolChains/FreeBSD.cpp
M clang/lib/Driver/ToolChains/Serenity.cpp
M clang/test/Driver/freebsd-mips-as.c
M clang/test/Driver/freebsd.c
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M flang-rt/lib/cuda/allocator.cpp
M flang/include/flang/Lower/AbstractConverter.h
M flang/include/flang/Lower/Bridge.h
M flang/include/flang/Lower/PFTBuilder.h
M flang/include/flang/Optimizer/Builder/Runtime/CUDA/Descriptor.h
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/include/flang/Runtime/CUDA/descriptor.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/PFTBuilder.cpp
M flang/lib/Lower/Runtime.cpp
M flang/lib/Optimizer/Builder/Runtime/CUDA/Descriptor.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Transforms/AffinePromotion.cpp
M flang/lib/Optimizer/Transforms/ControlFlowConverter.cpp
M flang/lib/Optimizer/Transforms/FIRToSCF.cpp
M flang/test/Fir/CUDA/cuda-code-gen.mlir
M flang/test/Fir/FirToSCF/do-loop.fir
M flang/test/Fir/loop01.fir
M flang/test/HLFIR/assumed_shape_with_value_keyword.f90
M flang/test/HLFIR/optional_dummy.f90
M flang/test/Integration/OpenMP/parallel-private-reduction-worstcase.f90
M flang/test/Integration/ivdep.f90
M flang/test/Lower/CUDA/cuda-allocatable.cuf
M flang/test/Lower/CUDA/cuda-derived.cuf
M flang/test/Lower/CUDA/cuda-return01.cuf
M flang/test/Lower/CUDA/cuda-return02.cuf
M flang/test/Lower/HLFIR/intrinsic-subroutines.f90
M flang/test/Lower/MIF/change_team2.f90
M flang/test/Lower/OpenACC/Todo/acc-unstructured-combined-construct.f90
M flang/test/Lower/OpenACC/Todo/do-loops-to-acc-loops-todo.f90
M flang/test/Lower/OpenACC/acc-cache.f90
M flang/test/Lower/OpenACC/acc-declare.f90
M flang/test/Lower/OpenACC/acc-terminator.f90
M flang/test/Lower/OpenACC/acc-unstructured.f90
M flang/test/Lower/OpenMP/default-clause.f90
M flang/test/Lower/OpenMP/hlfir-seqloop-parallel.f90
M flang/test/Lower/OpenMP/loop-compound.f90
M flang/test/Lower/OpenMP/parallel-private-clause-fixes.f90
M flang/test/Lower/OpenMP/parallel-reduction3.f90
M flang/test/Lower/OpenMP/sections-predetermined-private.f90
M flang/test/Lower/OpenMP/shared-loop.f90
M flang/test/Lower/OpenMP/stop-stmt-in-region.f90
M flang/test/Lower/OpenMP/unstructured.f90
M flang/test/Lower/OpenMP/wsloop-reduction-allocatable-array-minmax.f90
M flang/test/Lower/OpenMP/wsloop-unstructured.f90
M flang/test/Lower/OpenMP/wsloop-variable.f90
M flang/test/Lower/allocatable-polymorphic.f90
M flang/test/Lower/branching-directive.f90
M flang/test/Lower/dispatch.f90
M flang/test/Lower/do_concurrent_loop_in_nested_block.f90
M flang/test/Lower/do_loop.f90
A flang/test/Lower/do_loop_execute_region_wrap.f90
M flang/test/Lower/do_loop_unstructured.f90
M flang/test/Lower/fail_image.f90
A flang/test/Lower/if_construct_execute_region_wrap.f90
M flang/test/Lower/ifconvert.f90
M flang/test/Lower/infinite_loop.f90
M flang/test/Lower/inline_directive.f90
M flang/test/Lower/ivdep.f90
M flang/test/Lower/loops.f90
M flang/test/Lower/loops2.f90
M flang/test/Lower/mixed_loops.f90
M flang/test/Lower/nsw.f90
M flang/test/Lower/pre-fir-tree02.f90
M flang/test/Lower/while_loop.f90
M flang/test/Transforms/DoConcurrent/skip_all_nested_loops.f90
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/hdr/CMakeLists.txt
M libc/test/UnitTest/CMakeLists.txt
M libc/test/UnitTest/ExecuteFunctionUnix.cpp
M libc/test/UnitTest/HermeticTestUtils.cpp
M libc/test/UnitTest/LibcDeathTestExecutors.cpp
M libc/test/src/stdlib/CMakeLists.txt
M libcxx/docs/Status/Cxx23Issues.csv
M libcxx/include/__configuration/availability.h
M libcxx/include/__functional/function.h
M libcxx/include/__ranges/lazy_split_view.h
M libcxx/test/libcxx/atomics/builtin_clear_padding.pass.cpp
M libcxx/test/std/numerics/numeric.ops/numeric.ops.sat/saturating.bitint.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.adjacent.transform/helpers.h
M libcxx/test/std/ranges/range.adaptors/range.adjacent.transform/iterator/member_types.compile.pass.cpp
M lld/ELF/Arch/RISCV.cpp
M lld/test/ELF/riscv-feature-zicfilp-unlabeled.s
M lldb/include/lldb/Core/ModuleSpec.h
M lldb/source/API/SBAddressRangeList.cpp
M lldb/source/API/SBMemoryRegionInfo.cpp
M lldb/source/Breakpoint/Breakpoint.cpp
M lldb/source/Breakpoint/BreakpointLocation.cpp
M lldb/source/Breakpoint/BreakpointLocationList.cpp
M lldb/source/Breakpoint/BreakpointOptions.cpp
M lldb/source/Breakpoint/BreakpointResolverName.cpp
M lldb/source/Breakpoint/Watchpoint.cpp
M lldb/source/Breakpoint/WatchpointList.cpp
M lldb/source/Core/Disassembler.cpp
M lldb/source/Core/DumpDataExtractor.cpp
M lldb/source/Core/DynamicLoader.cpp
M lldb/source/Core/FormatEntity.cpp
M lldb/source/Core/IOHandler.cpp
M lldb/source/Core/IOHandlerCursesGUI.cpp
M lldb/source/Core/Mangled.cpp
M lldb/source/Core/SearchFilter.cpp
M lldb/source/Core/SourceManager.cpp
M lldb/source/DataFormatters/FormattersHelpers.cpp
M lldb/source/DataFormatters/StringPrinter.cpp
M lldb/source/DataFormatters/TypeCategory.cpp
M lldb/source/DataFormatters/TypeSynthetic.cpp
M lldb/source/DataFormatters/ValueObjectPrinter.cpp
M lldb/source/DataFormatters/VectorType.cpp
M lldb/source/Expression/IRInterpreter.cpp
M lldb/source/Expression/Materializer.cpp
M lldb/source/Expression/REPL.cpp
M lldb/source/Host/common/ProcessLaunchInfo.cpp
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
M lldb/source/Plugins/TraceExporter/docs/htr.md
M lldb/source/Symbol/SymbolContext.cpp
M lldb/source/Symbol/Type.cpp
M lldb/source/Symbol/UnwindPlan.cpp
M lldb/source/Utility/Event.cpp
M lldb/source/Utility/ProcessInfo.cpp
M lldb/source/Utility/StructuredData.cpp
M lldb/source/ValueObject/ValueObject.cpp
M lldb/test/API/commands/gui/spawn-threads/TestGuiSpawnThreads.py
M llvm/docs/LangRef.md
M llvm/include/llvm/Analysis/ConstraintSystem.h
M llvm/include/llvm/IR/IntrinsicInst.h
M llvm/include/llvm/InitializePasses.h
A llvm/include/llvm/Transforms/Scalar/LogicalSROA.h
M llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
M llvm/lib/Analysis/ConstraintSystem.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp
M llvm/lib/Transforms/Scalar/CMakeLists.txt
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
A llvm/lib/Transforms/Scalar/LogicalSROA.cpp
M llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
M llvm/lib/Transforms/Utils/FixIrreducible.cpp
M llvm/lib/Transforms/Utils/UnifyLoopExits.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlanValue.h
M llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
M llvm/test/CodeGen/AArch64/scalable_masked_interleaved_stores.ll
M llvm/test/CodeGen/AArch64/sve-ldst-sext.ll
M llvm/test/CodeGen/AArch64/sve-ldst-zext.ll
A llvm/test/CodeGen/AArch64/vector-deinterleave-load.ll
A llvm/test/CodeGen/AArch64/vector-interleave-store.ll
A llvm/test/CodeGen/AArch64/vselect-masked-shift.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fcmp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmad.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fract.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.frexp.mant.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.cd.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-legalize-range-metadata.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector-pointer-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-weird-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/trunc-brc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/add-max.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-sin-cos-f16-f32.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bitop3.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-return-types.ll
M llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll
M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll
M llvm/test/CodeGen/AMDGPU/float-sopc-vopc.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaxnum.ll
M llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminnum.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/fsub-as-fneg-src-modifier.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/literal64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.flat.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.store.async.from.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.modf.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/lround.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/memset-pattern.ll
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-global.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-smem.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/RISCV/rvp-zip.ll
A llvm/test/CodeGen/SPIRV/constant/fp128-unsupported.ll
M llvm/test/CodeGen/SPIRV/structurizer/HLSLControlFlowHint-pass-check.ll
M llvm/test/Transforms/ConstraintElimination/gep-arithmetic-signed-predicates.ll
A llvm/test/Transforms/ConstraintElimination/lshr.ll
M llvm/test/Transforms/FixIrreducible/bug45623.ll
M llvm/test/Transforms/FixIrreducible/multiedge.ll
M llvm/test/Transforms/FixIrreducible/nested.ll
M llvm/test/Transforms/FixIrreducible/switch.ll
M llvm/test/Transforms/FixIrreducible/unreachable.ll
M llvm/test/Transforms/FixIrreducible/unsupported-terminator.ll
A llvm/test/Transforms/LSROA/array.ll
A llvm/test/Transforms/LSROA/basictest.ll
A llvm/test/Transforms/LSROA/escaping.ll
A llvm/test/Transforms/LSROA/nesting.ll
A llvm/test/Transforms/LSROA/normal-gep.ll
A llvm/test/Transforms/LSROA/phi.ll
A llvm/test/Transforms/LSROA/select.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleave-low-vf-cost.ll
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
M llvm/test/Transforms/UnifyLoopExits/basic.ll
M llvm/test/Transforms/UnifyLoopExits/integer_guards.ll
M llvm/test/Transforms/UnifyLoopExits/multiedge.ll
M llvm/test/Transforms/UnifyLoopExits/nested.ll
M llvm/test/Transforms/UnifyLoopExits/restore-ssa.ll
M llvm/test/Transforms/UnifyLoopExits/switch.ll
M llvm/test/Transforms/UnifyLoopExits/undef-phis.ll
M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsCG.cpp
M mlir/test/Dialect/LLVMIR/mem2reg.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-worker-reduction-private.mlir
M mlir/test/mlir-tblgen/op-result.td
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsCGTest.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/arpa/inet/BUILD.bazel
Log Message:
-----------
Merge branch 'users/aokblast/lldb/fix_auxilary_handle' into users/aokblast/lldb/mmap_fix_for_reexport
Compare: https://github.com/llvm/llvm-project/compare/c98bd8c93940...c7ad68262ff4
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