[all-commits] [llvm/llvm-project] 3cce63: Enforce single-operand form for llvm.loop.vectoriz...

[Madhur Amilkanthwar via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3cce637322a762daef7b50e4997c86af94d2d3c6
      https://github.com/llvm/llvm-project/commit/3cce637322a762daef7b50e4997c86af94d2d3c6
  Author: Madhur Amilkanthwar <madhura at nvidia.com>
  Date:   2026-08-07 (Fri, 07 Aug 2026)

  Changed paths:
    M clang/lib/CodeGen/CGLoopInfo.cpp
    M clang/test/CodeGenCXX/pragma-loop-predicate.cpp
    M llvm/docs/LangRef.md
    M llvm/include/llvm/IR/AutoUpgrade.h
    M llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
    M llvm/lib/IR/AutoUpgrade.cpp
    M llvm/lib/IR/Verifier.cpp
    M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
    A llvm/test/Bitcode/upgrade-loop-vectorize-predicate-enable.ll
    A llvm/test/Bitcode/upgrade-loop-vectorize-predicate-enable.ll.bc
    M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/predicated-costs.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/widen-gep-all-indices-invariant.ll
    M llvm/test/Transforms/LoopVectorize/ARM/prefer-tail-loop-folding.ll
    M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-loop-hint.ll
    M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-prefer-flag.ll
    M llvm/test/Transforms/LoopVectorize/VPlan/AArch64/sve-tail-folding-forced.ll
    M llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing.ll
    M llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
    M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
    M llvm/test/Transforms/LoopVectorize/X86/tail_folding_and_assume_safety.ll
    M llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll
    M llvm/test/Transforms/LoopVectorize/no-fold-tail-by-masking-iv-external-uses.ll
    M llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
    M llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
    M llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll
    M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-predicated-early-exit.ll
    M llvm/test/Verifier/llvm.loop.distribute.ll
    A llvm/test/Verifier/llvm.loop.vectorize.predicate.ll
    M mlir/lib/Target/LLVMIR/LoopAnnotationImporter.cpp
    M mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp
    M mlir/test/Target/LLVMIR/Import/metadata-loop.ll
    M mlir/test/Target/LLVMIR/loop-metadata.mlir

  Log Message:
  -----------
  Enforce single-operand form for llvm.loop.vectorize.predicate metadata (#213902)

Replace the two-operand boolean form
!{!"llvm.loop.vectorize.predicate.enable", i1 0/1} with a single-operand
enable/disable pair:

  !{!"llvm.loop.vectorize.predicate.enable"}
  !{!"llvm.loop.vectorize.predicate.disable"}

The Verifier rejects the two-operand form, AutoUpgrade rewrites old
bitcode, and the readers and producers in LLVM, Clang and MLIR are
updated.

Please refer to RFC:

https://discourse.llvm.org/t/rfc-enforce-single-operand-format-for-all-enable-metadata-nodes/90571/

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