[all-commits] [llvm/llvm-project] bc00b3: [AArch64][CostModel] Explicitly disable histograms...
Aiden Grossman via All-commits
all-commits at lists.llvm.org
Thu Aug 6 22:44:37 PDT 2026
Branch: refs/heads/users/boomanaiden154/main.clang-make-newpm-switch-respect-shoulddefaulttonewpm
Home: https://github.com/llvm/llvm-project
Commit: bc00b3aae17eb8d3f1dee2e8fbbdf5c3e4a36546
https://github.com/llvm/llvm-project/commit/bc00b3aae17eb8d3f1dee2e8fbbdf5c3e4a36546
Author: Gaëtan Bossu <gaetan.bossu at arm.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/histograms.ll
Log Message:
-----------
[AArch64][CostModel] Explicitly disable histograms for nxv1 types (#214470)
Currently, histograms are not disabled for vscale x 1 types, but LV will
implicitly not generate them because surrounding arithmetic instructions
are invalid for vscale x 1.
SDAG does not implement operand widening for histograms, so this patch
explicitly disables those cases.
Commit: 708dafb270b5f6971c6666cc0afe96d227fb198d
https://github.com/llvm/llvm-project/commit/708dafb270b5f6971c6666cc0afe96d227fb198d
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M llvm/tools/spirv-tools/CMakeLists.txt
Log Message:
-----------
[SPIR-V] Build vendored SPIRV-Tools in Release mode (#214159)
Default build mode in SPIRV-Tools is Debug
Commit: ac9e7f5e9d9170a56945c716b6c87126a3d0963d
https://github.com/llvm/llvm-project/commit/ac9e7f5e9d9170a56945c716b6c87126a3d0963d
Author: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
A clang-tools-extra/docs/clang-tidy/checks/bugprone/argument-comment.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/argument-comment.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/assert-side-effect.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/assert-side-effect.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/assignment-in-selection-statement.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/assignment-in-selection-statement.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/bitwise-pointer-cast.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/bitwise-pointer-cast.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/branch-clone.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/branch-clone.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/capturing-this-in-member-variable.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/capturing-this-in-member-variable.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/casting-through-void.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/casting-through-void.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/chained-comparison.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/chained-comparison.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/compare-pointer-to-member-virtual-function.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/compare-pointer-to-member-virtual-function.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/copy-constructor-init.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/copy-constructor-init.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/crtp-constructor-accessibility.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/crtp-constructor-accessibility.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/dangling-handle.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/dangling-handle.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/derived-method-shadowing-base-method.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/derived-method-shadowing-base-method.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/easily-swappable-parameters.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/easily-swappable-parameters.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/empty-catch.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/empty-catch.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/exception-copy-constructor-throws.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/exception-copy-constructor-throws.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/exception-escape.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/exception-escape.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/fold-init-type.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/fold-init-type.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/forwarding-reference-overload.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/forwarding-reference-overload.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/implicit-widening-of-multiplication-result.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/implicit-widening-of-multiplication-result.rst
Log Message:
-----------
[clang-tidy][docs] Rename bugprone check docs to Markdown [1/4] (#214412)
Tracking issue: #201242
See the [migration guide] for more information.
[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
This is the mechanical rename for part 1/4 of the remaining `bugprone`
check documentation.
The rewrite is provided by the next PR in this stack.
Commit: 11ba1b712acbee90dcc07b36467a7b2bb5a9b07b
https://github.com/llvm/llvm-project/commit/11ba1b712acbee90dcc07b36467a7b2bb5a9b07b
Author: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M clang-tools-extra/docs/clang-tidy/checks/bugprone/argument-comment.md
M clang-tools-extra/docs/clang-tidy/checks/bugprone/assert-side-effect.md
M clang-tools-extra/docs/clang-tidy/checks/bugprone/assignment-in-selection-statement.md
M clang-tools-extra/docs/clang-tidy/checks/bugprone/bitwise-pointer-cast.md
M clang-tools-extra/docs/clang-tidy/checks/bugprone/branch-clone.md
M clang-tools-extra/docs/clang-tidy/checks/bugprone/capturing-this-in-member-variable.md
M clang-tools-extra/docs/clang-tidy/checks/bugprone/casting-through-void.md
M clang-tools-extra/docs/clang-tidy/checks/bugprone/chained-comparison.md
M clang-tools-extra/docs/clang-tidy/checks/bugprone/compare-pointer-to-member-virtual-function.md
M clang-tools-extra/docs/clang-tidy/checks/bugprone/copy-constructor-init.md
M clang-tools-extra/docs/clang-tidy/checks/bugprone/crtp-constructor-accessibility.md
M clang-tools-extra/docs/clang-tidy/checks/bugprone/dangling-handle.md
M clang-tools-extra/docs/clang-tidy/checks/bugprone/derived-method-shadowing-base-method.md
M clang-tools-extra/docs/clang-tidy/checks/bugprone/easily-swappable-parameters.md
M clang-tools-extra/docs/clang-tidy/checks/bugprone/empty-catch.md
M clang-tools-extra/docs/clang-tidy/checks/bugprone/exception-copy-constructor-throws.md
M clang-tools-extra/docs/clang-tidy/checks/bugprone/exception-escape.md
M clang-tools-extra/docs/clang-tidy/checks/bugprone/fold-init-type.md
M clang-tools-extra/docs/clang-tidy/checks/bugprone/forwarding-reference-overload.md
M clang-tools-extra/docs/clang-tidy/checks/bugprone/implicit-widening-of-multiplication-result.md
Log Message:
-----------
[clang-tidy][docs] Rewrite bugprone check docs to Markdown [1/4] (#214413)
Tracking issue: #201242
See the [migration guide] for more information.
[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
This rewrites part 1/4 of the remaining bugprone check documentation
from reST to MyST Markdown.
AI Usage: This was prepared with rst2myst and GPT5.6-assisted cleanup.
I manually verified that the documentation renders as expected.
Preview site:
https://broken.life/llvm-staging/bugprone-markdown-port/
Commit: c7317d79aacf76b5eb2dc65010e574a5269838ef
https://github.com/llvm/llvm-project/commit/c7317d79aacf76b5eb2dc65010e574a5269838ef
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
A clang/test/CIR/CodeGen/tls-model.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Dialect/LLVMIR/alias.mlir
M mlir/test/Dialect/LLVMIR/global.mlir
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
M mlir/test/Target/LLVMIR/Import/global-variables.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[CIR][MLIR-LLVM] Add 'thread local mode/model' attribute support (#214337)
The main purpose of this patch is to implement the 'tls_model' attribute
for ClangIR. However, this required updating the LLVM-IR dialect to ALSO
support this, not just as a bool. This patch threads it into both sides.
CIR tries to refer to it as "TLS_Model" to match the C/C++ attribute
closely, the LLVM Dialect refers to it as ThreadLocalMode to reflect
better what LLVM does.
Left as still 'not done' (in CIR only!) is the lowering of the 'other'
kinds of thread-local settings, which are intended to do various levels
of locking/initialization. Those are left for a future implementation
effort. The C++ test itself is taken directly from classic codegen.
Commit: 0a9cfa09242aa1cc162e55ddf1bbcc50664d763d
https://github.com/llvm/llvm-project/commit/0a9cfa09242aa1cc162e55ddf1bbcc50664d763d
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
Log Message:
-----------
[mlir][llvm] Add operations for coroutine intrinsics (#214099)
This adds operations to the LLVM dialect to represent coroutine
intrinsics that were previously missing from the dialect. A few
coroutine operations were already in place. This change adds operations
for the remaining intrinsics that cab be generated by Clang. There are
some additional coroutine intrinsics defined in LLVM IR that aren't
covered, but I'm omitting those until they are needed.
We are in the process of implementing coroutine support in CIR, and
these are the operations we'll need for lowering to LLVM.
Assisted-by: Cursor / Grok 4.5
Commit: 3bace2206a56e39766a0697d1d63b05f537793a6
https://github.com/llvm/llvm-project/commit/3bace2206a56e39766a0697d1d63b05f537793a6
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/test/CodeGen/AArch64/neon/intrinsics.c
Log Message:
-----------
[CIR][AArch64] Update builtin handlers to use emitNeonCallToOp (#214075)
This is another change to prepare AArch64 builtin handling for the
transition to constrained FP handling. It replaces a number of places
where we were creating CIR operations directly with calls to
emitNeonCallToOp so that we will be able to centralize the constrained
FP handling.
This also updates the vrndns_f32 to eliminate a redundant load of the
operand, which is the only part of this change with a visible difference
in the output.
Assisted-by: Cursor / Grok 4.5
Commit: 02b08387ae43a19b5f2817641d36b9398a0e19e5
https://github.com/llvm/llvm-project/commit/02b08387ae43a19b5f2817641d36b9398a0e19e5
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/test/Target/LLVMIR/Import/intrinsic-unregistered.ll
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
Log Message:
-----------
[mlir][llvm] Add more constrained FP operations (#213745)
This change adds special constrained forms of transcendental operations
for the remaining cases that lower to contrained fp intrinsic calls. It
also adds fast-math flag support to the constrained operations, which is
needed to handle combinations of Clang command-line options such as
"-ffinite-math-only -ftrapping-math".
Assisted-by: Cursor / various models
Commit: b2ba87ae2551808b36fc74dfac8199d54c043b4a
https://github.com/llvm/llvm-project/commit/b2ba87ae2551808b36fc74dfac8199d54c043b4a
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M lldb/include/lldb/Target/DynamicLoader.h
M lldb/source/Core/DynamicLoader.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp
Log Message:
-----------
[lldb] Split DynamicLoader binary loading into locate and load (NFCI) (#214372)
LoadBinaryWithUUIDAndAddress both searched for a binary and registered
it with the Target. Split it into LocateBinaries, which only searches,
and LoadBinaryInTarget, which mutates the Target, with
LocateAndLoadBinary keeping the single binary case a one-liner.
The eight binary parameters and the results of the search are bundled in
a new BinarySpec struct, and both entry points return an llvm::Expected.
The motivation is a follow-up that runs LocateBinaries in parallel on
the thread pool. NFC, except for some small improvements to the error
handling because we don't write to the async output stream directly (and
fixed the newline).
Commit: 3705e63f8099e46c5a29ffef91a1cde9a91de392
https://github.com/llvm/llvm-project/commit/3705e63f8099e46c5a29ffef91a1cde9a91de392
Author: Daniel Chen <cdchen at ca.ibm.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M flang/lib/Semantics/compute-offsets.cpp
A flang/test/Lower/common-block-char0.f90
A flang/test/Semantics/common-block-char0.f90
Log Message:
-----------
[flang] Fix incorrect offset for zero-size COMMON block members. (#214174)
Fixes #214171
`ComputeOffsetsHelper::DoSymbol()` in
`flang/lib/Semantics/compute-offsets.cpp` returned early without calling
`symbol.set_offset()` when a symbol had zero size (e.g. CHARACTER*0). As
a result, every zero-size symbol in a COMMON block retained its default
offset of 0 — the block base address — instead of its correct sequential
position.
This incorrect offset caused two observable bugs:
1. **Wrong storage address**: LOC() and lowering always returned the
block base address for zero-size members instead of their actual
sequential position.
2. **False "cannot backward-extend" error**: When a zero-size COMMON
block member appeared in an EQUIVALENCE association, the backward-extend
check (`dep.offset > symbol.offset()`) incorrectly fired because
`symbol.offset()` was always 0. For example, the following valid code
was falsely rejected:
```fortran
program p09
integer(8) :: i8
character(0) :: zc0
character(8) :: c8
common /blk/ i8, zc0
equivalence (c8(5:8), zc0)
end program
Error before fix:
`error: 'zc0' cannot backward-extend COMMON block /blk/ via EQUIVALENCE
with 'c8'`
After the fix, `zc0` is correctly assigned offset 8 (after `i8`), so
`dep.offset` (4) < `symbol.offset()` (8) and no error is raised.
Commit: 4e95a2df34548e032b3a93eef431b73db24839d7
https://github.com/llvm/llvm-project/commit/4e95a2df34548e032b3a93eef431b73db24839d7
Author: Kamlesh Kumar <kamlesh.kumar at arm.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
A llvm/test/CodeGen/AArch64/fixed-vector-interleave-deinterleave-no-neon.ll
Log Message:
-----------
[CodeGen] Add scalarization for vector (de)interleave (#212547)
This is required when NEON is disabled with -mattr=-neon.
Commit: 2b32e13e65a35fa8f757eee89992e172f5cb0da5
https://github.com/llvm/llvm-project/commit/2b32e13e65a35fa8f757eee89992e172f5cb0da5
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/test/CodeGen/AMDGPU/fabs-vector-truncate.ll
Log Message:
-----------
[SDAG] Handle vector expansion when expanding FABS (#214341)
Before this, vector FABS that were scheduled for expansion would hit the
getSignAsIntValue() case and either assert there or fail later for lock
of instruction selection for a bitcast that's only looking at the scalar
size.
Now, we unroll to scalars as needed.
Test pre-committed in #214288
Commit: 05ecef4367dad077961380d643c83db83794f023
https://github.com/llvm/llvm-project/commit/05ecef4367dad077961380d643c83db83794f023
Author: Anshil Gandhi <95053726+gandhi56 at users.noreply.github.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
A llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-merge-readanylane.mir
Log Message:
-----------
[AMDGPU][GlobalISel] Pre-commit tests for readanylane merge regbank combine (NFC) (#214355)
Add regbank-combiner tests covering a copy to vgpr whose source is a
merge or
build_vector of `G_AMDGPU_READANYLANE` results mixed with uniform
values.
These currently keep the round trip through sgprs. The tests also cover
the two
cases where the transform must not fire:
- the sgpr merge has another user, so it has to be kept;
- all merge sources are uniform, so moving the copy to the sources would
not
remove any readanylane.
Pre-commit only, no functional change. The combine that removes the
round trip
is in the stacked PR.
Made with [Cursor](https://cursor.com)
---------
Co-authored-by: Cursor <cursoragent at cursor.com>
Co-authored-by: Matt Arsenault <Matthew.Arsenault at amd.com>
Commit: 79bc07942adcb4819d30075890c3e8cd75b2d8c1
https://github.com/llvm/llvm-project/commit/79bc07942adcb4819d30075890c3e8cd75b2d8c1
Author: Alok Kumar Sharma <AlokKumar.Sharma at amd.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M llvm/include/llvm/Transforms/IPO/MergeFunctions.h
M llvm/lib/Transforms/IPO/MergeFunctions.cpp
A llvm/test/Transforms/MergeFunc/merge-functions-branch-weights.ll
A llvm/test/Transforms/MergeFunc/merge-functions-reordered-blocks-branch-weights.ll
A llvm/test/Transforms/MergeFunc/merge-functions-select-weights.ll
A llvm/test/Transforms/MergeFunc/merge-functions-value-profile.ll
M llvm/unittests/Transforms/IPO/MergeFunctionsTest.cpp
Log Message:
-----------
Reland "[MergeFunctions] Preserve instruction-level profile metadata during merging" (#208009) (#210138)
This relands #208009, which was reverted in #209987 after an ASan
heap-use-after-free surfaced in MergeFunctionsTest.TrueOutputModuleTest.
The failure was caused by MergeFunctionsTest destroying
FunctionAnalysisManager before ModuleAnalysisManager, while MAM holds a
cached proxy result that calls FAM.clear() on destruction. This PR adds
a commit reordering those members, so they are destroyed in the correct
order, fixing the use-after-free.
Original PR: #208009
Revert PR: #209987
Commit: bd586dd26e3ba49616175c14cb2970c581fb94b7
https://github.com/llvm/llvm-project/commit/bd586dd26e3ba49616175c14cb2970c581fb94b7
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M lldb/source/Plugins/Process/wasm/ProcessWasm.cpp
M lldb/source/Plugins/Process/wasm/ThreadWasm.cpp
M lldb/test/API/functionalities/gdb_remote_client/TestWasm.py
Log Message:
-----------
[lldb] Use the standard GDB remote thread for a non-Wasm process (#214380)
CanDebug returns true whenever the plugin is requested by name, and the
architecture is not known until the stub reports it after connecting.
This means that a non-Wasm process can end up with a ThreadWasm whose
register context and unwinder have nothing to operate on.
Create the plain ThreadGDBRemote once the architecture is known, and add
a helper so that the check covers wasm64 as well as wasm32.
rdar://182229301
Commit: 08d27f08335973e084254d8c02033a322bdb3ead
https://github.com/llvm/llvm-project/commit/08d27f08335973e084254d8c02033a322bdb3ead
Author: elizabethandrews <elizabeth.andrews at intel.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/AST/TypeBase.h
M clang/include/clang/AST/TypeProperties.td
A clang/include/clang/Basic/SPIRVTypes.def
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/MicrosoftMangle.cpp
M clang/lib/AST/NSAPI.cpp
M clang/lib/AST/PrintfFormatString.cpp
M clang/lib/AST/Type.cpp
M clang/lib/AST/TypeLoc.cpp
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGDebugInfo.h
M clang/lib/CodeGen/CodeGenTypes.cpp
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/lib/CodeGen/QualTypeMapper.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Serialization/ASTCommon.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/UnifiedSymbolResolution/USRGeneration.cpp
A clang/test/AST/spirv-event-type.cpp
A clang/test/CodeGenCXX/spirv-event-type.cpp
A clang/test/Modules/spirv-event.cpp
A clang/test/Sema/spirv-event.c
A clang/test/SemaCXX/spirv-event.cpp
M clang/tools/libclang/CIndex.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
Log Message:
-----------
[Clang][SPIRV] Add __spirv_event_t builtin type (#207077)
Add a new builtin type __spirv_event_t for SPIR-V targets. It represents
SPIR-V's OpTypeEvent and lowers to the target("spirv.Event") extension
type.
We would like to expose SPIR-V instructions to users via builtins (not
yet
implemented). The builtins return an event type.
Assisted by Claude Opus 4.8 for writing tests.
Commit: a80d93f18afbd58b6700bafa7484c68e3aca34f6
https://github.com/llvm/llvm-project/commit/a80d93f18afbd58b6700bafa7484c68e3aca34f6
Author: Colin De Vlieghere <cdevlieghere at tesla.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/Transforms/Bufferize.h
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
M mlir/test/Dialect/ControlFlow/one-shot-bufferize.mlir
Log Message:
-----------
[mlir][bufferization] Bufferize all edges to a repeated successor (#214368)
bufferizeBlockSignature only rewrote the first successor index that
matched the target block. Branch ops such as cf.cond_br can list the
same destination more than once, but the later edges were left as
tensors and broke multi-block bufferization.
Now we simply iterate the block's BlockOperands so each successor edge
is handled once.
Commit: b870d4f83b0b98fb469e1ef5baa845f5e2e5f24a
https://github.com/llvm/llvm-project/commit/b870d4f83b0b98fb469e1ef5baa845f5e2e5f24a
Author: Maria Fernanda Guimarães <66797940+mafeguimaraes at users.noreply.github.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M clang-tools-extra/clangd/unittests/HoverTests.cpp
M clang/lib/Parse/ParseHLSL.cpp
M clang/test/AST/HLSL/resource_binding_attr.hlsl
Log Message:
-----------
[clangd][ParseHLSL] Fix register attribute source range for hover inside arguments (#212881)
Hovering on the slot identifier inside `register(t1)` (e.g. on `t1`)
previously produced no tooltip, only hovering on the `register` keyword
itself worked.
`HLSLResourceBindingAttr`'s `SourceRange` was zero-width: both the start
and end pointed to the start of the `register` keyword.
`ParseHLSLAnnotations` called `Attrs.addNew` with a single
`SourceLocation` instead of a full `SourceRange`. Since clangd's
`SelectionTree` only matches when the cursor falls inside an attribute's
range, a zero-width range never matched positions inside the argument.
Capture the closing `)` location before it's consumed in the
`AT_HLSLResourceBinding` case, and pass a full `SourceRange` (from the
attribute start to the closing paren) to `addNew`.
Fixes #212749
Commit: e791d91332ae094dc3b6bdd0ba227efbab941d31
https://github.com/llvm/llvm-project/commit/e791d91332ae094dc3b6bdd0ba227efbab941d31
Author: Petar Jovanovic <pjovanov at amd.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-wmma-xdl.mir
A llvm/test/CodeGen/AMDGPU/insert-delay-alu-wmma.mir
Log Message:
-----------
[AMDGPU] Skip s_delay_alu for WMMA C-reuse chains (#214101)
Consecutive wmma/swmmac ops accumulating into the same matrix C register
reuse the accumulator in place, so the tied srcC read is omitted and no
delay is needed. AMDGPUInsertDelayAlu did not model this and emitted an
s_delay_alu that stalls the reuse chain.
Detect a C-reuse edge (tied srcC exactly matches the previous wmma/
swmmac dest, with no intervening instruction) and skip the delay for
that operand. This applies on all wmma-capable targets (gfx11+).
Commit: 7c31d55c29ae0eb60f3ddcec5e1bf35942f6ed94
https://github.com/llvm/llvm-project/commit/7c31d55c29ae0eb60f3ddcec5e1bf35942f6ed94
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2026-08-07 (Fri, 07 Aug 2026)
Changed paths:
M llvm/test/tools/llubi/gep.ll
M llvm/tools/llubi/lib/Context.cpp
Log Message:
-----------
[llubi] Fix GEP return type on the fast path (#214235)
Closes https://github.com/llvm/llvm-project/issues/214144.
Commit: dea174bac7e37f68bb4ad5c204b06a5795b27e0f
https://github.com/llvm/llvm-project/commit/dea174bac7e37f68bb4ad5c204b06a5795b27e0f
Author: Grigory Pastukhov <gpastukhov at meta.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M clang-tools-extra/clang-tidy/modernize/ReturnBracedInitListCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/modernize/return-braced-init-list.md
M clang-tools-extra/test/clang-tidy/checkers/modernize/return-braced-init-list.cpp
Log Message:
-----------
[clang-tidy] modernize-return-braced-init-list: skip types with an initializer_list constructor (#205440)
`modernize-return-braced-init-list` rewrites `return T(args)` to `return
T{args}`. When `T` has a `std::initializer_list` constructor this can
change behavior: per [over.match.list], list-initialization prefers
initializer-list constructors, so the braced form may call a different
constructor than the parenthesized call.
Commit: f696e2759fafa77bf9c0b2cc78ce007fb95c3091
https://github.com/llvm/llvm-project/commit/f696e2759fafa77bf9c0b2cc78ce007fb95c3091
Author: Kaitlin Peng <kaitlinpeng at microsoft.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M clang/include/clang/Basic/HLSLIntrinsics.td
M clang/lib/Headers/hlsl/hlsl_compat_overloads.h
A clang/test/CodeGenHLSL/builtins/pow_mat-overloads.hlsl
A clang/test/CodeGenHLSL/builtins/pow_mat.hlsl
M clang/test/SemaHLSL/BuiltIns/binary-compat-overload-warnings.hlsl
M clang/test/SemaHLSL/BuiltIns/half-float-only-errors2.hlsl
A clang/test/SemaHLSL/BuiltIns/pow_mat-errors.hlsl
M llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
A llvm/test/CodeGen/DirectX/pow_mat.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/pow_mat.ll
Log Message:
-----------
[Matrix] Implement matrix support for the `pow` intrinsic (#212514)
Closes #184513.
This PR implements the matrix api for `pow` in `HLSLintrinsics.td`, adds
matrix codegen tests, matrix sema tests, and matrix backend tests.
Assisted-by: Github Copilot
Commit: 38ca11fed5ec1448f16b717c2676562c7f99b969
https://github.com/llvm/llvm-project/commit/38ca11fed5ec1448f16b717c2676562c7f99b969
Author: Christopher Ferris <cferris1000 at users.noreply.github.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M compiler-rt/lib/scudo/standalone/linux.cpp
M compiler-rt/lib/scudo/standalone/primary32.h
Log Message:
-----------
[scudo] Add check to verify locking is correct. (#214377)
Added checks that at the end of lockSlow, the lock is held and when
doing an unlock, the lock is held.
This found a bug in primary32.h:unmapTestOnly where the lock is not
held, so fixed that.
Commit: 429b2a7b3317384313000094f32e2dda7803f4fb
https://github.com/llvm/llvm-project/commit/429b2a7b3317384313000094f32e2dda7803f4fb
Author: schittir <sindhu.chittireddy at intel.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/Driver/ToolChains/SYCL.cpp
M clang/lib/Driver/ToolChains/SYCL.h
A clang/test/CodeGenSPIRV/spirv-host-adaptation-valist.cpp
A clang/test/Driver/sycl-msvc-version-propagation.cpp
A clang/test/Preprocessor/spir-host-adaptation-macros.cpp
A clang/test/Preprocessor/spirv-host-adaptation-macros.cpp
A clang/test/SemaSPIRV/spirv-host-adaptation-types.cpp
A clang/test/SemaSPIRV/spirv-host-adaptation-valist.cpp
Log Message:
-----------
[SYCL][SPIR-V][Windows] Extend BaseSPIRTargetInfo host-adaptation for Windows support (#208196)
The existing host-adaptation mechanism in BaseSPIRTargetInfo copies type
properties from the host but has gaps causing incorrect behavior on
Windows:
1. PointerWidth/PointerAlign, SizeType, PtrDiffType, IntPtrType were not
copied from the host; derived classes hardcoded LP64 defaults.
2. getBuiltinVaListKind() returned VoidPtr unconditionally instead of
delegating to the host's va_list kind.
3. Derived-class constructors unconditionally overwrote host-adapted
values, working on Linux only by coincidence.
This patch addresses these issues by copying pointer-related types
from the host in BaseSPIRTargetInfo, delegating va_list kind to the
host,
and setting architecture-appropriate defaults in derived classes when no
host is
present or when host and device pointer widths differ.
TO-DO (follow-up PR):
Diagnose invalid host-target pairings.
Commit: 7220098d29a9b1a2ac4b63e3f1973ddab9041a97
https://github.com/llvm/llvm-project/commit/7220098d29a9b1a2ac4b63e3f1973ddab9041a97
Author: Yao Qi <yao_qi at apple.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M lldb/test/API/macosx/expedited-stack-memory/TestExpeditedStackMemory.py
Log Message:
-----------
[lldb][test] Skip the frame 0 expedite test with an out-of-tree debugserver (#214448)
`test_memory_reads_when_examining_frame0_locals` asserts that examining
frame 0's locals reads no stack memory, which only holds when
debugserver
expedites the stopped frame's stack in `jThreadsInfo`. That is
added in b631e0cbd1c9, so the assertion only holds for an in-tree
debugserver.
The GreenDragon `lldb-cmake-sanitized` bot configures with
`-DLLDB_USE_SYSTEM_DEBUGSERVER=ON`, so it tests against the debugserver
shipped in Xcode. That one predates the expedite, so test fails:
```
FAIL: test_memory_reads_when_examining_frame0_locals
AssertionError: 2 != 0 : expected NO stack memory reads for frame 0 (its
stack is expedited in jThreadsInfo).
memory reads while examining locals: stack=2 heap=1 other=1 (total=4)
stack region: [0x16b540000,0x16f53c000)
stack reads: [0x16f53ac00,0x16f53ae00), [0x16f53aa00,0x16f53ac00)
```
It adds `@skipIfOutOfTreeDebugserver` to
`test_memory_reads_when_examining_frame0_locals`. The other three tests
in the file pass there because they only rely on the frame pointer
backchain expedite, which is old enough to be in the shipped
debugserver.
Commit: 92e1f6aaa25693c940acc362bc91cb5a6bc23426
https://github.com/llvm/llvm-project/commit/92e1f6aaa25693c940acc362bc91cb5a6bc23426
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/test/CodeGen/AMDGPU/do-not-fold-copy.mir
Log Message:
-----------
[AMDGPU] Fix SIFoldOperands miscompiling values that leave a divergent loop (#203256)
A scalar value latched per-lane inside a divergent loop was being folded
into a use after the loop, so every lane wrongly read the same value
Commit: 9bbd728946da0bc8c0aa757dfec19fe5e893ca45
https://github.com/llvm/llvm-project/commit/9bbd728946da0bc8c0aa757dfec19fe5e893ca45
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Driver/ToolChains/AMDGPU.cpp
A clang/test/Driver/Inputs/rocm/include/libhipcxx/cuda/std/atomic
M clang/test/Driver/hip-include-path.hip
Log Message:
-----------
[HIP] Add libhipcxx to the default header search path (#214279)
libhipcxx provides C++ library support for HIP device code, similar to
libcudacxx for CUDA. CUDA toolchains make libcudacxx available through
the
toolkit include path by default. HIP users should likewise be able to
include libhipcxx headers without an installation-specific include
option.
Add include/libhipcxx from the selected ROCm installation when the
directory exists. It follows the same search order and controls as the
other HIP include paths.
Commit: 0f962d8024e8a982279f941514f89e131e1bef40
https://github.com/llvm/llvm-project/commit/0f962d8024e8a982279f941514f89e131e1bef40
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
M llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir
Log Message:
-----------
[AMDGPU] Fix combineMasks dropping condition (#203180)
The problem is related to `S_AND (S_AND x, x), exec` case
When the nested mask op is the outer S_AND/S_OR first operand with two
identical operands, combineMasks kept exec instead of a nested operand,
folding to S_AND exec, exec and dropping the condition
Commit: b3946b5bb5c9a4b5feadfe532270ef823116a617
https://github.com/llvm/llvm-project/commit/b3946b5bb5c9a4b5feadfe532270ef823116a617
Author: Walter Lee <49250218+googlewalt at users.noreply.github.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M llvm/lib/CodeGen/Rematerializer.cpp
Log Message:
-----------
[CodeGen] Fix null pointer dereferencing issue (#214543)
Fixes #197580. Fixes 99f7018958ed3daf2abf8d49178c24fbf1eb1010.
In Rematerializer::isRegIdenticalAtUses(), handle case when DefVN is
null.
Commit: 5e8ac69abe478b1702000878d47fddb6234af725
https://github.com/llvm/llvm-project/commit/5e8ac69abe478b1702000878d47fddb6234af725
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/fpext-free.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
Log Message:
-----------
[AMDGPU] Fold fsub into fma_mix via free neg_lo modifier (#212305)
Rewrite the fsub->fma_mix pattern as `fma((-y), 1.0, x)` using the free
neg_lo modifier
instead of multiplying by -1.0 (which doesn't always flip the sign of
NaN), use the hardware free neg_lo bit, which does a true sign flip. As
a result, now the fold always matches fsub actual behavior instead of
only in the common case (non-NaN FP numbers)
Commit: 0376ce364eceee81b2e4885f23837846aeaedf69
https://github.com/llvm/llvm-project/commit/0376ce364eceee81b2e4885f23837846aeaedf69
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/misched-fusion-aes-post-ra.mir
A llvm/test/CodeGen/AArch64/misched-fusion-aes-pre-ra.mir
Log Message:
-----------
[AArch64] Improve AES clustering tests(NFC) (#213950)
- post-RA: rename test cases, reorder them, add artificially interfering
instruction in between pairs, add negative runlines
- add pre-RA test
- add missing label boundaries checks
Commit: 7b0121409bbfffe6c470c8b751875d9bc8259c71
https://github.com/llvm/llvm-project/commit/7b0121409bbfffe6c470c8b751875d9bc8259c71
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/misched-fusion-fmin-fmax-post-ra.mir
M llvm/test/CodeGen/AArch64/misched-fusion-fmin-fmax-pre-ra.mir
Log Message:
-----------
[AArch64] Use only virtual registers in pre-RA test(NFC) (#213951)
And add missing label boundaries checks.
Commit: 8de3384e15a1c0d7dc20f4a01623428a5962c328
https://github.com/llvm/llvm-project/commit/8de3384e15a1c0d7dc20f4a01623428a5962c328
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M libc/include/llvm-libc-macros/linux/fcntl-macros.h
M libc/include/llvm-libc-macros/linux/sched-macros.h
M libc/src/__support/threads/linux/CMakeLists.txt
M libc/src/__support/threads/linux/thread.cpp
Log Message:
-----------
[libc] Add more Linux-specific macro for fcntl and sched. (#213727)
* Add more `O_` flags (in particular, `O_LARGEFILE`) to fcntl-macros and
group all creation/status flags (shared and arch-specific) together.
* Add Linux `CLONE_` flags to sched-macros (to be exposed from
`<sched.h>`). Those are also provided in `<linux/sched.h>` kernel
header, but the libc users often expect to find them in regular
`<sched.h>` as those are passed to `clone()` syscall wrapper. Migrate
internal Linux thread implementation to use our own header (instead of
Linux kernel) for these macro.
Commit: 3316c0b7fd2b88d23f747bded0f2bf6b559bc5c3
https://github.com/llvm/llvm-project/commit/3316c0b7fd2b88d23f747bded0f2bf6b559bc5c3
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M llvm/test/Analysis/LoopAccessAnalysis/depend_diff_types.ll
Log Message:
-----------
[LAA] SCEV-licm-reduce depend_diff_types test (NFC) (#213875)
Reduce a couple of tests in depend_diff_types in a way that preserves
SCEV expressions, by creating invariants that we hoist outside the loop.
This makes the tests a bit clearer.
Illustration: https://godbolt.org/z/eTqdoPPzn
Co-authored-by: Andrei Elovikov <andrei.elovikov at sifive.com>
Commit: 10dbfc4863c9aea2fb237022c3f47fc24c02265e
https://github.com/llvm/llvm-project/commit/10dbfc4863c9aea2fb237022c3f47fc24c02265e
Author: Thibaut Goetghebuer-Planchon <thibaut.goetghebuer-planchon at arm.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
A mlir/test/Dialect/Tosa/tosa-layerwise-constant-fold-dense-resource.mlir
M mlir/test/Dialect/Tosa/tosa-layerwise-constant-fold.mlir
Log Message:
-----------
[mlir][tosa] Skip dense resource folding tests on big-endian platforms (#214479)
Commit: 36e1616725cb56bd4b9fee255d85294407b213cc
https://github.com/llvm/llvm-project/commit/36e1616725cb56bd4b9fee255d85294407b213cc
Author: Jakub Jakacki <jakub.jakacki at intel.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M compiler-rt/CMakeLists.txt
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
M compiler-rt/cmake/Modules/CompilerRTDarwinUtils.cmake
M compiler-rt/cmake/Modules/CompilerRTUtils.cmake
M compiler-rt/cmake/base-config-ix.cmake
M compiler-rt/include/CMakeLists.txt
M compiler-rt/lib/asan/tests/CMakeLists.txt
M compiler-rt/lib/builtins/CMakeLists.txt
M compiler-rt/lib/ctx_profile/tests/CMakeLists.txt
M compiler-rt/lib/fuzzer/tests/CMakeLists.txt
M compiler-rt/lib/gwp_asan/tests/CMakeLists.txt
M compiler-rt/lib/interception/tests/CMakeLists.txt
M compiler-rt/lib/memprof/tests/CMakeLists.txt
M compiler-rt/lib/orc/tests/CMakeLists.txt
M compiler-rt/lib/rtsan/tests/CMakeLists.txt
M compiler-rt/lib/sanitizer_common/tests/CMakeLists.txt
M compiler-rt/lib/sanitizer_ignorelists/CMakeLists.txt
M compiler-rt/lib/scudo/standalone/tests/CMakeLists.txt
M compiler-rt/lib/stats/CMakeLists.txt
M compiler-rt/lib/tsan/CMakeLists.txt
M compiler-rt/lib/tsan/dd/CMakeLists.txt
M compiler-rt/lib/tsan/rtl/CMakeLists.txt
M compiler-rt/lib/tsan/tests/CMakeLists.txt
M compiler-rt/lib/xray/tests/CMakeLists.txt
M compiler-rt/test/CMakeLists.txt
M compiler-rt/test/ctx_profile/CMakeLists.txt
M compiler-rt/test/rtsan/CMakeLists.txt
M compiler-rt/test/scudo/standalone/CMakeLists.txt
M compiler-rt/test/tsan/CMakeLists.txt
M compiler-rt/test/tysan/CMakeLists.txt
M llvm/runtimes/CMakeLists.txt
Log Message:
-----------
Rename Compiler-RT target to compiler-rt in CMake files (#214364)
Visual Studio 2026 has trouble generating valid solutions for projects
with mismatching directory names.
The change renames the Compiler-RT target to match the directory name
"compiler-rt" in all CMake files.
Commit: e310250eb80f282efe02dee4c94454a784c6886c
https://github.com/llvm/llvm-project/commit/e310250eb80f282efe02dee4c94454a784c6886c
Author: Tom Stellard <tstellar at redhat.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M .github/workflows/release-documentation.yml
M llvm/utils/release/build-docs.sh
Log Message:
-----------
workflows/release-documentation: Rework workflow to make it testable (#214304)
This includes several separate changes for the workflow, which were
necessary to get the testing to pass:
* Merged release-man-pages-validate-input into the release-documentation
job.
* Split the release note uploading into a separate job.
* Moved the environment declaration to the upload-man-pages job.
* Stopped forcing clang as the compiler in build-docs.sh script. This
was causing the runtimes build to fail, because the default Ubuntu
debian packages for clang where not providing all the necessary CMake
files. It seems that when you use clang as the compiler, the runtimes
try to use the cmake files installed along with it.
Commit: c736a3eb6cfa6bbbbac7f17b7afe0df88eddaec9
https://github.com/llvm/llvm-project/commit/c736a3eb6cfa6bbbbac7f17b7afe0df88eddaec9
Author: Kaitlin Peng <kaitlinpeng at microsoft.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M clang/lib/Sema/SemaExpr.cpp
A clang/test/CodeGenHLSL/Operators/half-vector-comparisons.hlsl
A clang/test/SemaHLSL/Operators/half-vector-comparisons.hlsl
Log Message:
-----------
[HLSL] Fix crash when comparing two half vectors (#214332)
Fixes #213814.
Comparing two half vectors in default mode crashed Clang with a
`convertHalfVecBinOp` assertion because the function expects the result
to be a half/short vector while HLSL returns an int vector. This PR
fixes the bug by skipping the conversion function when the result type
is not a half or short vector. This lets it fall through to the default
`BinaryOperator::Create` path, which builds the comparison correctly
with the int vector result type. The PR also adds regression tests
covering the six comparison operators.
Assisted-by: Claude Opus 4.8
Commit: fdd9151239f6bef182ce5b1a0b32c57318636bbb
https://github.com/llvm/llvm-project/commit/fdd9151239f6bef182ce5b1a0b32c57318636bbb
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M clang/docs/CIR/_raw/PostProcessCIRDocs.py
Log Message:
-----------
[clang][docs] Fix CIR docs post-processing script to use index.md (#214567)
This file was renamed in cf293b06, but I seem to have missed this
reference. I'm not sure if I properly validated the CIR docs build the
last time I did this, because I ran into this when attempting to build
`docs-clang-html` with CIR enabled.
LLM-assisted
Commit: db4ef1160ebd5e8fc1a222f16e6688992ce1c596
https://github.com/llvm/llvm-project/commit/db4ef1160ebd5e8fc1a222f16e6688992ce1c596
Author: Alex Crichton <alex at alexcrichton.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M lld/test/wasm/cooperative-threading.s
M lld/wasm/Driver.cpp
Log Message:
-----------
[WebAssembly] Default export tables with `--cooperative-threading` (#208263)
This commit is a change to `wasm-ld`'s behavior when the
`--cooperative-threading` flag is passed to the linker. The change here
is to by default work as if `--export-table` was passed as well. This is
required conventionally on this target because the table is where
function pointers are read from in the component model
`thread.new-indirect` intrinsic. If the table is not exported then
there's no way to turn the core module into a component so it's
effectively required. This behavior only applies to when the table isn't
otherwise imported, for example in shared libraries.
The other motivation behind this change is that it'll avoid the need to
manually specify `-Wl,--export-table` when compiling for the
`wasm32-wasip3` target. This additionally avoids the need for the Clang
driver to figure out if flags like `--import-table` were otherwise
passed. Basically it seemed best to put this in `wasm-ld` itself to
avoid as little juggling of pieces as necessary.
cc WebAssembly/wasi-libc#808
Commit: f180ce951b1a93c8998b029ad9b0649bb92552c8
https://github.com/llvm/llvm-project/commit/f180ce951b1a93c8998b029ad9b0649bb92552c8
Author: Yonah Goldberg <ygoldberg at nvidia.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M llvm/include/llvm/CodeGen/CodeGenCommonISel.h
M llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/MachineMemOperand.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/lib/CodeGen/CodeGenCommonISel.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/MIRParser/MILexer.cpp
M llvm/lib/CodeGen/MIRParser/MILexer.h
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/MachineOperand.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTX.h
M llvm/lib/Target/NVPTX/NVPTXForwardParams.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
A llvm/test/CodeGen/MIR/X86/mem-cache-hint-error.mir
A llvm/test/CodeGen/MIR/X86/mem-cache-hint-undefined-metadata.mir
A llvm/test/CodeGen/MIR/X86/mem-cache-hint.mir
M llvm/test/CodeGen/MIR/X86/memory-operands.mir
M llvm/test/CodeGen/NVPTX/address-folder.mir
A llvm/test/CodeGen/NVPTX/cache-hint-atomics.ll
A llvm/test/CodeGen/NVPTX/cache-hint-cache-policy.ll
A llvm/test/CodeGen/NVPTX/cache-hint-intrinsics.ll
A llvm/test/CodeGen/NVPTX/cache-hint-invalid.ll
A llvm/test/CodeGen/NVPTX/cache-hint-load-store.ll
A llvm/test/CodeGen/NVPTX/cache-hint-sm-version.ll
A llvm/test/CodeGen/NVPTX/cache-hint-transforms.ll
M llvm/test/CodeGen/NVPTX/machinelicm-no-preheader.mir
M llvm/test/CodeGen/NVPTX/proxy-reg-erasure.mir
M llvm/test/DebugInfo/NVPTX/inlinedAt_2.mir
M llvm/tools/llvm-reduce/ReducerWorkItem.cpp
M llvm/unittests/CodeGen/GlobalISel/GISelAliasTest.cpp
M llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
M llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp
M llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp
M llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
Log Message:
-----------
[SDAG][NVPTX] Cache control metadata support and lowering (#204067)
This is the follow up for commit
https://github.com/llvm/llvm-project/commit/0fc5d0ab0cea3afe32592f24af17b5d7e02c9dfe,
which added IR support for cache hint metadata, as described in
https://discourse.llvm.org/t/rfc-composable-and-extensible-memory-cache-control-hints-in-llvm-ir/89443.
See previous https://github.com/llvm/llvm-project/pull/175901 that I
closed in favor of this one.
This PR adds support in SelectionDAG and lowering in NVPTX.
Supported cache hints:
L1 eviction: L1::evict_first, L1::evict_last, L1::evict_unchanged,
L1::no_allocate (requires SM 70+)
L2 eviction: L2::evict_first, L2::evict_last (requires SM 70+)
L2 prefetch: L2::64B, L2::128B (SM 75+), L2::256B (SM 80+)
L2::cache_hint with 64-bit cache policy descriptor (SM 80+, PTX 7.4+)
L1 eviction: L1::evict_first, L1::evict_last, L1::evict_unchanged,
L1::no_allocate (requires SM 70+ and PTX 7.4+)
L2 eviction: L2::evict_first, L2::evict_last (requires SM 100+, PTX
8.8+, and a 256-bit .v8.b32 or .v4.b64 memory operation)
L2 prefetch: L2::64B, L2::128B (requires SM 75+ and PTX 7.4+), L2::256B
(requires SM 80+ and PTX 7.4+)
L2 cache policy: L2::cache_hint with a 64-bit cache policy descriptor
(requires SM 80+ and PTX 7.4+)
I know this is a fairly large PR, but I needed to plug the support all
the way through the backend. I supposed I could add machinery in
SelectionDAG as an initial PR, but I'm not sure if that makes sense. I
implemented lowering on load + store + memcpy. I supposed memcpy can go
in a follow-up, but it doesn't really reduce the size that much.
TODO:
- implement support in global ISEL
- Implement lowering in NVPTX for atomics + other intrinsics
(llvm.masked.load/store)
- Better handling of cache hint metadata in legalization. Today we will
often drop the metadata. If we legalize a wide vector load into a bunch
of smaller loads, for example, we should preserve the metadata.
- Preserve L2 eviction metadata for suitably aligned, 32-byte-multiple
memcpy operations
Design decisions:
- I encoded the metadata in the MachineMemOperand. I hope it's ok to
increase the size. I think this is the best place because similar
information (atomic info, range metadata, etc...) is all stored there.
- When the metadata node values (strings which are target dependent) are
not valid for NVPTX, I call `ctx.emitError` to emit a diagnostic. I
think this is best because we wouldn't want front-ends to accidentally
emit incorrect metadata and for it to silently be dropped.
Co-authored-by: Fiigii <feipeng.compiler at gmail.com>
Assisted by AI
Commit: 8972983ea1ce1496f50b8985be4c817ad40c8ed2
https://github.com/llvm/llvm-project/commit/8972983ea1ce1496f50b8985be4c817ad40c8ed2
Author: Elvina Yakubova <eyakubova at nvidia.com>
Date: 2026-08-07 (Fri, 07 Aug 2026)
Changed paths:
M bolt/lib/Core/Relocation.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/lib/Target/AArch64/AArch64MCSymbolizer.cpp
M bolt/test/AArch64/runtime-relocs.test
Log Message:
-----------
[BOLT][AArch64] Add TLSGD relocations support (#213700)
Commit: d50b9947b27ff3c907a16b96cee50e8782236feb
https://github.com/llvm/llvm-project/commit/d50b9947b27ff3c907a16b96cee50e8782236feb
Author: Meredith Julian <35236176+mjulian31 at users.noreply.github.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
A llvm/test/CodeGen/NVPTX/fp128-global.ll
Log Message:
-----------
[NVPTX][AsmPrinter] Allow fp128 aggregate types in NVPTX backend (#214546)
Fixes an issue where aggregate types containing fp128 non-zero elements
would cause "unsupported type" due to missing case in bufferLEByte. Adds
fp128-global.ll test.
Commit: 5194e33faad9d84fd8d21c0305621a17e0d8a49f
https://github.com/llvm/llvm-project/commit/5194e33faad9d84fd8d21c0305621a17e0d8a49f
Author: Lang Hames <lhames at gmail.com>
Date: 2026-08-07 (Fri, 07 Aug 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/RTBridge/Calls.h
M llvm/include/llvm/ExecutionEngine/Orc/RTBridge/SPS/Calls.h
M llvm/unittests/ExecutionEngine/Orc/SPSCallersTest.cpp
Log Message:
-----------
[ORC] Hoist Caller state into the base; add operator bool (#214483)
Move the ExecutionSession reference and callee address up from the SPS
implementation into the rt::Caller base, together with their constructor
and new executionSession() / calleeAddr() accessors. The named callers
(MainCaller, VoidVoidCaller, ...) become plain aliases of Caller rather
than subclasses, and rt::sps::Caller inherits the base constructor.
Add an explicit operator bool() reporting whether the caller has a
non-null callee address.
Give rt::sps::Caller::Create a SymbolLookupFlags parameter. Looking the
callee up as a weakly-referenced symbol now yields a caller with a null
callee (operator bool == false) when the symbol is absent, rather than
an error -- so callers for optional runtime functions can be constructed
and then tested for availability.
Adds SPSCallersTest coverage for operator bool and the accessors, and
for the required/weak x present/absent Create paths.
Commit: 3e9646a812300b86474e347066a37bf24b6fc10a
https://github.com/llvm/llvm-project/commit/3e9646a812300b86474e347066a37bf24b6fc10a
Author: YAMAMOTO Takashi <yamamoto at midokura.com>
Date: 2026-08-07 (Fri, 07 Aug 2026)
Changed paths:
A lld/test/wasm/shared-synthetic-symbols.s
M lld/wasm/Driver.cpp
Log Message:
-----------
[lld][WebAssembly] Allow linker-synthetic symbols to be undefine when building shared libraries (#153537)
Fixes: #103592
Commit: 9c121cd44867cd542964ae06617da1c40432bf2b
https://github.com/llvm/llvm-project/commit/9c121cd44867cd542964ae06617da1c40432bf2b
Author: Eric Christopher <echristo at gmail.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M llvm/include/llvm/DebugInfo/DWARF/DWARFExpressionPrinter.h
M llvm/lib/DebugInfo/DWARF/DWARFExpressionPrinter.cpp
A llvm/test/tools/llvm-objdump/ELF/ARM/debug-vars-ascii-packed-reg.s
M llvm/tools/llvm-objdump/SourcePrinter.cpp
M llvm/unittests/DebugInfo/DWARF/DWARFExpressionCompactPrinterTest.cpp
Log Message:
-----------
[DebugInfo] Fix compact DWARF expression failure handling (#213391)
printDwarfExpressionCompact has two pre-existing failure paths that
silently produce bad output.
The register-name callback is optional, but the short DW_OP_reg* and
DW_OP_breg* paths call it directly, so a missing callback falls over.
Use resolveRegName for every register form and report an unknown
register only after both name-resolution paths fail.
DW_OP_entry_value has the same problem: it ignores a failed recursive
print, wraps the partial output in entry(...), and returns true. Print
entry-value subexpressions into a temporary buffer and propagate failure
before adding entry(...), so a failed subexpression can't come back as
successful output.
While here, GetRegName in llvm-objdump has a latent ordering issue: it
writes an unknown-register diagnostic as soon as target lookup misses,
even though resolveRegName can still decode an ASCII-packed
virtual-register name. There's no natural in-tree input that hits this
today -- LLVM emits text PTX and there's no NVPTX disassembler -- but a
future out-of-tree disassembler using the same encoding would otherwise
print a valid %r1 as "<unknown register 2454065>%r1". Keep GetRegName
lookup-only and let the compact printer own the diagnostic.
The llvm-objdump test makes the theoretical path testable by putting
NVPTX's packed value for %r1 in ARM DWARF, so target lookup misses
before packed-name decoding succeeds. Add target-independent unit
coverage for missing callbacks, unknown registers, and nested failures.
Tested via make check.
Assisted by AI.
Commit: 52006000d1b886ca67c80554d06d3119c706749a
https://github.com/llvm/llvm-project/commit/52006000d1b886ca67c80554d06d3119c706749a
Author: dmaclach <dmaclach at gmail.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M clang-tools-extra/include-cleaner/lib/WalkAST.cpp
M clang-tools-extra/include-cleaner/unittests/WalkASTTest.cpp
Log Message:
-----------
[include-cleaner] Ensure receiver headers are kept when accessing ObjC properties (#212633)
When accessing Objective-C properties via dot-notation (e.g., obj.foo),
include-cleaner was previously only recording the usage of the property
itself or its underlying getter/setter methods. This could lead to cases
where the header declaring the receiver's type (Interface or Protocol)
was incorrectly flagged as unused if no other standard methods were
invoked on it.
Commit: 9219721a5d68b75a16e8d101e0114c2cff48ba3d
https://github.com/llvm/llvm-project/commit/9219721a5d68b75a16e8d101e0114c2cff48ba3d
Author: Yonah Goldberg <ygoldberg at nvidia.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M llvm/test/CodeGen/NVPTX/cache-hint-atomics.ll
M llvm/test/CodeGen/NVPTX/cache-hint-cache-policy.ll
M llvm/test/CodeGen/NVPTX/cache-hint-intrinsics.ll
M llvm/test/CodeGen/NVPTX/cache-hint-load-store.ll
M llvm/test/CodeGen/NVPTX/cache-hint-transforms.ll
Log Message:
-----------
[NVPTX] Fix broken cache hint metadata lit tests (#214600)
I just merged https://github.com/llvm/llvm-project/pull/204067 and
unfortunately forgot to locally compile all the PTX I was generating
from cache hint metadata in lit tests.
- I didn't know that .L2::cache_hint isn't valid on PTX volatile loads.
We need to drop the metadata then for volatile loads. I'll put this up
in a PR later, but for now just delete the lit test that generates the
invalid PTX. I'll add it back in the follow up.
- I forgot to provide SM version and PTX version when invoking ptxas for
the lit tests.
Commit: 77b44eb872002dae26be3de22671affbfb94a07b
https://github.com/llvm/llvm-project/commit/77b44eb872002dae26be3de22671affbfb94a07b
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
A clang/docs/ClangFormat.md
R clang/docs/ClangFormat.rst
A clang/docs/ClangFormatStyleOptions.md
R clang/docs/ClangFormatStyleOptions.rst
M clang/docs/tools/dump_format_help.py
M clang/docs/tools/dump_format_style.py
M clang/lib/Format/CMakeLists.txt
M clang/test/Format/docs_updated.test
Log Message:
-----------
[docs][clang-format] Rename clang-format docs *.rst -> *.md, update refs (#211397)
Tracking issue: #201242
See the [migration guide] for more information.
[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
This is the initial straight rename commit. It will probably break the
docs build, but it has to be a separate PR for blame preservation
purposes.
---------
Co-authored-by: owenca <owenpiano at gmail.com>
Commit: 668134e8acf10218663a0c33835bd4157ba358c4
https://github.com/llvm/llvm-project/commit/668134e8acf10218663a0c33835bd4157ba358c4
Author: Roy Shi <royitaqi at users.noreply.github.com>
Date: 2026-08-07 (Fri, 07 Aug 2026)
Changed paths:
M llvm/include/llvm/DebugInfo/GSYM/FunctionInfo.h
M llvm/include/llvm/DebugInfo/GSYM/GsymReader.h
M llvm/include/llvm/DebugInfo/GSYM/GsymReaderV1.h
M llvm/include/llvm/DebugInfo/GSYM/GsymReaderV2.h
M llvm/lib/DebugInfo/GSYM/FunctionInfo.cpp
M llvm/lib/DebugInfo/GSYM/GsymReader.cpp
M llvm/tools/llvm-gsymutil/Opts.td
M llvm/tools/llvm-gsymutil/llvm-gsymutil.cpp
M llvm/unittests/DebugInfo/GSYM/GSYMTest.cpp
Log Message:
-----------
[gsymutil] Add `--statistics` option (#186495)
# Motiviation
Currently, if one wants to know the size of the sections in a gSYM (e.g.
to check if they exceed 4GB), they have to dump the whole gSYM in the
text form, then process that huge text to get the sizes.
# New option `--statistics[=<format>]`
This patch adds a `llvm-gsymutil --statistics[=<format>]` option to
print the size info for all sections. It supports three formats:
* `text`: Default.
* `json`: Dense JSON.
* `pretty-json`: Pretty-printed JSON.
See example output below.
# Examples
```
royshi-mac-office ~/tmp % guuu v2.gsym --statistics
GSYM statistics for "v2.gsym":
UUID: 4C4C446A-5555-3144-A1CF-AEBBCCD48E61
Number of addresses: 6,382
File size: 3,095,960 bytes
Header: 20 bytes ( 0.00%)
Global data dir: 140 bytes ( 0.00%)
UUID section: 16 bytes ( 0.00%)
Address table: 25,528 bytes ( 0.82%)
Addr info offsets: 51,056 bytes ( 1.65%)
File table: 3,652 bytes ( 0.12%)
String table: 1,772,169 bytes (57.24%)
Function info data: 1,243,376 bytes (40.16%)
Size and name: 76,584 bytes ( 2.47%)
Line table info: 145,260 bytes ( 4.69%)
Inline info: 58,540 bytes ( 1.89%)
Call site info: 25,902 bytes ( 0.84%)
End of list: 51,056 bytes ( 1.65%)
Padding: 5,387 bytes ( 0.17%)
Merged func info: 880,647 bytes (28.45%)
InfoType/InfoLength/Count/FnSize: 102,900 bytes ( 3.32%)
Size and name: 209,160 bytes ( 6.76%)
Line table info: 424,847 bytes (13.72%)
Inline info: 2,058 bytes ( 0.07%)
Call site info: 2,242 bytes ( 0.07%)
Merged func info: 0 bytes ( 0.00%)
End of list: 139,440 bytes ( 4.50%)
Padding: 3 bytes ( 0.00%)
royshi-mac-office ~/tmp % guuu v2.gsym --statistics=pretty-json
{
"byte-sizes": {
"addr_info_offsets": 51056,
"address_table": 25528,
"file_size": 3095960,
"file_table": 3652,
"function_info_data": 1243376,
"function_info_type_sizes": {
"call_site_info": 25902,
"end_of_list": 51056,
"inline_info": 58540,
"line_table_info": 145260,
"merged_func_info": 880647,
"merged_func_info_type_sizes": {
"call_site_info": 2242,
"end_of_list": 139440,
"infotype_infolength_count_and_fnsize": 102900,
"inline_info": 2058,
"line_table_info": 424847,
"merged_func_info": 0,
"size_and_name": 209160
},
"padding": 5387,
"size_and_name": 76584
},
"global_data_directory": 140,
"header": 20,
"padding": 3,
"string_table": 1772169,
"uuid_section": 16
},
"num_addresses": 6382,
"path": "v2.gsym",
"uuid": "4C4C446A-5555-3144-A1CF-AEBBCCD48E61"
}
```
Commit: a43296488ed34006f3201a258e712ae01fe63214
https://github.com/llvm/llvm-project/commit/a43296488ed34006f3201a258e712ae01fe63214
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-08-07 (Fri, 07 Aug 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
Log Message:
-----------
[AMDGPU] Fix sign of zero in fpround(fmul) -> V_{MAD,FMA}_MIX{LO,HI} (#214544)
The isel patterns lowering `fptrunc (fmul float %a, %b)` to a mix
instruction passed +0.0 as the FMA addend. Under round-to-nearest fma(a,
b, +0.0) is +0.0 whenever a * b is -0.0, so the sign of zero was lost:
on gfx90a, `(half)(-1.0f * 0.0f)` returned +0.0.
Use a -0.0 addend instead, which is the correct multiplicative identity
for an FMA and is what the f32 sibling pattern in MadFmaMixFP32Pats has
always done.
Verified on gfx90a: (half)(-1.0f * 0.0f) now returns 0x8000.
Commit: 5be66d0a9afe1268bf7ff75c69a32b141d4f0096
https://github.com/llvm/llvm-project/commit/5be66d0a9afe1268bf7ff75c69a32b141d4f0096
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-08-07 (Fri, 07 Aug 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIModeRegisterDefaults.h
Log Message:
-----------
[NFC][AMDGPU] Let IR level callers query the FMA/FMAD predicates (#213310)
isFMADLegal and isFMAFasterThanFMulAndFAdd read the denormal mode out of
the MachineFunction, so nothing before instruction selection can ask
them whether an fmul/fadd pair will be fused. Take an explicit
DenormalFPEnv instead, and make the existing MachineFunction /
SelectionDAG / MachineInstr entry points thin wrappers over it.
Also override the IR level isFMAFasterThanFMulAndFAdd hook. The two
views agree by construction, since SIModeRegisterDefaults copies its
denormal fields out of getDenormalFPEnv.
isFMADLegal uses VT as written and does not look through vectors, so a
vector type reports false, as in the SelectionDAG overload it was
extracted from.
The patch is preparation for querying these from getArithmeticInstrCost
and a revived isProfitableToSinkOperands.
Contributes to #211092
Assisted-By: Claude Opus 5
Commit: 1c0eda0d2371a6a755f90299892a7b89dc917442
https://github.com/llvm/llvm-project/commit/1c0eda0d2371a6a755f90299892a7b89dc917442
Author: Mingjie Xu <xumingjie.enna1 at bytedance.com>
Date: 2026-08-07 (Fri, 07 Aug 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/unittests/Analysis/ScalarEvolutionTest.cpp
Log Message:
-----------
Revert "[SCEV] Speed up forgetLoop by avoiding def-use walk for loop-header PHIs" (#212485)
Reverts https://github.com/llvm/llvm-project/pull/201572
Multiple miscompilations are reported, see
https://github.com/llvm/llvm-project/issues/207744,
https://github.com/llvm/llvm-project/issues/212027
That commit made forgetLoop() rely on LoopUsers[L] and stop walking the
def-use chain of the loop-header PHIs. This is insufficient, because
some cached data is derived from the underlying IR of SCEVUnknown, it is
not reachable from LoopUsers[L].
After that commit, forgetLoop() no longer invalidated them, so stale
UnsignedRanges / SignedRanges, ConstantMultipleCache, ValuesAtScopes
cause miscompilations.
Commit: 1b8dcb4f42f7ce005a223259e0453440d7eed00f
https://github.com/llvm/llvm-project/commit/1b8dcb4f42f7ce005a223259e0453440d7eed00f
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2026-08-07 (Fri, 07 Aug 2026)
Changed paths:
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTX.h
M llvm/lib/Target/NVPTX/NVPTX.td
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
Log Message:
-----------
[NVPTX] Model SM architectures as subtarget features (NFC) (#214335)
Commit: 56a654b9a9cffd32318d7ca5c6ee997827c07ecf
https://github.com/llvm/llvm-project/commit/56a654b9a9cffd32318d7ca5c6ee997827c07ecf
Author: Shoreshen <372660931 at qq.com>
Date: 2026-08-07 (Fri, 07 Aug 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.h
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
Log Message:
-----------
[DAG] Change `isExtractSubvectorCheap` into `getExtractSubvectorCost` (#213614)
This changes `isExtractSubvectorCheap` into `getExtractSubvectorCost`.
This is preparing for #201056 in order to remove `isNarrowingProfitable`
bail out for `narrowInsertExtractVectorBinOp`.
The reason is `isNarrowingProfitable` should be applying on scalar
variable instead of vectors.
---------
Co-authored-by: shore <shorshen at amd.com>
Commit: c6eb5e390833295393e4d96c64adc67c4e3729b8
https://github.com/llvm/llvm-project/commit/c6eb5e390833295393e4d96c64adc67c4e3729b8
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M clang/docs/ClangFormat.md
M clang/docs/ClangFormatStyleOptions.md
M clang/docs/tools/dump_format_help.py
M clang/docs/tools/dump_format_style.py
M clang/include/clang/Format/Format.h
M clang/include/clang/Tooling/Inclusions/IncludeStyle.h
Log Message:
-----------
[docs][clang-format] Migrate generated clang-format docs to markdown (#211398)
Tracking issue: #201242
See the [migration guide] for more information.
This is a stacked PR based on #211397 , which will be a standalone
commit that
renames *.rst -> *.md before this PR lands for history preservation
purposes.
[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
First, the generator was updated to generate markdown constructs, and
then the Doxygen comments in `Format.h` and `IncludeStyle.h` were also
modified to use markdown constructs. Mostly this means using single
backticks instead of double backticks, which is the Doxygen-native way
of expressing code font blocks anyway, so that's good.
To validate, I built the Sphinx docs and the doxygen, and I confirmed
that the generator script is idempotent, meaning it doesn't change the
markdown output. When I add a new option to clang-format, it shows up in
the help text block, so it works.
Commit: 8307b46d3ad5ace00c21e1fec6ef4ef4284290e9
https://github.com/llvm/llvm-project/commit/8307b46d3ad5ace00c21e1fec6ef4ef4284290e9
Author: Fabian Parzefall <parzefall at meta.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M bolt/lib/RuntimeLibs/RuntimeLibrary.cpp
M bolt/test/CMakeLists.txt
M bolt/test/lit.cfg.py
A bolt/test/runtime/thin-archive.c
Log Message:
-----------
[BOLT] Support runtime libraries built as thin archives (#214292)
In some configurations, BOLT runtime libraries may be built as thin
archive. Use the more generic `Archive::create` to handle these.
Commit: 1bfd9391b208400ff72782712f0fd2e054dd95ec
https://github.com/llvm/llvm-project/commit/1bfd9391b208400ff72782712f0fd2e054dd95ec
Author: hev <wangrui at loongson.cn>
Date: 2026-08-07 (Fri, 07 Aug 2026)
Changed paths:
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/extractelement.ll
Log Message:
-----------
[LoongArch][NFC] Add tests for vector extraction with zero extension (#214119)
Commit: 5ab9b3ebbfcf6b49f183d0b3e029e5fd53a9a7af
https://github.com/llvm/llvm-project/commit/5ab9b3ebbfcf6b49f183d0b3e029e5fd53a9a7af
Author: Sameer Sahasrabuddhe <sameer.sahasrabuddhe at amd.com>
Date: 2026-08-07 (Fri, 07 Aug 2026)
Changed paths:
M llvm/docs/AMDGPUMemoryModel.md
Log Message:
-----------
[Docs][AMDGPU] fully specify volatile accesses in the memory model (#214168)
A non-atomic volatile access on AMDGPU includes store-available or
load-visible
semantics at the widest scope supported by its address space:
- system scope for global/generic,
- workgroup scope for local (LDS)
An atomic volatile access has the same availability and visibility as
its atomic
non-volatile variant.
Previous Reference: 2f499b9
This fully specifies the behavior that the LLVM memory model leaves
target-dependent, matching the implementation in SIMemoryLegalizer.
Assisted-By: Claude Opus 4.8
Commit: ceaff22ed2c3ceb84da3e9334f511bc3f5b757cd
https://github.com/llvm/llvm-project/commit/ceaff22ed2c3ceb84da3e9334f511bc3f5b757cd
Author: Shivam Gupta <shivam98.tkg at gmail.com>
Date: 2026-08-07 (Fri, 07 Aug 2026)
Changed paths:
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
M clang/test/CodeGen/constrained-math-builtins.c
M clang/test/CodeGen/fp-reassoc-pragma.cpp
Log Message:
-----------
[Clang][CodeGen] Respect FP pragma options for fneg and calls (#212141)
Apply expression-specific floating-point options when emitting fneg and
call instructions.
This prevents these instructions from retaining fast-math flags disabled
by local FP pragmas, such as #pragma clang fp reassociate(off).
Fixes #51905
Commit: 8d19df3660bb51b87b4b4baa79356f9688c58771
https://github.com/llvm/llvm-project/commit/8d19df3660bb51b87b4b4baa79356f9688c58771
Author: tudinhh <103348714+tudinhh at users.noreply.github.com>
Date: 2026-08-07 (Fri, 07 Aug 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
A llvm/test/Analysis/CostModel/RISCV/select-fp-zve32x.ll
Log Message:
-----------
[RISCV][CostModel] Fix invalid cost for vector select on targets without FP vector support (#183158)
Fixes #182047
**Issue:** Compiling floating-point vector selects (e.g., `<2 x float>`)
on RISC-V targets that only support integer vectors (like `zve32x`)
causes a compiler crash in the Loop Vectorizer (`emitInvalidCostRemarks`
unhandled `TypeSwitch`).
**Root Cause:** The Type Legalizer correctly scalarizes the unsupported
FP vector into `f32` operations. However,
`RISCVTTIImpl::getCmpSelInstrCost` attempted to cost
`Instruction::Select` natively without verifying floating-point vector
hardware support. It passed the scalarized type to
`getRISCVInstructionCost` to price a native vector merge instruction,
which returned `InstructionCost::getInvalid()`.
**Fix:** Added hardware support checks (`hasVInstructionsF16/32/64()`)
for floating-point types in the `Instruction::Select` block. If the
target lacks the required instructions, it falls back to
`BaseT::getCmpSelInstrCost` to correctly calculate the sequential
scalarized cost, allowing the vectorizer to safely bail out.
**Testing:**
* Added `llvm/test/Analysis/CostModel/RISCV/select-fp-zve32x.ll`
* Verified expected scalarized costs using
`update_analyze_test_checks.py`
Co-authored-by: Luke Lau <luke at igalia.com>
Commit: f2bfcf5dc1f650a35ea3f9bf17de0500301f0abf
https://github.com/llvm/llvm-project/commit/f2bfcf5dc1f650a35ea3f9bf17de0500301f0abf
Author: hev <wangrui at loongson.cn>
Date: 2026-08-07 (Fri, 07 Aug 2026)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/extractelement.ll
Log Message:
-----------
[LoongArch] Use unsigned vector extract for zero extension (#214120)
Add patterns to select VPICKVE2GR_BU/HU and [X]VPICKVE2GR_WU for vector
extraction followed by zero extension, eliminating redundant masking
instructions.
Commit: b6eb594ad0186dfb349c2903b899606c21c6b348
https://github.com/llvm/llvm-project/commit/b6eb594ad0186dfb349c2903b899606c21c6b348
Author: Carl Ritson <carl.ritson at amd.com>
Date: 2026-08-07 (Fri, 07 Aug 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIPostRABundler.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
M llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll
M llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/function-args.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/load-local-i16.ll
M llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll
M llvm/test/CodeGen/AMDGPU/load-local.128.ll
M llvm/test/CodeGen/AMDGPU/load-local.96.ll
M llvm/test/CodeGen/AMDGPU/max.i16.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memcpy-param-combinations.ll
M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
M llvm/test/CodeGen/AMDGPU/memmove-param-combinations.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
M llvm/test/CodeGen/AMDGPU/neg_ashr64_reduce.ll
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
A llvm/test/CodeGen/AMDGPU/reschedule-bundle-loads.mir
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i64.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
M llvm/test/CodeGen/AMDGPU/waterfall-call-target-av-register-failure.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
Log Message:
-----------
[AMDGPU] Reschedule loads in clauses to improve throughput (#102595)
After clauses are formed their internal loads can be reordered to
facilitate some additional opportunities for overlapping computation.
This late stage rescheduling causes no change in register pressure.
Commit: a42f703a4d5f0777b85c29fea27cba55fa4e05f9
https://github.com/llvm/llvm-project/commit/a42f703a4d5f0777b85c29fea27cba55fa4e05f9
Author: Alan Li <me at alanli.org>
Date: 2026-08-07 (Fri, 07 Aug 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
A llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ctlz-zero-poison-build-vector.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ctlz-zero-poison-extract-vector-elt.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ctlz-zero-poison-shuffle-vector.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/known-never-zero-vector.mir
M llvm/test/tools/UpdateTestChecks/update_givaluetracking_test_checks/Inputs/const.mir.expected
M llvm/utils/update_givaluetracking_test_checks.py
Log Message:
-----------
[GlobalISel][AMDGPU] Expand `isKnownNeverZero` for vector instructions (#211149)
A followup PR about adding some vector instruction patterns to
`isKnownNeverZero`, which firstly added in
https://github.com/llvm/llvm-project/pull/198438
The following instructions are added:
* `G_BUILD_VECTOR`
* `G_EXTRACT_VECTOR_ELT`
* `G_SHUFFLE_VECTOR`
Commit: eaf20bfb75c7601029ec160fd0a4a53b6b7d1e46
https://github.com/llvm/llvm-project/commit/eaf20bfb75c7601029ec160fd0a4a53b6b7d1e46
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2026-08-07 (Fri, 07 Aug 2026)
Changed paths:
M clang/test/Driver/hip-include-path.hip
Log Message:
-----------
[HIP] Remove device compilation from include path test (#214612)
The libhipcxx test checks the include paths produced by the driver. It
also ran a HIP device compilation, which requires the AMDGPU target and
fails in builds that do not enable it.
Remove the compilation and keep the driver command checks enabled in
all builds.
Buildbot failure:
https://lab.llvm.org/buildbot/#/builders/225/builds/14729
Commit: fa01521e37e1b2db4edbf6a41687a00153505a37
https://github.com/llvm/llvm-project/commit/fa01521e37e1b2db4edbf6a41687a00153505a37
Author: Lin Wang <linwang2048 at 163.com>
Date: 2026-08-07 (Fri, 07 Aug 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCV.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
A llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/atomic.test
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/branch.s
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/cascade-fma.s
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/div-fdiv.s
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/floating-point.test
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/fpr-bypass.s
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/gpr-bypass.s
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/integer.test
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-alu.s
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-fpu.s
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/mul-div-rv32.test
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/mul-div.test
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zba.test
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zbb.test
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zbc.test
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zbs.test
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zfh.test
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zfhmin.test
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zicond.test
Log Message:
-----------
[RISCV] Add scheduler definitions for XiangShan-KunMingHu (#148581)
This patch adds an initial scheduler model for the XiangShan KunMingHu
microarchitecture in the RISC-V backend, covering scalar instructions
only. Support for vector instructions is not included in this patch.
The model includes initial ProcResource definitions and WriteRes
mappings for scalar instructions, derived from the publicly available
XiangShan KunMingHu documentations:
* [XiangShan Docs](https://docs.xiangshan.cc/projects/design/en/latest/).
* [XiangShan User Guide](https://docs.xiangshan.cc/projects/user-guide/en/latest/).
* [XiangShan KunMingHu RTL](https://github.com/OpenXiangShan/XiangShan).
Simulator-based validation results will be provided in a follow-up
update. Measurement results from real hardware will also be added
afterwards to further validate and refine the model if necessary.
This implementation was contributed by the
[XSCC Team](https://github.com/orgs/OpenXiangShan/teams/xscc).
---------
Co-authored-by: Chyaka <lilium23187 at gmail.com>
Co-authored-by: Bhe6669 <hebo at bosc.ac.cn>
Co-authored-by: Tang Haojin <tanghaojin at outlook.com>
Co-authored-by: buggfg <wangyingying at bosc.ac.cn>
Commit: e6566492c03c164f4cc4a0775a864c8d59d3f941
https://github.com/llvm/llvm-project/commit/e6566492c03c164f4cc4a0775a864c8d59d3f941
Author: Baranov Victor <bar.victor.2002 at gmail.com>
Date: 2026-08-07 (Fri, 07 Aug 2026)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/InfiniteLoopCheck.cpp
M clang-tools-extra/clang-tidy/modernize/LoopConvertUtils.cpp
M clang-tools-extra/clang-tidy/modernize/ReturnBracedInitListCheck.cpp
M clang-tools-extra/clang-tidy/modernize/UseConstraintsCheck.cpp
M clang-tools-extra/clang-tidy/modernize/UseStartsEndsWithCheck.cpp
M clang-tools-extra/clang-tidy/objc/NSDateFormatterCheck.cpp
M clang-tools-extra/clang-tidy/readability/NonConstParameterCheck.cpp
M clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp
Log Message:
-----------
[clang-tidy][NFC] Apply llvm-redundant-casting check (#214024)
Commit: 34323ab08e6eed2caff556ecdeae20053cbaaae7
https://github.com/llvm/llvm-project/commit/34323ab08e6eed2caff556ecdeae20053cbaaae7
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-08-07 (Fri, 07 Aug 2026)
Changed paths:
M lldb/source/Core/Module.cpp
Log Message:
-----------
[lldb] Fix the lazy initialization of Module's global collections (NFC) (#214630)
Both collections were initialized with a check-then-set on a null
pointer, which is race-y. We can achieve the same thing by initializing
the pointer with the allocation, while retaining the leak.
Commit: fab90faf86a5846f7ed73c1caf322dcc79a6af5e
https://github.com/llvm/llvm-project/commit/fab90faf86a5846f7ed73c1caf322dcc79a6af5e
Author: Kane Wang <wangqiang1 at kylinos.cn>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
A llvm/test/CodeGen/RISCV/GlobalISel/lround-llround-f16.ll
A llvm/test/CodeGen/RISCV/GlobalISel/lround-llround.ll
Log Message:
-----------
[RISCV][GlobalISel] Legalize G_LROUND/G_LLROUND (#213889)
Add legalizer rules so `llvm.lround/llround` lower to`
fcvt.{w,l}.{h,s,d}` with FRM_RMM.
Commit: 424588ce0a14c9a310687424d8f0318553ef3fa7
https://github.com/llvm/llvm-project/commit/424588ce0a14c9a310687424d8f0318553ef3fa7
Author: Sam Elliott <aelliott at qti.qualcomm.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/test/CodeGen/AArch64/constant-pool-partition.ll
M llvm/test/CodeGen/AArch64/sitofp-to-tbl.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle-tbl.ll
M llvm/test/CodeGen/AArch64/zext-to-tbl.ll
A llvm/test/CodeGen/RISCV/constantpool-sizes.ll
M llvm/test/CodeGen/SystemZ/vec-perm-14.ll
M llvm/test/CodeGen/X86/constant-pool-partition.ll
M llvm/test/CodeGen/X86/constant-pool-remat-0.ll
M llvm/test/CodeGen/XCore/codemodel.ll
M llvm/test/CodeGen/XCore/epilogue_prologue.ll
Log Message:
-----------
[AsmPrinter] Emit type and size for Constant Pool Entries (#214387)
Commit: 0b5cc577664bbd6e031f93f162d23820e5e90d15
https://github.com/llvm/llvm-project/commit/0b5cc577664bbd6e031f93f162d23820e5e90d15
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-08-06 (Thu, 06 Aug 2026)
Changed paths:
M llvm/include/llvm/Target/TargetMachine.h
Log Message:
-----------
[Target] Add shouldDefaultToNewPM flag
This will allow for tools like clang/flang/llc to default to the NewPM
for targets that request it.
Future patches will update clang/llc and flip it for targets that have
been fully ported but shouldn't have a large blast radius (like Lanai
and MSP430).
Pursuant to
https://discourse.llvm.org/t/rfc-incrementally-enabling-the-newpm-for-codegen/91410/11.
Reviewers: arsenm, vikramRH, aengelke
Pull Request: https://github.com/llvm/llvm-project/pull/214570
Commit: 6ba9d2c075a73a5c72db29c7df94b29689cc82b6
https://github.com/llvm/llvm-project/commit/6ba9d2c075a73a5c72db29c7df94b29689cc82b6
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-08-07 (Fri, 07 Aug 2026)
Changed paths:
M .github/workflows/release-documentation.yml
M bolt/lib/Core/Relocation.cpp
M bolt/lib/RuntimeLibs/RuntimeLibrary.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/lib/Target/AArch64/AArch64MCSymbolizer.cpp
M bolt/test/AArch64/runtime-relocs.test
M bolt/test/CMakeLists.txt
M bolt/test/lit.cfg.py
A bolt/test/runtime/thin-archive.c
M clang-tools-extra/clang-tidy/bugprone/InfiniteLoopCheck.cpp
M clang-tools-extra/clang-tidy/modernize/LoopConvertUtils.cpp
M clang-tools-extra/clang-tidy/modernize/ReturnBracedInitListCheck.cpp
M clang-tools-extra/clang-tidy/modernize/UseConstraintsCheck.cpp
M clang-tools-extra/clang-tidy/modernize/UseStartsEndsWithCheck.cpp
M clang-tools-extra/clang-tidy/objc/NSDateFormatterCheck.cpp
M clang-tools-extra/clang-tidy/readability/NonConstParameterCheck.cpp
M clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp
M clang-tools-extra/clangd/unittests/HoverTests.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/argument-comment.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/argument-comment.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/assert-side-effect.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/assert-side-effect.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/assignment-in-selection-statement.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/assignment-in-selection-statement.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/bitwise-pointer-cast.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/bitwise-pointer-cast.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/branch-clone.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/branch-clone.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/capturing-this-in-member-variable.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/capturing-this-in-member-variable.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/casting-through-void.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/casting-through-void.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/chained-comparison.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/chained-comparison.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/compare-pointer-to-member-virtual-function.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/compare-pointer-to-member-virtual-function.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/copy-constructor-init.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/copy-constructor-init.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/crtp-constructor-accessibility.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/crtp-constructor-accessibility.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/dangling-handle.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/dangling-handle.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/derived-method-shadowing-base-method.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/derived-method-shadowing-base-method.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/easily-swappable-parameters.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/easily-swappable-parameters.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/empty-catch.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/empty-catch.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/exception-copy-constructor-throws.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/exception-copy-constructor-throws.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/exception-escape.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/exception-escape.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/fold-init-type.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/fold-init-type.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/forwarding-reference-overload.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/forwarding-reference-overload.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/implicit-widening-of-multiplication-result.md
R clang-tools-extra/docs/clang-tidy/checks/bugprone/implicit-widening-of-multiplication-result.rst
M clang-tools-extra/docs/clang-tidy/checks/modernize/return-braced-init-list.md
M clang-tools-extra/include-cleaner/lib/WalkAST.cpp
M clang-tools-extra/include-cleaner/unittests/WalkASTTest.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/return-braced-init-list.cpp
M clang/docs/CIR/_raw/PostProcessCIRDocs.py
A clang/docs/ClangFormat.md
R clang/docs/ClangFormat.rst
A clang/docs/ClangFormatStyleOptions.md
R clang/docs/ClangFormatStyleOptions.rst
M clang/docs/ReleaseNotes.md
M clang/docs/tools/dump_format_help.py
M clang/docs/tools/dump_format_style.py
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/AST/TypeBase.h
M clang/include/clang/AST/TypeProperties.td
M clang/include/clang/Basic/HLSLIntrinsics.td
A clang/include/clang/Basic/SPIRVTypes.def
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/Format/Format.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/include/clang/Tooling/Inclusions/IncludeStyle.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/MicrosoftMangle.cpp
M clang/lib/AST/NSAPI.cpp
M clang/lib/AST/PrintfFormatString.cpp
M clang/lib/AST/Type.cpp
M clang/lib/AST/TypeLoc.cpp
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGDebugInfo.h
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CodeGenTypes.cpp
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/lib/CodeGen/QualTypeMapper.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/SYCL.cpp
M clang/lib/Driver/ToolChains/SYCL.h
M clang/lib/Format/CMakeLists.txt
M clang/lib/Headers/hlsl/hlsl_compat_overloads.h
M clang/lib/Parse/ParseHLSL.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Serialization/ASTCommon.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/UnifiedSymbolResolution/USRGeneration.cpp
M clang/test/AST/HLSL/resource_binding_attr.hlsl
A clang/test/AST/spirv-event-type.cpp
A clang/test/CIR/CodeGen/tls-model.cpp
M clang/test/CodeGen/AArch64/neon/intrinsics.c
M clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
M clang/test/CodeGen/constrained-math-builtins.c
M clang/test/CodeGen/fp-reassoc-pragma.cpp
A clang/test/CodeGenCXX/spirv-event-type.cpp
A clang/test/CodeGenHLSL/Operators/half-vector-comparisons.hlsl
A clang/test/CodeGenHLSL/builtins/pow_mat-overloads.hlsl
A clang/test/CodeGenHLSL/builtins/pow_mat.hlsl
A clang/test/CodeGenSPIRV/spirv-host-adaptation-valist.cpp
A clang/test/Driver/Inputs/rocm/include/libhipcxx/cuda/std/atomic
M clang/test/Driver/hip-include-path.hip
A clang/test/Driver/sycl-msvc-version-propagation.cpp
M clang/test/Format/docs_updated.test
A clang/test/Modules/spirv-event.cpp
A clang/test/Preprocessor/spir-host-adaptation-macros.cpp
A clang/test/Preprocessor/spirv-host-adaptation-macros.cpp
A clang/test/Sema/spirv-event.c
A clang/test/SemaCXX/spirv-event.cpp
M clang/test/SemaHLSL/BuiltIns/binary-compat-overload-warnings.hlsl
M clang/test/SemaHLSL/BuiltIns/half-float-only-errors2.hlsl
A clang/test/SemaHLSL/BuiltIns/pow_mat-errors.hlsl
A clang/test/SemaHLSL/Operators/half-vector-comparisons.hlsl
A clang/test/SemaSPIRV/spirv-host-adaptation-types.cpp
A clang/test/SemaSPIRV/spirv-host-adaptation-valist.cpp
M clang/tools/libclang/CIndex.cpp
M compiler-rt/CMakeLists.txt
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
M compiler-rt/cmake/Modules/CompilerRTDarwinUtils.cmake
M compiler-rt/cmake/Modules/CompilerRTUtils.cmake
M compiler-rt/cmake/base-config-ix.cmake
M compiler-rt/include/CMakeLists.txt
M compiler-rt/lib/asan/tests/CMakeLists.txt
M compiler-rt/lib/builtins/CMakeLists.txt
M compiler-rt/lib/ctx_profile/tests/CMakeLists.txt
M compiler-rt/lib/fuzzer/tests/CMakeLists.txt
M compiler-rt/lib/gwp_asan/tests/CMakeLists.txt
M compiler-rt/lib/interception/tests/CMakeLists.txt
M compiler-rt/lib/memprof/tests/CMakeLists.txt
M compiler-rt/lib/orc/tests/CMakeLists.txt
M compiler-rt/lib/rtsan/tests/CMakeLists.txt
M compiler-rt/lib/sanitizer_common/tests/CMakeLists.txt
M compiler-rt/lib/sanitizer_ignorelists/CMakeLists.txt
M compiler-rt/lib/scudo/standalone/linux.cpp
M compiler-rt/lib/scudo/standalone/primary32.h
M compiler-rt/lib/scudo/standalone/tests/CMakeLists.txt
M compiler-rt/lib/stats/CMakeLists.txt
M compiler-rt/lib/tsan/CMakeLists.txt
M compiler-rt/lib/tsan/dd/CMakeLists.txt
M compiler-rt/lib/tsan/rtl/CMakeLists.txt
M compiler-rt/lib/tsan/tests/CMakeLists.txt
M compiler-rt/lib/xray/tests/CMakeLists.txt
M compiler-rt/test/CMakeLists.txt
M compiler-rt/test/ctx_profile/CMakeLists.txt
M compiler-rt/test/rtsan/CMakeLists.txt
M compiler-rt/test/scudo/standalone/CMakeLists.txt
M compiler-rt/test/tsan/CMakeLists.txt
M compiler-rt/test/tysan/CMakeLists.txt
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Semantics/compute-offsets.cpp
A flang/test/Lower/common-block-char0.f90
A flang/test/Semantics/common-block-char0.f90
M libc/include/llvm-libc-macros/linux/fcntl-macros.h
M libc/include/llvm-libc-macros/linux/sched-macros.h
M libc/src/__support/threads/linux/CMakeLists.txt
M libc/src/__support/threads/linux/thread.cpp
M lld/test/wasm/cooperative-threading.s
A lld/test/wasm/shared-synthetic-symbols.s
M lld/wasm/Driver.cpp
M lldb/include/lldb/Target/DynamicLoader.h
M lldb/source/Core/DynamicLoader.cpp
M lldb/source/Core/Module.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp
M lldb/source/Plugins/Process/wasm/ProcessWasm.cpp
M lldb/source/Plugins/Process/wasm/ThreadWasm.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/test/API/functionalities/gdb_remote_client/TestWasm.py
M lldb/test/API/macosx/expedited-stack-memory/TestExpeditedStackMemory.py
M llvm/docs/AMDGPUMemoryModel.md
M llvm/include/llvm/CodeGen/CodeGenCommonISel.h
M llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/MachineMemOperand.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFExpressionPrinter.h
M llvm/include/llvm/DebugInfo/GSYM/FunctionInfo.h
M llvm/include/llvm/DebugInfo/GSYM/GsymReader.h
M llvm/include/llvm/DebugInfo/GSYM/GsymReaderV1.h
M llvm/include/llvm/DebugInfo/GSYM/GsymReaderV2.h
M llvm/include/llvm/ExecutionEngine/Orc/RTBridge/Calls.h
M llvm/include/llvm/ExecutionEngine/Orc/RTBridge/SPS/Calls.h
M llvm/include/llvm/Transforms/IPO/MergeFunctions.h
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/CodeGenCommonISel.cpp
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/MIRParser/MILexer.cpp
M llvm/lib/CodeGen/MIRParser/MILexer.h
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/MachineOperand.cpp
M llvm/lib/CodeGen/Rematerializer.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/DebugInfo/DWARF/DWARFExpressionPrinter.cpp
M llvm/lib/DebugInfo/GSYM/FunctionInfo.cpp
M llvm/lib/DebugInfo/GSYM/GsymReader.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
M llvm/lib/Target/AMDGPU/SIModeRegisterDefaults.h
M llvm/lib/Target/AMDGPU/SIPostRABundler.cpp
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.h
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTX.h
M llvm/lib/Target/NVPTX/NVPTX.td
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXForwardParams.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
M llvm/lib/Target/RISCV/RISCV.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVProcessors.td
A llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Transforms/IPO/MergeFunctions.cpp
M llvm/runtimes/CMakeLists.txt
M llvm/test/Analysis/CostModel/AArch64/histograms.ll
A llvm/test/Analysis/CostModel/RISCV/select-fp-zve32x.ll
M llvm/test/Analysis/LoopAccessAnalysis/depend_diff_types.ll
M llvm/test/CodeGen/AArch64/constant-pool-partition.ll
A llvm/test/CodeGen/AArch64/fixed-vector-interleave-deinterleave-no-neon.ll
M llvm/test/CodeGen/AArch64/misched-fusion-aes-post-ra.mir
A llvm/test/CodeGen/AArch64/misched-fusion-aes-pre-ra.mir
M llvm/test/CodeGen/AArch64/misched-fusion-fmin-fmax-post-ra.mir
M llvm/test/CodeGen/AArch64/misched-fusion-fmin-fmax-pre-ra.mir
M llvm/test/CodeGen/AArch64/sitofp-to-tbl.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle-tbl.ll
M llvm/test/CodeGen/AArch64/zext-to-tbl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ctlz-zero-poison-build-vector.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ctlz-zero-poison-extract-vector-elt.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ctlz-zero-poison-shuffle-vector.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/known-never-zero-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-merge-readanylane.mir
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
M llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/do-not-fold-copy.mir
M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/fabs-vector-truncate.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll
M llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
M llvm/test/CodeGen/AMDGPU/fpext-free.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/function-args.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-wmma-xdl.mir
A llvm/test/CodeGen/AMDGPU/insert-delay-alu-wmma.mir
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/load-local-i16.ll
M llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll
M llvm/test/CodeGen/AMDGPU/load-local.128.ll
M llvm/test/CodeGen/AMDGPU/load-local.96.ll
M llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir
M llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/max.i16.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memcpy-param-combinations.ll
M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
M llvm/test/CodeGen/AMDGPU/memmove-param-combinations.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
M llvm/test/CodeGen/AMDGPU/neg_ashr64_reduce.ll
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
A llvm/test/CodeGen/AMDGPU/reschedule-bundle-loads.mir
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i64.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
M llvm/test/CodeGen/AMDGPU/waterfall-call-target-av-register-failure.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
A llvm/test/CodeGen/DirectX/pow_mat.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/extractelement.ll
M llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
A llvm/test/CodeGen/MIR/X86/mem-cache-hint-error.mir
A llvm/test/CodeGen/MIR/X86/mem-cache-hint-undefined-metadata.mir
A llvm/test/CodeGen/MIR/X86/mem-cache-hint.mir
M llvm/test/CodeGen/MIR/X86/memory-operands.mir
M llvm/test/CodeGen/NVPTX/address-folder.mir
A llvm/test/CodeGen/NVPTX/cache-hint-atomics.ll
A llvm/test/CodeGen/NVPTX/cache-hint-cache-policy.ll
A llvm/test/CodeGen/NVPTX/cache-hint-intrinsics.ll
A llvm/test/CodeGen/NVPTX/cache-hint-invalid.ll
A llvm/test/CodeGen/NVPTX/cache-hint-load-store.ll
A llvm/test/CodeGen/NVPTX/cache-hint-sm-version.ll
A llvm/test/CodeGen/NVPTX/cache-hint-transforms.ll
A llvm/test/CodeGen/NVPTX/fp128-global.ll
M llvm/test/CodeGen/NVPTX/machinelicm-no-preheader.mir
M llvm/test/CodeGen/NVPTX/proxy-reg-erasure.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
A llvm/test/CodeGen/RISCV/GlobalISel/lround-llround-f16.ll
A llvm/test/CodeGen/RISCV/GlobalISel/lround-llround.ll
A llvm/test/CodeGen/RISCV/constantpool-sizes.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/pow_mat.ll
M llvm/test/CodeGen/SystemZ/vec-perm-14.ll
M llvm/test/CodeGen/X86/constant-pool-partition.ll
M llvm/test/CodeGen/X86/constant-pool-remat-0.ll
M llvm/test/CodeGen/XCore/codemodel.ll
M llvm/test/CodeGen/XCore/epilogue_prologue.ll
M llvm/test/DebugInfo/NVPTX/inlinedAt_2.mir
A llvm/test/Transforms/MergeFunc/merge-functions-branch-weights.ll
A llvm/test/Transforms/MergeFunc/merge-functions-reordered-blocks-branch-weights.ll
A llvm/test/Transforms/MergeFunc/merge-functions-select-weights.ll
A llvm/test/Transforms/MergeFunc/merge-functions-value-profile.ll
M llvm/test/tools/UpdateTestChecks/update_givaluetracking_test_checks/Inputs/const.mir.expected
M llvm/test/tools/llubi/gep.ll
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/atomic.test
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/branch.s
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/cascade-fma.s
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/div-fdiv.s
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/floating-point.test
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/fpr-bypass.s
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/gpr-bypass.s
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/integer.test
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-alu.s
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-fpu.s
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/mul-div-rv32.test
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/mul-div.test
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zba.test
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zbb.test
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zbc.test
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zbs.test
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zfh.test
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zfhmin.test
A llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zicond.test
A llvm/test/tools/llvm-objdump/ELF/ARM/debug-vars-ascii-packed-reg.s
M llvm/tools/llubi/lib/Context.cpp
M llvm/tools/llvm-gsymutil/Opts.td
M llvm/tools/llvm-gsymutil/llvm-gsymutil.cpp
M llvm/tools/llvm-objdump/SourcePrinter.cpp
M llvm/tools/llvm-reduce/ReducerWorkItem.cpp
M llvm/tools/spirv-tools/CMakeLists.txt
M llvm/unittests/Analysis/ScalarEvolutionTest.cpp
M llvm/unittests/CodeGen/GlobalISel/GISelAliasTest.cpp
M llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
M llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp
M llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp
M llvm/unittests/DebugInfo/DWARF/DWARFExpressionCompactPrinterTest.cpp
M llvm/unittests/DebugInfo/GSYM/GSYMTest.cpp
M llvm/unittests/ExecutionEngine/Orc/SPSCallersTest.cpp
M llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
M llvm/unittests/Transforms/IPO/MergeFunctionsTest.cpp
M llvm/utils/release/build-docs.sh
M llvm/utils/update_givaluetracking_test_checks.py
M mlir/include/mlir/Dialect/Bufferization/Transforms/Bufferize.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Dialect/ControlFlow/one-shot-bufferize.mlir
M mlir/test/Dialect/LLVMIR/alias.mlir
M mlir/test/Dialect/LLVMIR/global.mlir
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
A mlir/test/Dialect/Tosa/tosa-layerwise-constant-fold-dense-resource.mlir
M mlir/test/Dialect/Tosa/tosa-layerwise-constant-fold.mlir
M mlir/test/Target/LLVMIR/Import/global-variables.ll
M mlir/test/Target/LLVMIR/Import/intrinsic-unregistered.ll
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.7
[skip ci]
Compare: https://github.com/llvm/llvm-project/compare/69611034169c...6ba9d2c075a7
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