[all-commits] [llvm/llvm-project] dd95c0: Precommit test

[Luke Lau via All-commits]

  Branch: refs/heads/users/lukel97/loop-vectorize/simplifyRecipes-worklist-inserter
  Home:   https://github.com/llvm/llvm-project
  Commit: dd95c05c624ece2ad7fc25b739c527323267fb3f
      https://github.com/llvm/llvm-project/commit/dd95c05c624ece2ad7fc25b739c527323267fb3f
  Author: Luke Lau <luke at igalia.com>
  Date:   2026-08-07 (Fri, 07 Aug 2026)

  Changed paths:
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll

  Log Message:
  -----------
  Precommit test


  Commit: fa4bd2570b34d3d3f020eefd9626f33b621d3ef1
      https://github.com/llvm/llvm-project/commit/fa4bd2570b34d3d3f020eefd9626f33b621d3ef1
  Author: Luke Lau <luke at igalia.com>
  Date:   2026-08-07 (Fri, 07 Aug 2026)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
    M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll

  Log Message:
  -----------
  [VPlan] Append recipes created via builder to worklist

The previous PR appended the top most created recipe to the worklist, and this PR extends it to any other nested recipes that were created, similar to InstCombine.

This removes the header mask in a good few more places on RISC-V as measured on SPEC CPU 2017, e.g. for the following loop:

```c
long f(const int *p, const int *q, long n) {
  long a = 0, b = 0;
  for (long i = 0;; i++) {
    if (p[i] && q[i]) { a += i; b += i; }
    if (i + 1 == n) break;
  }
  return a + b;
}
```

Before:

```asm
LBB0_1:
        sh2add  a4, a3, a0
        vsetvli a5, a2, e32, m1, ta, ma
        vle32.v v16, (a4)
        vmsne.vi        v0, v16, 0
        sh2add  a4, a3, a1
        vsetvli zero, zero, e64, m2, ta, ma
        vmsltu.vx       v16, v10, a5
        vle32.v v17, (a4), v0.t
        vsetvli zero, zero, e32, m1, ta, ma
        vmsne.vi        v17, v17, 0
        vmand.mm        v17, v0, v17
        vmand.mm        v0, v16, v17
        vsetvli zero, zero, e64, m2, tu, mu
        vadd.vv v8, v14, v8, v0.t
        vadd.vv v12, v14, v12, v0.t
        vsetvli zero, zero, e64, m2, ta, ma
        vadd.vx v14, v14, a5
        sub     a2, a2, a5
        add     a3, a3, a5
        bnez    a2, .LBB0_1
```

After:

```
.LBB0_1:
	sh2add	a4, a3, a0
	vsetvli	a5, a2, e32, m1, ta, ma
	vle32.v	v14, (a4)
	vmsne.vi	v0, v14, 0
	sh2add	a4, a3, a1
	vle32.v	v14, (a4), v0.t
	vmsne.vi	v14, v14, 0
	vmand.mm	v0, v0, v14
	vsetvli	zero, zero, e64, m2, tu, mu
	vadd.vv	v8, v12, v8, v0.t
	vadd.vv	v10, v12, v10, v0.t
	vsetvli	zero, zero, e64, m2, ta, ma
	vadd.vx	v12, v12, a5
	sub	a2, a2, a5
	add	a3, a3, a5
	bnez	a2, .LBB0_1
```

This copies the IRBuilderInstCombineInserter for IRBuilder approach from InstCombine, but templating VPBuilder + adding a VPBuilderBase seemed overkill so I've just made a dervied class with a virtual method instead, which does the same thing.

We can also remove the (X && Y) | (X && !Y) -> X combine, but this is left for another NFC PR.


Compare: https://github.com/llvm/llvm-project/compare/7e944a8f7c81...fa4bd2570b34

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