[all-commits] [llvm/llvm-project] 2b32e1: [SDAG] Handle vector expansion when expanding FABS...

[Krzysztof Drewniak via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2b32e13e65a35fa8f757eee89992e172f5cb0da5
      https://github.com/llvm/llvm-project/commit/2b32e13e65a35fa8f757eee89992e172f5cb0da5
  Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
  Date:   2026-08-06 (Thu, 06 Aug 2026)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    M llvm/test/CodeGen/AMDGPU/fabs-vector-truncate.ll

  Log Message:
  -----------
  [SDAG] Handle vector expansion when expanding FABS (#214341)

Before this, vector FABS that were scheduled for expansion would hit the
getSignAsIntValue() case and either assert there or fail later for lock
of instruction selection for a bitcast that's only looking at the scalar
size.

Now, we unroll to scalars as needed.

Test pre-committed in #214288



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