[all-commits] [llvm/llvm-project] 99f701: [CodeGen] Add initial multi-def rematerialization ...

[Lucas Ramirez via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 99f7018958ed3daf2abf8d49178c24fbf1eb1010
      https://github.com/llvm/llvm-project/commit/99f7018958ed3daf2abf8d49178c24fbf1eb1010
  Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
  Date:   2026-08-06 (Thu, 06 Aug 2026)

  Changed paths:
    M llvm/include/llvm/CodeGen/Rematerializer.h
    M llvm/lib/CodeGen/Rematerializer.cpp
    M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
    M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir
    M llvm/unittests/CodeGen/RematerializerTest.cpp

  Log Message:
  -----------
  [CodeGen] Add initial multi-def rematerialization support (#197580)

This significantly improves support for rematerializing registers with
more than one definition. In particular, this includes cases where
different lanes of a register are defined over multiple instructions.

There are still a few restrictions that can hopefully be relaxed in the
future.

- All defining instructions must be part of the same rematerialization
region.
- No pure user of the register (i.e., an MI that doesn't also defined a
part of the register) must read the register before its last definition.

These constraints ensure that the underlying DAG representation
maintained by the rematerializer is still valid, making this a
relatively incremental improvement.



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