[all-commits] [llvm/llvm-project] 1ac19e: [NVVM][NVPTX] Change TMA Tensor reduction ops to u...

[Rajat Bajpai via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1ac19e41a0674925911e88cc5218dfd95a09a3ac
      https://github.com/llvm/llvm-project/commit/1ac19e41a0674925911e88cc5218dfd95a09a3ac
  Author: Rajat Bajpai <rbajpai at nvidia.com>
  Date:   2026-08-06 (Thu, 06 Aug 2026)

  Changed paths:
    M llvm/docs/NVPTXUsage.md
    M llvm/include/llvm/IR/IntrinsicsNVVM.td
    M llvm/include/llvm/IR/NVVMIntrinsicUtils.h
    M llvm/lib/IR/AutoUpgrade.cpp
    M llvm/lib/IR/NVVMIntrinsicUtils.cpp
    M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
    M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
    M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
    M llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
    M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-reduce.ll
    M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
    M mlir/test/Target/LLVMIR/nvvm/tma_store_reduce.mlir

  Log Message:
  -----------
  [NVVM][NVPTX] Change TMA Tensor reduction ops to use flag for reduction ops (#213638)

Currently, TMA S2G reduction intrinsics use reduction operation in the
name. Now that we have pretty-printing and a range-based verifier (for
ImmArgs) available, this PR migrates the reduction operation to an
immediate flag argument. This simplifies adding Rubin architecture
extensions to this family, while also reducing the number of intrinsics
from 64 to 8.



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