[all-commits] [llvm/llvm-project] ea2fb2: [X86] Replace custom AND/OR/XOR reduction pattern ...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ea2fb2a1919eb64a7eb4e863be6aef17b570fb2d
      https://github.com/llvm/llvm-project/commit/ea2fb2a1919eb64a7eb4e863be6aef17b570fb2d
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2026-08-05 (Wed, 05 Aug 2026)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
    M llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
    M llvm/test/CodeGen/X86/pr53419.ll
    M llvm/test/CodeGen/X86/vector-extract-last-active.ll
    M llvm/test/CodeGen/X86/vector-reduce-and.ll
    M llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
    M llvm/test/CodeGen/X86/vector-reduce-or.ll
    M llvm/test/CodeGen/X86/vector-reduce-xor.ll
    M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll

  Log Message:
  -----------
  [X86] Replace custom AND/OR/XOR reduction pattern matching with ISD::VECREDUCE_AND/OR/XOR support (#199544)

The middle-end (SLP, VectorCombine and InstCombine) recognition and
handling of vector logic reduction patterns is sufficient now, so the
backend can work with ISD::VECREDUCE_AND/OR/XOR nodes directly.



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