[all-commits] [llvm/llvm-project] c15a90: [RISCV][MC] Add experimental Smijt, Ssijt, Smehv, ...

[Zeyi Xu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c15a90d299f4cab284f9d5e78922a86395de40a1
      https://github.com/llvm/llvm-project/commit/c15a90d299f4cab284f9d5e78922a86395de40a1
  Author: Zeyi Xu <mitchell.xu2 at gmail.com>
  Date:   2026-08-05 (Wed, 05 Aug 2026)

  Changed paths:
    M clang/test/Driver/print-supported-extensions-riscv.c
    M clang/test/Preprocessor/riscv-target-features.c
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.md
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVSystemOperands.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/CodeGen/RISCV/features-info.ll
    M llvm/test/MC/RISCV/attribute-arch.s
    M llvm/test/MC/RISCV/machine-csr-names.s
    M llvm/test/MC/RISCV/supervisor-csr-names.s
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

  Log Message:
  -----------
  [RISCV][MC] Add experimental Smijt, Ssijt, Smehv, and Ssehv support (#213431)

Add support for version 0.19 of the Smijt, Ssijt, Smehv, and Ssehv
extensions from the RISC-V fast interrupt specification.



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