[all-commits] [llvm/llvm-project] 79ab21: [AMDGPU] Model WMMA co-execution windows in the sc...
Austin Kerbow via All-commits
all-commits at lists.llvm.org
Tue Aug 4 14:41:32 PDT 2026
Branch: refs/heads/users/kerbowa/amdgpu-coexec-hazard-mode
Home: https://github.com/llvm/llvm-project
Commit: 79ab217dc4a76871dd0c93bbcb42374140c0e44a
https://github.com/llvm/llvm-project/commit/79ab217dc4a76871dd0c93bbcb42374140c0e44a
Author: Austin Kerbow <Austin.Kerbow at amd.com>
Date: 2026-08-04 (Tue, 04 Aug 2026)
Changed paths:
M llvm/include/llvm/CodeGen/MachineScheduler.h
M llvm/lib/CodeGen/MachineScheduler.cpp
A llvm/lib/Target/AMDGPU/AMDGPUCoExecInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
A llvm/test/CodeGen/AMDGPU/coexec-hazardrec-preRA.mir
M llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
M llvm/test/CodeGen/AMDGPU/fdiv.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/misched-into-wmma-hazard-shadow.mir
A llvm/test/CodeGen/AMDGPU/wmma-trans-multi-shadow-hazard.mir
Log Message:
-----------
[AMDGPU] Model WMMA co-execution windows in the scheduler for gfx1250
WMMA instructions in gfx1250 exposes an execution window during which
only certain other instruction classes may co-execute. Teach the hazard
recognizer about those windows so the scheduler can fill co-execution slots and
account for the resulting stalls. This adds a preRA hazard recognizer
mode.
Add AMDGPUCoExecInfo.h, a shared model of a co-execution window: the
per-stage capability bitmask, the stage types (CoExecStageType), and
CoExecInfo, which maps a multi-cycle instruction to its per-cycle slot
pattern via getCoExecInfo(). InstructionFlavor and its helpers move here
from AMDGPUCoExecSchedStrategy.h with no functional change so they can
be shared by the scheduler and the hazard recognizer.
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