[all-commits] [llvm/llvm-project] fa0232: [RISCV] Reduce spill/reload pairs when Xqcilo exte...

[Garvit Gupta via All-commits]

  Branch: refs/heads/release/23.x
  Home:   https://github.com/llvm/llvm-project
  Commit: fa0232af8b06ea5247a2abf49c11bbd558dd12e1
      https://github.com/llvm/llvm-project/commit/fa0232af8b06ea5247a2abf49c11bbd558dd12e1
  Author: Garvit Gupta <garvgupt at qti.qualcomm.com>
  Date:   2026-08-04 (Tue, 04 Aug 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/test/CodeGen/RISCV/xqcilo-xqcilia-frame-index.ll

  Log Message:
  -----------
  [RISCV] Reduce spill/reload pairs when Xqcilo extension is enabled (#212807)

[RISCV] Reduce spill/reload pairs when Xqcilo extension is enabled

Currently, `SelectAddrRegImm26` calls `SelectAddrFrameIndex` first,
causing bare frame-index loads (offset 0) to select 48-bit loads/stores at
ISel. Due to `AddedComplexity=2` on the QC48LdPat patterns, the wide
opcode won over the standard LW/SW even though the resolved frame offset
typically fits simm12.

This led to more spills and reloads in functions which are under high
register pressure because 48-bit loads and stores are not marked easily
rematerializable. Also, simply adding 48-bit loads and stores to
`isLoadFromStackSlot/isStoreToStackSlot` doesn't solve the regression
for the multi call case and only by making Isel produce the plain
32/64-bit loads and store opcodes as the baseline does RA behave
identically.

Therefor this PR fixes the issue by:

-Remove the `SelectAddrFrameIndex` call from SelectAddrRegImm26. Bare frame
indices now fall through to standard LW/SW selection at ISel, where RA
recognizes them as rematerializable stack loads.

-Add post-RA promotion in `eliminateFrameIndex`: when a plain LW/SW has a
resolved frame offset that exceeds simm12, promote the opcode to
the corresponding 48-bit load/store opcode and fold the 26-bit offset
directly. This preserves the intended large-offset optimization
without affecting RA decisions.

This solves the code size regression in high register pressure function
introduced by PR #209315

Assisted by Claude

(cherry picked from commit 8b18aa0b1ec2de76d47748a4d13c4de02b4d8580)



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