[all-commits] [llvm/llvm-project] 036af9: [Hexagon] Avoid predicating debug instructions (#2...

[Brian Cain via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 036af906f355771a5c2b3bb51a88d995c6010219
      https://github.com/llvm/llvm-project/commit/036af906f355771a5c2b3bb51a88d995c6010219
  Author: Brian Cain <brian.cain at oss.qualcomm.com>
  Date:   2026-08-02 (Sun, 02 Aug 2026)

  Changed paths:
    M llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
    A llvm/test/CodeGen/Hexagon/dont-predicate-debug.mir

  Log Message:
  -----------
  [Hexagon] Avoid predicating debug instructions (#212917)

The change is made in HexagonExpandCondsets::(predicate) function. The
debug instructions are not predicable as they cannot be separated into
conditional branches. So while predicating instructions in a machine
basic block if we encounter any debug instructions we need to skip these
instructions and continue with other instructions.

The scan that collects the registers defined and used between the
definition of the source register and the conditional transfer bailed
out as soon as it saw a non-virtual register operand, which a DBG_VALUE
can have. The transfer was then left as an unconditional A2_asrh plus an
A2_tfrf instead of being folded into a single predicated A4_pasrhf, so
again the generated code differed depending on whether debug info was
enabled.

Co-authored-by: Chandana Sinderikeri <csinderi at qti.qualcomm.com>



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