[all-commits] [llvm/llvm-project] 260527: [𝘀𝗽𝗿] initial version

[Alexander Richardson via All-commits]

  Branch: refs/heads/users/arichardson/spr/risc-vmcrvy-add-support-for-rvy-loadsstores
  Home:   https://github.com/llvm/llvm-project
  Commit: 26052724828bd8fcabd9f7c4ab14961b2702df31
      https://github.com/llvm/llvm-project/commit/26052724828bd8fcabd9f7c4ab14961b2702df31
  Author: Alexander Richardson <mail at alexrichardson.me>
  Date:   2026-07-31 (Fri, 31 Jul 2026)

  Changed paths:
    M clang/test/Driver/print-supported-extensions-riscv.c
    M llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
    M llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
    M llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
    M llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
    M llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
    M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
    M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoY.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZclsd.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZilsd.td
    M llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    M llvm/lib/Target/RISCV/RISCVSchedule.td
    M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
    M llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
    M llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
    M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
    M llvm/lib/TargetParser/RISCVISAInfo.cpp
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/CodeGen/RISCV/features-info.ll
    M llvm/test/CodeGen/RISCV/rvy/rvy-invalid-operands.mir
    M llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll
    M llvm/test/CodeGen/RISCV/target-abi-invalid.ll
    M llvm/test/MC/RISCV/insn_c.s
    M llvm/test/MC/RISCV/priv-invalid.s
    M llvm/test/MC/RISCV/priv-rv64-invalid.s
    M llvm/test/MC/RISCV/rv32dc-invalid.s
    M llvm/test/MC/RISCV/rv32fc-invalid.s
    M llvm/test/MC/RISCV/rv32zclsd-invalid.s
    A llvm/test/MC/RISCV/rvy/rvy-invalid-load-store.s
    A llvm/test/MC/RISCV/rvy/rvy-valid-load-store-64.s
    A llvm/test/MC/RISCV/rvy/rvy-valid-load-store.s
    A llvm/test/MC/RISCV/rvy/rvyc-invalid-load-store.s
    A llvm/test/MC/RISCV/rvy/rvyc-valid-load-store-64.s
    A llvm/test/MC/RISCV/rvy/rvyc-valid-load-store.s
    M llvm/test/MC/RISCV/target-abi-invalid.s
    M llvm/test/TableGen/RegClassByHwMode.td
    A llvm/test/TableGen/getRegClassFromMatchKind.td
    M llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
    M llvm/utils/TableGen/AsmMatcherEmitter.cpp

  Log Message:
  -----------
  [𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1-arichardson



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