[all-commits] [llvm/llvm-project] 037a0f: [RISCV][MC] Add experimental Smcsps and Sscsps sup...

[Zeyi Xu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 037a0f40a8e40784cbb9732709aa56d0f833c713
      https://github.com/llvm/llvm-project/commit/037a0f40a8e40784cbb9732709aa56d0f833c713
  Author: Zeyi Xu <mitchell.xu2 at gmail.com>
  Date:   2026-08-01 (Sat, 01 Aug 2026)

  Changed paths:
    M clang/test/Driver/print-supported-extensions-riscv.c
    M clang/test/Preprocessor/riscv-target-features.c
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.md
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    A llvm/lib/Target/RISCV/RISCVInstrInfoSmcsps.td
    M llvm/lib/Target/RISCV/RISCVSystemOperands.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/CodeGen/RISCV/features-info.ll
    M llvm/test/MC/RISCV/attribute-arch.s
    M llvm/test/MC/RISCV/machine-csr-names.s
    A llvm/test/MC/RISCV/smcsps-invalid.s
    A llvm/test/MC/RISCV/smcsps-valid.s
    M llvm/test/MC/RISCV/supervisor-csr-names.s
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

  Log Message:
  -----------
  [RISCV][MC] Add experimental Smcsps and Sscsps support (#211712)

Add experimental v0.19 support for the `Smcsps` and `Sscsps` conditional
stack pointer swap extensions.



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