[all-commits] [llvm/llvm-project] 0e42c8: NVPTX: Add target names in TargetParser (#212734)
Daniil Kovalev via All-commits
all-commits at lists.llvm.org
Fri Jul 31 09:09:18 PDT 2026
Branch: refs/heads/users/kovdan01/ptrauth-atts-for-synthetic-fns
Home: https://github.com/llvm/llvm-project
Commit: 0e42c871c2c8a40926ad929cfa334fd1d3c98dfa
https://github.com/llvm/llvm-project/commit/0e42c871c2c8a40926ad929cfa334fd1d3c98dfa
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/lib/Basic/Cuda.cpp
A llvm/include/llvm/TargetParser/NVPTXTargetParser.def
A llvm/include/llvm/TargetParser/NVPTXTargetParser.h
M llvm/lib/TargetParser/CMakeLists.txt
A llvm/lib/TargetParser/NVPTXTargetParser.cpp
M llvm/unittests/TargetParser/CMakeLists.txt
A llvm/unittests/TargetParser/NVPTXTargetParserTest.cpp
M llvm/utils/gn/secondary/llvm/lib/TargetParser/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/TargetParser/BUILD.gn
Log Message:
-----------
NVPTX: Add target names in TargetParser (#212734)
Track the canonical sm name and other target information.
This will eventually be used to reduce the pain of maintaining
OffloadArch in clang; all of the disjoint targets share an
enum which makes target specific covered switches annoying.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 1562871d4191f39de7ed0ae53f8ca48b8e2d4242
https://github.com/llvm/llvm-project/commit/1562871d4191f39de7ed0ae53f8ca48b8e2d4242
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
Log Message:
-----------
clang: Use NVPTX TargetParser for OpenMP unified-addressing check (#212746)
processRequiresDirective enumerated every OffloadArch value in a switch
only to error on nvptx architectures older than sm_60. Replace it with
NVPTX::supportsUnifiedAddressing() applied to the parsed target CPU so
we don't need to keep adding cases here every time a new target is
added.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 6e92d6d0577cbe102bd48f396301ea5cd0ebf247
https://github.com/llvm/llvm-project/commit/6e92d6d0577cbe102bd48f396301ea5cd0ebf247
Author: Rainer Orth <ro at gcc.gnu.org>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
M compiler-rt/lib/tsan/go/buildgo.sh
M compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp
Log Message:
-----------
[tsan] Fix buildgo.sh on FreeBSD/NetBSD (#213047)
This patch fixes the remaining compile errors when running `ninja
check-all` on FreeBSD and NetBSD:
- `sanitizer_linux.cpp` doesn't compile on NetBSD, so this patch adds a
cast:
```
sanitizer_common/sanitizer_linux.cpp:2492:10: error: format specifies
type 'unsigned long long' but the argument has type '__greg_t' (aka
'unsigned long') [-Werror,-Wformat]
```
- `tsan_interface_atomic.cpp` doesn't compile on both FreeBSD and
NetBSD, so this patch disables the warning:
```
tsan_interface_atomic.cpp:353:12: error: unused function template
'NoTsanAtomic' [-Werror,-Wunused-template]
tsan_interface_atomic.cpp:358:12: error: unused function template
'Atomic' [-Werror,-Wunused-template]
tsan_interface_atomic.cpp:389:12: error: unused function template
'NoTsanAtomic' [-Werror,-Wunused-template]
tsan_interface_atomic.cpp:394:12: error: unused function template
'Atomic' [-Werror,-Wunused-template]
tsan_interface_atomic.cpp:401:12: error: unused function template
'NoTsanAtomic' [-Werror,-Wunused-template]
tsan_interface_atomic.cpp:406:12: error: unused function template
'Atomic' [-Werror,-Wunused-template]
```
- `sanitizer_linux_libcdep.cpp` doesn't compile on NetBSD:
```
sanitizer_linux_libcdep.cpp:527:27: error: use of undeclared identifier
'__lwp_getprivate_fast'; did you mean '_lwp_getprivate'?
```
This is the same issue already handled in `tsan_platform_linux.cpp`: to
expose the `__lwp_getprivate_fast` definition in `<machine/mcontext.h>`,
`_RTLD_SOURCE` needs to be defined before `<machine/mcontext.h>` is
included (indirectly from `<signal.h>` in this case). It also needs to
include `<sys/types.h>` to get a definition of the `__aligned` macro.
Tested on `amd64-pc-freebsd15.1` and `amd64-pc-netbsd10.1`.
Commit: 40e33eb35417f565e2ed8a6c0dba63cbd618a926
https://github.com/llvm/llvm-project/commit/40e33eb35417f565e2ed8a6c0dba63cbd618a926
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/hoist-predicated-loads-with-predicated-stores.ll
Log Message:
-----------
[VPlan] Set correct VPIRFlags for FP selects when sinking stores. (#212973)
Selects of floats carry fast-math flags. Update getDefaultFlags to take
the result type and use it to handle selects. I am planning on extending
this to other similar opcodes, including PHIs.
Then update sinkPredicatedStores to pass through the correct default
flags.
This fixes a crash in cse when intersecting common metadata.
Fixes https://github.com/llvm/llvm-project/issues/212811.
PR: https://github.com/llvm/llvm-project/pull/212973
Commit: 5f10bade30ec9e73f19349df7eb833aae323a2e3
https://github.com/llvm/llvm-project/commit/5f10bade30ec9e73f19349df7eb833aae323a2e3
Author: Joel E. Denny <jdenny.ornl at gmail.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
M llvm/test/Transforms/LoopUnroll/branch-weights-freq/unroll-complete.ll
M llvm/test/Transforms/LoopUnroll/branch-weights-freq/unroll-partial-unconditional-latch.ll
Log Message:
-----------
[LoopUnroll] Fix freqs for unconditional latches: N>2, uniform (#182405)
This patch introduces the command-line option `-unroll-uniform-weights`.
When computing probabilities for the remaining N conditional latches in
the unrolled loop after converting some iterations' latches to
unconditional, LoopUnroll now supports the following three strategies:
- A. If N <= 2, use a simple formula to compute a single uniform
probability across those latches.
- B. Otherwise, if `-unroll-uniform-weights` is not specified, apply the
original loop's probability to all N latches and then, as needed, adjust
as few of them as possible.
- C. Otherwise, bisect the range [0,1] to find a single uniform
probability across all N latches. This patch implements this strategy.
An issue with C is that it could impact compiler performance, so this
patch makes it opt-in. Its appeal over B is that it treats all latches
the same given that we have no evidence showing that any latch should
have a higher or lower probability than any other. A has neither
problem, but I do not know how to apply it for N > 2. More experience or
feedback from others might determine that some strategies are not
worthwhile to maintain.
This patch depends on PR #182404.
Commit: 3d94aebde11a6410fc1ee93f12622114c60ace3d
https://github.com/llvm/llvm-project/commit/3d94aebde11a6410fc1ee93f12622114c60ace3d
Author: Rainer Orth <ro at gcc.gnu.org>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M flang/lib/Evaluate/intrinsics-library.cpp
Log Message:
-----------
[flang] Fix POSIX.1/XPG checks in intrinsics-library.cpp (#201072)
PR #201063 breaks the `flang` build on Solaris:
```
flang/lib/Evaluate/intrinsics-library.cpp:225:26: error: address of overloaded function 'acos' does not match required type '__float128 (__float128)'
flang/lib/Evaluate/intrinsics-library.cpp:225:26: error: address of overloaded function 'acos' does not match required type '_Complex __float128 (_Complex __float128)'
```
There are two problems here:
- The `__float128` support in `intrinsics-library.cpp` is guarded by the
POSIX.1 >= 2001/XPG >= 6 check, but only depends on `HAVE_QUADMATHLIB`.
- That check is done incorrectly: it tests for `_POSIX_C_SOURCE >=
200112L` or `_XOPEN_SOURCE >= 600`, which are no longer defined on
Solaris after the PR above. This check is due a misunderstanding of
those feature test macros: as detailed in [The Open Group Base
Specifications Issue 8, 2.2.1 POSIX.1
Symbols](https://pubs.opengroup.org/onlinepubs/9799919799/functions/V2_chap02.html),
those macros are expected to be **defined** by the user to ensure that
the features introduced by a particular version of POSIX.1 or XPG are
enabled, and only be checked by system headers. To test if they actually
are supported, the values of `_POSIX_VERSION` or `_XOPEN_VERSION` need
to be checked instead, as explained in [2.1.3.1 POSIX System
Interfaces](https://pubs.opengroup.org/onlinepubs/9799919799/basedefs/V1_chap02.html).
The feature test macros being defined by the system headers is a
non-portable glibc/AIX extension, it seems.
If the XPG6 features required for `flang` are present by default in a
compilation environment, `_POSIX_VERSION` or `_XOPEN_VERSION` will be
defined to the required values even without defining `_POSIX_C_SOURCE`
or `_XOPEN_SOURCE`.
Tested on `amd64-pc-solaris2.11`, `sparcv9-sun-solaris2.11`, and
`x86_64-pc-linux-gnu`.
Commit: bb7c7d1e2a6b4a3487df8604f94e0b981e873899
https://github.com/llvm/llvm-project/commit/bb7c7d1e2a6b4a3487df8604f94e0b981e873899
Author: satyanarayana reddy janga <satyajanga at gmail.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M lldb/source/Plugins/ObjectFile/Minidump/MinidumpFileBuilder.cpp
A lldb/test/API/functionalities/process_save_core_minidump/size_mismatch/Makefile
A lldb/test/API/functionalities/process_save_core_minidump/size_mismatch/TestProcessSaveCoreMinidumpSizeMismatch.py
A lldb/test/API/functionalities/process_save_core_minidump/size_mismatch/main.cpp
Log Message:
-----------
[lldb][minidump] Fix Memory64List DataSize over-counting on a failed read (#212861)
**Issue:**
save-core records each range's DataSize from the value
ReadMemoryInChunks returns. That value counts bytes read from the
inferior even when the callback dropped them: a chunk that errors
part-way returns Stop before AddData, so the partially-read bytes are
counted but never written.
Because the Memory64List locates every range by the cumulative DataSize
of the preceding ranges, an over-counted DataSize desyncs the shared
data blob: the descriptors claim more bytes than the file holds and
every later range reads back corrupted.
**Fix**
Record the bytes actually written (total_bytes_read) as the range's size
so the descriptor DataSize matches the data in the blob.
**Test**
Add an API test that custom-saves a fully-readable region alongside a
region whose tail is unreadable (a file mapped larger than the file),
and checks the Memory64List does not claim more data than the file holds
and that the readable region round-trips byte-for-byte.
Commit: 50a6209336d9796d26c1e6ecc9553093b074ecb2
https://github.com/llvm/llvm-project/commit/50a6209336d9796d26c1e6ecc9553093b074ecb2
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/clamp.ll
Log Message:
-----------
[AMDGPU] Canonicalize constant CLAMP source (#207902)
CLAMP lowers to v_max_f32, which canonicalizes its result: signaling
NaNs are quieted and denormals are flushed per the function denormal
mode
The constant fold returned the source unchanged, giving a different
result than the hardware. Route the folded constant through
getCanonicalConstantFP so it matches
Commit: dd3a4ed6fbca3696b724b46e2934f3c27534f245
https://github.com/llvm/llvm-project/commit/dd3a4ed6fbca3696b724b46e2934f3c27534f245
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/ne-tightening.ll
Log Message:
-----------
[ConstraintElim] Tighten bounds using inequalities with constants. (#213049)
Update ConstraintElimination to tighten existing bounds using
inequalities. Given an inequality %a != %b and %a >= %b, we can tighten
the fact to %a > %b.
For now this is limited to constant %b.
This helps to remove some checks in practice:
https://github.com/dtcxzyw/llvm-opt-benchmark-nightly/pull/819
Compile-time impact in the noise:
https://llvm-compile-time-tracker.com/compare.php?from=2f08dff5138a4ce908b6d4511a9439e859fedf86&to=fafe1d0d9d012654bc10e2b68d50ffe3b9fdbdcd&stat=instructions:u
PR: https://github.com/llvm/llvm-project/pull/213049
Commit: aae5b3f2a92cc1c08a4bd65ba397fba5e37272fe
https://github.com/llvm/llvm-project/commit/aae5b3f2a92cc1c08a4bd65ba397fba5e37272fe
Author: Michael Jones <michaelrj at google.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M compiler-rt/lib/scudo/standalone/primary64.h
Log Message:
-----------
[scudo] Fix GCC build after 212604 (#212904)
Change #212604 introduced an issue when building with gcc where it
complains there are "too few template-parameter-lists" (see log:
https://lab.llvm.org/buildbot/#/builders/131/builds/51269/steps/6/logs/stdio
)
This PR fixes the build.
Assisted-by: Automated tooling, human reviewed.
Commit: ff95a766e3c5588db19b9c93e1a6f49bd40a2823
https://github.com/llvm/llvm-project/commit/ff95a766e3c5588db19b9c93e1a6f49bd40a2823
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticCommonKinds.td
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/test/OpenMP/requires_codegen.cpp
Log Message:
-----------
clang: Use proper error for unified shared memory openmp error (#212750)
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 4304020b98e20a46dd8f56b361c5f62074e7b8a1
https://github.com/llvm/llvm-project/commit/4304020b98e20a46dd8f56b361c5f62074e7b8a1
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
Log Message:
-----------
[VPlan] Migrate VPBuilder to VPInsertPt fully (NFC) (#209764)
There is already a VPInsertPoint in VPBuilder which is used just with
InsertPointGuard. In order to share code, migrate VPBuilder to fully use
VPInsertPoint as the canonical insertion point.
Commit: b6e3037f6e6283392f306b58c8444e0efe40a23e
https://github.com/llvm/llvm-project/commit/b6e3037f6e6283392f306b58c8444e0efe40a23e
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M offload/unittests/OffloadAPI/program/olCreateProgram.cpp
Log Message:
-----------
[offload][lit] Disable failing olCreateProgram test on AMD (#213126)
Fails with an error about not being able to find `lld`. AMD team is
investigating, but disable the test in the meantime.
Context: https://github.com/llvm/llvm-project/pull/212860
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: b75ab58e83301a56e958ea011fd851c88d976fe5
https://github.com/llvm/llvm-project/commit/b75ab58e83301a56e958ea011fd851c88d976fe5
Author: Patrick Simmons <patrick.simmons at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SOPInstructions.td
A llvm/test/CodeGen/AMDGPU/s_bcnt0.ll
M llvm/test/CodeGen/AMDGPU/s_cmp_0.ll
Log Message:
-----------
[AMDGPU] Match bitsin(typeof(x)) - ctpop(x) to s_bcnt0_i32 (#164847)
This PR optimizes the pattern bitsin(typeof(x)) - popcnt(x) to
s_bcnt0_i32 on AMDGPU. It also creates a Clang builtin for s_bcnt0_i32
so that users can call this instruction directly instead of relying on
the compiler to match this pattern.
Commit: 79f9cdae9dd4502f72f596ff406b0d10ae4cc5a0
https://github.com/llvm/llvm-project/commit/79f9cdae9dd4502f72f596ff406b0d10ae4cc5a0
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M lldb/unittests/Utility/ArchSpecTest.cpp
Log Message:
-----------
[lldb] Add a unit test for Wasm architecture compatibility (#213070)
A Wasm module encodes neither a vendor nor an OS, so ObjectFileWasm
reports a bare wasm32 or wasm64 architecture. That keeps an on-disk
module compatible with the more specific triple a Wasm runtime reports
at launch, which lets the dynamic loader reuse the module instead of
reparsing it from process memory. An over-specified triple, including
one that spells out an unknown vendor and OS, does not match, because an
explicitly specified component still counts as specified.
Commit: cdec735f774869f2949a94a7bf2e446798bf3b8c
https://github.com/llvm/llvm-project/commit/cdec735f774869f2949a94a7bf2e446798bf3b8c
Author: Michael Jones <michaelrj at google.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
A libc/docs/_static/llvm_libc_logo.svg
M libc/docs/index.md
Log Message:
-----------
[libc][docs] Add logo to website (#213120)
Add the excellent new logo drawn by @ajordanr-google to the homepage.
Commit: b05a5d09547bea535b4c26ee522ce310db118c47
https://github.com/llvm/llvm-project/commit/b05a5d09547bea535b4c26ee522ce310db118c47
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M lldb/bindings/python/CMakeLists.txt
M lldb/bindings/python/python-swigsafecast.swig
M lldb/bindings/python/python-wrapper.swig
M lldb/docs/CMakeLists.txt
A lldb/examples/python/templates/scripted_synthetic_children.py
M lldb/include/lldb/API/SBPlatform.h
M lldb/include/lldb/DataFormatters/TypeSynthetic.h
A lldb/include/lldb/Interpreter/Interfaces/ScriptedSyntheticChildrenInterface.h
M lldb/include/lldb/Interpreter/ScriptInterpreter.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/include/lldb/lldb-forward.h
M lldb/source/DataFormatters/TypeSynthetic.cpp
M lldb/source/Interpreter/ScriptInterpreter.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/CMakeLists.txt
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPythonInterface.h
A lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedSyntheticChildrenPythonInterface.cpp
A lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedSyntheticChildrenPythonInterface.h
M lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
M lldb/unittests/ScriptInterpreter/Python/PythonTestSuite.cpp
Log Message:
-----------
[lldb/script] Migrate synthetic children providers onto ScriptedPythonInterface (#210845)
Give `type synthetic add -l` a formal
`ScriptedSyntheticChildrenInterface`, matching the architecture used
elsewhere in this series: a C++ interface header, a Python-backed
implementation, `PluginManager` registration with CLI/API usages, and a
generatable ABC template (`scripted_synthetic_children.py`) wired into
`scripting extension generate`.
Every method goes through the shared `Dispatch<T>()` machinery instead
of hand-rolling its own Locker/raw-SWIG calls. `Dispatch<T>()` is taught
to introspect the target method's arity via
`PythonCallable::GetArgInfo()` and drop trailing args before calling, so
providers that legitimately define an argument as optional
(`num_children(self)` vs. `num_children(self, max_count)`) still work
through the generic dispatch path.
This retires the ad-hoc `LLDBSwigPython_*` synthetic-children bridge
functions entirely.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: f0da3dd9289e1b76da2658a0e6dad0e05842bdfd
https://github.com/llvm/llvm-project/commit/f0da3dd9289e1b76da2658a0e6dad0e05842bdfd
Author: Zahira Ammarguellat <zahira.ammarguellat at intel.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/include/clang/AST/StmtOpenMP.h
M clang/lib/AST/StmtOpenMP.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/test/OpenMP/fuse_codegen.cpp
M clang/test/OpenMP/interchange_codegen.cpp
R clang/test/OpenMP/loop_transform_final_iv.c
M clang/test/OpenMP/reverse_codegen.cpp
M clang/test/OpenMP/stripe_codegen.cpp
M clang/test/OpenMP/tile_codegen.cpp
Log Message:
-----------
Revert "[OpenMP] Restore loop variable values after loop-transformation constructs. (#212853)" (#213127)
Revert "[OpenMP] Restore loop variable values after loop-transformation
constructs. (#212853)"
This reverts commit 2d697f8562d7845d5554cc1d2cd2264401b9d68f.
Reverting this PR. Bot is failing with:
Failed Tests (2):
libomptarget :: spirv64-intel :: offloading/target-tile.c
libomptarget :: x86_64-unknown-linux-gnu :: offloading/target-tile.c
Commit: cc0f33be52a5a04fd809d6e6e6e41c0af794283d
https://github.com/llvm/llvm-project/commit/cc0f33be52a5a04fd809d6e6e6e41c0af794283d
Author: Frank <147031176+frank-suwen at users.noreply.github.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/docs/ClangFormatStyleOptions.rst
M clang/docs/ReleaseNotes.md
M clang/include/clang/Format/Format.h
M clang/lib/Format/BreakableToken.cpp
M clang/lib/Format/Format.cpp
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/FormatTestComments.cpp
Log Message:
-----------
[clang-format] Add SpacesInComments option for block comments (#204727)
Adds a new `SpacesInBlockComments` clang-format option to control
spacing after `/*` and before `*/` in ordinary block comments.
Supported values:
* Always: formats `/*comment*/` as `/* comment */`
* Never: formats `/* comment */` as `/*comment*/`
* Leave: preserves existing spacing
Documentation comments such as `/** ... */` and `/*! ... */`, and
parameter comments such as `/*Arg=*/`, are left unchanged.
Tests added for all option values, multiline block comments, and
excluded parameter/doc comments.
Addresses #160682
Commit: 100e8df6fc863f39e6f3e06862ee9500e859121f
https://github.com/llvm/llvm-project/commit/100e8df6fc863f39e6f3e06862ee9500e859121f
Author: Qiongsi Wu <qiongsiwu at gmail.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/include/clang/Tooling/DependencyScanningTool.h
M clang/lib/Tooling/DependencyScanningTool.cpp
Log Message:
-----------
[clang][DependencyScanning] Extracting a Driver-free CompilerInstaneWithContext Initializer (#211405)
This PR extracts out an initializer of `CompilerInstanceWithContext`
that does not depend on any driver code in preperation of moving the
`CompilerInstanceWithContext` into `DependencyScanningWorker.cpp` as an
implementation detail that is not exposed by any APIs.
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Commit: 7650a43aa8a6dabe890e08d3d482aa25ae31c826
https://github.com/llvm/llvm-project/commit/7650a43aa8a6dabe890e08d3d482aa25ae31c826
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-branch-weights.ll
A llvm/test/Transforms/LoopVectorize/expression-recipe-branch-weights.ll
A llvm/test/Transforms/LoopVectorize/replicate-region-branch-weights-merged-mem-ops.ll
M llvm/test/Transforms/LoopVectorize/replicate-region-branch-weights.ll
Log Message:
-----------
[LV] Add tests for preserving branch weights through VPlan (NFC). (#213131)
Add coverage for carrying the branch weights of a predicated block from
VPlan0 through to the generated IR
Commit: c836b82d088424baa8a60de63136747add192732
https://github.com/llvm/llvm-project/commit/c836b82d088424baa8a60de63136747add192732
Author: Matsu <47756807+khaki3 at users.noreply.github.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M mlir/lib/Dialect/OpenACC/Transforms/ACCCGToGPU.cpp
M mlir/test/Dialect/OpenACC/acc-cg-to-gpu-reduction-array-shared.mlir
Log Message:
-----------
[mlir][OpenACC] Atomicize contended shared array reduction updates (#212971)
Example:
```fortran
!$acc parallel loop gang reduction(+:a)
do i = 1, N
!$acc loop worker reduction(+:a)
do j = 1, M
a(i) = a(i) + b(j,i)
end do
end do
```
In this code, the worker accumulator is block-shared, so every worker
updates
the same element with a plain read-modify-write and all but one partial
is lost.
Fix: make in-place updates of a block-shared array accumulator atomic,
unless
the element index varies per thread, in which case each thread owns its
element
and the plain update is already race-free.
---------
Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
Commit: 21d9869c206e12f1932aecff50d03f06f5a96339
https://github.com/llvm/llvm-project/commit/21d9869c206e12f1932aecff50d03f06f5a96339
Author: yebinchon <86588366+yebinchon at users.noreply.github.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/OpenACC/Passes.td
A flang/lib/Optimizer/OpenACC/Transforms/ACCDevicePtrToCUFKernel.cpp
M flang/lib/Optimizer/OpenACC/Transforms/CMakeLists.txt
A flang/test/Fir/OpenACC/device-ptr-to-cuf-kernel.mlir
Log Message:
-----------
[flang] Add a pass to get OpenACC device ptr for CUDA kernel (#212299)
When a CUDA kernel is launched inside an OpenACC data region, it does
not properly get the device pointers and instead uses host data. This PR
adds a pass to get the device pointers set up by the OpenACC data
construct and pass them explicitly to the CUDA kernel.
Note: A possibly non-contiguous array argument is currently not supported. This pass will skip these cases.
---------
Co-authored-by: Yebin Chon <ychon at nvidia.com>
Commit: 256a6d2807a980c1477df0ed3b6ea6763460b967
https://github.com/llvm/llvm-project/commit/256a6d2807a980c1477df0ed3b6ea6763460b967
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
Log Message:
-----------
[AMDGPU] Use a single SubtargetPredicate for fp8/bf8 -> f32 conversions (#212888)
Add FeatureCvtFP8SDWASrcSel for the form that takes the byte from the SDWA src0_sel field and FeatureCvtFP8ByteSel for the form that takes it from a byte_sel operand. Both imply FeatureFP8ConversionInsts, and a subtarget provides one of them, so the multiclass-generated HasCvtFP8SDWASrcSel and HasCvtFP8ByteSel replace the GFX9 and GFX11Plus predicates outright.
Assisted-By: Claude Opus 5
Commit: f279abcc818a89c2c73c305a1ce5a9a18d2215ec
https://github.com/llvm/llvm-project/commit/f279abcc818a89c2c73c305a1ce5a9a18d2215ec
Author: Kewen Meng <Kewen.Meng at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M offload/test/unit/lit.cfg.py
M offload/test/unit/lit.site.cfg.in
Log Message:
-----------
[Offload][Test] Add llvm bin in the PATH for offload-unit suite (#213149)
This PR makes the offload-unit suite put llvm bin directory on PATH so
that tests need lld can find. It fixes the issue exposed in:
https://github.com/llvm/llvm-project/pull/212860
Commit: 2d0b45bc0a7fcb29aa77242b9262eb7c9eba5333
https://github.com/llvm/llvm-project/commit/2d0b45bc0a7fcb29aa77242b9262eb7c9eba5333
Author: johnnyb2543 <134093951+johnnyb2543 at users.noreply.github.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Prevent re-assigning type on finalized tokens (#210763)
Prevents a finalized token inside modifyContext from being reassigned
through the setType member function by checking if the token is
finalized.
This ensures ill-defined code like does not trigger an assertion failure
during reformatting.
Fixes #210509
Commit: 613154323d2f06b8018065d88c2781529cf77c75
https://github.com/llvm/llvm-project/commit/613154323d2f06b8018065d88c2781529cf77c75
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/OpenACC/Transforms/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 21d9869 (#213147)
This fixes 21d9869c206e12f1932aecff50d03f06f5a96339 (#212299).
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=21d9869c206e12f1932aecff50d03f06f5a96339
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 197e68dbd324fa48d45666a9c95a83303c995356
https://github.com/llvm/llvm-project/commit/197e68dbd324fa48d45666a9c95a83303c995356
Author: Rafael Auler <rafaelauler at meta.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M .github/CODEOWNERS
Log Message:
-----------
Revert "[github] Move BOLT reviewers to team (#211422)" (#213141)
We haven't really being tagged in new PRs anymore, so it looks like this
is not working.
Revert for now until we can fix this, so we don't miss PRs.
This reverts commit 04f124f6151e8c8410e28aba28dc38e590e34c58.
Commit: 7e35cbb1b6f5915ab732a22e83b3afc20e29181a
https://github.com/llvm/llvm-project/commit/7e35cbb1b6f5915ab732a22e83b3afc20e29181a
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXBaseInfo.h
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h
M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.h
Log Message:
-----------
[NVPTX] Cleanup PTX virtual register encoding (NFC) (#212395)
Unify the scheme used to carry PTX virtual registers through
`MCOperand`s. The register class was encoded and decoded
by two hand-written switchtables, one in
`NVPTXAsmPrinter::encodeVirtualRegister` and one in
`NVPTXInstPrinter::printRegName`, kept in sync only by
comment. Both now share a `VirtualRegisterKind` enum and
`getVirtualRegisterPrefix` in `NVPTXBaseInfo.h`, which also
subsumes `getNVPTXRegClassStr` and drops the stale
`%f`/`%fd` cases left over from the typed float register
classes.
Co-Authored by Opus-5.
Commit: 56a48d712006ff7d9a09eef6a86b78d4b2eec3aa
https://github.com/llvm/llvm-project/commit/56a48d712006ff7d9a09eef6a86b78d4b2eec3aa
Author: Thurston Dang <thurston at google.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M compiler-rt/test/msan/vararg_shadow.cpp
Log Message:
-----------
[msan][test] Disable UB cases in vararg_shadow.cpp (#204246)
This patch comments out the tests for char and float, which have
undefined behavior: `warning: second argument to 'va_arg' is of
promotable type 'char'/'float'; this va_arg has undefined behavior
because arguments will be promoted to 'int'/'double' [-Wvarargs]`.
The non-UB way to rewrite the tests is to use `va_arg()` with int and
double types (when the original variables are char and float), but there
are already test cases for int and double.
Note also that the float test makes an assumption that
`cast<float>(cast<double>(float))` will maintain the original shadow,
which MSan need not guarantee. In particular,
https://github.com/llvm/llvm-project/pull/204197 breaks that assumption
(which led to a buildbot breakage and revert).
Commit: 30611cae030a654be821dfc817126568ac6d2baa
https://github.com/llvm/llvm-project/commit/30611cae030a654be821dfc817126568ac6d2baa
Author: Adam Bzowski <adam.bzowski at arm.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/test/AArch64/constant_island_pie_update.s
Log Message:
-----------
[BOLT] Fix RELR addend updates for non-zero image bases (#213000)
This patch fixes an AArch64 BOLT failure exposed by LLVM commit
`fbba327208d7f6994f9a28a51dca3e913e3b444a`, which enabled packed
relative relocations (RELR) globally. BOLT incorrectly used a virtual
relocation address as a file offset when updating RELR addends,
corrupting instrumented executables when their image base was non-zero.
The observed CMake compiler-check failure was only a consequence of the
corrupted BOLT-instrumented Clang executable crashing; the defect itself
is in BOLT, not CMake.
The regression test links an AArch64 PIE with a non-zero image base and
verifies that BOLT updates the RELR addend at the correct file offset.
Assisted-by: Codex
Commit: f68fba7a512c0dd3662540259e032a4a4de653b1
https://github.com/llvm/llvm-project/commit/f68fba7a512c0dd3662540259e032a4a4de653b1
Author: Anshil Gandhi <95053726+gandhi56 at users.noreply.github.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/DependencyGraphTest.cpp
Log Message:
-----------
[SandboxVec][DAG] Fix notifyEraseInstr to skip scheduled neighbors (#212868)
Guard both loops with !PredN->scheduled() so scheduled neighbors are
left untouched, and add a unit test that erases a node with one
scheduled and one unscheduled predecessor to cover the fix.
Commit: 17088c9b104e807ba29a0d115796bc6de23e9f63
https://github.com/llvm/llvm-project/commit/17088c9b104e807ba29a0d115796bc6de23e9f63
Author: Anshil Gandhi <95053726+gandhi56 at users.noreply.github.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/VecUtils.cpp
A llvm/test/Transforms/SandboxVectorizer/topdown_vec.ll
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
Log Message:
-----------
[SandboxVectorizer] Implement topdown/bottomup vectorizers in unison (#205249)
Extend the Sandbox Vectorizer's `bottom-up-vec` pass so a single
implementation can vectorize in either direction, and add the top-down
strategy that walks def-use chains forward from a seed.
Direction selection
--------------------
The pass direction is chosen from the Region's auxiliary pass argument:
"bottom-up" (or empty, the default) and "top-down" map onto a
SchedDirection, and any other value is rejected with a fatal usage
error.
The vectorizer always runs in the same direction as the scheduler.
Top-down traversal
------------------
Bottom-up starts from a seed slice (e.g. stores to consecutive
addresses)
and recurses into operands. Top-down instead starts from a seed of
consecutive loads and recurses into *users*:
- vectorizeRec() registers the current bundle's vector (pre-order)
before
recursing, so instructions are marked vectorized as soon as they are
claimed. This prevents sibling user bundles from claiming the same
instruction and guarantees termination.
- VecUtils::getNextUserBundles() drives the walk. For each user of lane
0
it tries to assemble a matching user for every remaining lane, requiring
the same opcode, type, parent block, and operand-usage indices, and
claiming each instruction at most once. Only complete bundles (one user
per lane) are returned.
- A non-Widen legality result stops the walk down that path: the bundle
is
left scalar and no action is recorded. DiamondReuse results cannot occur
top-down because already-vectorized users are skipped, so a bundle never
contains an instruction already in InstrMaps.
Operand and external-use handling
---------------------------------
Because a user bundle is emitted after its operand bundle, emitVectors()
looks up each operand's vector in InstrMaps and creates a pack when the
operand was not vectorized. emitUnpacksForExternalUses() now redirects
only the genuinely external (non-vectorized) uses via
replaceUsesWithIf(),
instead of a blanket replaceAllUsesWith() that would corrupt the
operands
of user bundles not yet emitted. Scheduling is currently skipped for the
top-down direction (TODO).
Refactoring
-----------
Unify the two strategies to avoid code duplication: introduce a shared
BundleTy alias, move user-bundle collection into VecUtils (with unit
tests), and thread the direction through legality checks and vector
emission.
Depends on #207237
Co-authored-by: Cursor <cursoragent at cursor.com>
Commit: 4912831bc346aa48a3c06475ad8d24f37f84bc8d
https://github.com/llvm/llvm-project/commit/4912831bc346aa48a3c06475ad8d24f37f84bc8d
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M lldb/include/lldb/Target/Target.h
M lldb/source/Target/Target.cpp
M lldb/source/Target/TargetProperties.td
M lldb/test/API/commands/settings/TestSettings.py
Log Message:
-----------
[lldb] Add target.jit-engine setting (#212998)
Add a target.jit-engine setting that lets users choose which LLVM
execution engine (MCJIT or ORC) is used to JIT expressions. Defaults to
MCJIT to preserve current behavior. This is groundwork for migrating
expression evaluation from MCJIT to ORC; IRExecutionUnit does not yet
consult this setting.
Commit: 71af911facd88e41df273a95d658c3293aa4edee
https://github.com/llvm/llvm-project/commit/71af911facd88e41df273a95d658c3293aa4edee
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M lldb/docs/CMakeLists.txt
M lldb/docs/python_extensions.md
Log Message:
-----------
[lldb/docs] Document the remaining scripted-extension plugin categories (#213140)
`python_extensions.md` only covered the first five plugin categories.
This commit adds the missing sections for every plugin category added
since: `ScriptedBreakpointResolver`, `ScriptedHook`,
`ScriptedStackFrameRecognizer`, `ScriptedCommand`, `ParsedCommand`,
`ScriptedStringSummary`, and `ScriptedSyntheticChildren`.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: a1d93f19bed4c73051f9379e2c64d4303b6866ca
https://github.com/llvm/llvm-project/commit/a1d93f19bed4c73051f9379e2c64d4303b6866ca
Author: Abhinav Gaba <abhinav.gaba at intel.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M offload/libomptarget/omptarget.cpp
A offload/test/offloading/firstprivate_packed_buffer_lifetime.c
Log Message:
-----------
[OpenMP][Offload] Fix use-after-free of the packed firstprivate transfer buffer (#212905)
`packAndTransfer()` called `submitData()`, which captured the address of
the data of
the `SmallVector` member of `PrivateArgumentManagerTy`, as the host
source of an
async transfer. The manager was later moved into an `AsyncInfo`
post-processing
lambda, changing the underlying address of the data:
`addPostProcessingFunction()`
copies the closure rather than moving it, but even if it "moved", the
address of the data owned by `SmallVector`'s inline capacity would have
changed.
The AMDGPU plugin read from the stale host source address when doing the
actual transfer.
Fix: allocate the packed buffer via
`getOrCreateSourceBufferForSubmitData()`, so
that `AsyncInfo` owns it. The non-packed
corresponding-pointer-initialization
path in this same class already built its source buffer that way.
Commit: 06361fb2efd0a6818800891d9e410615483fce6c
https://github.com/llvm/llvm-project/commit/06361fb2efd0a6818800891d9e410615483fce6c
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
M clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenStmt.cpp
M clang/lib/CIR/CodeGen/CIRGenVTables.cpp
A clang/test/CIR/CodeGen/attr-musttail.cpp
Log Message:
-----------
[CIR] Implement most of 'musttail' statement attr (#213154)
This implements the basics, and leaves NYI in a few places (particularly
those that require cleanup calculations). There IS some additional work
that needs to be done when the ABI work is put in place as well, and the
thunk 'tail' hint isn't implemented either, and is left as a
missing-feature.
This is necessary for compiling the bytecode interpreter in Clang in a
few places during self-build.
Commit: 8fbdc8cd027176fb54c5fbcd7688fe78eed0154f
https://github.com/llvm/llvm-project/commit/8fbdc8cd027176fb54c5fbcd7688fe78eed0154f
Author: jimingham <jingham at apple.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
Log Message:
-----------
If the address of the isa_pointer is returned as an error don't ask if it is a tagged pointer (#213163)
The answer isn't right and the wrong type might stick and cause
downstream failures.
Note, the correct solution to this is to distinguish between "couldn't
get the address" and "got a real value of LLDB_INVALID_ADDRESS" but
piping an optional all the way down and then through all the uses is an
intrusive change which I don't have time for right now. That only risk
is that this really IS a tagged pointer with the value
LLDB_INVALID_ADDRESS, so this seems an acceptable workaround.
I ran across this when debugging the ObjC test failures in the ObjC
testuite after 8b9cce358bef26ae4cb9275dd6a43f903bafbaa0. This patch
clears up all those testsuite failures, which should stand as a test for
this patch when I resubmit that change.
Commit: 6d9de525456298c7df08d77942d3ec50dddf5eaa
https://github.com/llvm/llvm-project/commit/6d9de525456298c7df08d77942d3ec50dddf5eaa
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/test/CodeGen/AMDGPU/bug-pk-f32-imm-fold.mir
M llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
M llvm/test/CodeGen/AMDGPU/coexec-sched-flavor-classification.mir
Log Message:
-----------
[AMDGPU] Duplicate packed fp32 instructions (#212857)
These have different semantics on gfx9 and gfx12 with respect to
scalar operands.
Commit: 53e16d7708c39ecc03f97d32d1db9afdd355deca
https://github.com/llvm/llvm-project/commit/53e16d7708c39ecc03f97d32d1db9afdd355deca
Author: Akshay K <iit.akshay at gmail.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
A clang/include/clang/CIR/CIRDataLayoutSpec.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
A clang/lib/CIR/CodeGen/CIRDataLayoutSpec.cpp
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
M clang/lib/CIR/CodeGen/CMakeLists.txt
M clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
A clang/test/CIR/CodeGen/pointer-width-32bit.cpp
A clang/test/CIR/IR/pointer-data-layout.cir
A clang/test/CIR/Tools/pointer-width-from-triple.cir
M clang/tools/cir-translate/cir-translate.cpp
Log Message:
-----------
[CIR] Pointer and vptr width from a CIR-native data-layout entry (#204185)
PointerType and VPtrType have hard-coded sizes and alignments of 64/8
bits. On targets with 32-bit pointers (e.g., nvptx, spirv32), this trips
the record layout builder. Any record containing a pointer hit the
insertPadding assertion (offset >= size)
because the pointer was sized at 8 bytes while the following field was
placed at the AST-mandated 4-byte offset.
### Changes:
- CIRGenerator: attaches a CIR-native cir.ptr data-layout entry at
module setup, storing {size-in-bits, abi-align-in-bits} read
from the target DataLayout (only for the default address space).
- CIRTypes: PointerType reads its size/alignment from that entry
(falling back to 64/8 when absent); VPtrType routes through a cir.ptr so
it picks up the same width.
- LowerToLLVM: strips the cir.ptr entry during CIR→LLVM lowering, since
cir.ptr has no meaning in LLVM IR.
- Unit test: checking 4-byte pointer/vptr layout on nvptx, verified
across CIR, CIR→LLVM.
Commit: 0879c1092c66242027065634210692cc06359fee
https://github.com/llvm/llvm-project/commit/0879c1092c66242027065634210692cc06359fee
Author: hulxv <hulxxv at gmail.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/extenddftf2.cpp
A compiler-rt/lib/builtins/extendsfdf2.cpp
A compiler-rt/lib/builtins/extendsftf2.cpp
A compiler-rt/lib/builtins/extendxftf2.cpp
A compiler-rt/lib/builtins/truncdfsf2.cpp
A compiler-rt/lib/builtins/trunctfdf2.cpp
A compiler-rt/lib/builtins/trunctfsf2.cpp
A compiler-rt/lib/builtins/trunctfxf2.cpp
M libc/shared/builtins.h
A libc/shared/builtins/extenddftf2.h
A libc/shared/builtins/extendsfdf2.h
A libc/shared/builtins/extendsftf2.h
A libc/shared/builtins/extendxftf2.h
A libc/shared/builtins/truncdfsf2.h
A libc/shared/builtins/trunctfdf2.h
A libc/shared/builtins/trunctfsf2.h
A libc/shared/builtins/trunctfxf2.h
M libc/src/__support/builtins/CMakeLists.txt
A libc/src/__support/builtins/extenddftf2.h
A libc/src/__support/builtins/extendsfdf2.h
A libc/src/__support/builtins/extendsftf2.h
A libc/src/__support/builtins/extendxftf2.h
A libc/src/__support/builtins/fpconvert_helper.h
A libc/src/__support/builtins/truncdfsf2.h
A libc/src/__support/builtins/trunctfdf2.h
A libc/src/__support/builtins/trunctfsf2.h
A libc/src/__support/builtins/trunctfxf2.h
M libc/test/shared/CMakeLists.txt
M libc/test/shared/shared_builtins_test.cpp
Log Message:
-----------
[compiler-rt][builtins] libc-backed floating-point extend/trunct builtins (#209984)
Add libc-backed floating-point extend/truncate builtins
Part of #197824
Commit: 0142992aea1df89fec8c20bf77520e37bfb69e2a
https://github.com/llvm/llvm-project/commit/0142992aea1df89fec8c20bf77520e37bfb69e2a
Author: Yusuke MINATO <minato.yusuke at fujitsu.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/test/Driver/flang/multiple-inputs-mixed.f90
A clang/test/Driver/flang/runtimes.f90
Log Message:
-----------
Reapply "[NFC][clang][Driver] Add tests for --driver-mode=flang" (#211724)
This reapplies #207658.
Some targets do not support flang_rt or clang_rt.
It seems difficult to create a blocklist, so the tests are now
configured to explicitly specify the known-working targets.
The specified targets are extracted from tests in flang/test/Driver.
-----
The original commit message:
This patch intends to clarify the current behaviors, not to state the
expected/desirable behaviors.
Commit: d9278ad4e640cf04e5fa0bd22898f5aa0351b564
https://github.com/llvm/llvm-project/commit/d9278ad4e640cf04e5fa0bd22898f5aa0351b564
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M lldb/include/lldb/Core/BugReporter.h
M lldb/source/Commands/CommandObjectDiagnostics.cpp
A lldb/source/Core/BugReporter.cpp
M lldb/source/Core/CMakeLists.txt
M lldb/source/Plugins/BugReporter/GitHub/GitHubReporter.cpp
M lldb/test/Shell/Diagnostics/TestReport.test
Log Message:
-----------
[lldb] Ask the reporter what happened in a bug report (#213173)
A diagnostics bundle records the state of the debugger, never what the
user was doing or what they expected instead, so reports arrive with a
generic title and no description of the problem. Pre-fill the report
with the questions only the person filing it can answer, and print a
checklist when the bundle is written so an incomplete report doesn't get
shared as-is.
rdar://183356348
Commit: 2e3f4ef5855e07f4bd2b0a1270e6101beceb1f8c
https://github.com/llvm/llvm-project/commit/2e3f4ef5855e07f4bd2b0a1270e6101beceb1f8c
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
A llvm/test/CodeGen/SPIRV/legalization/matrix-wide-vector-shader.ll
Log Message:
-----------
[SPIRV] Legalize Cast Instructions for Matrix Types (#212619)
fixes #186864
This is a more limited fix. that doesn't require us to change the whole
legalization strategy for SPIR-V.
To get the last fix to work it looks like I would have to have changed
every global opcode to no longer use power of 2 based legalization.
This change with power of 2 fixed the transpose case in the offload
testsuite when we do the conversion of bools to i32s before we call
transpose.
There remains an issue when a i1 makes it into a transpose intrinsic.
That said I can only trigger that case via llvmir and not HLSL so will
move on for now.
Commit: b4d2b2f9a31ba82b5bcbf9060748bde8beae814b
https://github.com/llvm/llvm-project/commit/b4d2b2f9a31ba82b5bcbf9060748bde8beae814b
Author: Michael G. Kazakov <mike.kazakov at gmail.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M libcxx/include/__algorithm/pstl.h
M libcxx/include/__pstl/backend_fwd.h
M libcxx/include/__pstl/backends/default.h
M libcxx/test/libcxx/algorithms/pstl.iterator-requirements.verify.cpp
M libcxx/test/libcxx/algorithms/pstl.nodiscard.verify.cpp
A libcxx/test/std/algorithms/alg.sorting/alg.lex.comparison/pstl.lexicographical_compare.pass.cpp
A libcxx/test/std/algorithms/alg.sorting/alg.lex.comparison/pstl.lexicographical_compare_comp.pass.cpp
M libcxx/test/std/algorithms/pstl.exception_handling.pass.cpp
Log Message:
-----------
[libc++][pstl] Implementation of parallel std::lexicographical_compare() based on std::mismatch() (#212366)
This PR adds an implementation of parallel
`std::lexicographical_compare()` based on parallel `std::mismatch()`.
The implementation is close to a one-liner:
```c++
auto __res = _Mismatch()(__policy, __first1, __last1, __first2, __last2, [&](_Ref1 __lhs, _Ref2 __rhs) {
return !__comp(__lhs, __rhs) && !__comp(__rhs, __lhs);
});
```
Included tests check that:
- Semantics of the iterator-only version is correct.
- Semantics of the predicated version is correct.
- The functions correctly SFINAE out when the first argument is not an
execution policy.
- The `noexcept` policy is followed.
- The `nodiscard` policy is followed.
- `static_assert` verifies iterators' categories.
Part of #99938.
Commit: 71e0359a1acd9ab267c72fcf9dfb683afc59fbea
https://github.com/llvm/llvm-project/commit/71e0359a1acd9ab267c72fcf9dfb683afc59fbea
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/RTBridge/Calls.h
M llvm/include/llvm/ExecutionEngine/Orc/RTBridge/SPS/Calls.h
M llvm/lib/ExecutionEngine/Orc/Shared/OrcRTBridge.cpp
Log Message:
-----------
[ORC] Generalize RTBridge callers over signature types. (#213179)
Recast the RTBridge callers as templates parameterized on the call
signature, so future executor accessors can be added as thin
declarations rather than hand-written classes.
rt::Caller<RetT(ArgTs...)> is the runtime-agnostic caller interface for
a given signature, providing the asynchronous and synchronous call
operators and the associated result types. rt::MainCaller is now an
alias for rt::Caller<int64_t(ArrayRef<std::string>)>.
rt::sps::Caller<BaseT, SPSSigT, CIName> implements any such interface by
invoking an executor-side SPS wrapper in the runtime's controller
interface, deducing the argument and result types from BaseT. A concrete
caller is a typedef supplying the interface, its SPS signature, and the
CI entry-point name; see rt::sps::MainCaller.
MainCaller's observable behavior is unchanged (the existing
SPSCallersTest still passes). The out-of-line destructor anchor in
OrcRTBridge.cpp is dropped, as the templated base now provides an inline
defaulted destructor.
Commit: 5e90b7bad3cc0960a26f46969063c5acf03ac137
https://github.com/llvm/llvm-project/commit/5e90b7bad3cc0960a26f46969063c5acf03ac137
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
A llvm/test/DebugInfo/X86/DW_AT_LLVM_stmt_seq_split_dwarf.ll
Log Message:
-----------
[DebugInfo] Make DW_AT_LLVM_stmt_seq work with split DWARF (#213128)
Before this change, we would end up with a relocation in the dwo, which
would then result in an error.
Commit: 8b04cf374d4ac63edf973eb23b0566c21b6f638f
https://github.com/llvm/llvm-project/commit/8b04cf374d4ac63edf973eb23b0566c21b6f638f
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
Log Message:
-----------
[AMDGPU] Rename packed 64-bit features to include SingleSGPR. NFCI. (#212891)
Commit: 88329c4ad200b71e0cbcc7ac0093c7caf934ddea
https://github.com/llvm/llvm-project/commit/88329c4ad200b71e0cbcc7ac0093c7caf934ddea
Author: Kazu Hirata <kazu at google.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/include/llvm/ADT/SetVector.h
M llvm/lib/Transforms/IPO/Attributor.cpp
Log Message:
-----------
[ADT] Introduce SetVector::reserve (NFC) (#209951)
This patch introduces SetVector::reserve to allocate capacity in the
underlying containers.
We also adopt SetVector::reserve across Attributor.cpp where the exact
number of unique functions being inserted is known ahead of time.
Assisted-by: Antigravity
Commit: ca5549224e06c5ed57332bf1bc89c0ac06c69e60
https://github.com/llvm/llvm-project/commit/ca5549224e06c5ed57332bf1bc89c0ac06c69e60
Author: Thurston Dang <thurston at google.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vcvt.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vcvt_f32_su32.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/vararg_shadow.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/f16c-intrinsics-upgrade.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/vararg_shadow.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/vararg_shadow.ll
Log Message:
-----------
Reland "[msan] Apply handleGenericVectorConvertIntrinsic() to fptrunc/fpext" (#213161)
Reverts llvm/llvm-project#204221 i.e., reapplies
https://github.com/llvm/llvm-project/pull/204197. The original patch was
reverted was due to a buildbot failure in vararg_shadow.cpp that relied
on undefined behavior as well as an unwarranted assumption that the
shadow is preserved when round-tripping from float->double->float. The
UB cases have been disabled in
https://github.com/llvm/llvm-project/pull/204246.
Original commit message:
The current instrumentation uses handleShadowOr(), which effectively
truncates or zero-extends the shadows for fptrunc/fpext respectively;
this is overly lax because floating-point has both mantissa and exponent
components (e.g., if the mantissa is initialized but the exponent is
uninitialized, an fptrunc might end up with a fully initialized shadow,
which is incorrect; conversely, if a floating-point value is fully
uninitialized, we want the fpext'ed shadow to be fully uninitialized,
not zero-extended). This patch strengthens the instrumentation of
fptrunc/fpext by using handleGenericVectorConvertIntrinsic(), which
applies an "all-or-nothing" approach to uninitialized bits of each
scalar.
Note: https://github.com/llvm/llvm-project/pull/203903 auto-upgraded
aarch64_neon_vcvtfp2hf and aarch64_neon_vcvthf2fp to fptrunc and fpext,
which had the effect of weakening MSan's instrumentation for those NEON
intrinsics. This patch restores the stronger instrumentation for them
(and also generalizes it to all instances of fptrunc and fpext).
Commit: 151b53deb836f82fdc068f05d4af1b42e1c4748a
https://github.com/llvm/llvm-project/commit/151b53deb836f82fdc068f05d4af1b42e1c4748a
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/Relocations.cpp
M lld/test/ELF/aarch64-thunk-sort.s
Log Message:
-----------
[ELF] Remove -z sort-thunks (#213074)
The option was added by #211721 (sort forward thunks by descending
destination to prevent convergence failures) as a temporary opt-out.
Tests have been migrated to the default order.
Commit: 4311bccd19e2db25e7c410acd9d77a86d2b779d1
https://github.com/llvm/llvm-project/commit/4311bccd19e2db25e7c410acd9d77a86d2b779d1
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
R llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
R llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
Log Message:
-----------
[NVPTX] Move NVPTXAsmPrinter and NVPTXDAGToDAGISel out of headers (NFC) (#213162)
Both headers were only included by their own `.cpp` file, so move the
class definitions into anonymous namespaces there and delete the
headers.
`getFromTypeWidthForLoad` was the only thing `NVPTXISelLowering.cpp`
needed from the ISel class, so it moves to `NVPTXUtilities` as a free
function.
Commit: 08bfd2e3fd81e6930b12076a670fc9e59ef32a84
https://github.com/llvm/llvm-project/commit/08bfd2e3fd81e6930b12076a670fc9e59ef32a84
Author: Henry Jiang <henry_jiang2 at apple.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/utils/perf-training/perf-helper.py
Log Message:
-----------
[clang] perf_helper.py ignore clang warning/note when parsing cc1 command (#212401)
Parsing cc1 command fails in `perf_helper` when `clang: note:` or
`clang: warning:` due to driver warnings. As an example, harmless macOS
sdk mismatch and `-Wunused-command-line-argument`.
Commit: 1ddfb94fa6c645af9e10ad4946d9b7aea3c46454
https://github.com/llvm/llvm-project/commit/1ddfb94fa6c645af9e10ad4946d9b7aea3c46454
Author: Krisitan Erik Olsen <kristian.erik at outlook.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaChecking.cpp
A clang/test/CodeGenCXX/GH211943.cpp
Log Message:
-----------
[Sema] Fix crash in __builtin_dump_struct with -Werror -Wformat-pedantic (#212377)
`DiagnosticErrorTrap::hasErrorOccurred()` treats warnings promoted to
errors by `-Werror` as real errors, causing `BuiltinDumpStructGenerator`
to bail out before building the `PseudoObjectExpr` wrapper. CodeGen then
encounters the untransformed `CallExpr` with a placeholder builtin type
and hits `llvm_unreachable` in `CodeGenTypes::ConvertType`.
Use `hasUnrecoverableErrorOccurred()` instead, which ignores `-Werror`
promoted warnings and only bails on genuine compilation errors.
Fixes #211943
Commit: 503e7f6a2674bd80490d69670e86e6b8d823215c
https://github.com/llvm/llvm-project/commit/503e7f6a2674bd80490d69670e86e6b8d823215c
Author: Henry Jiang <henry_jiang2 at apple.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/include/module.modulemap
Log Message:
-----------
Module Build Fix: Add NVPTXTargetParser.def as a header (#213194)
Fixes module build `-DLLVM_ENABLE_MODULES=ON` in
https://ci.swift.org/job/llvm.org/job/clang-stage2-Rthinlto/job/main/457
by adding missing header for `NVPTXTargetParser.def`.
rdar://183685761
Commit: c57b2b6103cb4bb6c4c2bee901c1eee2b966e5f0
https://github.com/llvm/llvm-project/commit/c57b2b6103cb4bb6c4c2bee901c1eee2b966e5f0
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
M llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
M llvm/test/CodeGen/X86/merge-store-partially-alias-loads.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
Log Message:
-----------
DAG: Use poison in getLoad/getStore for offsets (#212066)
Commit: 8b1821512db03f0cf0d443ac836f42ab993e9c53
https://github.com/llvm/llvm-project/commit/8b1821512db03f0cf0d443ac836f42ab993e9c53
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/unittests/Target/ARM/InstSizes.cpp
M llvm/unittests/Target/ARM/MachineInstrTest.cpp
Log Message:
-----------
ARM: Thread float ABI through ARMSubtarget (NFC) (#212931)
Commit: 7fc837632399955e281bce975033ff7b389eb790
https://github.com/llvm/llvm-project/commit/7fc837632399955e281bce975033ff7b389eb790
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/test/CodeGenOpenCL/builtins-amdgcn-global-load-store.cl
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
Log Message:
-----------
AMDGPU: Add missing flat-global-insts to gfx13 frontend feature map (#213121)
Commit: cee7b71929312666c5cf48eb79873893811b99a7
https://github.com/llvm/llvm-project/commit/cee7b71929312666c5cf48eb79873893811b99a7
Author: Kirill A. Korinsky <kirill at korins.ky>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/test/CodeGen/SPARC/reserved-regs-named.ll
Log Message:
-----------
[SPARC] Accept named register aliases (#212838)
Handle r0-r31, sp, fp and the optional '%' prefix in llvm.read_register
and llvm.write_register.
Commit: afd4c46353bf77b9f4ebfde664e4fcf8d2ef2fc8
https://github.com/llvm/llvm-project/commit/afd4c46353bf77b9f4ebfde664e4fcf8d2ef2fc8
Author: Kamlesh Kumar <kamlesh.kumar at arm.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/sve-structured-store-memoperands.ll
M llvm/test/CodeGen/AArch64/sve-vector-interleave.ll
Log Message:
-----------
[AArch64] Preserve store memoperand (#210936)
Commit: 5b1539c0fca2e3f9362d100848983a3cc4272764
https://github.com/llvm/llvm-project/commit/5b1539c0fca2e3f9362d100848983a3cc4272764
Author: David Green <david.green at arm.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-addo-zero.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-binop-reassoc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-conflict.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-crash.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-and-mask.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-or-pattern-align.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-or-pattern.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-mulo-zero.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-narrow-binop-feeding-add.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-select-to-fminmax.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-use-vector-truncate.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-ashr-shl-to-sext-inreg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-binop-same-val.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-br.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-bzero.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-commute-shift.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-concat-vectors.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-s1.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-funnel-shifts-to-rotates.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-hoist-same-hands.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-icmp-redundant-trunc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-invert-cmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-not-really-equiv-insts.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-prop-extends-phi.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-ptradd-chain.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-select.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-sextload-from-sextinreg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector-disjoint-mask.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector-undef-rhs.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-simplify-add.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-undef.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-xor-of-and-with-same-reg.mir
Log Message:
-----------
[AArch64][GlobalISel] Update prelegalize tests with concrete types. NFC (#213199)
Commit: 79537625e213b6a5f329da1d5a443de265346a5e
https://github.com/llvm/llvm-project/commit/79537625e213b6a5f329da1d5a443de265346a5e
Author: Kamlesh Kumar <kamlesh.kumar at arm.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/avoid-ld4.ll
Log Message:
-----------
[AArch64] Avoid factor-4 deinterleaved loads feeding uitofp (#210894)
Avoid generating ld4 when all values produced by the deinterleaved load
are fed into uitofp. Keeping the loads separate allows the backend to
optimize them into shifts and masks.
Commit: a7fa385ffa27504240e90e2b857455459dbd11de
https://github.com/llvm/llvm-project/commit/a7fa385ffa27504240e90e2b857455459dbd11de
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx13.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-raw-buffer-atomic-max.cl
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
Log Message:
-----------
AMDGPU: Add missing atomic-fmin-fmax-global to gfx13 feature map (#213119)
fillAMDGCNFeatureMap omitted atomic-fmin-fmax-global-f32 and
atomic-fmin-fmax-global-f64 for gfx1310/gfx13-generic, so clang wrongly
rejected the raw_ptr_buffer_atomic_f{min,max}_f{32,64} builtins on those
targets even though the backend enables the features. Add them to the
gfx13 case.
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: 14192adddc39cb28b7bcb1e6d50dc6ef87f4d54b
https://github.com/llvm/llvm-project/commit/14192adddc39cb28b7bcb1e6d50dc6ef87f4d54b
Author: Peter Rong <peterrong96 at gmail.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/lib/AST/Expr.cpp
M clang/lib/Sema/SemaDecl.cpp
A clang/test/SemaObjC/objc-constant-literal-dict-key-restrictions.m
Log Message:
-----------
[clang][Sema] Fix ObjC file-scope literal diagnostic (#209688)
A non-constant ObjC collection literal used as a file-scope initializer
should get the targeted err_objc_literal_nonconstant_at_file_scope
pointing at the offending element. CheckForConstantInitializer instead
inspected the wrapped Init/Culprit, so under -fobjc-arc, for id-typed
variables, or with parentheses it skipped the per-element loop and fell
back to the generic "initializer element is not a compile-time constant"
on the whole @{...}/@[...] -- or blamed the wrong element (e.g. a valid
string key rather than the non-constant value).
Unwrap the culprit with IgnoreParenImpCasts and drive classification and
per-element reporting off it, mirroring BuildObjC{Array,Dictionary}Literal
(unwrap before each isa<>; keys must be string literals, values/elements
constant object literals). Also treat CK_ARCReclaimReturnedObject as
transparent in Expr::isConstantInitializer so ARC-wrapped literals are
recognized and the reported culprit is the literal itself.
Add objc-constant-literal-dict-key-restrictions.m (macOS no-ARC, iOS ARC,
ObjC++), with each culprit on its own line so -verify checks the caret.
[Assisted-by](https://t.ly/Dkjjk): Opus 4.8
Commit: 6a38e4e0971285ccd7cca1b732f644a49f772d49
https://github.com/llvm/llvm-project/commit/6a38e4e0971285ccd7cca1b732f644a49f772d49
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h
Log Message:
-----------
[BFI] Simplify computeMassInLoops. NFC (#213200)
Iterate backwards with a plain iterator instead of dancing with
prev(base()).
Commit: 0312615e54f021ed2dc400a3ecd6698058490ae6
https://github.com/llvm/llvm-project/commit/0312615e54f021ed2dc400a3ecd6698058490ae6
Author: Mariya Podchishchaeva <mariya.podchishchaeva at intel.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/Maintainers.md
Log Message:
-----------
[clang][doc] Use my private email for now (#213058)
I'm in the middle of changing employers and will loose access to the
current email soon for a while.
Commit: 9f6b782c7a993dedc8fe8b6e69c36c9684191f27
https://github.com/llvm/llvm-project/commit/9f6b782c7a993dedc8fe8b6e69c36c9684191f27
Author: Anutosh Bhat <andersonbhat491 at gmail.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll
Log Message:
-----------
[WebAssembly] Fix legalization of v8f16 insertelement (#212992)
```
define <8 x half> @insert_v8f16(<8 x half> %v, half %x) {
%r = insertelement <8 x half> %v, half %x, i32 3
ret <8 x half> %r
}
```
```
llc \
-mtriple=wasm32-unknown-unknown \
-mattr=+simd128,+fp16 \
-o /dev/null \
/private/tmp/wasm-v8f16-insert-only.ll
```
Would lead to
```
Initial selection DAG: %bb.0 'insert_v8f16:'
SelectionDAG has 10 nodes:
t0: ch,glue = EntryToken
t2: v8f16 = WebAssemblyISD::ARGUMENT TargetConstant:i32<0>
t4: i32 = WebAssemblyISD::ARGUMENT TargetConstant:i32<1>
t5: i16 = truncate t4
t6: f16 = bitcast t5
t8: v8f16 = insert_vector_elt t2, t6, Constant:i32<3>
t9: ch = WebAssemblyISD::RETURN t0, t8
Soft promote half operand 1:
t8: v8f16 = insert_vector_elt t2, t6, Constant:i32<3>
SoftPromoteHalfOperand Op #1:
t8: v8f16 = insert_vector_elt t2, t6, Constant:i32<3>
LLVM ERROR: Do not know how to soft promote this operator's operand!
```
Commit: 652e04312e8c5f4fc90ac16be494c3562c111ab9
https://github.com/llvm/llvm-project/commit/652e04312e8c5f4fc90ac16be494c3562c111ab9
Author: Ramon Munoz Jr <ramon.g.munoz.jr at intel.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/include/llvm/MC/MCSubtargetInfo.h
Log Message:
-----------
[MC] Add default ctor to SubtargetSubTypeAliasKV for zero-alias targets- #38762 (#212919)
Fixes a Windows MSVC 2019-only build break from 02da012 ("TableGen: Use
a compact table for CPU aliases", #211952).
That commit added std::array<SubtargetSubTypeAliasKV, NumAliases> to
SubtargetSubTypeKVStorage. SubtargetSubTypeAliasKV uses relative string
offsets, so it is non-copyable and declares only a two-argument
constructor -
no default constructor. In the MSVC 2019 STL, std::array<T, 0> still
holds a
real _Ty _Elems[1] and value-initializes it, so it requires T to be
default-constructible. Any target that defines no ProcessorAlias records
instantiates std::array<..., 0> and fails to compile. MSVC 2022 changed
this
member to a conditionally-empty type, so only MSVC 2019 is affected.
Fix: add a constexpr default constructor.
Co-Authored-By: Claude Opus 5
Signed-off-by: Munoz Jr, Ramon <ramon.g.munoz.jr at intel.com>
Commit: d91967e13ea281e37930cc592d35dfd3c5447a3f
https://github.com/llvm/llvm-project/commit/d91967e13ea281e37930cc592d35dfd3c5447a3f
Author: David Green <david.green at arm.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/GlobalISel/combine-2-icmps-of-0-and-or.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-add-of-sub.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-addv.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-and-or-disjoint-mask.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-anyext-crash.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-avg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-binop-neg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-binop-undef-left-to-zero.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-build-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-fcmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-icmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-cast.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-const-infinite-loop.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-fp-const-lhs.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-int-const-lhs.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-const-fold-barrier-rhs.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-fma.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-fp-rounding.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-itofp-zero.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-unary-int.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-copy.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ctlz-cttz-zero-poison.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-trunc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ext.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-extract-vec-elt.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fabs.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-flog2.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fminimum-fmaximum.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fminnum-fmaxnum.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fneg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fpowi.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fptrunc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-freeze.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fshl.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fshr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fsqrt.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-of-binop-to-icmp-of-0.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-to-lhs-known-bits.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-inttoptr-ptrtoint.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-logic-of-compare.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-mul-to-shl.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-mul.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-mulo-with-2.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-narrow-binop.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-neg-and-one-to-sext-inreg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-op-trunc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-or-and-xor.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-or-of-and.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-overflow.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-int2ptr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-reassociation.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ptrtoint.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-same-op.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-sdiv.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-debugloc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-trunc-sextload.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-shift-immed-mismatch-crash.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-shifts-undef.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-shufflevector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-srem-by-pow2.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-trunc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-udivrem-use-bug.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-umulh-to-lshr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-unary-undef-to-zero.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge-undef.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-use-vector-truncate-order.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-vscale.mir
Log Message:
-----------
[AArch64][GlobalISel] Update combine tests with concrete types. NFC (#213212)
Commit: 88fb1a93f4dd4e2bc5637b5e30ff0fab9edc21a9
https://github.com/llvm/llvm-project/commit/88fb1a93f4dd4e2bc5637b5e30ff0fab9edc21a9
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
Log Message:
-----------
[clang][bytecode][NFC] Use auto* if we can (#213209)
Instead of just auto.
Commit: e1823e8b1778997d12ba947350190af5ee845ca9
https://github.com/llvm/llvm-project/commit/e1823e8b1778997d12ba947350190af5ee845ca9
Author: Nathaniel McCallum <nathaniel at mccallum.life>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/test/CodeGen/X86/fptosi-sat-scalar-f16.ll
M llvm/test/CodeGen/X86/fptosi-sat-scalar.ll
Log Message:
-----------
[X86] Fix miscompile of fptosi.sat.iN.f16 for NaN under avx512fp16 (#210556)
`X86TargetLowering::LowerFP_TO_INT_SAT` incorrectly lowered
`llvm.fptosi.sat.iN.f16` for N = 13, 14, 15, 16 under `avx512fp16`
codegen: NaN inputs produced the destination type's minimum value
instead of the 0 that the intrinsic's documented semantics require.
Vector forms that scalarize through this lowering are affected under
the same condition, applied per element. See the third commit message
for the full root-cause analysis and fix rationale.
---
Assisted-by: Claude (Anthropic)
Assisted-by: Codex (OpenAI)
The investigation, root-cause analysis, fix, and tests in this PR were
developed with substantial AI assistance (Claude), including four
independent AI-assisted review rounds (Codex). I reviewed and take
responsibility for all code, analysis, and claims in this PR, and can
answer questions about the reasoning above.
Commit: bcf20310bdafd37253c6c849cd9bd3ba5b79752f
https://github.com/llvm/llvm-project/commit/bcf20310bdafd37253c6c849cd9bd3ba5b79752f
Author: Jakob Koschel <jakobkoschel at google.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M compiler-rt/test/cfi/anon-namespace.cpp
M compiler-rt/test/cfi/bad-cast.cpp
M compiler-rt/test/cfi/base-derived-destructor.cpp
M compiler-rt/test/cfi/cross-dso-diagnostic.cpp
M compiler-rt/test/cfi/cross-dso/icall/diag.cpp
M compiler-rt/test/cfi/cross-dso/icall/icall-from-dso.cpp
M compiler-rt/test/cfi/cross-dso/icall/icall.cpp
M compiler-rt/test/cfi/cross-dso/simple-fail.cpp
M compiler-rt/test/cfi/cross-dso/target_out_of_bounds.cpp
M compiler-rt/test/cfi/icall/bad-signature.c
M compiler-rt/test/cfi/lit.cfg.py
M compiler-rt/test/cfi/mfcall.cpp
M compiler-rt/test/cfi/multiple-inheritance.cpp
M compiler-rt/test/cfi/nvcall.cpp
M compiler-rt/test/cfi/overwrite.cpp
M compiler-rt/test/cfi/simple-fail.cpp
M compiler-rt/test/cfi/target_uninstrumented.cpp
M compiler-rt/test/cfi/vdtor.cpp
Log Message:
-----------
[ubsan] Test CFI summaries globally (#206434)
Always enable report_error_type=1 and print_summary=1 for CFI tests, and
update existing tests to check for cfi-bad-type. This allows us to
verify summary output comprehensively across the test suite.
This is a prerequisite for the change to the UBSan summary for CFI in
https://github.com/llvm/llvm-project/pull/203341.
Assisted-by: Automated tooling, human reviewed.
Commit: 5eb4272b04144bded2ca1819c2d93b1cd4f1a26b
https://github.com/llvm/llvm-project/commit/5eb4272b04144bded2ca1819c2d93b1cd4f1a26b
Author: Kareem Ergawy <kergawy at nvidia.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/test/Fir/Todo/select_case_with_character.fir
M flang/test/Fir/convert-to-llvm-invalid.fir
M flang/test/Fir/convert-to-llvm.fir
Log Message:
-----------
[flang][CodeGen] Replace fir.select* FIR-to-LLVM patterns with stubs that emit conversion errors (#212978)
`fir.select`, `fir.select_case`, `fir.select_rank`, and
`fir.select_type` are lowered to cf.* earlier in the pipeline
(`--fir-select-ops-conversion` and `--fir-polymorphic-op`). Their
FIR-to-LLVM conversion patterns are dead in a correct pipeline. Replace
them with a single templated stub
`SelectShouldHaveBeenConvertedStub<OP>` that emits `"'fir.<op>' op
should have already been converted"` and fails legalization, so running
`--fir-to-llvm-ir` standalone on stale IR reports a clear diagnostic
instead of "unable to legalize".
`Fir/convert-to-llvm.fir`'s six select* test blocks are removed (the
lowering no longer runs; CF-level coverage lives in
`Fir/SelectOpsConversion/`). `Fir/convert-to-llvm-invalid.fir` gains a
stub-error test per op. `Fir/Todo/select_case_with_character.fir` is
retargeted to check the equivalent diagnostic now emitted by
`--fir-select-ops-conversion`.
Co-Authored-By: Claude Sonnet 4.6 (1M context) <noreply at anthropic.com>
PR Stack:
* https://github.com/llvm/llvm-project/pull/212977
* ▶️ https://github.com/llvm/llvm-project/pull/212978
Co-authored-by: Claude Sonnet 4.6 (1M context) <noreply at anthropic.com>
Commit: 2897ee1dbbbfb2d28ba23105b85697824b4a98a5
https://github.com/llvm/llvm-project/commit/2897ee1dbbbfb2d28ba23105b85697824b4a98a5
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/docs/AMDGPUMemoryModel.md
Log Message:
-----------
[AMDGPU][Docs] Memory Model: Refactor location-order to cover reads (#213044)
This shouldn't change anything semantically, only make the spec
(a) closer to the Vulkan spec, which includes reads in their location-ordered
relation: https://docs.vulkan.org/spec/latest/appendices/memorymodel.html#memory-model-location-ordered
(b) more uniform: this way, the may-see constraints are the same as the vanilla
LLVM constraints, only with all occurrences of "happens-before" replaced by
"location-ordered before".
Commit: a3ae1e0a8d5edaebe9e934e69fc4df84ed89d365
https://github.com/llvm/llvm-project/commit/a3ae1e0a8d5edaebe9e934e69fc4df84ed89d365
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
Log Message:
-----------
[clang][bytecode][NFC] Enforce internal linkage (#213208)
For a struct and a function.
Commit: 21b0fc84c2f5fac1d3f763cfa581762684ad2a89
https://github.com/llvm/llvm-project/commit/21b0fc84c2f5fac1d3f763cfa581762684ad2a89
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
Log Message:
-----------
[clang][bytecode][NFC] Remove redundant casts (#213210)
Commit: 99b3c767c34a04af0a2bbb1fd41bf1b2cb62b331
https://github.com/llvm/llvm-project/commit/99b3c767c34a04af0a2bbb1fd41bf1b2cb62b331
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
M llvm/test/CodeGen/RISCV/branch-on-zero.ll
M llvm/test/Transforms/IndVarSimplify/ARM/code-size.ll
M llvm/test/Transforms/IndVarSimplify/replace-loop-exit-folds.ll
M llvm/test/Transforms/LoopIdiom/basic.ll
M llvm/test/Transforms/LoopStrengthReduce/AArch64/expand-ptrtoaddr-reuse-ptrtoint.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-metadata.ll
M llvm/test/Transforms/LoopVectorize/opaque-ptr.ll
M llvm/unittests/Transforms/Utils/ScalarEvolutionExpanderTest.cpp
Log Message:
-----------
[Analysis] Optimise mul(const, (udiv %n, const)) during SCEV expansion (#212769)
We sometimes see SCEV expansions like this:
%lshr = lshr i64 %n, 2
%shl = shl i64 %lshr, 2
which originate from SCEV mul and udiv expressions:
mul(4, udiv(%n, 4))
that both share the same multiplicand, divisor. The instcombine pass
normally canonicalises this into
%and = and %n, -4
which is the final IR typically seen by the backend. In the case of SCEV
expansion during a pass like the loop vectoriser, instcombine does clean
this up. However, before this is cleaned up it will lead to
over-estimation of costs of SCEV checks, since the shifts are costed
separately and added up. It doesn't seem like there is an easy way to
look at the use count of a SCEV node in the SCEVExpander code. However,
I think for simple cases like this it's always beneficial to fold them
even if there are multiple uses of the SCEV udiv because we're dropping
both shifts.
Commit: 9d1018038c01d12801ccca9da5e6b5589989750a
https://github.com/llvm/llvm-project/commit/9d1018038c01d12801ccca9da5e6b5589989750a
Author: Lukas Sommer <lukas.sommer at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/RegAllocGreedy.cpp
A llvm/test/CodeGen/AMDGPU/greedy-wwm-copy-prologue-assert.mir
Log Message:
-----------
[RegAlloc] Avoid split past block-prologue interference (#209704)
`leaveIntvAtTop` skips the target-specific block prologue when
determining the insertion point.
If the block prologue itself contains an instruction that interferes
with the interval, we must leave the interval before the block,
otherwise we will hit an assertion in `splitLiveThroughBlock`.
---------
Signed-off-by: Lukas Sommer <lukas.sommer at amd.com>
Commit: 28896ffcde9a773361e5d61191ebc2100abf5bcf
https://github.com/llvm/llvm-project/commit/28896ffcde9a773361e5d61191ebc2100abf5bcf
Author: Benedek Kaibas <82393336+benedekaibas at users.noreply.github.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/test/Analysis/dangling-ptr-deref.cpp
M clang/test/Analysis/lifetime-bound.cpp
Log Message:
-----------
[analyzer][NFC] Add test cases for the lifetime test suite (#212254)
During the development of the lifetime checkers I had many important
test cases saved locally and were never imported to the test files of
the checkers. This PR adds those missing test cases to the test files.
By adding these test cases it helps tracking the state of the lifetime
checkers and what improvements they need in order to have better
coverage and reduce the false positive rate.
*AI policy*: During the development I have consulted with claude sonnet
5 to list me test case scenarios it thinks are useful and then reviewed
its feedback and implemented/wrote those test cases by myself. Since
some of the test cases are edge cases I wanted to make sure the
implementation is on the right track.
Commit: 5eb876fcaf460a9ee1dac9490b4b2871674b80ec
https://github.com/llvm/llvm-project/commit/5eb876fcaf460a9ee1dac9490b4b2871674b80ec
Author: Benedek Kaibas <82393336+benedekaibas at users.noreply.github.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/include/clang/StaticAnalyzer/Core/BugReporter/BugReporterVisitors.h
M clang/include/clang/StaticAnalyzer/Core/BugReporter/Z3CrosscheckVisitor.h
M clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/RetainCountChecker/RetainCountDiagnostics.cpp
M clang/lib/StaticAnalyzer/Checkers/VAListChecker.cpp
M clang/lib/StaticAnalyzer/Core/BugReporter.cpp
M clang/lib/StaticAnalyzer/Core/BugReporterVisitors.cpp
M clang/lib/StaticAnalyzer/Core/Z3CrosscheckVisitor.cpp
Log Message:
-----------
[analyzer][NFC] Match the parameters order of getEndPath and finalizeVisitor with VisitNode (#212883)
Currently the ordering of the parameters in `getEndPath` and
`finalizeVisitor` functions does not match the declaration of the
`VisitNode` function. This PR resolves it by reordering the parameters
among these functions to be consistent.
Commit: 2b4f6c42a7dbc8b28c71a334a9fbecce99b68eaf
https://github.com/llvm/llvm-project/commit/2b4f6c42a7dbc8b28c71a334a9fbecce99b68eaf
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx13.cl
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll
Log Message:
-----------
AMDGPU: Add missing mqsad-pk-insts to gfx13 frontend feature map (#213124)
fillAMDGCNFeatureMap omitted mqsad-pk-insts for gfx1310/gfx13-generic,
so clang wrongly rejected __builtin_amdgcn_mqsad_pk_u16_u8 on those
targets even though the backend enables the feature. Add it to the gfx13 case.
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: df81098826f9b45df3cbe2f29af3c44d69d5851a
https://github.com/llvm/llvm-project/commit/df81098826f9b45df3cbe2f29af3c44d69d5851a
Author: Sergey Shcherbinin <sscherbinin at nvidia.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
A llvm/test/tools/llvm-profgen/X86/first-loadable-address.test
M llvm/tools/llvm-profgen/ProfiledBinary.cpp
Log Message:
-----------
[llvm-profgen] Preserve zero-valued first PT_LOAD address (#212258)
FirstLoadableAddress was initialized with if (!FirstLoadableAddress), so
a valid first PT_LOAD at vaddr 0 was treated as unset and overwritten by
a later segment. Track whether the first loadable segment has been seen
instead.
Assisted by GPT-5
Commit: 4fbad31a8adf437e1d0f1307ff4c26a248462b09
https://github.com/llvm/llvm-project/commit/4fbad31a8adf437e1d0f1307ff4c26a248462b09
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
M mlir/test/Conversion/SPIRVToLLVM/arithmetic-ops-to-llvm.mlir
Log Message:
-----------
[mlir][SPIR-V] Add SPIRVToLLVM conversions for FMod and SMod (#206933)
Commit: 814c0e672dfc81ae02a0772879f993a57bdbc1ad
https://github.com/llvm/llvm-project/commit/814c0e672dfc81ae02a0772879f993a57bdbc1ad
Author: Jeremy Johnson <jeremy.johnson at arm.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
Log Message:
-----------
[mlir][tosa] Switch matmul_t output to bf16 from fp16 (#212970)
Note that this implements the TOSA specification change:
https://github.com/arm/tosa-specification/pull/67
---------
Signed-off-by: Jeremy Johnson <jeremy.johnson at arm.com>
Commit: 9b734e25473bc9e299a4b58575b9b0e618925b78
https://github.com/llvm/llvm-project/commit/9b734e25473bc9e299a4b58575b9b0e618925b78
Author: Siyi Xu <siyix at nvidia.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/BasicPtxBuilderInterface.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/BasicPtxBuilderInterface.cpp
M mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir
Log Message:
-----------
[mlir][NVVM] Add memory clobber support to inline_ptx and BasicPtxBui… (#212937)
PTX with memory side effects (stores, atomics, mbarrier operations with
acquire/release semantics) emitted through `nvvm.inline_ptx` lowers to
`llvm.inline_asm` with register constraints only. Without a `~{memory}`
clobber, LLVM may reorder memory accesses across the inline assembly.
There was no way to express the clobber through this op or the
`BasicPtxBuilderInterface` machinery.
This patch adds, as discussed with @grypp:
- A `hasMemoryClobber` interface method (default `false`) on
`BasicPtxBuilderOpInterface`; when it returns `true`, `PtxBuilder`
appends `~{memory}` to the constraints of the generated inline assembly,
after all register constraints and tied indices.
- An opt-in `memory_clobber` boolean attribute (default `false`) on
`nvvm.inline_ptx` exposing this. Existing behavior is unchanged unless
the attribute is set to `true`.
For example:
```mlir
nvvm.inline_ptx "mbarrier.init.b64 [$0], $1;" ro(%p, %c : !llvm.ptr, i32) memory_clobber = true
```
now lowers to inline assembly with constraints `"l,r,~{memory}"`.
Tests: constraint emission with/without the attribute, combination with
predicate (`"l,r,b,~{memory}"`), read-write operands with tied indices
(`"=f,=f,r,r,0,1,~{memory}"`), and the no-operand case (`"~{memory}"`).
The op documentation's first example (mbarrier.init) is updated to show
correct usage.
Commit: 65cd5388148e798798507dd9301e1dfe564f8ab3
https://github.com/llvm/llvm-project/commit/65cd5388148e798798507dd9301e1dfe564f8ab3
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/VPlan/icmp-uniforms.ll
M llvm/test/Transforms/LoopVectorize/bsd_regex.ll
M llvm/test/Transforms/LoopVectorize/extract-last-veclane.ll
M llvm/test/Transforms/LoopVectorize/float-induction.ll
M llvm/test/Transforms/LoopVectorize/forked-pointers.ll
M llvm/test/Transforms/LoopVectorize/histograms.ll
M llvm/test/Transforms/LoopVectorize/if-conversion-nest.ll
M llvm/test/Transforms/LoopVectorize/if-conversion.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-2.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-pred-stores.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization-2.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/loop-scalars.ll
M llvm/test/Transforms/LoopVectorize/multiple-address-spaces.ll
M llvm/test/Transforms/LoopVectorize/non-const-n.ll
M llvm/test/Transforms/LoopVectorize/phi-cost.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-cond.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
M llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
M llvm/test/Transforms/LoopVectorize/reduction.ll
M llvm/test/Transforms/LoopVectorize/runtime-check.ll
M llvm/test/Transforms/LoopVectorize/scalable-inductions.ll
M llvm/test/Transforms/LoopVectorize/scalar_after_vectorization.ll
M llvm/test/Transforms/LoopVectorize/store-shuffle-bug.ll
M llvm/test/Transforms/LoopVectorize/trunc-reductions.ll
M llvm/test/Transforms/LoopVectorize/vector-geps.ll
Log Message:
-----------
[LV][NFC] Remove almost all remaining instcombine passes in RUN lines (#213067)
Commit: 4120b5f5a3770cea9b26063eaca3d18153307961
https://github.com/llvm/llvm-project/commit/4120b5f5a3770cea9b26063eaca3d18153307961
Author: Yingying Wang <3171290993 at qq.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
A llvm/test/CodeGen/RISCV/frame-base-addr-reuse.mir
M llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv32.mir
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/zdinx-large-spill.mir
Log Message:
-----------
[RISCV] Deduplicate frame base address materializations for large stack frames (#211748)
For large stack frames, `eliminateFrameIndex` materializes the frame
base with a `LUI+ADD` sequence for every frame index access. When
multiple accesses share the same 4096-aligned base, this generates
redundant `LUI+ADD` sequences that `MachineLateInstrsCleanup` cannot
eliminate because it operates on individual instructions.
Introduce `PseudoAddUpperImm` to represent the `LUI+ADD` sequence as a
single pseudo instruction during frame index elimination. This enables
`MachineLateInstrsCleanup` to CSE identical frame base computations
within a basic block. The pseudo is expanded back to `LUI+ADD` in
`RISCVPostRAExpandPseudo`.
This patch improves SPEC CPU2026 `cactus` performance by 18% on the
SpaceMit K3 processor.
### Example
Before :
```assembly
lui a0, 4
add a0, a0, sp
fsd fa3, -1976(a0)
lui a0, 4 # redundant
add a0, a0, sp # redundant
ld s10, -160(a0)
```
After :
```assembly
lui a0, 4
add a0, a0, sp
fsd fa3, -1976(a0)
ld s10, -160(a0) # reuses a0
```
Commit: 6f9c189f738d47c7ad80f6bdf928fea441bfa8d6
https://github.com/llvm/llvm-project/commit/6f9c189f738d47c7ad80f6bdf928fea441bfa8d6
Author: Jakob Koschel <jakobkoschel at google.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M compiler-rt/lib/ubsan/ubsan_checks.inc
M compiler-rt/lib/ubsan/ubsan_handlers.cpp
M compiler-rt/lib/ubsan/ubsan_handlers_cxx.cpp
M compiler-rt/test/cfi/anon-namespace.cpp
M compiler-rt/test/cfi/bad-cast.cpp
M compiler-rt/test/cfi/base-derived-destructor.cpp
M compiler-rt/test/cfi/cross-dso-diagnostic.cpp
M compiler-rt/test/cfi/cross-dso/icall/diag.cpp
M compiler-rt/test/cfi/cross-dso/icall/icall-from-dso.cpp
M compiler-rt/test/cfi/cross-dso/icall/icall.cpp
M compiler-rt/test/cfi/cross-dso/simple-fail.cpp
M compiler-rt/test/cfi/cross-dso/target_out_of_bounds.cpp
M compiler-rt/test/cfi/icall/bad-signature.c
M compiler-rt/test/cfi/mfcall.cpp
M compiler-rt/test/cfi/multiple-inheritance.cpp
M compiler-rt/test/cfi/nvcall.cpp
M compiler-rt/test/cfi/overwrite.cpp
M compiler-rt/test/cfi/simple-fail.cpp
M compiler-rt/test/cfi/target_uninstrumented.cpp
M compiler-rt/test/cfi/vdtor.cpp
Log Message:
-----------
[ubsan] Report specific CFI checks in UBSan summaries (#213224)
Instead of reporting generic `cfi-bad-type` in UBSan summaries for CFI
failures, report the specific CFI check kind (e.g., `cfi-vcall`,
`cfi-nvcall`, `cfi-icall`, `cfi-mfcall`, `cfi-derived-cast`,
`cfi-unrelated-cast`).
This is done by splitting CFIBadType into specific error types in
ubsan_checks.inc, and updating the handlers to report the appropriate
ErrorType based on the check kind. The suppression flag name for all of
them remains `cfi` to maintain backward compatibility.
Also replaces cfi-bad-type expectations in the existing tests.
Assisted-by: Automated tooling, human reviewed.
Commit: 5808b2d513d1baa3355d078193006ab9384a4ee3
https://github.com/llvm/llvm-project/commit/5808b2d513d1baa3355d078193006ab9384a4ee3
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/test/CodeGen/SPIRV/atomicrmw-uinc-udec-wrap.ll
Log Message:
-----------
[SPIR-V] Expand atomicrmw nand through compare-exchange (#213217)
Commit: ed0b5c0a428202f29f1477f1dbc31c1ab6083341
https://github.com/llvm/llvm-project/commit/ed0b5c0a428202f29f1477f1dbc31c1ab6083341
Author: Sean Clarke <sclarke at tenstorrent.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
A llvm/test/Transforms/LoopIdiom/cyclic-redundancy-check-memoryssa.ll
Log Message:
-----------
[LoopIdiom] Update MemorySSA when optimizing CRC with lookup table (#213054)
Although the lookup table optimization of CRC loops inserts a `load`
instruction, MemorySSA is not properly updated, and is oblivious to the
new memory access. Insert a memory use immediately after creating the
`load` instruction, and verify MemorySSA at the end of the optimization
if applicable.
Commit: 55418a582c8ced243b4a6eda9b9d7280499af56c
https://github.com/llvm/llvm-project/commit/55418a582c8ced243b4a6eda9b9d7280499af56c
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/include/llvm/Target/GenericOpcodes.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-region.mir
M llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
Log Message:
-----------
GlobalISel: Don't use GISelMatchGenericTypes for floating point opcodes (#212814)
With GISelMatchGenericTypes, AMDGPU had the same input pattern for
G_ATOMICRMW_FADD that checks for v2s16, so the one that is first
in the tablegen table always fires (it was v2f16 in this case).
Should explicitly check for v2f16/v2bf16.
Commit: 81cd5b6217f12ada97e0f1791ba8545120c13230
https://github.com/llvm/llvm-project/commit/81cd5b6217f12ada97e0f1791ba8545120c13230
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M lldb/source/Utility/Args.cpp
M lldb/test/API/commands/register/register_command/TestRegisters.py
Log Message:
-----------
[lldb] Convert generic register names in a case insensitive way (#213001)
Part of #212778.
There are 3 types of register name:
* The primary name, displayed by default.
* An optional alias, for example AArch64 "lr" is also "x30".
* Generic convenience names like "sp", "ra" and so on.
The first two types are handled case insensitively, but generic names
were not. For example:
(lldb) register read RA
error: Invalid register name 'RA'
(lldb) register read ra
lr = 0x0000fffff7e27400
In this change I've fixed that.
This does close a workaround for #212778, where you could get to the
actual x86_64 "sp" by using "sP". However, this is only known to work on
Linux, and other architectures are negatively impacted by the bug so I'm
fixing it.
Commit: 303ec27d8b231f9fb3078333894fe9813761e566
https://github.com/llvm/llvm-project/commit/303ec27d8b231f9fb3078333894fe9813761e566
Author: antoine moynault <antoine.moynault at linaro.org>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/include/llvm/ProfileData/SampleProfReader.h
M llvm/lib/Transforms/IPO/SampleProfile.cpp
M llvm/lib/Transforms/IPO/SampleProfileMatcher.cpp
M llvm/unittests/ProfileData/SampleProfTest.cpp
Log Message:
-----------
Revert "[ProfileData] Implement contains in SampleProfileNameTable (NFC)" (#213231)
Reverts llvm/llvm-project#211995
Broke arm 32-bit buildbots (narrowing conversion uint64_t -> size_t)
Commit: 9621bedd8a7a09c5e48a12697ff2d0463067e341
https://github.com/llvm/llvm-project/commit/9621bedd8a7a09c5e48a12697ff2d0463067e341
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M lldb/include/lldb/Core/Module.h
M lldb/source/Core/Module.cpp
Log Message:
-----------
[lldb] Only preload a Module's symbols once (#213094)
Creating several targets for the same file concurrently could deadlock.
Targets share Module objects. Therefore, each concurrent
`SBDebugger::CreateTarget()` call creates a `PreloadSymbols()` task for
the *same* Module. The thread pool running those tasks can pick up a
duplicate preload task for the same Module. The mutex used by the Module
is recursive, so the thread starts the task again, enters the same
`std::call_once` and deadlocks.
Preloading only needs to happen once: it does work taht a later lookup
would do anyway. If it's already in progress, skip it. This deduplicate
the task that causes the deadlock.
At desk, this fixes a timeout in
`api/multiple-targets/TestMultipleTargets.py`, roughly 1/40 runs. To
reproduce the issue, I shrunk the thread pool to 2 threads, which makes
it always timeout.
Commit: dcce9de575fdb9f652f38c2ba1b62f4a4da66515
https://github.com/llvm/llvm-project/commit/dcce9de575fdb9f652f38c2ba1b62f4a4da66515
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.td
M clang/test/CodeGen/amdgpu-builtin-is-invocable.c
M clang/test/CodeGen/amdgpu-builtin-processor-is.c
M clang/test/CodeGenCXX/dynamic-cast-address-space.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx13.cl
A clang/test/SemaOpenCL/builtins-amdgcn-cvt-sr-pk-bf16-f32-err.cl
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.pk.bf16.ll
M llvm/test/MC/AMDGPU/gfx950-unsupported.s
Log Message:
-----------
AMDGPU: Give v_cvt_sr_pk_bf16_f32 its own subtarget feature (#213150)
v_cvt_sr_pk_bf16_f32 was gated on bf16-cvt-insts, but that feature is
also present on gfx950 where the (non-sr) v_cvt_pk_bf16_f32 was first
added. The stochastic-rounding v_cvt_sr_pk_bf16_f32 was only added
for gfx1250 and has no gfx950 encoding, so it would mis-select and
later hit the "Invalid opcode" assert. Introduce
cvt-sr-pk-bf16-f32-inst, currently added to gfx13 and 125*
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: 275365f4f94a6e66b933d3d62cb62ac081daa3a9
https://github.com/llvm/llvm-project/commit/275365f4f94a6e66b933d3d62cb62ac081daa3a9
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
Log Message:
-----------
GlobalISel: Fix lowerMergeValues when dst type is float (#212795)
Lowering is done in the integer domain. Similar to the type
mismatch when dst is a pointer, make a bitcast when dst is float.
Commit: 81a8451de62458a29dd5cef6d0c52d0a6271ca30
https://github.com/llvm/llvm-project/commit/81a8451de62458a29dd5cef6d0c52d0a6271ca30
Author: yingopq <115543042+yingopq at users.noreply.github.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsCallingConv.td
M llvm/lib/Target/Mips/MipsRegisterInfo.cpp
A llvm/test/CodeGen/Mips/write_register_gp.ll
Log Message:
-----------
[Mips] Fix $gp was restored when used as global register variable (#201778)
The function `eliminateDeadMI` would check `if (MRI.isReserved(Reg))`,
now we only set GP to reserved when `!Subtarget.isABICalls()`. So
`eliminateDeadMI` delete the `move $gp, $4`. And we would restore $gp
after instr selection through `$gp_64 = LD $sp_64, 8`.
Check the module metadata `llvm.named.register.$28` to detect if $28 is
used as global register. Then append new conditon when set $gp to
reserverd status and return CalleeSavedRegs without $gp.
Fix #176546.
Commit: ea56c331a6afe1334eb3ce3b1bf9974079fb79c3
https://github.com/llvm/llvm-project/commit/ea56c331a6afe1334eb3ce3b1bf9974079fb79c3
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/LocalStackSlotAllocation.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/OptimizePHIs.cpp
M llvm/lib/CodeGen/StackColoring.cpp
M llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/diverged-entry-basic-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/diverged-entry-basic.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_cond.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
M llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-usub_cond.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-usub_sat.ll
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/issue130120-eliminate-frame-index.ll
M llvm/test/CodeGen/AMDGPU/issue139317-bad-opsel-reg-sequence-fold.ll
M llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
M llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
M llvm/test/CodeGen/AMDGPU/memset-pattern.ll
M llvm/test/CodeGen/AMDGPU/sgpr-scavenge-fi-stack-id.ll
M llvm/test/CodeGen/AMDGPU/structurize-hoist.ll
M llvm/test/CodeGen/AMDGPU/valu-i1.ll
M llvm/test/CodeGen/ARM/O3-pipeline.ll
M llvm/test/CodeGen/LoongArch/jr-without-ra.ll
M llvm/test/CodeGen/LoongArch/opt-pipeline.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
M llvm/test/CodeGen/SPIRV/llc-pipeline.ll
M llvm/test/CodeGen/Thumb2/mve-blockplacement.ll
M llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
M llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll
M llvm/test/CodeGen/X86/2011-09-14-valcoalesce.ll
Log Message:
-----------
[MachineLICM] Use `RegisterClassInfo::getRegPressureSetLimit` (#211715)
This recommits #119826, which taught `MachineLICM` to use
`RegisterClassInfo` when computing register pressure limits so
reserved registers are accounted for (#118787).
The original change was reverted by eeac0ff because it increased
compile time by causing repeated `RegisterClassInfo` computations.
This PR is based on #210826, in which `MachineRegisterClassInfo`
analysis pass was added. `MachineRegisterClassInfo` is required
by `MachineLICM` now, but the intervening machine passes that do
not affect `RegisterClassInfo` now preserve it, so the analysis
is reused instead of recomputed.
Assisted-by: TRAE CLI (GPT-5.5)
Commit: 81f89bb526ce322cb4c29196e3c29472bad32e65
https://github.com/llvm/llvm-project/commit/81f89bb526ce322cb4c29196e3c29472bad32e65
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-wide-add.ll
M llvm/test/CodeGen/AArch64/vector-absolute-difference.ll
Log Message:
-----------
[LLVM][CodeGen][SVE] Use pairwise instruction for partial_reduce_[s/u]mla. (#212772)
Commit: 136347be7aac1614000a9072d794d91ca16aa4f1
https://github.com/llvm/llvm-project/commit/136347be7aac1614000a9072d794d91ca16aa4f1
Author: Manasij Mukherjee <manasijm at nvidia.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
Log Message:
-----------
[TableGen] Speed up intrinsic lookups with DenseMap (NFC) (#213198)
Store in DenseMap, avoids linear lookups.
Speeds up NVPTX -gen-dag-isel and -gen-instr-info by 10%.
RISCV shows similar gains.
Neutral or marginally beneficial for other targets.
Commit: 8db13de265a5f12d49147930da6d16a3ad7b40e3
https://github.com/llvm/llvm-project/commit/8db13de265a5f12d49147930da6d16a3ad7b40e3
Author: Luke Lau <luke at igalia.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Remove redundant x && (y && x) -> x && y combine (#213219)
It can be subsumed by making the combine above commutative. In theory
this isn't NFC as it changes the order, in practice it doesn't make a
difference.
Commit: 6ebd9e1a12235fdc42e3e7b157678e6711af9c62
https://github.com/llvm/llvm-project/commit/6ebd9e1a12235fdc42e3e7b157678e6711af9c62
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/RTBridge/Calls.h
M llvm/include/llvm/ExecutionEngine/Orc/RTBridge/SPS/Calls.h
M llvm/unittests/ExecutionEngine/Orc/SPSCallersTest.cpp
Log Message:
-----------
[ORC] Add VoidVoid and IntVoid Callers, with tests. (#213211)
Add rt::VoidVoidCaller (void()) and rt::IntVoidCaller (int64_t())
runtime-agnostic interfaces and their rt::sps implementations, targeting
the orc_rt_ci_sps_call_void_void and orc_rt_ci_sps_call_int_void
controller-interface wrappers. Both are experimental and may be removed.
Extend SPSCallersTest to cover the new callers. VoidVoidCaller is the
first caller instantiated with a void result type, which exposed a
latent bug in sps::Caller::callAsync: its result handler declared a
CalleeRetT parameter, ill-formed when CalleeRetT is void. It now
special-cases void via `if constexpr`.
Commit: 5aec353bd686dbca51755e772971c65ee6ae70f6
https://github.com/llvm/llvm-project/commit/5aec353bd686dbca51755e772971c65ee6ae70f6
Author: Folkert de Vries <folkert at folkertdev.nl>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/test/CodeGen/PowerPC/copysignl.ll
Log Message:
-----------
[NFC][PowerPC] add more `copysign` tests (#213236)
Commit: 090b6569b6ed5cabfc84284542c5ce8b51735015
https://github.com/llvm/llvm-project/commit/090b6569b6ed5cabfc84284542c5ce8b51735015
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M libcxx/include/__memory/array_cookie.h
M libcxx/include/__memory/unique_ptr.h
M libcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.class/unique.ptr.observers/assert.subscript.pass.cpp
Log Message:
-----------
[libc++] Make __has_array_cookie a variable template (#212767)
Using variable templates is slightly faster to compile and more
readable, so we might as well use them.
Commit: e147e5b7d029651554c24ecaaa4086a7cc74e90a
https://github.com/llvm/llvm-project/commit/e147e5b7d029651554c24ecaaa4086a7cc74e90a
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M libcxx/include/__atomic/clear_padding.h
Log Message:
-----------
[libc++] Simplify clear_padding.h a bit (#212426)
Commit: 3a809f644c863a17ac665e19d7dcbf7209688d18
https://github.com/llvm/llvm-project/commit/3a809f644c863a17ac665e19d7dcbf7209688d18
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M libcxx/test/libcxx/clang_tidy.sh.py
A libcxxabi/.clang-tidy
Log Message:
-----------
[libc++abi] Add a clang-tidy config and test (#207324)
This essentially copies the `.clang-tidy` file from libc++ into
libc++abi, except that the naming conventions are updated to not add
underscores and some checks are disabled that don't pass currently. They
will be fixed in follow-ups.
Commit: bcddf2a29177380c62481ee25362064f99ff07d3
https://github.com/llvm/llvm-project/commit/bcddf2a29177380c62481ee25362064f99ff07d3
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/reduction-fadd-reassoc.ll
Log Message:
-----------
[SLP][NFC]Add some extra tests for reductions, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/213257
Commit: 0a1f0aafed6dfce910e18090bfd408838b9a727a
https://github.com/llvm/llvm-project/commit/0a1f0aafed6dfce910e18090bfd408838b9a727a
Author: PushkarSingh <149073046+iitianpushkar at users.noreply.github.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/include/clang/Analysis/AnyCall.h
A clang/unittests/Analysis/AnyCallTest.cpp
M clang/unittests/Analysis/CMakeLists.txt
Log Message:
-----------
[clang][Analysis] Add argument accessors to clang::AnyCall (#212934)
Add APIs to `clang::AnyCall` for accessing expression-backed call
arguments.
`AnyCall` already exposes formal parameters through `parameters()`,
`param_begin()`, `param_end()`, `param_size()`, and `param_empty()`.
This adds the corresponding argument-side helpers:
- `arguments()`
- `arg_begin()`
- `arg_end()`
- `arg_size()`
- `arg_empty()`
- `getArg()`
This lets clients reuse `AnyCall` for callee/argument inspection instead
of
open-coding argument extraction.
Prequel PR to #206337
Commit: e44068cc129912c88dcdeae0d1b5dc5937eb1059
https://github.com/llvm/llvm-project/commit/e44068cc129912c88dcdeae0d1b5dc5937eb1059
Author: Karim Alweheshy <karim.alweheshy at gmail.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M lld/MachO/ObjC.cpp
M lld/test/MachO/objc-category-merging-minimal.s
M lld/test/MachO/objc-category-merging-swift.s
Log Message:
-----------
[lld][MachO] Preserve class-address addends in ObjC category merging (#211431)
Mach-O category merging can encounter Swift class references as an
enclosing
metadata symbol plus a non-zero addend after LTO removes the exact
class-address alias. For example, a category can refer to a `CMf` symbol
plus
the offset of the class object within that metadata record.
`tryGetSymbolAtIsecOffset()` previously resolved such a relocation to
the
enclosing symbol and discarded the residual addend. `getClassRo()` then
read
the class layout at the wrong address. For valid Swift metadata this can
return
null; before the defensive check in the first commit the linker
dereferenced
that result and crashed, while the check alone safely skipped a category
that
could have been merged.
Preserve the class reference as a symbol and residual addend throughout:
- category grouping;
- class and metaclass RO-data lookup;
- source-language detection; and
- relocations synthesized for merged categories.
An exact symbol at the target address is still preferred. When no exact
alias
survives, retain the offset from the closest containing symbol. The
defensive
checks remain in place for genuinely incomplete or unsupported metadata.
The Swift regression now omits the exact class-address alias and points
the
category classlist directly into the enclosing metadata record, matching
the
shape observed after ThinLTO.
Testing:
- Release + assertions AArch64 LLVM/LLD build
- focused `llvm-lit` coverage for the alias-free Swift metadata and
missing-metadata cases
- full Swift 6 application link with `-objc_category_merging`
The application result is integration evidence for correctness and
folding
coverage
Commit: a6a1cb05d247f1fc4414bb6d789f390b2554eac7
https://github.com/llvm/llvm-project/commit/a6a1cb05d247f1fc4414bb6d789f390b2554eac7
Author: Sergey Semenov <sergey.semenov at intel.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M libsycl/src/detail/global_objects.hpp
Log Message:
-----------
[libsycl] Add missing header include to global_objects.hpp (#213020)
Fixes a build error observed on Windows.
Commit: c29bcd45ddd96c5d3ea0d5f7de051b5174966a3b
https://github.com/llvm/llvm-project/commit/c29bcd45ddd96c5d3ea0d5f7de051b5174966a3b
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M lldb/source/Plugins/Platform/Windows/PlatformWindows.cpp
Log Message:
-----------
[lldb][Windows] Don't cut the loader helper off after 250ms (#213010)
`LoadLibraryW` runs on the debuggee with a timeout of 250ms (the
default). On a loaded machine (in CI), this timeout is reached quite
often, causing tests failures.
This patch gives both loader helpers an explicit timeout of 5s (clamped
to half the overall timeout so the two stay consistent).
Commit: e84daa62201acd161c6b77375eb26d0b0ac63ed2
https://github.com/llvm/llvm-project/commit/e84daa62201acd161c6b77375eb26d0b0ac63ed2
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/session_helpers.py
M lldb/test/API/tools/lldb-dap/console/TestDAP_console.py
M lldb/test/API/tools/lldb-dap/console/TestDAP_redirection_to_console.py
M lldb/test/API/tools/lldb-dap/restart/TestDAP_restart.py
M lldb/test/API/tools/lldb-dap/restart/TestDAP_restart_console.py
Log Message:
-----------
[lldb-dap] Migrate console and restart tests (#213019)
Migrated Tests
- TestDAP_console.py
- TestDAP_redirection_to_console.py
- TestDAP_restart.py
- TestDAP_restart_console.py
Commit: b4efecb0379353d51a172209193e500b6cb2a0f2
https://github.com/llvm/llvm-project/commit/b4efecb0379353d51a172209193e500b6cb2a0f2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx13.cl
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.msad.u8.ll
Log Message:
-----------
AMDGPU: Add missing msad-insts to gfx13 frontend feature map (#213122)
fillAMDGCNFeatureMap omitted msad-insts for gfx1310/gfx13-generic, so
clang wrongly rejected __builtin_amdgcn_msad_u8 on those targets even
though the backend enables the feature (FeatureGFX9 generation,
inherited through FeatureGFX13). Add it to the gfx13 case.
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: 3f9b96996cac75b960adf84f5722afe48c20b480
https://github.com/llvm/llvm-project/commit/3f9b96996cac75b960adf84f5722afe48c20b480
Author: Zmicier Prybysh <zprybysh at baylibre.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/ConvertConv2DToImg2Col.cpp
M mlir/test/Dialect/Linalg/convert-conv2d-to-img2col.mlir
Log Message:
-----------
[mlir][linalg] Support non-unit dilations in im2col decomposition (#208424)
The im2col patterns for conv_2d_nhwc_hwcf, conv_2d_nchw_fchw and
conv_2d_nhwc_fhwc avoided non-unit dilations, but the restriction
doesn't seem to be fundamental: dilation only affects the gather step,
which can fold it into its indexing map. Generalize the convolved index
expression from `oh * stride + fh` to `oh * stride + fh * dilation` and
drop the match failures.
Verified by comparing the results of a dilated convolution lowered
directly to loops against the im2col decomposition with mlir-runner.
Assisted-By: Claude Code (for generating tests).
Commit: 2f30bd168ccb47a82a25faba92cae4d6d0b47f0d
https://github.com/llvm/llvm-project/commit/2f30bd168ccb47a82a25faba92cae4d6d0b47f0d
Author: Michael G. Kazakov <mike.kazakov at gmail.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M libcxx/test/std/algorithms/alg.nonmodifying/alg.adjacent.find/pstl.adjacent_find.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.adjacent.find/pstl.adjacent_find_pred.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.find.first.of/pstl.find_first_of.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.find.first.of/pstl.find_first_of_pred.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/mismatch/pstl.mismatch.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/mismatch/pstl.mismatch_pred.pass.cpp
Log Message:
-----------
[libc++][NFC] Make size_t -> int conversions explicit in a few PSTL tests (#213145)
The implicit truncating conversions that were introduced in some PSTL
tests are causing warnings on MSVC. This PR fixes that.
See
https://github.com/llvm/llvm-project/pull/212366#discussion_r3679252259
for more details.
Commit: 4dc60bbb98a8531841383c51a1b7e65a0ec1d05e
https://github.com/llvm/llvm-project/commit/4dc60bbb98a8531841383c51a1b7e65a0ec1d05e
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/tools/llvm-calc-occupancy/CMakeLists.txt
Log Message:
-----------
[Build] Fix llvm-calc-occupancy link errors when using LLVM_LINK_LLVM_DYLIB. (#213262)
Commit: 95ee221ea8fade17576845f12df8c2cd26f85aa5
https://github.com/llvm/llvm-project/commit/95ee221ea8fade17576845f12df8c2cd26f85aa5
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
R flang/docs/FIRArrayOperations.md
M flang/docs/HighLevelFIR.md
M flang/docs/ReleaseNotes.md
M flang/docs/index.md
M flang/include/flang/Optimizer/Builder/MutableBox.h
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/test/Fir/fir-ops.fir
M flang/test/Fir/invalid.fir
M flang/test/HLFIR/inline-elemental.fir
M flang/test/Transforms/loop-versioning.fir
M flang/test/Transforms/simplifyintrinsics.fir
Log Message:
-----------
[flang] Delete the legacy array-value operations from FIR (#213159)
Nothing in flang has produced fir.array_load, fir.array_fetch,
fir.array_update, fir.array_modify, fir.array_access, fir.array_amend,
or fir.array_merge_store since the legacy (non-HLFIR) expression
lowering was deleted (#210385, #210621, #210639, #210873), and the
array-value-copy pass that legalized them is gone (#211816, #212643).
Delete the operations and the surface that existed only for them:
- FIROps.td: the "Array value operations" section including the
copy-in/copy-out design comment; FIROps.cpp: the ops verifiers, effects
and getExtents. fir.array_coor is unrelated and stays, as does the
validTypeParams helper shared with fir.pack_array.
- Tests: the ops roundtrip/verifier blocks in fir-ops.fir and
invalid.fir; scaffolding rewrites in inline-elemental.fir (store via
hlfir.designate; hlfir.apply-in-do_loop coverage preserved),
loop-versioning.fir @test4 (the versioned loops are untouched), and
simplifyintrinsics.fir (inert copy-back loops dropped; no CHECK lines
affected).
- Docs: FIRArrayOperations.md (+ the index.md toctree line); past-tense
updates in HighLevelFIR.md; a stale comment in MutableBox.h; a
release-note entry recording the removal for downstream projects.
FIRLangRef is generated from FIROps.td and follows automatically.
Assisted-by: AI
Commit: 315bbbc18c45079bab55575325b4d4f79aa9a4cd
https://github.com/llvm/llvm-project/commit/315bbbc18c45079bab55575325b4d4f79aa9a4cd
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
M llvm/utils/gn/secondary/llvm/test/BUILD.gn
A llvm/utils/gn/secondary/llvm/tools/llvm-calc-occupancy/BUILD.gn
Log Message:
-----------
[gn] port b11722f1d3bd5de (llvm-calc-occupancy) (#213266)
Commit: f79a8888eb831238423362d004739683e2a20d93
https://github.com/llvm/llvm-project/commit/f79a8888eb831238423362d004739683e2a20d93
Author: Zorojuro <sawantsukumar at gmail.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M libc/src/__support/FPUtil/CMakeLists.txt
M libc/src/__support/FPUtil/dyadic_float.h
M libc/src/__support/FPUtil/float128.h
M libc/test/src/__support/FPUtil/float128_test.cpp
Log Message:
-----------
[libc] Fix float128-to-integer conversion UB (#211593)
https://github.com/llvm/llvm-project/pull/200565#discussion_r3643991194
Fixes the recent issue pointed out in the above comment
about undefined behavior for float128 in the case of extremely large
values and extremely small values.
Commit: f5ffd86a9bd6dd9327669448c3b604ce9b658941
https://github.com/llvm/llvm-project/commit/f5ffd86a9bd6dd9327669448c3b604ce9b658941
Author: Nerixyz <nerixdev at outlook.de>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M lldb/source/Symbol/Variable.cpp
M lldb/test/API/functionalities/scripted_frame_provider/TestScriptedFrameProvider.py
Log Message:
-----------
[lldb] Treat synthetic variables as always in scope (#204177)
When the variables in scope are requested, synthetic variables wouldn't
be returned, because `Variable::IsInScope` would return false. With this
PR, we return true for synthetic variables.
There's still one inconsistency between `frame var` and
`SBFrame::GetVariables` where `frame var` shows "re-exported" variables
from real frames (here: `variable_in_main`). Note that
`IsSyntheticValueType` returns false for `variable_in_main`.
Commit: 5df5e8d9fd6386d99c37cb72ea92c99819c801bc
https://github.com/llvm/llvm-project/commit/5df5e8d9fd6386d99c37cb72ea92c99819c801bc
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
A llvm/test/CodeGen/AMDGPU/arbitrary-fp-from-float-fp8-f16-hw.ll
A llvm/test/CodeGen/AMDGPU/arbitrary-fp-to-float-fp8-hw.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.mir
M llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
Log Message:
-----------
[AMDGPU] Add custom lowering of llvm.convert.from.arbitrary.fp for FP8 (#194144)
Map conversions from FP8 source formats to v_cvt_{,pk_}f32_{fp8,bf8} and v_cvt_{pk_}f16_{fp8,bf8} HW instructions.
Commit: d73beb2ee622eb1aaa13a4bdbe25799031f647f8
https://github.com/llvm/llvm-project/commit/d73beb2ee622eb1aaa13a4bdbe25799031f647f8
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/Builder/FIRBuilder.h
R flang/include/flang/Optimizer/Builder/Runtime/Ragged.h
M flang/include/flang/Runtime/ragged.h
M flang/lib/Optimizer/Builder/CMakeLists.txt
M flang/lib/Optimizer/Builder/FIRBuilder.cpp
R flang/lib/Optimizer/Builder/Runtime/Ragged.cpp
R flang/unittests/Optimizer/Builder/Runtime/RaggedTest.cpp
M flang/unittests/Optimizer/CMakeLists.txt
Log Message:
-----------
[flang] Delete the unused ragged-array runtime builders (#213160)
The ragged-array machinery served the legacy FORALL mask temporaries,
whose lowering was removed with the legacy expression lowering (#210639,
#210873) and the array-value-copy pass (#212643). The builders
(fir::runtime::genRaggedArrayAllocate/Deallocate) and the
getRaggedArrayHeaderType helper have no compiler callers left; only
their own unit test exercised them. Delete the builders, the helper, and
the unit test.
The flang-rt runtime entry points
(RaggedArrayAllocate/RaggedArrayDeallocate in
flang-rt/lib/runtime/ragged.cpp and their declarations in
flang/include/flang/Runtime/ragged.h) are ABI and remain.
Assisted-by: AI
Commit: f6b3f9399e98ef8b79388176e94c910d67669e1f
https://github.com/llvm/llvm-project/commit/f6b3f9399e98ef8b79388176e94c910d67669e1f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
DAG: Use poison for some load/store offsets in legalizer (#167756)
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 7d5dd438b286d4812a8d2e753262cb6db1c3be51
https://github.com/llvm/llvm-project/commit/7d5dd438b286d4812a8d2e753262cb6db1c3be51
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/struct_ucred.h
M libc/include/sys/socket.yaml
Log Message:
-----------
[libc] Add 'struct ucred' definition. (#213152)
This is a Linux extension that allows to obtain credentials of a peer
process connected to a socket, e.g. via passing `SO_PEERCRED` to
`getsockopt` function.
Commit: c325d6fcb6db298f681ae1c450b89b4c255fb3ce
https://github.com/llvm/llvm-project/commit/c325d6fcb6db298f681ae1c450b89b4c255fb3ce
Author: Bryth <matteo.rizza-murgier at sipearl.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M mlir/test/Dialect/Complex/canonicalize.mlir
Log Message:
-----------
[mlir][complex] Fix canonicalize tests (#213259)
Remove trailing spaces and double line breaks, fix variable
re-definitions, make variables match regex consistent.
Commit: fd7993ea2dcc76f915da1baf1b36f5cd560722a8
https://github.com/llvm/llvm-project/commit/fd7993ea2dcc76f915da1baf1b36f5cd560722a8
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/aarch64/headers.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/riscv/headers.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/config/linux/x86_64/headers.txt
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-macros/CMakeLists.txt
M libc/include/llvm-libc-macros/linux/CMakeLists.txt
A libc/include/llvm-libc-macros/linux/sys-statfs-macros.h
A libc/include/llvm-libc-macros/sys-statfs-macros.h
A libc/include/sys/statfs.yaml
M libc/src/sys/CMakeLists.txt
A libc/src/sys/statfs/CMakeLists.txt
A libc/src/sys/statfs/fstatfs.h
A libc/src/sys/statfs/linux/CMakeLists.txt
A libc/src/sys/statfs/linux/fstatfs.cpp
A libc/src/sys/statfs/linux/statfs.cpp
A libc/src/sys/statfs/statfs.h
M libc/test/src/sys/CMakeLists.txt
A libc/test/src/sys/statfs/CMakeLists.txt
A libc/test/src/sys/statfs/linux/CMakeLists.txt
A libc/test/src/sys/statfs/linux/fstatfs_test.cpp
A libc/test/src/sys/statfs/linux/statfs_test.cpp
Log Message:
-----------
[libc] Add <sys/statfs.h> header and entrypoints. (#213108)
Implement `statfs` and `fstatfs` functions on Linux.
We already have `struct statfs` and syscall wrappers defined (to
implement POSIX `<sys/statvfs.h>`). Use them to provide Linux-specific
functions as well.
Commit: 8719d58faf6fb5780bf44fc89df72c951f381f5b
https://github.com/llvm/llvm-project/commit/8719d58faf6fb5780bf44fc89df72c951f381f5b
Author: Sean Clarke <sclarke at tenstorrent.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
M llvm/test/Transforms/LoopIdiom/cyclic-redundancy-check.ll
Log Message:
-----------
[LoopIdiom] Fix miscompile for big-endian sub-byte CRC (#213040)
The Sarwate lookup table optimization shifts the top bits of the
`Indexer` down to the low byte before indexing into the table. Though
uncommon, if the CRC has a sub-byte width, the top bits of `Indexer`
must be shifted *up* to align with the low byte, but this is never
accounted for. Shift `Indexer` either right *or* left depending on CRC
bitwidth.
Commit: 1505b3e83d2810fbff92b645a1b67e18918900c0
https://github.com/llvm/llvm-project/commit/1505b3e83d2810fbff92b645a1b67e18918900c0
Author: Kseniya Tikhomirova <kseniya.tikhomirova at intel.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M libsycl/src/detail/context_impl.cpp
M libsycl/src/detail/context_impl.hpp
M libsycl/src/detail/platform_impl.cpp
M libsycl/src/detail/queue_impl.cpp
M libsycl/unittests/mock/helpers.cpp
M libsycl/unittests/mock/helpers.hpp
M libsycl/unittests/mock/mock.cpp
Log Message:
-----------
[libsycl] Add liboffload context handler to default context (#213249)
Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
Commit: 3e65a09adcd9a57bf495b73e2b96c77b13ae7779
https://github.com/llvm/llvm-project/commit/3e65a09adcd9a57bf495b73e2b96c77b13ae7779
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M offload/test/jit/empty_kernel_lvl1.c
M offload/test/jit/empty_kernel_lvl2.c
Log Message:
-----------
[ClangLinkerWrapper][SPIRV] Fix embed bitcode option (#213137)
We need to pass the right linker option and not try to containerize it.
Fixes two OpenMP offload JIT tests, the other has some front end assert
I will look at.
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Commit: 7b8d7c9d687b177f0b61ef71992b5ed847334eba
https://github.com/llvm/llvm-project/commit/7b8d7c9d687b177f0b61ef71992b5ed847334eba
Author: Arun Thangamani <arun.thangamani at intel.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M mlir/lib/Dialect/X86/Transforms/VectorContractToAMXDotProduct.cpp
M mlir/test/Dialect/X86/AMX/vector-contract-to-tiled-dp.mlir
Log Message:
-----------
[mlir][x86] Adds extra pattern for AMX lowering (#213228)
This patch add extra pattern for `AMX` lowering, where the `M`, `N`, and
`K` loops are removed as part of `Canonicalization `
Commit: 25aec49d40d52ab730d360fc362ecd8b46e00db5
https://github.com/llvm/llvm-project/commit/25aec49d40d52ab730d360fc362ecd8b46e00db5
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/CodeGen/WindowScheduler.h
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.h
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
A llvm/test/CodeGen/AArch64/sms-analyzeloop-remarks.mir
A llvm/test/CodeGen/AArch64/sms-schedule-remark.mir
M llvm/test/CodeGen/Hexagon/swp-ws-exp.mir
M llvm/test/CodeGen/Hexagon/swp-ws-fail-0.mir
M llvm/test/CodeGen/PowerPC/sms-remark.ll
Log Message:
-----------
[llvm][AArch64] Add pipeliner remarks (#213157)
Commit: afd6d6eeb013c08a9d7c682d01c6a2152023c9cd
https://github.com/llvm/llvm-project/commit/afd6d6eeb013c08a9d7c682d01c6a2152023c9cd
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCompatibilityAnalysis.h
M llvm/test/Transforms/SLPVectorizer/X86/fmuladd-copyable-mul-part.ll
Log Message:
-----------
[SLP]Support copyables in the fmuladd multiplicand
Allow a non-fmuladd lane V to be modeled as fmuladd(V, 1.0, -0.0),
which equals V for every V (V * 1.0 is exact, and V + -0.0 preserves
signed zeros). The addend modeling is still preferred; the
multiplicand is used as a fallback when the addend operand does not
allow vectorization. The copyable position is kept as an operand
index in InstructionsState, so other operands can be modeled later.
Reviewers: hiraditya, RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/212808
Commit: 55923bf5df245f44083c096914da4a005ba5d6a8
https://github.com/llvm/llvm-project/commit/55923bf5df245f44083c096914da4a005ba5d6a8
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/CStringChecker.cpp
M clang/test/Analysis/string-search-modeling.c
Log Message:
-----------
[analyzer] Don't fold wide string literals in CStringChecker (#213281)
`getStringRefAtRegion()` read literal contents via
`StringLiteral::getBytes()`, which returns the literal's raw trailing
storage. For wide literals (`u""`, `U""`, `L""`) that storage holds the
code units in *host* byte order: `LiteralSupport` writes them through
`reinterpret_cast<UTF16*>/<UTF32*>`, and `StringLiteral::getCodeUnit()`
reads them back the same way. Interpreting those bytes as a target byte
string made the strchr-family constant folding depend on the endianness
of the machine running the analyzer.
Bail out on `getCharByteWidth() != 1`, matching the contract the rest of
the checker already relies on -- `evalStrcmpCommon()` uses
`getString()`, which asserts it. Wide literals now fall back to the
symbolic-offset path and keep both branches.
Fixes up #212124
Inspired from:
https://github.com/llvm/llvm-project/pull/212124#issuecomment-5143598098
Supersedes #213279
Commit: 96ca8cf60e0d2ee992f714dbe6ebc4cd079e50a7
https://github.com/llvm/llvm-project/commit/96ca8cf60e0d2ee992f714dbe6ebc4cd079e50a7
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/LocalStackSlotAllocation.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/OptimizePHIs.cpp
M llvm/lib/CodeGen/StackColoring.cpp
M llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/diverged-entry-basic-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/diverged-entry-basic.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_cond.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
M llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-usub_cond.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-usub_sat.ll
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/issue130120-eliminate-frame-index.ll
M llvm/test/CodeGen/AMDGPU/issue139317-bad-opsel-reg-sequence-fold.ll
M llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
M llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
M llvm/test/CodeGen/AMDGPU/memset-pattern.ll
M llvm/test/CodeGen/AMDGPU/sgpr-scavenge-fi-stack-id.ll
M llvm/test/CodeGen/AMDGPU/structurize-hoist.ll
M llvm/test/CodeGen/AMDGPU/valu-i1.ll
M llvm/test/CodeGen/ARM/O3-pipeline.ll
M llvm/test/CodeGen/LoongArch/jr-without-ra.ll
M llvm/test/CodeGen/LoongArch/opt-pipeline.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
M llvm/test/CodeGen/SPIRV/llc-pipeline.ll
M llvm/test/CodeGen/Thumb2/mve-blockplacement.ll
M llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
M llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll
M llvm/test/CodeGen/X86/2011-09-14-valcoalesce.ll
Log Message:
-----------
Revert "[MachineLICM] Use `RegisterClassInfo::getRegPressureSetLimit`" (#213287)
Reverts llvm/llvm-project#211715 because of some failures.
Commit: 61b16cb275a4823059b34f67c41c265098b6d35f
https://github.com/llvm/llvm-project/commit/61b16cb275a4823059b34f67c41c265098b6d35f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
A clang/test/SemaOpenCL/builtins-amdgcn-image-bvh-intersect-ray-err.cl
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
Log Message:
-----------
AMDGPU: Do not give gfx12.5 bvh-ray-tracing-insts (#213246)
bvh-ray-tracing-insts was listed in the FeatureGFX12 generation, so
gfx1250/gfx1251/gfx12-5-generic inherited it even though they have no
BVH. Move the feature out of the common base and into FeatureISAVersion12.
This stops clang from wrongly accepting __builtin_amdgcn_image_bvh_intersect_ray*
on gfx1250.
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: cb1642b6f9e458bf8ff5d2c41e22a7f7cf6ee419
https://github.com/llvm/llvm-project/commit/cb1642b6f9e458bf8ff5d2c41e22a7f7cf6ee419
Author: Rashmi Mudduluru <r_mudduluru at apple.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/MemoryUnsafeCastChecker.cpp
M clang/test/Analysis/Checkers/WebKit/memory-unsafe-cast.mm
Log Message:
-----------
[Webkit Checkers][SaferCpp] Detect implicit `id`-to-specific-type casts in MemoryUnsafeCastChecker (#213113)
Flag arguments of type `id` implicitly converted to a specific
Objective-C pointer type at a call, message send, or constructor call
(e.g. passing `id` where an `NSString *` parameter is expected). These
conversions compile without a visible cast but throw at runtime if the
object is not actually of that type.
rdar://148708396
Commit: 28d9aec513c63beffd2631412adfae327763559e
https://github.com/llvm/llvm-project/commit/28d9aec513c63beffd2631412adfae327763559e
Author: Sean Clarke <sclarke at tenstorrent.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
M llvm/test/Transforms/LoopIdiom/AArch64/cyclic-redundancy-check.ll
M llvm/test/Transforms/LoopIdiom/RISCV/cyclic-redundancy-check.ll
M llvm/test/Transforms/LoopIdiom/X86/cyclic-redundancy-check.ll
A llvm/test/Transforms/LoopIdiom/crc-debugify-remarks.ll
M llvm/test/Transforms/LoopIdiom/cyclic-redundancy-check.ll
Log Message:
-----------
[LoopIdiom] Use costing to determine CRC strategy (#211040)
The CRC loop clmul optimization currently only runs under optsize,
despite being significantly faster than the Sarwate table optimization
in many cases. Model the costs of each approach and weigh them against
each other to determine which optimization should be used. Since the
benefits of clmul are unclear for optsize, simply bail in that case
instead.
Assisted-by: Claude Opus 4.8
Commit: 5f4d725bca798dc9ab56af114865212849eb6bda
https://github.com/llvm/llvm-project/commit/5f4d725bca798dc9ab56af114865212849eb6bda
Author: Qiongsi Wu <qiongsiwu at gmail.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/include/clang/DependencyScanning/DependencyConsumer.h
M clang/include/clang/DependencyScanning/DependencyScannerImpl.h
M clang/include/clang/Tooling/DependencyScanningTool.h
M clang/lib/Tooling/DependencyScanningTool.cpp
M clang/test/ClangScanDeps/modules-full-by-mult-mod-names-diagnostics.c
M clang/test/ClangScanDeps/modules-invalid-target.c
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
Log Message:
-----------
[clang][DependencyScanning] Implement the Streaming Style By-name Scanning API (#211406)
This PR implements a streaming stype by-name scanning API. The new API
takes a `DependencyConsumer`, a `DiagnosticsConsumer` and a
`getNextName` lambda. Any diagnositcs flow to the `DependencyConsumer`,
and the results flows to to `DependencyConsumer`. The `getNextName`
lambda is allows the client to stream names into the API, and the API
keeps scanning dependencies for input names until `getNextName` does not
return more names.
rdar://178088113
---
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Commit: 61090066768ecb5f88d0514bb586f24fa22f98c5
https://github.com/llvm/llvm-project/commit/61090066768ecb5f88d0514bb586f24fa22f98c5
Author: Qiongsi Wu <qiongsiwu at gmail.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/include/clang/DependencyScanning/DependencyScanningWorker.h
M clang/include/clang/Tooling/DependencyScanningTool.h
M clang/lib/DependencyScanning/DependencyScanningWorker.cpp
M clang/lib/Tooling/DependencyScanningTool.cpp
Log Message:
-----------
[clang][DependencyScanning] Relocate CompilerInstanceWithContext to DependencyScanningWorker.cpp (#211407)
This PR relocates all `CompilerInstanceWithContext` code to
`DependencyScanningWorker.cpp` and hides them as implementation details,
since no public APIs should use `CompilerInstanceWithContext` directly.
---
<sub>Stack created with <a
href="https://github.com/github/gh-stack">GitHub Stacks CLI</a> • <a
href="https://gh.io/stacks-feedback">Give Feedback 💬</a></sub>
Commit: e2fa55de001abaa4f540253bd9443763606e1a0b
https://github.com/llvm/llvm-project/commit/e2fa55de001abaa4f540253bd9443763606e1a0b
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M .github/CODEOWNERS
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/test/AArch64/constant_island_pie_update.s
M clang/Maintainers.md
M clang/docs/ClangFormatStyleOptions.rst
M clang/docs/ReleaseNotes.md
M clang/include/clang/AST/StmtOpenMP.h
M clang/include/clang/Analysis/AnyCall.h
M clang/include/clang/Basic/BuiltinsAMDGPU.td
M clang/include/clang/Basic/DiagnosticCommonKinds.td
A clang/include/clang/CIR/CIRDataLayoutSpec.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/DependencyScanning/DependencyConsumer.h
M clang/include/clang/DependencyScanning/DependencyScannerImpl.h
M clang/include/clang/DependencyScanning/DependencyScanningWorker.h
M clang/include/clang/Format/Format.h
M clang/include/clang/StaticAnalyzer/Core/BugReporter/BugReporterVisitors.h
M clang/include/clang/StaticAnalyzer/Core/BugReporter/Z3CrosscheckVisitor.h
M clang/include/clang/Tooling/DependencyScanningTool.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/Expr.cpp
M clang/lib/AST/StmtOpenMP.cpp
M clang/lib/Basic/Cuda.cpp
A clang/lib/CIR/CodeGen/CIRDataLayoutSpec.cpp
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
M clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenStmt.cpp
M clang/lib/CIR/CodeGen/CIRGenVTables.cpp
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
M clang/lib/CIR/CodeGen/CMakeLists.txt
M clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/DependencyScanning/DependencyScanningWorker.cpp
M clang/lib/Format/BreakableToken.cpp
M clang/lib/Format/Format.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/StaticAnalyzer/Checkers/CStringChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/RetainCountChecker/RetainCountDiagnostics.cpp
M clang/lib/StaticAnalyzer/Checkers/VAListChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/MemoryUnsafeCastChecker.cpp
M clang/lib/StaticAnalyzer/Core/BugReporter.cpp
M clang/lib/StaticAnalyzer/Core/BugReporterVisitors.cpp
M clang/lib/StaticAnalyzer/Core/Z3CrosscheckVisitor.cpp
M clang/lib/Tooling/DependencyScanningTool.cpp
M clang/test/Analysis/Checkers/WebKit/memory-unsafe-cast.mm
M clang/test/Analysis/dangling-ptr-deref.cpp
M clang/test/Analysis/lifetime-bound.cpp
M clang/test/Analysis/string-search-modeling.c
A clang/test/CIR/CodeGen/attr-musttail.cpp
A clang/test/CIR/CodeGen/pointer-width-32bit.cpp
A clang/test/CIR/IR/pointer-data-layout.cir
A clang/test/CIR/Tools/pointer-width-from-triple.cir
M clang/test/ClangScanDeps/modules-full-by-mult-mod-names-diagnostics.c
M clang/test/ClangScanDeps/modules-invalid-target.c
M clang/test/CodeGen/amdgpu-builtin-is-invocable.c
M clang/test/CodeGen/amdgpu-builtin-processor-is.c
A clang/test/CodeGenCXX/GH211943.cpp
M clang/test/CodeGenCXX/dynamic-cast-address-space.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx13.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-global-load-store.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-raw-buffer-atomic-max.cl
M clang/test/Driver/flang/multiple-inputs-mixed.f90
A clang/test/Driver/flang/runtimes.f90
M clang/test/OpenMP/fuse_codegen.cpp
M clang/test/OpenMP/interchange_codegen.cpp
R clang/test/OpenMP/loop_transform_final_iv.c
M clang/test/OpenMP/requires_codegen.cpp
M clang/test/OpenMP/reverse_codegen.cpp
M clang/test/OpenMP/stripe_codegen.cpp
M clang/test/OpenMP/tile_codegen.cpp
A clang/test/SemaObjC/objc-constant-literal-dict-key-restrictions.m
A clang/test/SemaOpenCL/builtins-amdgcn-cvt-sr-pk-bf16-f32-err.cl
A clang/test/SemaOpenCL/builtins-amdgcn-image-bvh-intersect-ray-err.cl
M clang/tools/cir-translate/cir-translate.cpp
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
A clang/unittests/Analysis/AnyCallTest.cpp
M clang/unittests/Analysis/CMakeLists.txt
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/FormatTestComments.cpp
M clang/utils/perf-training/perf-helper.py
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/extenddftf2.cpp
A compiler-rt/lib/builtins/extendsfdf2.cpp
A compiler-rt/lib/builtins/extendsftf2.cpp
A compiler-rt/lib/builtins/extendxftf2.cpp
A compiler-rt/lib/builtins/truncdfsf2.cpp
A compiler-rt/lib/builtins/trunctfdf2.cpp
A compiler-rt/lib/builtins/trunctfsf2.cpp
A compiler-rt/lib/builtins/trunctfxf2.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
M compiler-rt/lib/scudo/standalone/primary64.h
M compiler-rt/lib/tsan/go/buildgo.sh
M compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp
M compiler-rt/lib/ubsan/ubsan_checks.inc
M compiler-rt/lib/ubsan/ubsan_handlers.cpp
M compiler-rt/lib/ubsan/ubsan_handlers_cxx.cpp
M compiler-rt/test/cfi/anon-namespace.cpp
M compiler-rt/test/cfi/bad-cast.cpp
M compiler-rt/test/cfi/base-derived-destructor.cpp
M compiler-rt/test/cfi/cross-dso-diagnostic.cpp
M compiler-rt/test/cfi/cross-dso/icall/diag.cpp
M compiler-rt/test/cfi/cross-dso/icall/icall-from-dso.cpp
M compiler-rt/test/cfi/cross-dso/icall/icall.cpp
M compiler-rt/test/cfi/cross-dso/simple-fail.cpp
M compiler-rt/test/cfi/cross-dso/target_out_of_bounds.cpp
M compiler-rt/test/cfi/icall/bad-signature.c
M compiler-rt/test/cfi/lit.cfg.py
M compiler-rt/test/cfi/mfcall.cpp
M compiler-rt/test/cfi/multiple-inheritance.cpp
M compiler-rt/test/cfi/nvcall.cpp
M compiler-rt/test/cfi/overwrite.cpp
M compiler-rt/test/cfi/simple-fail.cpp
M compiler-rt/test/cfi/target_uninstrumented.cpp
M compiler-rt/test/cfi/vdtor.cpp
M compiler-rt/test/msan/vararg_shadow.cpp
R flang/docs/FIRArrayOperations.md
M flang/docs/HighLevelFIR.md
M flang/docs/ReleaseNotes.md
M flang/docs/index.md
M flang/include/flang/Optimizer/Builder/FIRBuilder.h
M flang/include/flang/Optimizer/Builder/MutableBox.h
R flang/include/flang/Optimizer/Builder/Runtime/Ragged.h
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/include/flang/Optimizer/OpenACC/Passes.td
M flang/include/flang/Runtime/ragged.h
M flang/lib/Evaluate/intrinsics-library.cpp
M flang/lib/Optimizer/Builder/CMakeLists.txt
M flang/lib/Optimizer/Builder/FIRBuilder.cpp
R flang/lib/Optimizer/Builder/Runtime/Ragged.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
A flang/lib/Optimizer/OpenACC/Transforms/ACCDevicePtrToCUFKernel.cpp
M flang/lib/Optimizer/OpenACC/Transforms/CMakeLists.txt
A flang/test/Fir/OpenACC/device-ptr-to-cuf-kernel.mlir
M flang/test/Fir/Todo/select_case_with_character.fir
M flang/test/Fir/convert-to-llvm-invalid.fir
M flang/test/Fir/convert-to-llvm.fir
M flang/test/Fir/fir-ops.fir
M flang/test/Fir/invalid.fir
M flang/test/HLFIR/inline-elemental.fir
M flang/test/Transforms/loop-versioning.fir
M flang/test/Transforms/simplifyintrinsics.fir
R flang/unittests/Optimizer/Builder/Runtime/RaggedTest.cpp
M flang/unittests/Optimizer/CMakeLists.txt
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/aarch64/headers.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/riscv/headers.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/config/linux/x86_64/headers.txt
A libc/docs/_static/llvm_libc_logo.svg
M libc/docs/index.md
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-macros/CMakeLists.txt
M libc/include/llvm-libc-macros/linux/CMakeLists.txt
A libc/include/llvm-libc-macros/linux/sys-statfs-macros.h
A libc/include/llvm-libc-macros/sys-statfs-macros.h
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/struct_ucred.h
M libc/include/sys/socket.yaml
A libc/include/sys/statfs.yaml
M libc/shared/builtins.h
A libc/shared/builtins/extenddftf2.h
A libc/shared/builtins/extendsfdf2.h
A libc/shared/builtins/extendsftf2.h
A libc/shared/builtins/extendxftf2.h
A libc/shared/builtins/truncdfsf2.h
A libc/shared/builtins/trunctfdf2.h
A libc/shared/builtins/trunctfsf2.h
A libc/shared/builtins/trunctfxf2.h
M libc/src/__support/FPUtil/CMakeLists.txt
M libc/src/__support/FPUtil/dyadic_float.h
M libc/src/__support/FPUtil/float128.h
M libc/src/__support/builtins/CMakeLists.txt
A libc/src/__support/builtins/extenddftf2.h
A libc/src/__support/builtins/extendsfdf2.h
A libc/src/__support/builtins/extendsftf2.h
A libc/src/__support/builtins/extendxftf2.h
A libc/src/__support/builtins/fpconvert_helper.h
A libc/src/__support/builtins/truncdfsf2.h
A libc/src/__support/builtins/trunctfdf2.h
A libc/src/__support/builtins/trunctfsf2.h
A libc/src/__support/builtins/trunctfxf2.h
M libc/src/sys/CMakeLists.txt
A libc/src/sys/statfs/CMakeLists.txt
A libc/src/sys/statfs/fstatfs.h
A libc/src/sys/statfs/linux/CMakeLists.txt
A libc/src/sys/statfs/linux/fstatfs.cpp
A libc/src/sys/statfs/linux/statfs.cpp
A libc/src/sys/statfs/statfs.h
M libc/test/shared/CMakeLists.txt
M libc/test/shared/shared_builtins_test.cpp
M libc/test/src/__support/FPUtil/float128_test.cpp
M libc/test/src/sys/CMakeLists.txt
A libc/test/src/sys/statfs/CMakeLists.txt
A libc/test/src/sys/statfs/linux/CMakeLists.txt
A libc/test/src/sys/statfs/linux/fstatfs_test.cpp
A libc/test/src/sys/statfs/linux/statfs_test.cpp
M libcxx/include/__algorithm/pstl.h
M libcxx/include/__atomic/clear_padding.h
M libcxx/include/__memory/array_cookie.h
M libcxx/include/__memory/unique_ptr.h
M libcxx/include/__pstl/backend_fwd.h
M libcxx/include/__pstl/backends/default.h
M libcxx/test/libcxx/algorithms/pstl.iterator-requirements.verify.cpp
M libcxx/test/libcxx/algorithms/pstl.nodiscard.verify.cpp
M libcxx/test/libcxx/clang_tidy.sh.py
M libcxx/test/std/algorithms/alg.nonmodifying/alg.adjacent.find/pstl.adjacent_find.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.adjacent.find/pstl.adjacent_find_pred.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.find.first.of/pstl.find_first_of.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.find.first.of/pstl.find_first_of_pred.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/mismatch/pstl.mismatch.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/mismatch/pstl.mismatch_pred.pass.cpp
A libcxx/test/std/algorithms/alg.sorting/alg.lex.comparison/pstl.lexicographical_compare.pass.cpp
A libcxx/test/std/algorithms/alg.sorting/alg.lex.comparison/pstl.lexicographical_compare_comp.pass.cpp
M libcxx/test/std/algorithms/pstl.exception_handling.pass.cpp
M libcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.class/unique.ptr.observers/assert.subscript.pass.cpp
A libcxxabi/.clang-tidy
M libsycl/src/detail/context_impl.cpp
M libsycl/src/detail/context_impl.hpp
M libsycl/src/detail/global_objects.hpp
M libsycl/src/detail/platform_impl.cpp
M libsycl/src/detail/queue_impl.cpp
M libsycl/unittests/mock/helpers.cpp
M libsycl/unittests/mock/helpers.hpp
M libsycl/unittests/mock/mock.cpp
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/Relocations.cpp
M lld/MachO/ObjC.cpp
M lld/test/ELF/aarch64-thunk-sort.s
M lld/test/MachO/objc-category-merging-minimal.s
M lld/test/MachO/objc-category-merging-swift.s
M lldb/bindings/python/CMakeLists.txt
M lldb/bindings/python/python-swigsafecast.swig
M lldb/bindings/python/python-wrapper.swig
M lldb/docs/CMakeLists.txt
M lldb/docs/python_extensions.md
A lldb/examples/python/templates/scripted_synthetic_children.py
M lldb/include/lldb/API/SBPlatform.h
M lldb/include/lldb/Core/BugReporter.h
M lldb/include/lldb/Core/Module.h
M lldb/include/lldb/DataFormatters/TypeSynthetic.h
A lldb/include/lldb/Interpreter/Interfaces/ScriptedSyntheticChildrenInterface.h
M lldb/include/lldb/Interpreter/ScriptInterpreter.h
M lldb/include/lldb/Target/Target.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/include/lldb/lldb-forward.h
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/session_helpers.py
M lldb/source/Commands/CommandObjectDiagnostics.cpp
A lldb/source/Core/BugReporter.cpp
M lldb/source/Core/CMakeLists.txt
M lldb/source/Core/Module.cpp
M lldb/source/DataFormatters/TypeSynthetic.cpp
M lldb/source/Interpreter/ScriptInterpreter.cpp
M lldb/source/Plugins/BugReporter/GitHub/GitHubReporter.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
M lldb/source/Plugins/ObjectFile/Minidump/MinidumpFileBuilder.cpp
M lldb/source/Plugins/Platform/Windows/PlatformWindows.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/CMakeLists.txt
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPythonInterface.h
A lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedSyntheticChildrenPythonInterface.cpp
A lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedSyntheticChildrenPythonInterface.h
M lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
M lldb/source/Symbol/Variable.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Target/TargetProperties.td
M lldb/source/Utility/Args.cpp
M lldb/test/API/commands/register/register_command/TestRegisters.py
M lldb/test/API/commands/settings/TestSettings.py
A lldb/test/API/functionalities/process_save_core_minidump/size_mismatch/Makefile
A lldb/test/API/functionalities/process_save_core_minidump/size_mismatch/TestProcessSaveCoreMinidumpSizeMismatch.py
A lldb/test/API/functionalities/process_save_core_minidump/size_mismatch/main.cpp
M lldb/test/API/functionalities/scripted_frame_provider/TestScriptedFrameProvider.py
M lldb/test/API/tools/lldb-dap/console/TestDAP_console.py
M lldb/test/API/tools/lldb-dap/console/TestDAP_redirection_to_console.py
M lldb/test/API/tools/lldb-dap/restart/TestDAP_restart.py
M lldb/test/API/tools/lldb-dap/restart/TestDAP_restart_console.py
M lldb/test/Shell/Diagnostics/TestReport.test
M lldb/unittests/ScriptInterpreter/Python/PythonTestSuite.cpp
M lldb/unittests/Utility/ArchSpecTest.cpp
M llvm/docs/AMDGPUMemoryModel.md
M llvm/include/llvm/ADT/SetVector.h
M llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/CodeGen/WindowScheduler.h
M llvm/include/llvm/ExecutionEngine/Orc/RTBridge/Calls.h
M llvm/include/llvm/ExecutionEngine/Orc/RTBridge/SPS/Calls.h
M llvm/include/llvm/MC/MCSubtargetInfo.h
M llvm/include/llvm/ProfileData/SampleProfReader.h
M llvm/include/llvm/Target/GenericOpcodes.td
M llvm/include/llvm/Target/TargetSelectionDAG.td
A llvm/include/llvm/TargetParser/NVPTXTargetParser.def
A llvm/include/llvm/TargetParser/NVPTXTargetParser.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/include/module.modulemap
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/OrcRTBridge.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.h
M llvm/lib/Target/Mips/MipsCallingConv.td
M llvm/lib/Target/Mips/MipsRegisterInfo.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXBaseInfo.h
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
R llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
R llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.h
M llvm/lib/Target/NVPTX/NVPTXUtilities.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/lib/TargetParser/CMakeLists.txt
A llvm/lib/TargetParser/NVPTXTargetParser.cpp
M llvm/lib/Transforms/IPO/Attributor.cpp
M llvm/lib/Transforms/IPO/SampleProfile.cpp
M llvm/lib/Transforms/IPO/SampleProfileMatcher.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCompatibilityAnalysis.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/VecUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combine-2-icmps-of-0-and-or.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-add-of-sub.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-addv.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-and-or-disjoint-mask.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-anyext-crash.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-avg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-binop-neg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-binop-undef-left-to-zero.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-build-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-fcmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-icmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-cast.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-const-infinite-loop.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-fp-const-lhs.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-int-const-lhs.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-const-fold-barrier-rhs.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-fma.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-fp-rounding.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-itofp-zero.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-unary-int.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-copy.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ctlz-cttz-zero-poison.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-trunc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ext.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-extract-vec-elt.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fabs.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-flog2.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fminimum-fmaximum.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fminnum-fmaxnum.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fneg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fpowi.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fptrunc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-freeze.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fshl.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fshr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fsqrt.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-of-binop-to-icmp-of-0.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-to-lhs-known-bits.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-inttoptr-ptrtoint.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-logic-of-compare.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-mul-to-shl.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-mul.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-mulo-with-2.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-narrow-binop.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-neg-and-one-to-sext-inreg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-op-trunc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-or-and-xor.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-or-of-and.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-overflow.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-int2ptr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-reassociation.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ptrtoint.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-same-op.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-sdiv.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-debugloc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-trunc-sextload.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-shift-immed-mismatch-crash.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-shifts-undef.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-shufflevector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-srem-by-pow2.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-trunc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-udivrem-use-bug.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-umulh-to-lshr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-unary-undef-to-zero.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge-undef.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-use-vector-truncate-order.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-vscale.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-addo-zero.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-binop-reassoc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-conflict.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-crash.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-and-mask.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-or-pattern-align.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-or-pattern.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-mulo-zero.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-narrow-binop-feeding-add.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-select-to-fminmax.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-use-vector-truncate.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-ashr-shl-to-sext-inreg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-binop-same-val.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-br.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-bzero.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-commute-shift.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-concat-vectors.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-s1.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-funnel-shifts-to-rotates.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-hoist-same-hands.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-icmp-redundant-trunc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-invert-cmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-not-really-equiv-insts.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-prop-extends-phi.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-ptradd-chain.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-select.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-sextload-from-sextinreg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector-disjoint-mask.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector-undef-rhs.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-simplify-add.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-undef.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-xor-of-and-with-same-reg.mir
A llvm/test/CodeGen/AArch64/avoid-ld4.ll
M llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
A llvm/test/CodeGen/AArch64/sms-analyzeloop-remarks.mir
A llvm/test/CodeGen/AArch64/sms-schedule-remark.mir
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-wide-add.ll
A llvm/test/CodeGen/AArch64/sve-structured-store-memoperands.ll
M llvm/test/CodeGen/AArch64/sve-vector-interleave.ll
M llvm/test/CodeGen/AArch64/vector-absolute-difference.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-region.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
A llvm/test/CodeGen/AMDGPU/arbitrary-fp-from-float-fp8-f16-hw.ll
A llvm/test/CodeGen/AMDGPU/arbitrary-fp-to-float-fp8-hw.ll
M llvm/test/CodeGen/AMDGPU/bug-pk-f32-imm-fold.mir
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
M llvm/test/CodeGen/AMDGPU/coexec-sched-flavor-classification.mir
M llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
A llvm/test/CodeGen/AMDGPU/greedy-wwm-copy-prologue-assert.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.pk.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.msad.u8.ll
M llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
A llvm/test/CodeGen/AMDGPU/s_bcnt0.ll
M llvm/test/CodeGen/AMDGPU/s_cmp_0.ll
M llvm/test/CodeGen/Hexagon/swp-ws-exp.mir
M llvm/test/CodeGen/Hexagon/swp-ws-fail-0.mir
A llvm/test/CodeGen/Mips/write_register_gp.ll
M llvm/test/CodeGen/PowerPC/copysignl.ll
M llvm/test/CodeGen/PowerPC/sms-remark.ll
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/branch-on-zero.ll
A llvm/test/CodeGen/RISCV/frame-base-addr-reuse.mir
M llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv32.mir
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/zdinx-large-spill.mir
M llvm/test/CodeGen/SPARC/reserved-regs-named.ll
M llvm/test/CodeGen/SPIRV/atomicrmw-uinc-udec-wrap.ll
A llvm/test/CodeGen/SPIRV/legalization/matrix-wide-vector-shader.ll
M llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll
A llvm/test/CodeGen/X86/fptosi-sat-scalar-f16.ll
M llvm/test/CodeGen/X86/fptosi-sat-scalar.ll
M llvm/test/CodeGen/X86/merge-store-partially-alias-loads.ll
A llvm/test/DebugInfo/X86/DW_AT_LLVM_stmt_seq_split_dwarf.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vcvt.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vcvt_f32_su32.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/vararg_shadow.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/f16c-intrinsics-upgrade.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/vararg_shadow.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/vararg_shadow.ll
M llvm/test/MC/AMDGPU/gfx950-unsupported.s
M llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
M llvm/test/Transforms/ConstraintElimination/ne-tightening.ll
M llvm/test/Transforms/IndVarSimplify/ARM/code-size.ll
M llvm/test/Transforms/IndVarSimplify/replace-loop-exit-folds.ll
M llvm/test/Transforms/LoopIdiom/AArch64/cyclic-redundancy-check.ll
M llvm/test/Transforms/LoopIdiom/RISCV/cyclic-redundancy-check.ll
M llvm/test/Transforms/LoopIdiom/X86/cyclic-redundancy-check.ll
M llvm/test/Transforms/LoopIdiom/basic.ll
A llvm/test/Transforms/LoopIdiom/crc-debugify-remarks.ll
A llvm/test/Transforms/LoopIdiom/cyclic-redundancy-check-memoryssa.ll
M llvm/test/Transforms/LoopIdiom/cyclic-redundancy-check.ll
M llvm/test/Transforms/LoopStrengthReduce/AArch64/expand-ptrtoaddr-reuse-ptrtoint.ll
M llvm/test/Transforms/LoopUnroll/branch-weights-freq/unroll-complete.ll
M llvm/test/Transforms/LoopUnroll/branch-weights-freq/unroll-partial-unconditional-latch.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll
M llvm/test/Transforms/LoopVectorize/VPlan/icmp-uniforms.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-branch-weights.ll
M llvm/test/Transforms/LoopVectorize/bsd_regex.ll
A llvm/test/Transforms/LoopVectorize/expression-recipe-branch-weights.ll
M llvm/test/Transforms/LoopVectorize/extract-last-veclane.ll
M llvm/test/Transforms/LoopVectorize/float-induction.ll
M llvm/test/Transforms/LoopVectorize/forked-pointers.ll
M llvm/test/Transforms/LoopVectorize/histograms.ll
M llvm/test/Transforms/LoopVectorize/hoist-predicated-loads-with-predicated-stores.ll
M llvm/test/Transforms/LoopVectorize/if-conversion-nest.ll
M llvm/test/Transforms/LoopVectorize/if-conversion.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-2.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-metadata.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-pred-stores.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization-2.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/loop-scalars.ll
M llvm/test/Transforms/LoopVectorize/multiple-address-spaces.ll
M llvm/test/Transforms/LoopVectorize/non-const-n.ll
M llvm/test/Transforms/LoopVectorize/opaque-ptr.ll
M llvm/test/Transforms/LoopVectorize/phi-cost.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-cond.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
M llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
M llvm/test/Transforms/LoopVectorize/reduction.ll
A llvm/test/Transforms/LoopVectorize/replicate-region-branch-weights-merged-mem-ops.ll
M llvm/test/Transforms/LoopVectorize/replicate-region-branch-weights.ll
M llvm/test/Transforms/LoopVectorize/runtime-check.ll
M llvm/test/Transforms/LoopVectorize/scalable-inductions.ll
M llvm/test/Transforms/LoopVectorize/scalar_after_vectorization.ll
M llvm/test/Transforms/LoopVectorize/store-shuffle-bug.ll
M llvm/test/Transforms/LoopVectorize/trunc-reductions.ll
M llvm/test/Transforms/LoopVectorize/vector-geps.ll
M llvm/test/Transforms/SLPVectorizer/X86/fmuladd-copyable-mul-part.ll
A llvm/test/Transforms/SLPVectorizer/X86/reduction-fadd-reassoc.ll
A llvm/test/Transforms/SandboxVectorizer/topdown_vec.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
A llvm/test/tools/llvm-profgen/X86/first-loadable-address.test
M llvm/tools/llvm-calc-occupancy/CMakeLists.txt
M llvm/tools/llvm-profgen/ProfiledBinary.cpp
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
M llvm/unittests/ExecutionEngine/Orc/SPSCallersTest.cpp
M llvm/unittests/ProfileData/SampleProfTest.cpp
M llvm/unittests/Target/ARM/InstSizes.cpp
M llvm/unittests/Target/ARM/MachineInstrTest.cpp
M llvm/unittests/TargetParser/CMakeLists.txt
A llvm/unittests/TargetParser/NVPTXTargetParserTest.cpp
M llvm/unittests/Transforms/Utils/ScalarEvolutionExpanderTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/DependencyGraphTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/TargetParser/BUILD.gn
M llvm/utils/gn/secondary/llvm/test/BUILD.gn
A llvm/utils/gn/secondary/llvm/tools/llvm-calc-occupancy/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/TargetParser/BUILD.gn
M mlir/include/mlir/Dialect/LLVMIR/BasicPtxBuilderInterface.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
M mlir/lib/Dialect/LLVMIR/IR/BasicPtxBuilderInterface.cpp
M mlir/lib/Dialect/Linalg/Transforms/ConvertConv2DToImg2Col.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCCGToGPU.cpp
M mlir/lib/Dialect/X86/Transforms/VectorContractToAMXDotProduct.cpp
M mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir
M mlir/test/Conversion/SPIRVToLLVM/arithmetic-ops-to-llvm.mlir
M mlir/test/Dialect/Complex/canonicalize.mlir
M mlir/test/Dialect/Linalg/convert-conv2d-to-img2col.mlir
M mlir/test/Dialect/OpenACC/acc-cg-to-gpu-reduction-array-shared.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
M mlir/test/Dialect/X86/AMX/vector-contract-to-tiled-dp.mlir
M offload/libomptarget/omptarget.cpp
M offload/test/jit/empty_kernel_lvl1.c
M offload/test/jit/empty_kernel_lvl2.c
A offload/test/offloading/firstprivate_packed_buffer_lifetime.c
M offload/test/unit/lit.cfg.py
M offload/test/unit/lit.site.cfg.in
M offload/unittests/OffloadAPI/program/olCreateProgram.cpp
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/OpenACC/Transforms/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/kovdan01/ptrauth-atts-for-synthetic-fns
Commit: b3abf3d29d31c5b16711a3daa782275b8edbbe20
https://github.com/llvm/llvm-project/commit/b3abf3d29d31c5b16711a3daa782275b8edbbe20
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
M llvm/test/Transforms/GCOVProfiling/ptrauth-module-flags-aarch64.ll
Log Message:
-----------
Address review comments
Compare: https://github.com/llvm/llvm-project/compare/b7f90a05dfc4...b3abf3d29d31
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