[all-commits] [llvm/llvm-project] f24da9: [RISC-V] Fix assert after 255162a (#212791)
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Fri Jul 31 07:56:16 PDT 2026
Branch: refs/heads/users/alexey-bataev/spr/slpsupport-copyables-in-the-fmuladd-multiplicand
Home: https://github.com/llvm/llvm-project
Commit: f24da9d03ba5d25c523e050da2ca3c4060ca23d5
https://github.com/llvm/llvm-project/commit/f24da9d03ba5d25c523e050da2ca3c4060ca23d5
Author: Nemanja Ivanovic <nemanja.i.llvm at gmail.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
A llvm/test/CodeGen/RISCV/epilog-crash.ll
Log Message:
-----------
[RISC-V] Fix assert after 255162a (#212791)
The iterator passed-in may point to the end of the block which causes an
assertion failure when attempting to inspect the MI it points to. Guard
against this.
Commit: 8d445c6cab429f062d5b73db5f243fff7b49c276
https://github.com/llvm/llvm-project/commit/8d445c6cab429f062d5b73db5f243fff7b49c276
Author: carlobertolli <carlo.bertolli at amd.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/bitop3-shared-operand.ll
Log Message:
-----------
[AMDGPU][NFC] Add previously failing bitop3 tests. (#212335)
The following two expressions used to return the wrong truth table for
v_bitop3:
; ((b & T) | T) & ~T, where T = a & c
; U ^ (~U | T), where T = c ^ b and U = (T | a) & T
The fix was implemented in:
https://github.com/llvm/llvm-project/pull/198556
Assisted-by: Cursor (Claude)
Commit: 421d2e88e4f08f39a4bd48b9591c62d1145ec0ac
https://github.com/llvm/llvm-project/commit/421d2e88e4f08f39a4bd48b9591c62d1145ec0ac
Author: Harrison Hao <57025411+harrisonGPU at users.noreply.github.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/include/llvm/Frontend/OpenMP/ConstructDecompositionT.h
Log Message:
-----------
[OpenMP] Fix ambiguous namespace lookup with delayed template parsing (#212720)
Running `check-llvm` on Windows fails while compiling LLVMFrontendTests
with the following error:
error: reference to 'detail' is ambiguous
Clang enables delayed template parsing by default when targeting the
MSVC ABI on Windows. When ConstructDecompositionT is instantiated after
a using-directive for `llvm::omp`, both `::detail` and
`llvm::omp::detail` are
visible, making `detail::find_unique` ambiguous.
Explicitly qualify find_unique with the global namespace. This fixes
check-llvm on Windows and other environments using
-fdelayed-template-parsing, without changing behavior.
Commit: e0e0b57127085fd6b246ce8a7a4ba5d3da32c1f3
https://github.com/llvm/llvm-project/commit/e0e0b57127085fd6b246ce8a7a4ba5d3da32c1f3
Author: David Green <david.green at arm.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/ValueTypes.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
Log Message:
-----------
Revert "[Codegen] Replace any_of with is_contained. NFC (#212289)" (#212794)
This reverts commit 52f6c88c2c1b6f0c10b9c8fb09ec35e147c593e3 due to
errors in the C++20 builder.
It does not revert the followup from #212711.
Commit: e12e16f6e03ba4b9008314dbb885e8c1dddf875f
https://github.com/llvm/llvm-project/commit/e12e16f6e03ba4b9008314dbb885e8c1dddf875f
Author: Alexis Perry-Holby <aperry at lanl.gov>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
A flang/docs/MeetingNotes/2026/2026-07-29.md
Log Message:
-----------
[flang] Add Flang Community Call Notes for July 29th meeting (#212810)
Commit: eb64c21b7954bdb66ed9ebaefcf400715be321eb
https://github.com/llvm/llvm-project/commit/eb64c21b7954bdb66ed9ebaefcf400715be321eb
Author: Zhen Wang <zhenw at nvidia.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M flang/include/flang/Evaluate/tools.h
M flang/test/Lower/CUDA/cuda-data-transfer.cuf
M flang/test/Lower/CUDA/cuda-managed-assign.cuf
Log Message:
-----------
[flang][cuda] Restrict managed data transfers to whole-array assignments (#212593)
Assignments involving managed or unified data are lowered to
`cuf.data_transfer`, a synchronous copy. The predicate only excluded
scalar left-hand sides, so array sections were transferred too, turning
a loop that assigns one section per
iteration into a sequence of blocking copies.
Key the decision on the managed operand instead: a transfer when the
managed variable or array is whole, host code when it is a section or an
element. Managed data is host-addressable, so the host assignment is
safe. Managed function results and assignments involving device memory
are unaffected.
This is the behavior specified in the CUDA Fortran Programming Guide
3.4.1:
> An assignment statement where the right hand side is a managed array
section and
> the left hand side is any host or managed variable copies data using
generated
> host code.
Commit: 1f5e93294eddb3309d530392344ee0271ccaa64c
https://github.com/llvm/llvm-project/commit/1f5e93294eddb3309d530392344ee0271ccaa64c
Author: Ian Anderson <iana at apple.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M llvm/docs/CommandGuide/llvm-readobj.rst
M llvm/include/llvm/BinaryFormat/MachO.def
M llvm/include/llvm/BinaryFormat/MachO.h
M llvm/include/llvm/ExecutionEngine/Orc/MachOBuilder.h
M llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h
M llvm/include/llvm/MC/MCMachObjectWriter.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/include/llvm/Object/MachO.h
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCMachOStreamer.cpp
M llvm/lib/MC/MCParser/DarwinAsmParser.cpp
M llvm/lib/MC/MachObjectWriter.cpp
M llvm/lib/ObjCopy/MachO/MachOLayoutBuilder.cpp
M llvm/lib/Object/MachOObjectFile.cpp
M llvm/lib/ObjectYAML/MachOEmitter.cpp
M llvm/lib/ObjectYAML/MachOYAML.cpp
M llvm/test/ExecutionEngine/JITLink/Generic/Inputs/MachO_Universal_libFoo_dylib.yaml
A llvm/test/MC/MachO/target-triple-padding.s
A llvm/test/MC/MachO/target-triple.s
A llvm/test/Object/Inputs/macho-invalid-target-triple-name_offset-toobig.yaml
A llvm/test/Object/Inputs/macho-invalid-target-triple-name_offset-toosmall.yaml
A llvm/test/Object/Inputs/macho-invalid-target-triple-name_toobig.yaml
A llvm/test/Object/Inputs/macho-invalid-target-triple-small.yaml
M llvm/test/Object/macho-invalid.test
A llvm/test/ObjectYAML/MachO/target_triple_command.yaml
A llvm/test/tools/dsymutil/AArch64/lc_target_triple.test
A llvm/test/tools/dsymutil/AArch64/lc_target_triple_duplicate.test
A llvm/test/tools/dsymutil/AArch64/lc_target_triple_universal.test
A llvm/test/tools/dsymutil/Inputs/lc_target_triple.arm64
A llvm/test/tools/dsymutil/Inputs/lc_target_triple_duplicate.arm64
A llvm/test/tools/dsymutil/Inputs/lc_target_triple_universal.arm64
A llvm/test/tools/llvm-objcopy/MachO/lc-target-triple.test
A llvm/test/tools/llvm-objdump/MachO/target-triple.yaml
A llvm/test/tools/llvm-readobj/MachO/target-triple.test
M llvm/tools/dsymutil/MachOUtils.cpp
M llvm/tools/llvm-objdump/MachODump.cpp
M llvm/tools/llvm-readobj/MachODumper.cpp
M llvm/tools/llvm-readobj/ObjDumper.h
M llvm/tools/llvm-readobj/Opts.td
M llvm/tools/llvm-readobj/llvm-readobj.cpp
M llvm/tools/obj2yaml/macho2yaml.cpp
M llvm/unittests/ExecutionEngine/Orc/MachOBuilderTest.cpp
Log Message:
-----------
[llvm][macho] Support the LC_TARGET_TRIPLE load command (#210276)
Add support for the new LC_TARGET_TRIPLE load command.
rdar://140301164
Commit: e24eb10725e514cece9a21da97040165a199f23c
https://github.com/llvm/llvm-project/commit/e24eb10725e514cece9a21da97040165a199f23c
Author: Corentin Jabot <corentinjabot at gmail.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M clang-tools-extra/clangd/unittests/PreambleTests.cpp
M clang/include/clang/Lex/Preprocessor.h
M clang/lib/Frontend/FrontendAction.cpp
M clang/lib/Frontend/PrintPreprocessedOutput.cpp
M clang/lib/Frontend/Rewrite/InclusionRewriter.cpp
M clang/lib/Lex/PPDirectives.cpp
R clang/test/Frontend/linemarker-invalid-escape.c
M clang/test/Frontend/rewrite-includes.c
M clang/test/Modules/cxx20-hu-05.cpp
M clang/test/Modules/cxx20-hu-06.cpp
M clang/test/Parser/cxx11-user-defined-literals.cpp
M clang/test/Preprocessor/line-directive-output.c
M clang/test/Preprocessor/line-directive.c
M clang/test/VFS/external-names-multi-overlay.c
M clang/test/VFS/fallback.c
Log Message:
-----------
[Clang] Treat line directives as header names. (#211512)
We treated line directives as being unevaluated string literal. However
- The standard has no such restriction - or rather the standard has
different, unclear restriction (https://wg21.link/CWG2693)
- Because of Windows paths, it's common for "C:\foo\bar" to be used, and
these should not form escape sequences.
To remain consistent with other implementations, we do not allow `#line
1 <>` at this time. We do however support `#line 1 ""` to avoid a
breaking change.
Fixes a regression introduced by #201413
Commit: 32eae3a39471911888ba50bf03379450b4d96e3e
https://github.com/llvm/llvm-project/commit/32eae3a39471911888ba50bf03379450b4d96e3e
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Semantics/stmt-func04.f90
Log Message:
-----------
[flang] Statement function dummy names do not clash with host or unreferenced global names (#212396)
The check added for F2023 19.4 p2 (statement function dummy argument
name may be the same as an accessible name only if that name is a scalar
variable) looked the name up through the whole host scope chain and,
failing that, in the global scope. Both lookups overshoot what is
"accessible" in the scoping unit:
* Per F2023 19.5.1.4 p2 item (11), the appearance of a name as a
dummy-arg-name in a stmt-function-stmt makes any host entity of that
name inaccessible by host association throughout the scoping unit, so a
host entity can never conflict with the dummy.
* A global entity to which the scoping unit makes no reference at all is
not accessible in it; otherwise conformance would depend on whether
unrelated program units happen to be compiled in the same file.
This caused bogus errors on conforming code such as
```
program p
logical, external :: x
contains
subroutine s
real :: f
f(x) = x * x ! 'x' is an implicitly typed real dummy here
end
end
```
where the dummy 'x' must be implicitly typed real (both NAG and gfortran
accept this and type it that way; flang already typed it correctly, but
rejected the program).
Restrict the lookup to names made visible by the scoping unit itself
(declared, referenced, or USE-associated there), matching the lookup
HandleStmtFunction already uses to type the dummies.
Assisted-by: AI
Commit: 13ac5c62ce5aab0395849fec322eb402ab784b76
https://github.com/llvm/llvm-project/commit/13ac5c62ce5aab0395849fec322eb402ab784b76
Author: Thirumalai Shaktivel <74826228+Thirumalai-Shaktivel at users.noreply.github.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Semantics/OpenMP/declare-target02.f90
M flang/test/Semantics/OpenMP/threadprivate02.f90
Log Message:
-----------
[flang][openmp] Add semantic checks in THREADPRIVATE/DECLARE TARGET (#209084)
The problem is that the automatic object was used as the
threadprivate argument.
Solution:
>From the documentation (J3/24-007):
> C814 An automatic data object shall not have the SAVE attribute.
> C862 The SAVE attribute shall not be specified for a dummy argument,
> a function result, an automatic data object, or an object
> that is in a common block.
The bare SAVE statement makes any valid local variables tagged
with the SAVE attribute. As the restriction mentioned above, the
automatic object cannot have a SAVE attribute and shall not be
used as the THREADPRIVATE argument. This patch adds semantic
checks for dummy arguments, function results, and automatic data
objects in both THREADPRIVATE and DECLARE TARGET directives.
[flang][OpenMP] Fix DECLARE TARGET to reject distinct result name
When a function uses a distinct result name (e.g. result(res)),
DECLARE TARGET(res) was not diagnosed because ResolveOmpDesignator
rebound it to the procedure, skipping the IsFunctionResult check.
Commit: 13310e947e510320bfde9a800a6292265f630b97
https://github.com/llvm/llvm-project/commit/13310e947e510320bfde9a800a6292265f630b97
Author: Navaneeth Shanmugasundaram <nshanmug at qti.qualcomm.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M llvm/utils/git/github-automation.py
Log Message:
-----------
[GitHub] Fix authentication for release workflow git push (#212634)
Update the push URL format to use GitHub's required authentication
format with the 'x-access-token' prefix. GitHub now requires:
https://x-access-token:{token}@github.com/{repo}
instead of the deprecated format:
https://{token}@github.com/{repo}
Without this change, the release workflow fails when attempting to push
branches with the error:
fatal: could not read Password for 'https://***@github.com':
No such device or address
This occurs because Git attempts to prompt for credentials in the
non-interactive GitHub Actions environment when the token format is not
recognized.
Fixes the /cherry-pick command in the issue-release-workflow.
Signed-off-by: nshanmug <nshanmug at qti.qualcomm.com>
Commit: b979a119274a13fdee769478702148006219fc5b
https://github.com/llvm/llvm-project/commit/b979a119274a13fdee769478702148006219fc5b
Author: Adam Smith <adams at nvidia.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
A clang/test/CIR/CodeGen/call-conv-lowering-x86_64-indirect.c
A clang/test/CIR/Transforms/abi-lowering/indirect-call-classification-attr.cir
R clang/test/CIR/Transforms/abi-lowering/indirect-call-nyi.cir
A clang/test/CIR/Transforms/abi-lowering/indirect-call-test-target.cir
A clang/test/CIR/Transforms/abi-lowering/indirect-call.cir
Log Message:
-----------
[CIR] Lower indirect calls in CallConvLowering (#211636)
Indirect calls were unsupported by CallConvLowering. `rewriteCallSite` bailed
with "indirect call not yet implemented", and the pass driver rejected any
module that both needed call-site rewriting and contained an indirect call. A
function pointer whose signature required ABI reshaping (a by-value struct
argument, or an sret return) could not be compiled at all, even though a
direct call to the same signature lowered fine.
The callee is opaque, but its type is a pointer to a `FuncType` that carries the
full signature. Classification is now driven from that pointee signature
through the same LLVM ABI path as the direct case: `classifyX86_64Function` is
split into `classifyX86_64Signature`, taking a return type, an argument
`TypeRange`, and an `emitError` callback. The driver collects indirect calls,
classifies each callee signature (x86_64, or the test target used by the pass
tests), and runs `rewriteCallSite`. `prependIndirectCallee` re-adds the callee
as operand 0, bitcasting the function pointer to the coerced signature when it
differs so the rebuilt call matches its reshaped return.
The `classification-attr` driver mode injects a per-function classification
that cannot describe a callee resolved at run time, so an indirect call is a
diagnosed error there rather than being left silently unrewritten while direct
calls are coerced.
Commit: f958a55f66a062b4c005015b691a949deb24e237
https://github.com/llvm/llvm-project/commit/f958a55f66a062b4c005015b691a949deb24e237
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M lldb/test/CMakeLists.txt
A lldb/test/Shell/MCP/TestHelp.test
A lldb/test/Shell/MCP/TestUnknownArgument.test
A lldb/test/Shell/MCP/TestVersion.test
M lldb/test/Shell/helper/toolchain.py
M lldb/tools/lldb-mcp/lldb-mcp.cpp
Log Message:
-----------
[lldb-mcp] Add --help and --version (#212680)
lldb-mcp accepted no arguments at all, so --help and --version fell
through to the protocol loop and blocked reading stdin, and a mistyped
flag was silently ignored while the tool waited for MCP traffic. Handle
both flags and reject anything else with a usage message.
Commit: 130dccc2c3192d9f49c2e85bcd047ed67a9fa9e1
https://github.com/llvm/llvm-project/commit/130dccc2c3192d9f49c2e85bcd047ed67a9fa9e1
Author: Nikita Taranov <nikita.taranov at clickhouse.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M compiler-rt/test/xray/TestCases/Posix/fdr-mode.cpp
Log Message:
-----------
[XRay][test] Raise fdr-mode.cpp unwrite threshold to deflake it (#211595)
It was observed failing on `sanitizer-aarch64-linux` ([build
40750](https://lab.llvm.org/buildbot/#/builders/51/builds/40750)).
The failure is in the `UNWRITE` run
(`XRAY_FDR_OPTIONS="func_duration_threshold_us=5000"`), which asserts
that every short function record is "unwritten" (rewound) except
arg1-logging records. In the failing output an `fA()` enter/exit pair
survived:
```
<stdin>:9: - { func-id: 3, function: 'fA()', cpu: 0, thread: 1909237, kind: function-enter, tsc: 1784775492023431847 }
<stdin>:10: - { func-id: 3, function: 'fA()', cpu: 0, thread: 1909237, kind: function-exit, tsc: 1784775492029462345 }
<stdin>:11: - { func-id: 4, function: 'fArg(int)', args: [ 1 ], ..., kind: function-enter-arg, ... }
```
so `UNWRITE-NEXT` (and `UNWRITE-NOT: function-enter`) no longer hold.
FDR mode only rewinds a function's enter record when its exit lands
within the threshold (`XRayFDRController::functionExit`: `TSC -
LastFunctionEntryTSC < CycleThreshold`).
```
1784775492029462345 - 1784775492023431847 = 6,030,498 cycles / 1 GHz = 6.03 ms > 5 ms threshold
```
i.e. the thread was preempted for ~6 ms mid-function, so the record was
(correctly, by the runtime's own rule) not unwritten.
The proposed fix is to raise the `UNWRITE` run's
`func_duration_threshold_us` from `5000` to `100000`, so realistic
scheduling jitter cannot push a short function over the threshold. This
mirrors the accepted fix for the sibling test in
[PR #186611](https://github.com/llvm/llvm-project/pull/186611)
(`basic-filtering.cpp`), which flaked the same way.
Commit: 125080fbaa17ddab3313f580a2d2ab686a03be55
https://github.com/llvm/llvm-project/commit/125080fbaa17ddab3313f580a2d2ab686a03be55
Author: Steven Wu <stevenwu at apple.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M llvm/cmake/config-ix.cmake
Log Message:
-----------
[Darwin][tests] Partially restore some of the change in #212329 (#212826)
Restore the fallback path for ld-classic in #212329 to fix some of the
failing CI jobs due to some Xcode releases doesn't have the new linker
that supports `-save-temps` flag. Restore the logic so that `ld-classic`
is preferred over `ld` but no longer requires ld64/ld-classic.
In legacy releases only has ld64, ld64 is used. In latest releases where
ld64 is removed, new linker is feature completed and fully compatible
with ld64. During the transition period where ld64 is shipped as
ld-classic, prefer ld64 since new linker might not be feature complete.
rdar://183454376
Commit: aa924278efbd4f76329bb95ebd33fd3e445d4ff4
https://github.com/llvm/llvm-project/commit/aa924278efbd4f76329bb95ebd33fd3e445d4ff4
Author: Lucas Mellone <github.snugness349 at passinbox.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M libcxx/include/cmath
Log Message:
-----------
[libc++][math] Add missing `constexpr since C++23` comment for `signbit` (#212458)
Adds the missing `// constexpr since C++23` for `std::signbit` in the
synopsis comments of `<cmath>`.
Follows-up: https://github.com/llvm/llvm-project/pull/105946.
Commit: d6a165836cc7bc64bda1ceab22937839cb88d5cc
https://github.com/llvm/llvm-project/commit/d6a165836cc7bc64bda1ceab22937839cb88d5cc
Author: Roland McGrath <mcgrathr at google.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M clang/cmake/caches/Fuchsia-stage2.cmake
Log Message:
-----------
[CMake][Fuchsia] Compile runtimes with -ffuchsia-api-level (#211753)
Use the supplied Fuchsia SDK's version_history.json to deduce the
oldest API level still supported, and target that for toolchain
runtimes so they'll be runtime-compatible when linked into user
programs that target any SDK-supported API level.
Commit: 0e351245ff0cf7a824207658c189ef099b3aaaab
https://github.com/llvm/llvm-project/commit/0e351245ff0cf7a824207658c189ef099b3aaaab
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M lldb/test/API/tools/lldb-dap/longpath/TestDAP_launch_longPath.py
M lldb/test/API/tools/lldb-dap/stackTrace/subtleFrames/TestDAP_subtleFrames.py
M lldb/test/API/tools/lldb-dap/unknown/TestDAP_unknownRequest.py
Log Message:
-----------
[lldb-dap] Migrate unknownRequest, subtleFrames and longpath (#211627)
Migrated tests:
- TestDAP_unknownRequest.py
- TestDAP_subtleFrames.py
- TestDAP_launch_longPath.py
Commit: 8d404384dd842d43362732a11b233ee3d6ead023
https://github.com/llvm/llvm-project/commit/8d404384dd842d43362732a11b233ee3d6ead023
Author: Jackson Stogel <jtstogel at gmail.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M libc/src/__support/CPP/CMakeLists.txt
M libc/src/__support/CPP/string.h
M libc/src/stdlib/linux/CMakeLists.txt
M libc/src/stdlib/linux/realpath.cpp
M libc/test/src/__support/CPP/string_test.cpp
M libc/test/src/stdlib/CMakeLists.txt
M libc/test/src/stdlib/realpath_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[libc][realpath] Follow symlinks (#212164)
This commit updates realpath to call `readlinkat` on symlinks during
path resolution.
Some notes on implementation:
- `PendingPath` uses a `cpp::string` to store unprocessed path
components. This could be more efficient by using a `PATH_MAX` buffer
and storing the path at the end of the buffer, which would allow for
easy prepending. However, using a `cpp::string` avoids the pointer
arithmetic and memory management that would involve.
- This PR implements `cpp::string::replace` to avoid pointer arithmetic
inside `realpath`. This should hopefully not be too inefficient, since
`prepend` reuses space from processed path components there's enough
room, there certainly exist some bad inputs that would cause many
`memmove` operations.
Commit: 7bed6591be3191446ec2cf92ef247487fff03a84
https://github.com/llvm/llvm-project/commit/7bed6591be3191446ec2cf92ef247487fff03a84
Author: Diego Novillo <dnovillo at nvidia.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
M llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable-skip-type-not-in-regs.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable-static-member.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-type-array-of-composite-drop.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-type-composite-nested-drop.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-type-composite-skip-member-not-in-regs.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-type-composite-static-member-skipped.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-type-composite.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-type-pointer-to-composite-drop.ll
Log Message:
-----------
[SPIRV] Emit NonSemantic DebugTypeComposite and DebugTypeMember. (#211638)
This PR adds `DebugTypeComposite` (opcode 10) and `DebugTypeMember`
(opcode 11):
1. `partitionTypes` clusters `DICompositeType` with
`DW_TAG_structure_type`, `DW_TAG_class_type`, or `DW_TAG_union_type`.
2. Each composite emits one `DebugTypeMember` per `DW_TAG_member`, then
a `DebugTypeComposite`. Members precede the composite.
3. Tag maps class, structure, and union to 0, 1, and 2. A forward
declaration emits `DebugInfoNone` for Size and no members.
4. A member whose type is not in `DebugTypeRegs` is skipped.
`DebugTypeMember` has no Parent operand, per the spec. Only the
composite references its members.
Tests in `llvm/test/CodeGen/SPIRV/debug-info/`:
1. `debug-type-composite.ll`: a struct with two members and a forward
declaration.
2. `debug-type-composite-skip-member-not-in-regs.ll`: a member whose
type is a pointer with no DWARF address space, exercising the skip.
`debug-global-variable-skip-type-not-in-regs.ll` and
`debug-global-variable-static-member.ll` assumed composites and members
are never emitted. Both now use a no-address-space pointer to avoid
disabling the existing test.
Commit: a42bed3f72c427dcd023aae169bec9305ec29ed6
https://github.com/llvm/llvm-project/commit/a42bed3f72c427dcd023aae169bec9305ec29ed6
Author: fineg74 <61437305+fineg74 at users.noreply.github.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M offload/plugins-nextgen/common/CMakeLists.txt
M offload/plugins-nextgen/common/src/JIT.cpp
Log Message:
-----------
[OFFLOAD] Add JIT support for SPIRV backend (#212823)
This PR adds support for SPIRV to plugins JIT. It is required in cases
when kernel is supplied in bitcode format for spirv triple.
Commit: 16f116f476c248c345fd8ffe4b3e863f2700161f
https://github.com/llvm/llvm-project/commit/16f116f476c248c345fd8ffe4b3e863f2700161f
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M lldb/include/lldb/Host/JSONTransport.h
M lldb/include/lldb/Protocol/MCP/Transport.h
M lldb/source/Host/common/JSONTransport.cpp
M lldb/source/Protocol/MCP/Transport.cpp
M lldb/unittests/Host/JSONTransportTest.cpp
Log Message:
-----------
[lldb] Reply to malformed requests and use JSON-RPC error codes (#212678)
The transport dropped a message that failed to parse: it logged the
error and returned, so a peer waiting on that request hung forever and
every message already buffered behind it was discarded. Keep going after
a failed parse, and add ReplyWithParseError so a message that is valid
JSON but not a valid request is answered against its own id. Unparseable
JSON still gets no reply, since it carries no id and JSON-RPC forbids
inventing one.
Method-not-found was raised with createStringError, which converts
through inconvertibleErrorCode() to -32603, so clients could not tell a
misspelled method from a server fault. Use the MethodNotFound error,
which already carries -32601, and give InvalidParams the -32602 code it
was missing.
Commit: 58a93a1eec10d30dfa358afda73f402fb308a5e4
https://github.com/llvm/llvm-project/commit/58a93a1eec10d30dfa358afda73f402fb308a5e4
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M lldb/source/Plugins/Protocol/MCP/Tool.cpp
Log Message:
-----------
[lldb-mcp] Run managed debug sessions synchronously (#212681)
A debugger created for an MCP session has no event loop to service
asynchronous stops, so a resume returned before the process stopped and
every subsequent command failed against a still-running process. That
made breakpoint debugging unusable: `run` reported only the launch, and
`bt` that followed it errored out. Create these debuggers in synchronous
mode, as lldb-dap does.
Commit: 33c7ef4a631db53440f569f048660474e0a46bd6
https://github.com/llvm/llvm-project/commit/33c7ef4a631db53440f569f048660474e0a46bd6
Author: 陈子昂 <2802328816 at qq.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/lib/Headers/riscv_packed_simd.h
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
Log Message:
-----------
[Clang][RISCV] Add packed pair byte intrinsics (#212589)
Add the 32-bit byte forms and the 64-bit byte/halfword forms of the
P-extension packed pair intrinsics to riscv_packed_simd.h using generic
shufflevector IR.
Extend the existing packed pair shuffle lowering to recognize the mixed
even/odd forms and select ppaireo/ppairoe in addition to ppaire/ppairo.
Add Clang CodeGen, LLVM CodeGen, and intrinsic header tests for the new
forms.
Commit: 0475ef459c0bf24d79330372fef29a4aaf68c87d
https://github.com/llvm/llvm-project/commit/0475ef459c0bf24d79330372fef29a4aaf68c87d
Author: Kewen Meng <Kewen.Meng at amd.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M clang/include/clang/AST/StmtOpenMP.h
M clang/lib/AST/StmtOpenMP.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/test/OpenMP/fuse_codegen.cpp
M clang/test/OpenMP/interchange_codegen.cpp
R clang/test/OpenMP/loop_transform_final_iv.c
M clang/test/OpenMP/reverse_codegen.cpp
M clang/test/OpenMP/stripe_codegen.cpp
M clang/test/OpenMP/tile_codegen.cpp
Log Message:
-----------
Revert "[OpenMP] Restore loop variable values after loop-tranformation constructs." (#212832)
Reverts llvm/llvm-project#208533
PR breaks several bots. Revert to unblock.
https://lab.llvm.org/buildbot/#/builders/10/builds/32840
https://lab.llvm.org/buildbot/#/builders/88/builds/24941
https://lab.llvm.org/buildbot/#/builders/225/builds/13974
Commit: bacfe2950f8218268fcc0a8765644ea0c15f0360
https://github.com/llvm/llvm-project/commit/bacfe2950f8218268fcc0a8765644ea0c15f0360
Author: Mikhail Romanov <mmromanov at ispras.ru>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M mlir/lib/Dialect/Transform/IR/TransformOps.cpp
Log Message:
-----------
[MLIR] Fix transform.apply_patterns with apply_cse option (#212818)
This patch fixes a crash in `transform.apply_patterns` when `apply_cse`
is enabled and the target operation does not have the
`IsolatedFromAbove` trait.
For non-`IsolatedFromAbove` targets, `transform.apply_patterns` cannot
apply patterns directly to the target operation. Instead, it collects
the operations within the target into a worklist and passes that
worklist to `applyOpPatternsGreedily`. When `apply_cse` is enabled,
pattern application and CSE are performed repeatedly until a fixpoint is
reached.
Previously, the worklist was collected only once before entering the
fixpoint loop. However, pattern application may erase operations from
the IR, leaving stale pointers in the cached worklist. Reusing this
worklist in subsequent iterations may therefore result in a crash.
This patch rebuilds the worklist at the beginning of each iteration,
ensuring that it always reflects the current IR state.
A representative reproducer is shown below:
```llvm
module attributes {transform.with_named_sequence} {
func.func @test(%A: tensor<128x256xf32>,
%B: tensor<256x512xf32>,
%C: tensor<128x512xf32>) -> tensor<128x512xf32> {
%res = linalg.matmul
ins(%A, %B : tensor<128x256xf32>, tensor<256x512xf32>)
outs(%C : tensor<128x512xf32>) -> tensor<128x512xf32>
return %res : tensor<128x512xf32>
}
transform.named_sequence @__transform_main(%root: !transform.any_op) {
%matmul = transform.structured.match
ops{["linalg.matmul"]}
in %root
: (!transform.any_op) -> !transform.any_op
%tiled, %loops:3 =
transform.structured.tile_using_for %matmul
tile_sizes [4, 4, 4]
: (!transform.any_op)
-> (!transform.any_op,
!transform.any_op,
!transform.any_op,
!transform.any_op)
transform.structured.vectorize %tiled : !transform.any_op
transform.apply_patterns to %loops#0 {
transform.apply_patterns.canonicalization
} {apply_cse} : !transform.any_op
transform.yield
}
}
```
Here, `transform.apply_patterns` is applied to the `scf.for` loop
produced by tiling, which is not `IsolatedFromAbove`. Running `mlir-opt
--transform-interpreter` on this example crashes before this change and
completes successfully with this patch.
Signed-off-by: Mikhail Romanov <mmromanov at ispras.ru>
Commit: a9749e8e26273338c6c115c0d70c538fa30bba85
https://github.com/llvm/llvm-project/commit/a9749e8e26273338c6c115c0d70c538fa30bba85
Author: Andre Kuhlenschmidt <akuhlenschmi at nvidia.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M flang/include/flang/Parser/tools.h
M flang/include/flang/Semantics/expression.h
M flang/lib/Parser/tools.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Semantics/modfile31.f90
M flang/test/Semantics/resolve60.f90
Log Message:
-----------
[flang][semantics] Accept BOZ initializers for C enum values (#211904)
Fortran 2023 7.6.1 errata f23/013 changes R762 so an interoperable
enumerator may be a named-constant initialized by a
boz-literal-constant, and specifies the value as
INT(boz-literal-constant, C_INT).
Handle that named-constant restriction directly in enum resolution while
preserving the usual scalar integer expression checks for non-enumerator
contexts. This mirrors the general named-constant initializer path,
which already converts BOZ values through the declared type before
folding.
Commit: 499db7987c994cf9a7742928bfd88ceb7bd12204
https://github.com/llvm/llvm-project/commit/499db7987c994cf9a7742928bfd88ceb7bd12204
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M clang/lib/CMakeLists.txt
Log Message:
-----------
Revert "[Clang] Don't build static analyzer if disabled" (#212836)
Breaks unusual build configs where clang-tidy static analyzer is enabled
while clang static analyzer is disabled.
Reverts llvm/llvm-project#212024
Commit: 5c57064076a189c457fc0cff463fb2090ccc7347
https://github.com/llvm/llvm-project/commit/5c57064076a189c457fc0cff463fb2090ccc7347
Author: Rafael Auler <rafaelauler at meta.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M bolt/include/bolt/Core/DebugData.h
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Core/DIEBuilder.cpp
M bolt/lib/Core/DebugData.cpp
M bolt/lib/Rewrite/DWARFRewriter.cpp
Log Message:
-----------
[BOLT] Stop materializing .dwo DIE vectors early in the pipeline (#207292)
Summary: preprocessDWODebugInfo() eagerly force-extracted every .dwo
compile unit's DIE tree (getNonSkeletonUnitDIE(false)) very early in
BOLT pipeline, way before DWARFRewriter kicked in. Those vectors then
sit in memory throughout the entire rewrite pipeline, directly
contributing to BOLT's RSS peak. I did a fair amount of digging and
didn't find any reason as to why we need to keep all DIEs of DWO CU
materialized at all, since DWARFRewriter won't even read this vector
(the #197359 concurrency fix did use that, but that is unnecessary). The
problem is that these DIE trees are a massive contribution to RSS when
processing large binaries where we have 10s of K of dwos, storing
complete trees for each processed dwo.
This diff changes the #197359 concurrency fix to not rely on the DIE
sibling/children structure. It parses DWP type units selectively per
compile unit (DIEBuilder::buildDWPTypeUnitsForUnit ->
collectReferencedTypeSignatures) by finding the DW_FORM_ref_sig8
references in a unit's DIEs to decide which type units belong in that
unit's output .dwo. That walk previously used DWARFDie::children(),
which requires the unit's full DIE vector. Here we rewrite the walk to
stream the unit's DIEs one at a time with
DWARFDebugInfoEntry::extractFast (the same technique already used by
DIEBuilder::constructFromUnit and DWARFRewriter::partitionCUs), reading
DW_FORM_ref_sig8 attributes off a single reusable transient entry. The
tree structure is irrelevant -- every DIE in the unit is visited
regardless -- so no DIE vector is
built. collectReferencedTypeSignatures now takes a DWARFUnit& instead of
a DWARFDie.
With the walk self-sufficient:
- preprocessDWODebugInfo() now extracts only the .dwo CU DIE
(getNonSkeletonUnitDIE(true)); nothing reads the full array off it
anymore (constructFromUnit and the signature walk both stream).
- BinaryContext::collectDebugScopeBoundaries() drops its split-DWARF
fast-path, which called DWARFUnit::dies() (= full extraction); DWO units
are now streamed like monolithic ones.
The result is that .dwo DIE vectors are never materialized during BOLT
processing.
Expected to be a ~10% RSS win on large split-dwarf binaries.
Depends on #207291
Commit: 9064e230ab52b82853dbe0d79c8cc75d708a0907
https://github.com/llvm/llvm-project/commit/9064e230ab52b82853dbe0d79c8cc75d708a0907
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M .github/CODEOWNERS
Log Message:
-----------
Add some bazel libc review coverage (#209789)
This should improve timezone coverage for keeping the bazel build
working due to libc breakages, e.g. #209433 broke things and the bazel
fixer bot sent out #209689. But since it wasn't landed until just
recently, manual fixes were needed for other changes like #209449. This
wouldn't be as bad if the bazel fixer bot could handle layered
breakages.
Commit: 834d585b7c6836996e7fd78ad3fe7675d7c490e2
https://github.com/llvm/llvm-project/commit/834d585b7c6836996e7fd78ad3fe7675d7c490e2
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
A llvm/test/tools/llubi/ptrtoint_cast.ll
M llvm/tools/llubi/lib/Context.cpp
M llvm/tools/llubi/lib/Interpreter.cpp
Log Message:
-----------
[llubi] Fix ptrtoint's return type (#212839)
Closes https://github.com/llvm/llvm-project/issues/212788.
Commit: 86fb40ddfa3c7cd5c32d758f4b1709d01028a7db
https://github.com/llvm/llvm-project/commit/86fb40ddfa3c7cd5c32d758f4b1709d01028a7db
Author: Kazu Hirata <kazu at google.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M llvm/include/llvm/ProfileData/SampleProfReader.h
M llvm/lib/Transforms/IPO/SampleProfile.cpp
M llvm/lib/Transforms/IPO/SampleProfileMatcher.cpp
M llvm/unittests/ProfileData/SampleProfTest.cpp
Log Message:
-----------
[ProfileData] Implement contains in SampleProfileNameTable (NFC) (#211995)
This patch implements contains(StringRef) and contains(uint64_t) in
SampleProfileNameTable and SampleProfileReader to serve symbol
membership queries directly from the reader -- "is this symbol in the
name table?".
Without this patch, users of the sample profile reader, namely
SampleProfileLoader::doInitialization and SampleProfileNameSet, each
construct their own StringSet<> containing all name table entries.
That is, we end up with two instances of StringSet<> with identical
contents. Since these instances hold their own copies of symbol
strings on the heap, both the constructor and destructor take up a
large portion of compilation time.
This patch teaches SampleProfileReader::contains to directly serve
symbol membership queries.
- For EytzingerSampleProfileNameTable, contains performs binary search
directly across the three concatenated Eytzinger table spans
(CSKeys, FlatKeys, and Inlinees) in a cache-friendly manner.
- Other representations of the name table lazily construct an internal
DenseSet on demand.
This patch updates existing customers to call Reader->contains.
RFC:
https://discourse.llvm.org/t/rfc-faster-sample-profile-loading/90957/8
Assisted-by: Antigravity
Commit: 6554a9709a9b9d12ec7eacd7c0a51eac5f94ddff
https://github.com/llvm/llvm-project/commit/6554a9709a9b9d12ec7eacd7c0a51eac5f94ddff
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M clang/test/Driver/aarch64-ptrauth.c
Log Message:
-----------
[PAC][clang][test] Fix incorrect usage of `-NOT` suffix for FileCheck (#212445)
Previously, `-NOT` checks were not doing what was intended: checking
that given strings are not present within the same line where other
patterns are confirmed present by other checks. `-NOT` semantics is
checking pattern absense in between other checks, not total absense.
This patch makes use of `--implicit-check-not` instead for this purpose.
Commit: 705d0ec6115cef3232eafe6221f42f78e7b884e8
https://github.com/llvm/llvm-project/commit/705d0ec6115cef3232eafe6221f42f78e7b884e8
Author: Maryam Moghadas <maryammo at ca.ibm.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M llvm/include/llvm/MC/MCGOFFStreamer.h
M llvm/lib/MC/MCGOFFStreamer.cpp
A llvm/test/CodeGen/SystemZ/zos-common-global.ll
Log Message:
-----------
[SystemZ][z/OS] Implement emitCommonSymbol in MCGOFFStreamer (#210179)
Common globals were not emitted in GOFF object files due to a missing
emitCommonSymbol implementation. This adds the implementation to emit
the required SD/ED/PR ESD records in the GOFF object file.
Commit: ae76985401e3e89e273e43da283f513c7316272d
https://github.com/llvm/llvm-project/commit/ae76985401e3e89e273e43da283f513c7316272d
Author: Sameer Sahasrabuddhe <sameer.sahasrabuddhe at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/docs/_static/custom.css
Log Message:
-----------
[Docs] don't stylize syntax errors in code blocks (#212698)
When a code block in the documentation contains (almost) pseudocode, the
Pygments parser flags errors and renders them with red-bordered boxes.
This is unnecessarily ugly. We can see examples of this in the LangRef
with LLVM code blocks.
Instead set the style to just render them as plain text. This is still
recognizable as incorrect syntax, but does not distract the reader from
the actual example.
Assisted-by: Claude Opus 4.8
Commit: b76b177fc93645cc5a6d2c1e0fc9d941415b1282
https://github.com/llvm/llvm-project/commit/b76b177fc93645cc5a6d2c1e0fc9d941415b1282
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.h
M llvm/test/Transforms/SLPVectorizer/X86/bv-shuffle-mask.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable-with-non-scheduled-parent-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/extracts-non-extendable.ll
M llvm/test/Transforms/SLPVectorizer/X86/ordering-bug.ll
M llvm/test/Transforms/SLPVectorizer/X86/reassociate-ops.ll
M llvm/test/Transforms/SLPVectorizer/X86/supernode.ll
Log Message:
-----------
[SLP] Gather operands of associative binary chains into one node
Flatten associative single-use chains like ((a+b)+c)+d into one N-ary
tree node instead of nested 2-operand entries, so vectorizable operand
groupings (consecutive loads, broadcasts) spanning the whole chain
aren't hidden by the nesting. The flattened layout is kept only when it
scores better than the natural 2-operand shape. Codegen combines the
columns pairwise, reusing a scalar's IR flags where a combine step
reproduces it exactly and dropping nsw/nuw/nnan/ninf otherwise, since
regrouping can change what may overflow or produce NaN/Inf. Controlled
by the hidden -slp-reassociate-ops flag (default on).
Reviewers: bababuck, RKSimon, hiraditya
Pull Request: https://github.com/llvm/llvm-project/pull/208514
Commit: 8e564ec0a2215967b1a305d9fd27200a5bece2b0
https://github.com/llvm/llvm-project/commit/8e564ec0a2215967b1a305d9fd27200a5bece2b0
Author: Finn Plummer <mail at inbelic.dev>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
A llvm/include/llvm/Frontend/HLSL/SemanticSignatures.h
M llvm/include/llvm/Support/DXILABI.h
M llvm/lib/Frontend/HLSL/CMakeLists.txt
A llvm/lib/Frontend/HLSL/SemanticSignatures.cpp
M llvm/unittests/Frontend/CMakeLists.txt
A llvm/unittests/Frontend/HLSLSemanticSignatureMetadataTest.cpp
Log Message:
-----------
[HLSL] Add in-memory representation of Semantic Signatures (#209907)
Defines the `SemanticSignatureElement` struct in
`llvm/Frontend/HLSL/SemanticSignatures` to represent a semantic
signature in-memory for use during packing and metadata
construction/parsing.
Adds unit testing of the conversion.
Resolves: https://github.com/llvm/llvm-project/issues/204878
Assisted by: Claude Opus 4.8
Commit: ec27629e6f82e17c5f900f6d16ad1d65766cd4e3
https://github.com/llvm/llvm-project/commit/ec27629e6f82e17c5f900f6d16ad1d65766cd4e3
Author: Adam Smith <adams at nvidia.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenStmt.cpp
M clang/lib/CIR/Dialect/Transforms/GotoSolver.cpp
M clang/test/CIR/CodeGen/goto-address-label-table.c
A clang/test/CIR/CodeGen/goto-indirect-cleanup-nyi.c
A clang/test/CIR/CodeGen/goto-indirect-nested.c
M clang/test/CIR/CodeGen/label-values.c
A clang/test/CIR/IR/goto-indirect.cir
M clang/test/CIR/Transforms/goto_solver.cir
Log Message:
-----------
[CIR] Defer indirect goto resolution to GotoSolver (#206176)
A computed `goto *p` placed inside a nested scope -- an if or a loop
body --
made CIRGen produce invalid IR that the region verifier rejected with
"reference to block defined in another region", aborting the compile.
Regular
`goto` avoids this because CIRGen emits a symbolic
`cir.goto` that references no block and is later resolved into a
`cir.br` by
GotoSolver, which runs after FlattenCFG has merged the nested scopes
into one
region. Indirect goto skipped that indirection: `emitIndirectGotoStmt`
built
a real indirect-branch block during CIRGen and branched to it from
inside the
nested region, and `finishIndirectBranch` wired the `cir.indirect_br`
successors at the end of the function -- both while the scopes were
still
separate regions.
This gives indirect goto the same symbolic treatment. A new terminator,
`cir.indirect_goto`, carries the target address and references no
successor,
so it is valid in any region. GotoSolver now rewrites each one into a
`cir.br` to a single shared block holding the `cir.indirect_br` over
every
address-taken label; running after FlattenCFG, it sees all blocks in one
region, so the cross-region branch can no longer occur. GotoSolver
already
collects the address-taken labels -- from `cir.block_address` ops and
from
block-address attributes in global initializers -- so the CIRGen-side
bookkeeping it supersedes (the lazily-built indirect-goto block, the
per-function target list, and the `CIRGenModule` block-address-to-label
map)
is removed.
An indirect goto that branches out of a scope needing cleanup (a VLA
stack
restore, or a non-trivial destructor on the edge) must run that cleanup
on the
branch, which this does not implement. Rather than emit a branch that
silently skips the cleanup, `emitIndirectGotoStmt` reports it with
`errorNYI`.
With the fix, the `evalloop`, `20041214-1`, and `comp-goto-1` programs
in the
LLVM test-suite go from a CIRGen crash to building and running.
Commit: ce0c2f8e3e66588ac8304fe3f5304652fac877fb
https://github.com/llvm/llvm-project/commit/ce0c2f8e3e66588ac8304fe3f5304652fac877fb
Author: Deric C. <cheung.deric at gmail.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.h
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/SemaHLSL/Availability/avail-diag-default-compute.hlsl
A clang/test/SemaHLSL/Resources/Textures-derivative-availability.hlsl
Log Message:
-----------
[HLSL] Add availability attributes to texture sample methods that require implicit derivatives (#212846)
This PR adds availability attributes to texture sample methods that
require implicit derivatives (fixes
https://github.com/llvm/llvm-project/issues/198885)
To make these availability attributes actually get checked,
`DiagnoseHLSLAvailability::HandleFunctionOrMethodRef` in `SemaHLSL.cpp`
has been changed to check availability attributes regardless of whether
or not a function has a body/definition (fixes
https://github.com/llvm/llvm-project/issues/212842).
Assisted by: Claude Opus 5
Commit: 13834ee4dc48abe421c9c13e65b67909f62624a0
https://github.com/llvm/llvm-project/commit/13834ee4dc48abe421c9c13e65b67909f62624a0
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRDialect.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Interfaces/CIROpInterfaces.h
M clang/include/clang/CIR/Interfaces/CIROpInterfaces.td
A clang/test/CIR/IR/fenv.cir
M clang/unittests/CIR/CMakeLists.txt
A clang/unittests/CIR/FenvOpTest.cpp
Log Message:
-----------
[CIR] Introduce fenv attribute for strict fp handling (#211144)
This introduces a new CIR attribute that will be used to describe
floating-point environment assumptions and restrictions, allowing for
general modeling of floating-point environment access. A new interface
is also introduced to simplify handling of default settings when the
attribute or one of its optional components is not present.
This patch adds the attribute and interface to FPBinaryOp,
BinaryFPToFPBuiltinOp, and UnaryFPToFPBuiltin. Support for generating
operations with this attribute and lowering them to the LLVM dialect
will be added in a future change.
Assisted-by: Cursor / claude-opus-4.8
Commit: 045fc453c8ccf78b1ccc0bd6b63a719645311cec
https://github.com/llvm/llvm-project/commit/045fc453c8ccf78b1ccc0bd6b63a719645311cec
Author: Philip DePetro <pdepetro at meta.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M lldb/test/API/commands/expression/expr-with-fork/TestExprWithFork.py
Log Message:
-----------
[lldb] Fix flaky test_expr_with_fork_trap by increasing expression timeout (#212574)
The test evaluates an expression that forks a child which returns
normally (triggering SIGTRAP from the JIT wrapper trap at _start). The
parent blocks in waitpid() until the detached child terminates. With the
default 250ms expression timeout, the kernel sometimes doesn't schedule
the detached child fast enough, causing waitpid() to still be blocking
when the timeout fires and the expression gets interrupted.
Set a 5-second expression timeout to give the kernel ample time to
schedule the detached child process.
Commit: 8a50e79aabbde1b669c939c35b752864d25af2eb
https://github.com/llvm/llvm-project/commit/8a50e79aabbde1b669c939c35b752864d25af2eb
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M clang/lib/CIR/Dialect/Transforms/FlattenCFG.cpp
Log Message:
-----------
[CIR] Switch FlattenCFGPass to no longer use greedy manager. (#211368)
This showed up doing a self-build of MLIR's Presburger
IntegerRelation.cpp, which is a bit pathalogical. It resulted in us
doing a lot of rewrite patterns during flatten, taking about 20s. After
this patch, we're down to sub-1s spent doing that.
This is because applyOpPatternsGreedily was re-enqueing every child
opops every time we modified anything nearby. This caused us in cases
where there were operations that were visited TONS of times just because
a parent got modified.
This patch replaces this with a very simple inside-out iteration of
these operations. The recent loop-op 'cleanup' flattening modification
necessitates us re-visiting these sometimes (hence the loop).
This patch is effectively 'NFC' other than build time, so there really
isn't a test I could write.
AI: Note: I've used Claude Opus 4.8 to help me with this patch. I've
read/attempted to comprehend as much of this as possible, but I'm still
pretty inexperienced as to how to manage passes/etc. Claude promises me
this is the best way, and I haven't been able to find anything better
grepping around other transformations in other projects, but please
comment if you have a better idea!
Commit: 8c4dce6ba0d1eb7d6cc273bdd7496f7bfc4162e3
https://github.com/llvm/llvm-project/commit/8c4dce6ba0d1eb7d6cc273bdd7496f7bfc4162e3
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
A clang/test/CIR/CodeGen/arithmetic-fence-builtin.c
Log Message:
-----------
[CIR] Implement non-reassoc __arithmetic_fence (#211915)
This builtin is a no-op (just a load/store) if we don't have reassociate
turned on. This patch implements the 'easy' path to unblock libraries
that use this builtin.
Commit: b9afaf239da61761b870921941bcee1279da0373
https://github.com/llvm/llvm-project/commit/b9afaf239da61761b870921941bcee1279da0373
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M clang/test/Driver/invalid-target-id.cl
M clang/test/Driver/openmp-invalid-target-id.c
Log Message:
-----------
clang/AMDGPU: Add missing driver tests for invalid target names (#212451)
Make sure -march and -mcpu both error for nonoffload and for
-Xopenmp-target arguments. Defends against regression I almost
introduced.
Commit: 1d894ed4930663405e7aed2b608d7f04a709c4e5
https://github.com/llvm/llvm-project/commit/1d894ed4930663405e7aed2b608d7f04a709c4e5
Author: Ian Anderson <iana at apple.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M llvm/test/MC/MachO/target-triple-padding.s
M llvm/test/MC/MachO/target-triple.s
M llvm/test/Object/Inputs/macho-invalid-target-triple-name_offset-toosmall.yaml
M llvm/test/Object/Inputs/macho-invalid-target-triple-name_toobig.yaml
Log Message:
-----------
[llvm][macho][test] Fix failing target triple tests (#212876)
`llvm-mc -triple arm64-*` requires aarch64-registered-target.
Commit: f3159b97be5deff08b5bcb6a5d4cf71c991b5555
https://github.com/llvm/llvm-project/commit/f3159b97be5deff08b5bcb6a5d4cf71c991b5555
Author: Ryan Buchner <rbuchner at qti.qualcomm.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/RISCV/external.ll
Log Message:
-----------
[SLP] Precommit test for deferred extracts (#212658)
Tests for #211680.
Commit: 738cbf1883083525a76a6eeb30671ea778661bd3
https://github.com/llvm/llvm-project/commit/738cbf1883083525a76a6eeb30671ea778661bd3
Author: Christopher Ferris <cferris1000 at users.noreply.github.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M compiler-rt/lib/scudo/standalone/combined.h
M compiler-rt/lib/scudo/standalone/primary32.h
M compiler-rt/lib/scudo/standalone/primary64.h
M compiler-rt/lib/scudo/standalone/tests/combined_test.cpp
M compiler-rt/lib/scudo/standalone/tests/primary_test.cpp
M compiler-rt/lib/scudo/standalone/wrappers_c.cpp
Log Message:
-----------
[scudo] Fix all deadlocks with condition code variables. (#212604)
Added a ScopedFLLock that automatically handles notify calls if there
are waiters. Replace all ScopedLock of FLLock with this new
ScopedFLLock. Updated the enable function to properly notify FLLock
waiters if necessary.
Added a new function for re-enabling in the child process after a fork
to clear the variables used by the condition code.
Commit: 739bf5e18d9df470c540c5c61f086c95ae5aa370
https://github.com/llvm/llvm-project/commit/739bf5e18d9df470c540c5c61f086c95ae5aa370
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M lldb/include/lldb/lldb-enumerations.h
M lldb/source/Core/Section.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/ObjectFile/wasm/ObjectFileWasm.cpp
M lldb/source/Plugins/ObjectFile/wasm/ObjectFileWasm.h
A lldb/source/Plugins/ObjectFile/wasm/WasmAddress.h
M lldb/source/Plugins/Process/wasm/ProcessWasm.cpp
M lldb/source/Plugins/Process/wasm/ProcessWasm.h
M lldb/source/Symbol/ObjectFile.cpp
M lldb/test/API/functionalities/gdb_remote_client/TestWasm.py
A lldb/test/Shell/ObjectFile/wasm/wasm-globals.yaml
Log Message:
-----------
[lldb] Add support for Wasm globals (#212516)
WebAssembly globals are not addressable: they live in an index space of
their own and hold values (rather than bytes) in the module, or need to
be read from the runtime.
Give them a synthetic address space in which an address holds the global
index where it would otherwise hold an offset, and a section spanning
that index space so a global becomes a symbol. With a process, a read of
such an address asks the engine over qWasmGlobal. Without one, the
object file serves the initializer, which is all that is known before
the module is instantiated.
The section is based in a range of its own rather than at zero. Code and
linear memory are both addressed from zero, so a global index would
otherwise name a code or data address as well.
The import section now parses each import descriptor by kind, because
the global index space includes imported globals and finding the next
import means knowing the shape of the current one.
Commit: 1842e2d1e66cdf850d6afdd3a16506175097fd78
https://github.com/llvm/llvm-project/commit/1842e2d1e66cdf850d6afdd3a16506175097fd78
Author: Ian Anderson <iana at apple.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M clang/lib/Basic/Targets/OSTargets.h
M clang/test/Sema/darwin-tls.c
Log Message:
-----------
[clang][darwin] Firmware needs to support thread local storage (#212657)
rdar://182496170
Commit: 20fd9488f9b5eb50e4b2c595faa8018b2728cb27
https://github.com/llvm/llvm-project/commit/20fd9488f9b5eb50e4b2c595faa8018b2728cb27
Author: Qiongsi Wu <qiongsiwu at gmail.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
A clang/test/ClangScanDeps/modules-async-scan.c
Log Message:
-----------
[clang][DependencyScanning] Adding a test that exercies the async-scanning code path (#211402)
This PR adds a test that exercises the async-scanning code path to
sanity check that async-scanning generates identical results as TU
scanning.
---
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href="https://github.com/github/gh-stack">GitHub Stacks CLI</a> • <a
href="https://gh.io/stacks-feedback">Give Feedback 💬</a></sub>
Commit: 316a29603228c5d5000e0ddf8dfba2a494ac7ee9
https://github.com/llvm/llvm-project/commit/316a29603228c5d5000e0ddf8dfba2a494ac7ee9
Author: Qiongsi Wu <qiongsiwu at gmail.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
A clang/test/ClangScanDeps/canonicalize-macros-multiarch.c
Log Message:
-----------
[clang][DependencyScanning] Adding a Multiarch clang-scan-deps Test (#211404)
This test adds coverage of multiarch scanning command macro
canonicalization.
---
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href="https://github.com/github/gh-stack">GitHub Stacks CLI</a> • <a
href="https://gh.io/stacks-feedback">Give Feedback 💬</a></sub>
Commit: 5c49c5fa5678dffdaa7e6c19b83e52a5b89cfbc2
https://github.com/llvm/llvm-project/commit/5c49c5fa5678dffdaa7e6c19b83e52a5b89cfbc2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
R llvm/test/TableGen/RuntimeLibcallEmitter-conflict-warning.td
A llvm/test/TableGen/RuntimeLibcallEmitter-multiple-impls.td
M llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp
Log Message:
-----------
RuntimeLibcalls: Emit all available impls for a libcall, not just one (#210915)
The intent is RuntimeLibcalls should represent all functions that are
callable from the module, which may have contextually selectable
alternatives. Previously we had this warning since there was no mechanism
to select which one you want, and as a workaround the library call sets avoided
adding the variants which should nto be selected.
Now targets can use initLibcallLoweringInfo, so remove the warning to
unblock more libcall cleanups. Eventually initLibcallLoweringInfo should also
be tablegen driven.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 1b161aad81546fc7ea42f3c14d29b02065197e55
https://github.com/llvm/llvm-project/commit/1b161aad81546fc7ea42f3c14d29b02065197e55
Author: joaosaffran <joaosaffranllvm at gmail.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/HLSLIntrinsics.td
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/Headers/hlsl/hlsl_intrinsic_helpers.h
M clang/test/CodeGenHLSL/builtins/cross.hlsl
M clang/test/SemaHLSL/BuiltIns/cross-errors.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
R llvm/test/CodeGen/DirectX/cross.ll
R llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cross.ll
Log Message:
-----------
[HLSL] Move cross implementation to header files (#211446)
This patch removes the previous implementation of cross; instead, it
adds a new one inside the header files.
Fix: https://github.com/llvm/llvm-project/issues/135425
Assisted by: Claude Opus 4.8
---------
Co-authored-by: Joao Saffran <jderezende at microsoft.com>
Commit: 17efc66a340e35ae03a18e34e7f267832fff7940
https://github.com/llvm/llvm-project/commit/17efc66a340e35ae03a18e34e7f267832fff7940
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 739bf5e (#212885)
This fixes 739bf5e18d9df470c540c5c61f086c95ae5aa370 (#212516).
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=739bf5e18d9df470c540c5c61f086c95ae5aa370
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: ade128740327db281859708ddcb3b072903b3414
https://github.com/llvm/llvm-project/commit/ade128740327db281859708ddcb3b072903b3414
Author: Augusto Noronha <anoronha at apple.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M llvm/lib/DWARFLinker/Classic/DWARFLinker.cpp
A llvm/test/tools/dsymutil/X86/keep-enumerators.test
Log Message:
-----------
[DWARFLinker] Keep DW_TAG_enumerator children of a live enumeration_type (#212849)
Swift allows functions inside enums:
enum Foo: Int {
case bar = 0
func baz() { ... }
}
DW_TAG_enumeration_type "Foo"
DW_TAG_enumerator "bar"
DW_TAG_subprogram "baz" DW_AT_declaration
...
DW_TAG_subprogram DW_AT_low_pc(...) DW_AT_specification -> "baz"
dieNeedsChildrenToBeMeaningful() did not list DW_TAG_enumeration_type,
so the parent walk skipped the enum's children.
Assisted-by: claude
rdar://183549452
Commit: 64dfcdb01ffa6aac06f6cf3b4ed7a4f8ce74c986
https://github.com/llvm/llvm-project/commit/64dfcdb01ffa6aac06f6cf3b4ed7a4f8ce74c986
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/test/CIR/IR/fenv.cir
M clang/unittests/CIR/FenvOpTest.cpp
Log Message:
-----------
[CIR] Add fenv attribute to more builtins (#212880)
This adds the #cir.fenv attribute to the CIR_UnaryFPToIntBuiltinOp and
CIR_TernaryFPToFPBuiltinOp base classes, and through them to the
cir.lround, cir.llround, cir.lrint, cir.llrint, and cir.fma operations.
This attribute is still missing from various cast and compare
operations. Those will be added in a follow-up change.
Assisted-by: Cursor / various models
Commit: b0541c38cd786cc4abeec921a92a9b0153c188a4
https://github.com/llvm/llvm-project/commit/b0541c38cd786cc4abeec921a92a9b0153c188a4
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/CoreEngine.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/ExprEngine.h
M clang/lib/StaticAnalyzer/Checkers/AnalyzerStatsChecker.cpp
M clang/lib/StaticAnalyzer/Core/CoreEngine.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
Log Message:
-----------
[NFC][analyzer] Remove BlockEdge parameter of processCFGBlockEntrance (#212804)
As a side effect of my previous refactoring efforts, the method
`ExprEngine::processCFGBlockEntrance` had two very similar parameters: a
`BlockEdge` and a `BlockEntrance` instance.
These are both subclasses of `ProgramPoint`, stored the same data (the
`BlockEntrance` was initialized with data taken from the `BlockEdge`
just before the call) and the `BlockEdge` was almost completely unused
within `processCFGBlockEntrance`.
The only reason for having the `BlockEdge` was that it was stored in the
debug statistic table `blocksExhausted`; so this commit transitions that
simple debug code to use `BlockEntrance` instances instead (which is
also perfectly sufficient for its goals). This allows the removal of the
redundant argument of `processCFGBlockEntrance`.
This prepares the ground for further cleanup in this method.
Commit: 0d1c3c0ba49bf35f272b0b3baa1fb880e641b9c4
https://github.com/llvm/llvm-project/commit/0d1c3c0ba49bf35f272b0b3baa1fb880e641b9c4
Author: Adam Smith <adams at nvidia.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Dialect/IR/CIRTypeConstraints.td
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/test/CIR/CodeGen/enum-bool.cpp
M clang/test/CIR/IR/cmp.cir
Log Message:
-----------
[CIR] Allow boolean operands in cir.cmp (#206846)
GROMACS uses scoped enums with a boolean underlying type as type-safe
flags (`enum class EmulateGpuNonbonded : bool`), and compares them with
`==` / `!=` / `<`. A scoped enum is not integer-promoted before the
comparison, so the operand reaches `cir.cmp` as a `!cir.bool` (CIR
already
represents a boolean-underlying enum with `!cir.bool`). The `cir.cmp`
operand constraint `CIR_ComparableType` does not list bool, so module
verification fails before the CIR-to-CIR passes with:
```
'cir.cmp' op operand #0 must be comparable type, but got '!cir.bool'
```
Add bool to `CIR_ComparableType` and let the comparison lowering compare
`!cir.bool` the same way it already compares pointers, as an unsigned
`icmp` (`ult` for `<`), which is what classic CodeGen does with these as
`i1`. Plain `bool` comparisons are unchanged, since they still carry the
AST integral promotion and compare as `i32`, and unscoped `enum : bool`
still promotes too.
Six translation units in a minimal GROMACS build hit this
(`taskassignment/decidegpuusage`, `mdrun/runner`, the three `domdec`
topology files, and a gtest-based test), and they compile under
`-fclangir` with the fix. `enum-bool.cpp` covers all six comparison
predicates, and `cmp.cir` gains an unpromoted `!cir.bool` round-trip
next to the existing promoted one. The signature checks in
`enum-bool.cpp` are split into `LLVMCIR` and `OGCG`
because classic codegen marks these `i1` values `zeroext` and CIR does
not, which is call-conv lowering being off in the default pipeline
rather
than anything specific to bool.
Commit: 76403ad686f735341f765603978c30b92cc1617b
https://github.com/llvm/llvm-project/commit/76403ad686f735341f765603978c30b92cc1617b
Author: Zhen Wang <zhenw at nvidia.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M flang/include/flang/Evaluate/tools.h
M flang/test/Lower/CUDA/cuda-managed-assign.cuf
Log Message:
-----------
[flang][cuda] Keep data transfers for allocatable assignments with device data (#212855)
An assignment to a whole allocatable was lowered as a host assignment to
keep reallocation semantics, without checking the memory kind, so a
device allocatable assigned from a managed array wrote device memory
from the host and segfaulted.
Keep the transfer when either side is device or constant data. CUDA
Fortran Programming Guide 3.4.1 makes an assignment between managed and
device data a copy in both directions, with no exception for an
allocatable left-hand side.
Commit: a9349342b25dbf68cd89c432f5c808a58742b77a
https://github.com/llvm/llvm-project/commit/a9349342b25dbf68cd89c432f5c808a58742b77a
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
M flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
M flang/test/Fir/CUDA/cuda-constructor-2.f90
Log Message:
-----------
[flang][cuda] Unify registration under -gpu=mem:unified (#212871)
Always use the cuf operation under -gpu=unified as registration might be
differed to the backend. Add a UnitAttr to distinguish device resident
variable that will not use cudaRegisterHostVar but cudaRegisterVar.
Commit: cd1db2648ecd53b7a67faf7cc2acd1d0a63777e0
https://github.com/llvm/llvm-project/commit/cd1db2648ecd53b7a67faf7cc2acd1d0a63777e0
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/unittests/CIR/BUILD.gn
Log Message:
-----------
[gn build] Port 13834ee4dc48 (#212896)
Commit: c4dbdfc12e8ab5e7df90bde1aedbec566e552f09
https://github.com/llvm/llvm-project/commit/c4dbdfc12e8ab5e7df90bde1aedbec566e552f09
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Frontend/HLSL/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Frontend/BUILD.gn
Log Message:
-----------
[gn build] Port 8e564ec0a221 (#212897)
Commit: 2815f298d1fae984188d3854acd6f0ca503fcd53
https://github.com/llvm/llvm-project/commit/2815f298d1fae984188d3854acd6f0ca503fcd53
Author: Deric C. <cheung.deric at gmail.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/SemaHLSL/Resources/Textures-double-element-type-errors.hlsl
A clang/test/SemaHLSL/Resources/Textures-integer-element-type.hlsl
Log Message:
-----------
[HLSL] Add sema for use of samplers and gathers on textures of doubles and ints (#212613)
Fixes https://github.com/llvm/llvm-project/issues/198882 and
https://github.com/llvm/llvm-project/issues/198883
This PR:
- Implements sema checks to reject the use of samplers and gathers on
textures of doubles.
- Implements sema checks to reject use of samplers on textures of
integers before shader model 6.7
Assisted by: Claude Opus 5
Commit: c56ea6d942e7160d6d2ec82ace17a31c7806ae9e
https://github.com/llvm/llvm-project/commit/c56ea6d942e7160d6d2ec82ace17a31c7806ae9e
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/MacroFusion.h
M llvm/lib/CodeGen/MacroFusion.cpp
M llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp
M llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
M llvm/lib/Target/ARM/ARMMacroFusion.cpp
M llvm/lib/Target/PowerPC/PPCMacroFusion.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/lib/Target/X86/X86MacroFusion.cpp
M llvm/test/TableGen/MacroFusion.td
M llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp
Log Message:
-----------
[MacroFusion] Add SDep param to predicates(NFC) (#212255)
This patch aims to extend the API for macro fusion predicates with an
additional SDep param which allows each predicate to individually decide
wether a pair should be macro fused based on the kind of dependency
between the 2 instructions.
A followup patch https://github.com/llvm/llvm-project/pull/212603
introduces a real user in AArch64.
Commit: 397743f4301326b23f70d0f8505090eb8be30dcf
https://github.com/llvm/llvm-project/commit/397743f4301326b23f70d0f8505090eb8be30dcf
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenStmt.cpp
M clang/test/CIR/CodeGen/complex.cpp
Log Message:
-----------
[CIR] Implement complex rvalues NYI (#211645)
emitReturnOfRValue had an NYI for _Complex types, so returning one as an
Rvalue (see example of a lambda invoker) would NYI. Since the logic to
the store is already handled in the lower-to-LLVM, this ended up being a
pretty trivial patch.
Note; There are some differences in how this lowers, because our calling
convention for the ret is different here, and we maintain the 'complex'
type differently even through LLVM-IR. However, the IR looks to be
equivilent.
Commit: d998634dbeaa1b651026f1180043f68ba62c2313
https://github.com/llvm/llvm-project/commit/d998634dbeaa1b651026f1180043f68ba62c2313
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/test/Driver/aarch64-ptrauth.c
Log Message:
-----------
[PAC][clang] Enable `-fptrauth-elf-got` as part of pauthtest (#212446)
Commit: 3ca8b6e0afef0370c189721f71cb9092ea8009fd
https://github.com/llvm/llvm-project/commit/3ca8b6e0afef0370c189721f71cb9092ea8009fd
Author: Ayokunle Amodu <ayokunle321 at gmail.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinNVPTX.cpp
M clang/test/CIR/CodeGenCUDA/builtins-nvvm-atomic.cu
Log Message:
-----------
[CIR][CUDA] Add support for NVVM xchg builtins (#211815)
Adds codegen support for the scoped and unscoped NVVM atomic exchange
builtins:
`atom_xchg,` `atom_cta_xchg,` and `atom_sys_xchg.`
These are lowered to the corresponding CIR `cir.atomic.xchg` operations
and subsequently lowered to LLVM `atomicrmw xchg` instructions.
Commit: 5e0a2aa0d72b832ee9a9b2f29d6183e1d94f4354
https://github.com/llvm/llvm-project/commit/5e0a2aa0d72b832ee9a9b2f29d6183e1d94f4354
Author: compilersutra <osc at compilersutra.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/test/CodeGen/X86/win64-eh-unwindv2-errors.mir
Log Message:
-----------
[X86] Make WinEH crash test reliable under ASan (#212820)
The WinEH unwind `v2 error` test uses `not --crash` for malformed MIR
inputs.
In AddressSanitizer builds, the default `abort_on_error=0` can prevent
the
expected fatal error from being reported as a crash, causing FileCheck
to
receive no diagnostic output.
Set `ASAN_OPTIONS=abort_on_error=1` for the expected-crash invocations
in
`win64-eh-unwindv2-errors.mir`.
## Testing
- ASan build focused test passes.
- Non-ASan build focused test passes.
- Five additional serial ASan reruns pass.
- `git diff --check` passes.
Fixes #212684
Co-authored-by: aabhinavg1 <tiwariabhinavak at gmail.com>
Commit: e82a934f56d27a06168d2e8c04edf3b223f4920f
https://github.com/llvm/llvm-project/commit/e82a934f56d27a06168d2e8c04edf3b223f4920f
Author: Anshul Nigham <nigham at google.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M llvm/docs/_static/custom.css
Log Message:
-----------
[docs] de-highlight code snippet errors in dark mode (#212894)
Apply https://github.com/llvm/llvm-project/pull/212698 to dark mode as
well as light mode.
Commit: 3889ccc1a35fdd3f18eecbc01663534fb3f64478
https://github.com/llvm/llvm-project/commit/3889ccc1a35fdd3f18eecbc01663534fb3f64478
Author: wieDasDing <6884440+dingxiangfei2009 at users.noreply.github.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M llvm/lib/MC/MCParser/MasmParser.cpp
A llvm/test/tools/llvm-ml/textequ_expansion.asm
Log Message:
-----------
[llvm-ml] make TEXTEQU directive not to eagerly expand macros in arguments (#209526)
We observed a crash in `TEXTEQU` that pastes two macros into one.
```masm
.data
part1 TEXTEQU <1>
part2 TEXTEQU <0>
joined TEXTEQU part1, part2 ; crash
```
`part1` is immediately rewritten into `1` as integer, which is rejected
by `TEXTEQU` parser. We need to keep `part1` as identifier for `TEXTEQU`
to pick up later.
Commit: e7b04c15e6b18294c923f874f16e2d5a8e885706
https://github.com/llvm/llvm-project/commit/e7b04c15e6b18294c923f874f16e2d5a8e885706
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M libc/include/CMakeLists.txt
M libc/include/dirent.yaml
M libc/include/llvm-libc-macros/CMakeLists.txt
A libc/include/llvm-libc-macros/dirent-macros.h
M libc/include/llvm-libc-macros/linux/CMakeLists.txt
A libc/include/llvm-libc-macros/linux/dirent-macros.h
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/reclen_t.h
M libc/include/llvm-libc-types/struct_dirent.h
A libc/include/llvm-libc-types/struct_posix_dent.h
M libc/test/src/dirent/dirent_test.cpp
Log Message:
-----------
[libc] Modernize and extend dirent.h header. (#212902)
Extend the `<dirent.h>` header with macro and types specified in recent
POSIX.1-2024:
* Add `posix_dent` structure, which has more fields than `dirent`, that
are actually used in practice. This struct would be identical to
`dirent` that we have on Linux
* Add `reclen_t` type for `d_reclen` field.
* Add macro `DT_BLK` and friends
Also, extend the tests to verify the values of `d_type` field, now that
we have the proper macro defined.
Assisted by: Gemini, human-verified
Commit: 5857e09ae75d08c93de717f5a2e1c0e2c1ddd06f
https://github.com/llvm/llvm-project/commit/5857e09ae75d08c93de717f5a2e1c0e2c1ddd06f
Author: Finn Plummer <mail at inbelic.dev>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M llvm/unittests/Frontend/HLSLSemanticSignatureMetadataTest.cpp
Log Message:
-----------
[NFC][HLSL] Fix msan errors in tests (#212901)
Some of the tests were not initializing all the fields prior to
generating metadata, this caused a read of uninitialized memory and
caused the sanitizer to fail.
Assisted by: Claude Opus 5
Caught here: https://lab.llvm.org/buildbot/#/builders/94/builds/19767
Commit: 1a5fc1c6b6bfff561f767d5e2ffe8b0a7d81cb34
https://github.com/llvm/llvm-project/commit/1a5fc1c6b6bfff561f767d5e2ffe8b0a7d81cb34
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/Passes.td
M mlir/lib/Dialect/Linalg/Transforms/FoldIntoElementwise.cpp
M mlir/test/Dialect/Linalg/elementwise/fold.mlir
Log Message:
-----------
[mlir] [linalg] Fold broadcast/transpose into linalg.generic (#212415)
Currently we are able to fold broadcast/transpose into
linalg.elementwise. This patch extends the ability to fold
broadcast/transpose into linalg.generic.
For example,
```
%empty = tensor.empty() : tensor<8x16xf32>
%broadcasted = linalg.broadcast ins(%A : tensor<8xf32>) outs(%empty : tensor<8x16xf32>) dimensions = [1]
%result = linalg.generic {
indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>,
affine_map<(d0, d1) -> (d0, d1)>],
iterator_types = ["parallel", "parallel"]
} ins(%broadcasted : tensor<8x16xf32>) outs(%B : tensor<8x16xf32>) {
^bb0(%in: f32, %out: f32):
%v = arith.addf %in, %in : f32
linalg.yield %v : f32
} -> tensor<8x16xf32>
```
we can fold the broadcast into:
```
%result = linalg.generic {
indexing_maps = [affine_map<(d0, d1) -> (d0)>,
affine_map<(d0, d1) -> (d0, d1)>],
iterator_types = ["parallel", "parallel"]
} ins(%A: tensor<8xf32>) outs(%B : tensor<8x16xf32>) {
^bb0(%in: f32, %out: f32):
%v = arith.addf %in, %in : f32
linalg.yield %v : f32
} -> tensor<8x16xf32>
```
For simplicity, we only consider all parallel linalg.generic right now.
AI assisted.
Commit: 44a11330d9c246c7c042c16f26a10373956731f7
https://github.com/llvm/llvm-project/commit/44a11330d9c246c7c042c16f26a10373956731f7
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M lldb/bindings/python/CMakeLists.txt
M lldb/docs/CMakeLists.txt
A lldb/examples/python/templates/scripted_string_summary.py
M lldb/include/lldb/API/SBTypeSummary.h
M lldb/include/lldb/DataFormatters/TypeSummary.h
A lldb/include/lldb/Interpreter/Interfaces/ScriptedStringSummaryInterface.h
M lldb/include/lldb/Interpreter/ScriptInterpreter.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/include/lldb/lldb-forward.h
M lldb/source/API/SBTypeSummary.cpp
M lldb/source/Commands/CommandObjectType.cpp
M lldb/source/DataFormatters/TypeSummary.cpp
M lldb/source/Interpreter/ScriptInterpreter.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/CMakeLists.txt
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPythonInterface.h
A lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedStringSummaryPythonInterface.cpp
A lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedStringSummaryPythonInterface.h
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
Log Message:
-----------
[lldb/script] Add class-based summary providers via ScriptedStringSummaryInterface (#210469)
Commit: dc57785129b1e3dfd489ef8c39e74a262d90a0c2
https://github.com/llvm/llvm-project/commit/dc57785129b1e3dfd489ef8c39e74a262d90a0c2
Author: Jianjian Guan <jacquesguan at me.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
A clang/test/CIR/CodeGenBuiltins/RISCV/riscv-xandesperf-rv32.c
A clang/test/CIR/CodeGenBuiltins/RISCV/riscv-xandesperf-rv64.c
Log Message:
-----------
[CIR][RISCV] Support XAndesPerf builtins (#211490)
Commit: bdddd3e7202477e37c0a73dd036a0377d762f2e6
https://github.com/llvm/llvm-project/commit/bdddd3e7202477e37c0a73dd036a0377d762f2e6
Author: Zane Hambly <zanehambly at gmail.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
A llvm/test/MC/X86/intel-syntax-data32-16.s
Log Message:
-----------
[X86] Apply the data32 mode switch in the Intel matcher (#212417)
In .code16, `data32 push 8` in Intel syntax assembled as `pushw $8` with
the 66 prefix dropped, and `data32 push 0x1234` truncated the immediate
to 16 bits. AT&T syntax gets both right.
`ForcedDataPrefix` is set while parsing either syntax, but only
`matchAndEmitATTInstruction` switched mode on it, so the Intel path took
the operand size from the mode and never saw the prefix.
Do the same switch in `matchAndEmitIntelInstruction`. The mode has to go
back to 16-bit before the instruction is emitted, otherwise the 32-bit
form is emitted without its 66 prefix. That function has several error
returns partway through matching, so a scope guard covers those.
Encodings after the change match both AT&T syntax and GNU as:
```
data32 push 8 [0x6a,0x08] -> [0x66,0x6a,0x08]
data32 push 0x1234 [0x68,0x34,0x12] -> [0x66,0x68,0x34,0x12,0x00,0x00]
```
Fixes #156286
Commit: a01f8c85bcac35be5b6b9d5f081a3763feb5b530
https://github.com/llvm/llvm-project/commit/a01f8c85bcac35be5b6b9d5f081a3763feb5b530
Author: higher-performance <higher.performance.github at gmail.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M libcxx/include/variant
Log Message:
-----------
Speed up compilation of typical invocations of std::visit(std::variant<...>) for up to 11 types (#164196)
Similar to https://reviews.llvm.org/D90168 which was reverted (https://github.com/llvm/llvm-project/issues/62648#issuecomment-1832315651), but uses `switch` statements rather than function pointer tables.
Commit: 7ded638ea33b96d9fd628e2a5cbc06df12ede153
https://github.com/llvm/llvm-project/commit/7ded638ea33b96d9fd628e2a5cbc06df12ede153
Author: William Tran-Viet <wtranviet at proton.me>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M libcxx/include/CMakeLists.txt
A libcxx/include/__fwd/optional.h
A libcxx/include/__optional/common.h
A libcxx/include/__optional/comparison.h
A libcxx/include/__optional/hash.h
A libcxx/include/__optional/make_optional.h
A libcxx/include/__optional/nullopt_t.h
A libcxx/include/__optional/optional.h
A libcxx/include/__optional/optional_ref.h
A libcxx/include/__optional/swap.h
M libcxx/include/module.modulemap.in
M libcxx/include/optional
M libcxx/test/std/experimental/iterator/ostream.joiner/ostream.joiner.creation/make_ostream_joiner.pass.cpp
M libcxx/test/std/experimental/iterator/ostream.joiner/ostream.joiner.ops/ostream_joiner.op.assign.pass.cpp
M libcxx/test/std/utilities/optional/optional.bad_optional_access/derive.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/ctor.verify.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/deduct.verify.cpp
M libcxx/test/std/utilities/optional/optional.object/optional_requires_destructible_object.verify.cpp
Log Message:
-----------
[libc++] Granularize `<optional>` (#206644)
Certain headers require `optional<T&>`, so it may be beneficial to split
out `optional<T>` and `optional<T&>`. This can allow consumers to only
bring in the `optional` flavour it needs..
- Parcel out the respective pieces into their own header.
- Certain sources rely on transitive includes brought in by
`<optional>`, so they're kept there for now, and only tests have been
fixed.
---------
Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
Commit: 693d0a9d04fcbdd20730922f3218cfed701d3004
https://github.com/llvm/llvm-project/commit/693d0a9d04fcbdd20730922f3218cfed701d3004
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCompatibilityAnalysis.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCompatibilityAnalysis.h
Log Message:
-----------
[SLP][modularisation][NFC] Extract InstructionsState (2/3) (#211461)
Move the InstructionsState class out of SLPVectorizer.cpp into the
existing private module SLPVectorizer/SLPCompatibilityAnalysis.{h,cpp}.
The class declaration (with trivial accessors) lives in the header; the
non-trivial method bodies are defined out-of-line in the .cpp:
isSameOperation
getMatchingMainOpOrAltOp
isMulDivLikeOp
isAddSubLikeOp
isCopyableElement
isExpandedBinOp
isExpandedOperand
isNonSchedulable
Part of the effort to modularize SLPVectorizer.cpp. See the RFC:
https://discourse.llvm.org/t/modularizing-slpvectorizer-cpp/90922
Commit: c94c7cc893d72dfa37c1cfe667ea9dac6da5e4a4
https://github.com/llvm/llvm-project/commit/c94c7cc893d72dfa37c1cfe667ea9dac6da5e4a4
Author: agozillon <Andrew.Gozillon at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp
M flang/test/Lower/OpenMP/defaultmap.f90
Log Message:
-----------
[Flang][OpenMP] Remove present modifier application on descriptor (#211856)
This was a minor change upstreamed in the original PR:
https://github.com/llvm/llvm-project/pull/208133
However, it is a modification that needs a little more thought from a
specification perspective before it is rolled out, there's a number of
code bases that depend on the presence modifier being applied only to
the underlying data. However, this leads to inconsistencies when a user
makes use of any reference semantic modifiers when mapping as they
SHOULD be allowed to specify present applying to the descriptor. So, we
need to work out what the correct defualt behaviour is, and regardless
of the default support a user intentionally specifying presence
application on a descriptor via reference semantics.
For now, we will revert to previous state.
Commit: e5359187080a4250c40fe9aee8b1cb9b518a63ef
https://github.com/llvm/llvm-project/commit/e5359187080a4250c40fe9aee8b1cb9b518a63ef
Author: Anutosh Bhat <andersonbhat491 at gmail.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/AArch64/extract-fmul-cost.ll
Log Message:
-----------
[AArch64][SLP][NFC] Precommit scalar fmul extract cost test (#212837)
Precommit a baseline SLP test for the AArch64 scalar fmul extract cost.
The current cost model overestimates the cost of the lane-1 use, so only
one of the two fadd pairs is vectorized at the selected SLP threshold.
A follow-up patch will correct this #212739 should correct this.
Commit: 3f28472185bb8df103f2fbf9f3ccc22b62f1fe1c
https://github.com/llvm/llvm-project/commit/3f28472185bb8df103f2fbf9f3ccc22b62f1fe1c
Author: adeshcom14 <aadikane at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
A llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.ll
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
Log Message:
-----------
[AMDGPU] Fix S_ADD_I32 frame index folding emitting COPY with immediate (#212440)
When eliminating a frame index in `S_ADD_I32 %fi, imm`,
`SIRegisterInfo::eliminateFrameIndex` can simplify `0 + offset` into a
COPY or S_MOV_B32. The pass used a `MachineOperand` reference captured
before `removeOperand()`, which becomes stale after operands are removed
and shifted. That caused the wrong opcode to be selected (`COPY` instead
of `S_MOV_B32`), producing invalid machine IR such as `copy s4, 4`.
The invalid COPY is later hit by Machine Copy Propagation, which asserts
when calling `getReg()` on the immediate source operand.
Co-authored-by: Matt Arsenault <Matthew.Arsenault at amd.com>
Commit: 508b5be88431b3cce7546baf752ed628a531d699
https://github.com/llvm/llvm-project/commit/508b5be88431b3cce7546baf752ed628a531d699
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
Log Message:
-----------
AMDGPU: Add supports-wgp subtarget feature (#212704)
Commit: b65d79f8800e3d15d1f6cbf1a52f5426da992b59
https://github.com/llvm/llvm-project/commit/b65d79f8800e3d15d1f6cbf1a52f5426da992b59
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll
M llvm/test/MC/AMDGPU/literals.s
M llvm/test/MC/AMDGPU/mai.s
Log Message:
-----------
[AMDGPU] Exclude CDNA parts from POPS exiting wave id pattern (#210892)
POPS hardware is graphics-pipe-only and absent on compute-only CDNA
targets (gfx908, gfx90a, gfx940, gfx942, gfx950), which incorrectly
matched the isGFX9GFX10 predicate and selected a nonexistent register
Commit: f21b9cc9c6386cc1f4b057d8af6a3fdf617cddf9
https://github.com/llvm/llvm-project/commit/f21b9cc9c6386cc1f4b057d8af6a3fdf617cddf9
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
A clang/test/CIR/CodeGen/builtin-cpu-is-cputype.c
A clang/test/CIR/CodeGen/builtin-cpu-is-subtype.c
A clang/test/CIR/CodeGen/builtin-cpu-is-vendor.c
A clang/test/CIR/CodeGen/builtin-cpu-supports.c
Log Message:
-----------
[CIR] Implement __builtin_cpu_supports, _init, and _is (#212900)
These are pretty trivial checks to a builtin variable, so this
implements it for x86, as this shows up in self-build. The tests are
pulled from classic-codegen and shows that we do the reasonable thing
for each of them.
Commit: 806935948ba3532ba559d614f97cc7688d9cb2ee
https://github.com/llvm/llvm-project/commit/806935948ba3532ba559d614f97cc7688d9cb2ee
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/test/Driver/amdgpu-mcpu.cl
M clang/test/Misc/target-invalid-cpu-note/amdgcn.c
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td
M llvm/lib/Target/AMDGPU/GCNProcessors.td
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/test/CodeGen/AMDGPU/hsa-default-device.ll
M llvm/test/TableGen/AMDGPUTargetDefErrors.td
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
Log Message:
-----------
AMDGPU: Handle more TargetParser queries in tablegen (#212357)
Previously we had various enum switches. Start generated tables
indexed by enums. Avoid some special cases by defining the dummy
"generic" and "generic-hsa" targets as real processors.
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: e1f93b045410f3872d3524d91d71ba5eceda0030
https://github.com/llvm/llvm-project/commit/e1f93b045410f3872d3524d91d71ba5eceda0030
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/lib/Target/MSP430/MSP430Subtarget.cpp
Log Message:
-----------
MSP430: Mark more generic libgcc functions as available (#212927)
The generic soft-float, conversion, comparison and integer helper
routines (__addsf3, __divli's __divsi3, __ashlsi3, ...) exist in the
MSP430 libgcc port alongside the preferred __mspabi_* variants. They
were previously removed to force selection of the __mspabi_* names, back
when only one implementation per libcall could be recorded.
Stop hiding them: only __lshrsi3 stays excluded, since the MSP430 libgcc
port provides the 32-bit logical right shift solely under __mspabi_srll
and never defines a generic __lshrsi3.
Repost of #210962
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 7330a8ddc106483031a67d5a74215fc3e1509905
https://github.com/llvm/llvm-project/commit/7330a8ddc106483031a67d5a74215fc3e1509905
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td
M llvm/lib/Target/AMDGPU/GCNProcessors.td
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
Log Message:
-----------
AMDGPU: TableGen subarch to major subarch table (#212605)
Replace the hand-written AMDGPUMajorFamilies array with a
generated lookup table. Adds a special case for the major
arches missing a concrete generic target definition (we probably
should just define those to avoid this).
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: 26d08c22c68bbb9e644012c4e5cae32f68d897cb
https://github.com/llvm/llvm-project/commit/26d08c22c68bbb9e644012c4e5cae32f68d897cb
Author: saloni-shinde-Q <saloshin at qti.qualcomm.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
M llvm/test/MC/RISCV/rv32d-invalid.s
M llvm/test/MC/RISCV/rv32dc-invalid.s
M llvm/test/MC/RISCV/rv32f-invalid.s
M llvm/test/MC/RISCV/rv32fc-invalid.s
M llvm/test/MC/RISCV/rv32q-invalid.s
M llvm/test/MC/RISCV/rv32zdinx-invalid.s
M llvm/test/MC/RISCV/rv32zfh-invalid.s
M llvm/test/MC/RISCV/rv32zfinx-invalid.s
M llvm/test/MC/RISCV/rv32zhinx-invalid.s
M llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
M llvm/test/MC/RISCV/rv64d-invalid.s
M llvm/test/MC/RISCV/rv64f-invalid.s
M llvm/test/MC/RISCV/rv64q-invalid.s
M llvm/test/MC/RISCV/rv64xtheadfmemidx-invalid.s
M llvm/test/MC/RISCV/rv64zdinx-invalid.s
M llvm/test/MC/RISCV/rv64zfh-invalid.s
M llvm/test/MC/RISCV/rv64zfinx-invalid.s
M llvm/test/MC/RISCV/rv64zhinx-invalid.s
M llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
M llvm/test/MC/RISCV/rvzfbfmin-invalid.s
M llvm/test/MC/RISCV/rvzfhmin-invalid.s
Log Message:
-----------
[RISCV][MC] Improve FPR Error Messages (#212492)
This patch improves the error messages for the following register classes:
1. FPR RegClasses (FPR16, FPR32, FPR64, FPR128, FPR256)
2. Compressed FPR RegClasses (FPR16C, FPR32C, FPR64C)
3. GPR-as-FPR classes used by Zfinx/Zdinx extensions (GPRAsFPR16, GPRAsFPR32, GPRF64AsFPR, GPRPairAsFPR).
---------
Co-authored-by: Saloni Shinde <saloshin at qti.qualcomm.com>
Commit: b42621f842571a92cec2961fa5c4fc518d4ca91a
https://github.com/llvm/llvm-project/commit/b42621f842571a92cec2961fa5c4fc518d4ca91a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
Log Message:
-----------
AMDGPU: TableGen the subarch to processor name mapping table (#212606)
Replace the hand-written AMDGPUSubArchNames array (SubArch -> canonical
GPU name) with a generated table.
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: 23a22244b099a9950a5f265460e392bc44beb3b4
https://github.com/llvm/llvm-project/commit/23a22244b099a9950a5f265460e392bc44beb3b4
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
A llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/features-info.ll
A llvm/test/MC/RISCV/zilx-invalid.s
A llvm/test/MC/RISCV/zilx-valid-rv32.s
A llvm/test/MC/RISCV/zilx-valid-rv64.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV][MC] Support experimental Zilx extension
This adds the MC support for `Zilx` (Indexed Integer Load Instructions)
extension.
Doc: https://github.com/riscv/riscv-zilx
Reviewers: topperc, tclin914, kito-cheng
Pull Request: https://github.com/llvm/llvm-project/pull/209419
Commit: 8a1ff7feefc5825cc10349b8946fe555f435d53b
https://github.com/llvm/llvm-project/commit/8a1ff7feefc5825cc10349b8946fe555f435d53b
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
M llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td
M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
A llvm/test/CodeGen/RISCV/zilx-opt-w-instrs.mir
A llvm/test/CodeGen/RISCV/zilx.ll
Log Message:
-----------
[RISCV] Support CodeGen of Zilx extension
Thanks for `XTheadMemIdx` extension that makes life easier.
Reviewers: lukel97, topperc, kito-cheng, tclin914
Reviewed By: topperc
Pull Request: https://github.com/llvm/llvm-project/pull/209420
Commit: b84c5f4abcfb464e362bcd2b8eb58ef96ecbae9d
https://github.com/llvm/llvm-project/commit/b84c5f4abcfb464e362bcd2b8eb58ef96ecbae9d
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h
Log Message:
-----------
[BFI] Simplify/optimize getMass/getContainingLoop. NFC (#212938)
A block can head both a natural loop and the irreducible loop wrapping
it (`@crossloops` in BlockFrequencyInfo/irreducible.ll).
getContainingLoop and getMass unroll to a fixed depth of two through
isDoubleLoopHeader and isADoublePackage. Depth two holds because
IrreducibleGraph::addEdge drops edges into the enclosing loop's headers,
keeping such a header out of any nested SCC.
(The old comment "If it's a node inside a packaged loop, it returns the
loop's mass." is wrong.)
Walk the Parent chain instead to drop the depth two assumption. Testing
`IsPackaged` before isHeader also skips the Nodes[0] load on the common
path.
Commit: de26036ecb4b450e5e1bdc49ee7101e3ce294bc4
https://github.com/llvm/llvm-project/commit/de26036ecb4b450e5e1bdc49ee7101e3ce294bc4
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/test/Misc/target-invalid-cpu-note/amdgcn.c
M clang/test/Misc/target-invalid-cpu-note/r600.c
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
Log Message:
-----------
AMDGPU: Eliminate old macro driven processor name parsing (#212608)
Previously the generated inc file had a series of macros for use
with StringSwitch; now just directly scan the generated name table.
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: f08211e71e8fec39ff64facef84cb104ea8119e7
https://github.com/llvm/llvm-project/commit/f08211e71e8fec39ff64facef84cb104ea8119e7
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/test/CodeGen/AArch64/fmlal-loreg.ll
M llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
M llvm/test/TableGen/aarch64-register-info-stats.td
Log Message:
-----------
[AArch64] Remove assembler-only register classes (#211527)
ZPRMul2, ZPRMul4 and PPRMul2 register classes are used solely by the asm
parser to validate other register classes (ZPR2Mul2, ZPR4Mul4,
PPR2Mul2). Since they're real register classes TableGen synthesizes
numerous intersection classes and pressure sets from them.
Removing them and validating the constraint directly in the assembly
parser reduces:
- generated register classes: 521 -> 403 (~22%)
- generated pressure sets: 188 -> 60 (68%)
- generated register-info size: 11.9 MB -> 9.1 MB (23%)
Also improves CTMark geomean -0.23% on stage1-aarch64-O3.
https://llvm-compile-time-tracker.com/compare.php?from=a90dbb43cd67856f681feba82d51a0d5fbcae3c2&to=5565d4907cdf960cc142a7507f16e551f51919b0&stat=instructions%3Au
Assisted-by: codex
Commit: fc764a7c2b12c508c72e04a606dd2d2c815e2d94
https://github.com/llvm/llvm-project/commit/fc764a7c2b12c508c72e04a606dd2d2c815e2d94
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/lib/Target/ARM/ARMSubtarget.cpp
Log Message:
-----------
ARM: Mark more generic libgcc functions as available (#210961)
Generic libgcc/compiler-rt functions coexist with aeabi variants
(e.g., __divsi3 and __aeabi_idiv) according to my reading of the
build. At least in compiler-rt, some are aliases.
They were previously removed from the available set on AEABI+AAPCS
targets to force selection of the preferred __aeabi_* variants, back when
only one implementation per libcall could be recorded.
Now that multiple implementations can be available per libcall, stop
hiding the generics and select the __aeabi_* variant explicitly as the
preferred implementation. This reduces the number of special cases to
consider for future libcalls info improvements.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 13e5ce40eff159ed9b2db3660b41c47ca640ce51
https://github.com/llvm/llvm-project/commit/13e5ce40eff159ed9b2db3660b41c47ca640ce51
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/test/CodeGen/X86/avx512-gather-scatter-intrin-deprecated.ll
M llvm/test/CodeGen/X86/avx512-gather-scatter-intrin.ll
Log Message:
-----------
[X86] Regenerate gather tests with missing VPADD constant asm comments (#212940)
Reduces diff in a future patch
Commit: 70e39de33f37680281a98d12d4003654929a802c
https://github.com/llvm/llvm-project/commit/70e39de33f37680281a98d12d4003654929a802c
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/test/CodeGen/X86/vec_int_to_fp.ll
Log Message:
-----------
[X86] vec_int_to_fp.ll - regenerate tests with missing VPADD constant asm comments (#212941)
Reduces diff in a future patch
Commit: 07897c2bde598dc4c42b159472bbb70057f3388b
https://github.com/llvm/llvm-project/commit/07897c2bde598dc4c42b159472bbb70057f3388b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/test/TableGen/AMDGPUTargetDefErrors.td
M llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
Log Message:
-----------
AMDGPU: TableGen the subarch triple name table (#212627)
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: 2b45696fcafc0c92ea0ad73483b1e175c97c834a
https://github.com/llvm/llvm-project/commit/2b45696fcafc0c92ea0ad73483b1e175c97c834a
Author: yingopq <115543042+yingopq at users.noreply.github.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/test/MC/Mips/macro-ddiv-bad.s
M llvm/test/MC/Mips/macro-ddivu-bad.s
M llvm/test/MC/Mips/macro-div-bad.s
M llvm/test/MC/Mips/macro-divu-bad.s
Log Message:
-----------
[Mips] Fix Clang crashes when assembling MIPS div/rem with register-name symbol as divisor (#200354)
Add check before getimm().
Fix #185363.
Commit: cb8513d5a5b8d7ad52b9903f6a46fbe603298468
https://github.com/llvm/llvm-project/commit/cb8513d5a5b8d7ad52b9903f6a46fbe603298468
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/CSKY/CSKYAsmPrinter.cpp
Log Message:
-----------
CSKY: Avoid constructing a temporary CSKYSubtarget in AsmPrinter (#212944)
This was reconstructing a subtarget equivalent to the global
subtarget instead of just using the available one.
Commit: 60074081ea925868392d4256a5578ffd6f88db42
https://github.com/llvm/llvm-project/commit/60074081ea925868392d4256a5578ffd6f88db42
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
M llvm/lib/Target/RISCV/RISCVSchedAndes45.td
M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
M llvm/lib/Target/RISCV/RISCVSchedTTAscalonX.td
M llvm/lib/Target/RISCV/RISCVScheduleV.td
Log Message:
-----------
[RISCV] Split and rename WriteVSlideI/WriteVISlide1X/WriteVFSlide1F (#212184)
Split each of these SchedWrites into separate slide-up and slide-down
variants:
- WriteVSlideI -> WriteVSlideUpI, WriteVSlideDownI
- WriteVISlide1X -> WriteVISlide1Up, WriteVISlide1Down
- WriteVFSlide1F -> WriteVFSlide1Up, WriteVFSlide1Down
SpacemiT X100 and A100 have different latencies and/or throughput for
slide up vs. slide down operations, so they need separate SchedWrites to
model that difference.
Commit: 46919d267fd440dc3a82672e188b57fc441deafb
https://github.com/llvm/llvm-project/commit/46919d267fd440dc3a82672e188b57fc441deafb
Author: Sameer Sahasrabuddhe <sameer.sahasrabuddhe at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/docs/AMDGPUAsyncOperations.md
Log Message:
-----------
[Docs][AMDGPU] Explain completion of async operations (#212756)
This improves the somewhat hand-wavey "memory model" currently described
for async operations. While this version is also not complete, it
prepares for the more complete memory model being written down.
Commit: 27c735597e2c8251b271e93b8a00a1cc27a65d76
https://github.com/llvm/llvm-project/commit/27c735597e2c8251b271e93b8a00a1cc27a65d76
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M mlir/test/Target/SPIRV/debug.mlir
M mlir/test/Target/SPIRV/non-uniform-ops.mlir
Log Message:
-----------
[NFC][mlir][SPIR-V] Use Subgroup scope in GroupNonUniform tests (#212928)
After https://github.com/KhronosGroup/SPIRV-Tools/pull/6811 spirv-val
rejects Workgroup scope on these ops
Commit: ef7f2f611993a4bc59e181d2bf8fc6269d7e1c7d
https://github.com/llvm/llvm-project/commit/ef7f2f611993a4bc59e181d2bf8fc6269d7e1c7d
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
A llvm/test/CodeGen/RISCV/rvv/vlmax-peephole.mir
Log Message:
-----------
[RISCV] Fix crash in convertToVLMAX when AVL is an ADDI of a frame index (#212923)
`getConstant()` recognizes an AVL that is an immediate by checking
the opcode is `ADDI`, then reading the second operand and checking
if it is `X0`. However the second operand may be a frame index and
`getReg()` asserts with "This is not a register operand!".
We should guard the register access with `isReg()` before comparing
against `X0`.
Fixes #212797.
Commit: 9aee37146dc374f3668bef37e3e15c29abb1a1e0
https://github.com/llvm/llvm-project/commit/9aee37146dc374f3668bef37e3e15c29abb1a1e0
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/docs/LangRef.md
M llvm/include/llvm/IR/Module.h
M llvm/include/llvm/Support/CodeGen.h
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/Module.cpp
M llvm/lib/IR/Verifier.cpp
A llvm/test/Assembler/module-flags-float-abi.ll
M llvm/test/Bitcode/upgrade-ppc-float-abi.ll
A llvm/test/Linker/module-flags-float-abi.ll
A llvm/test/Verifier/module-flags-float-abi.ll
Log Message:
-----------
IR: Introduce "float-abi" module flag (#210821)
This is intended to eliminate the FloatABIType TargetOptions field.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: ddb662d3cbadb7c2c96cc2c00f95a3a5562d5b06
https://github.com/llvm/llvm-project/commit/ddb662d3cbadb7c2c96cc2c00f95a3a5562d5b06
Author: Anutosh Bhat <andersonbhat491 at gmail.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
A llvm/test/Analysis/CostModel/WebAssembly/vector-shift.ll
Log Message:
-----------
[WebAssembly][TTI] Avoid crash when costing scalable vector shifts (#212759)
I see the following
```
anutosh491 at Anutoshs-MacBook-Air llvm-project % cat /private/tmp/wasm-scalable-shift-cost.ll
define <vscale x 4 x i32> @shift(<vscale x 4 x i32> %x,
<vscale x 4 x i32> %amount) {
%result = shl <vscale x 4 x i32> %x, %amount
ret <vscale x 4 x i32> %result
}
anutosh491 at Anutoshs-MacBook-Air llvm-project % build-assert/bin/opt \
-mtriple=wasm32-unknown-unknown \
-mattr=+simd128 \
-passes='print<cost-model>' \
-disable-output \
/private/tmp/wasm-scalable-shift-cost.ll
Printing analysis 'Cost Model Analysis' for function 'shift':
Cost Model: Assertion failed: (isa<To>(Val) && "cast<Ty>() argument of incompatible type!"), function cast, file Casting.h, line 572.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
Stack dump:
0. Program arguments: build-assert/bin/opt -mtriple=wasm32-unknown-unknown -mattr=+simd128 -passes=print<cost-model> -disable-output /private/tmp/wasm-scalable-shift-cost.ll
1. Running pass "function(print<cost-model>)" on module "/private/tmp/wasm-scalable-shift-cost.ll"
2. Running pass "print<cost-model>" on function "shift"
#0 0x0000000105b7a56c llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/Users/anutosh491/work/llvm-project/build-assert/bin/opt+0x102f6256c)
#1 0x0000000105b78248 llvm::sys::RunSignalHandlers() (/Users/anutosh491/work/llvm-project/build-assert/bin/opt+0x102f60248)
#2 0x0000000105b7b170 SignalHandler(int, __siginfo*, void*) (/Users/anutosh491/work/llvm-project/build-assert/bin/opt+0x102f63170)
#3 0x000000018b5f7744 (/usr/lib/system/libsystem_platform.dylib+0x1804fb744)
#4 0x000000018b5ed8d8 (/usr/lib/system/libsystem_pthread.dylib+0x1804f18d8)
#5 0x000000018b4f4644 (/usr/lib/system/libsystem_c.dylib+0x1803f8644)
#6 0x000000018b4f38a0 (/usr/lib/system/libsystem_c.dylib+0x1803f78a0)
#7 0x0000000104036ddc llvm::BasicTTIImplBase<llvm::WebAssemblyTTIImpl>::getArithmeticInstrCost(unsigned int, llvm::Type*, llvm::TargetTransformInfo::TargetCostKind, llvm::TargetTransformInfo::OperandValueInfo, llvm::TargetTransformInfo::OperandValueInfo, llvm::ArrayRef<llvm::Value const*>, llvm::Instruction const*) const (/Users/anutosh491/work/llvm-project/build-assert/bin/opt+0x10141eddc)
#8 0x000000010403b0ac llvm::TargetTransformInfoImplCRTPBase<llvm::WebAssemblyTTIImpl>::getInstructionCost(llvm::User const*, llvm::ArrayRef<llvm::Value const*>, llvm::TargetTransformInfo::TargetCostKind) const (/Users/anutosh491/work/llvm-project/build-assert/bin/opt+0x1014230ac)
#9 0x00000001049162c8 llvm::TargetTransformInfo::getInstructionCost(llvm::User const*, llvm::ArrayRef<llvm::Value const*>, llvm::TargetTransformInfo::TargetCostKind) const (/Users/anutosh491/work/llvm-project/build-assert/bin/opt+0x101cfe2c8)
#10 0x00000001058d90b4 llvm::TargetTransformInfo::getInstructionCost(llvm::User const*, llvm::TargetTransformInfo::TargetCostKind) const (/Users/anutosh491/work/llvm-project/build-assert/bin/opt+0x102cc10b4)
#11 0x000000010468a368 getCost(llvm::Instruction&, llvm::TargetTransformInfo::TargetCostKind, llvm::TargetTransformInfo&) (/Users/anutosh491/work/llvm-project/build-assert/bin/opt+0x101a72368)
#12 0x0000000104689dd4 llvm::CostModelPrinterPass::run(llvm::Function&, llvm::AnalysisManager<llvm::Function>&) (/Users/anutosh491/work/llvm-project/build-assert/bin/opt+0x101a71dd4)
#13 0x0000000105186554 llvm::PassManager<llvm::Function, llvm::AnalysisManager<llvm::Function>>::run(llvm::Function&, llvm::AnalysisManager<llvm::Function>&) (/Users/anutosh491/work/llvm-project/build-assert/bin/opt+0x10256e554)
#14 0x000000010518a680 llvm::ModuleToFunctionPassAdaptor::run(llvm::Module&, llvm::AnalysisManager<llvm::Module>&) (/Users/anutosh491/work/llvm-project/build-assert/bin/opt+0x102572680)
#15 0x0000000105185418 llvm::PassManager<llvm::Module, llvm::AnalysisManager<llvm::Module>>::run(llvm::Module&, llvm::AnalysisManager<llvm::Module>&) (/Users/anutosh491/work/llvm-project/build-assert/bin/opt+0x10256d418)
#16 0x0000000106127cb0 llvm::runPassPipeline(llvm::StringRef, llvm::Module&, llvm::TargetMachine*, llvm::TargetLibraryInfoImpl*, llvm::ToolOutputFile*, llvm::ToolOutputFile*, llvm::ToolOutputFile*, llvm::StringRef, llvm::ArrayRef<llvm::PassPlugin>, llvm::ArrayRef<std::__1::function<void (llvm::PassBuilder&)>>, llvm::opt_tool::OutputKind, llvm::opt_tool::VerifierKind, bool, bool, bool, bool, bool, bool, bool, bool) (/Users/anutosh491/work/llvm-project/build-assert/bin/opt+0x10350fcb0)
#17 0x0000000106131eac optMain (/Users/anutosh491/work/llvm-project/build-assert/bin/opt+0x103519eac)
#18 0x000000018b22fe00
zsh: abort build-assert/bin/opt -mtriple=wasm32-unknown-unknown -mattr=+simd128
```
Commit: 98146752c8a6a7b3b3af1f0820f2f530aee5b925
https://github.com/llvm/llvm-project/commit/98146752c8a6a7b3b3af1f0820f2f530aee5b925
Author: Kirill A. Korinsky <kirill at korins.ky>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
A llvm/test/MC/Sparc/Directives/seg.s
Log Message:
-----------
[SPARC] Support the .seg directive (#209001)
Support the legacy .seg directive used by SunOS SPARC assembly. Map
"text", "data", "data1", and "bss" to their corresponding MC sections,
using subsection 1 for "data1".
Commit: 506d70de59b3d37f65757d7694cd3618ed50afee
https://github.com/llvm/llvm-project/commit/506d70de59b3d37f65757d7694cd3618ed50afee
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Analysis/BlockFrequencyInfoImpl.cpp
Log Message:
-----------
[BFI] Compute the minimum frequency only when dumping. NFC (#212957)
Commit: 6ddd80af0bfbc1927f8bb2935120f6f4cedadc9a
https://github.com/llvm/llvm-project/commit/6ddd80af0bfbc1927f8bb2935120f6f4cedadc9a
Author: Yao Qi <yao_qi at apple.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M lldb/source/Target/Memory.cpp
M lldb/unittests/Target/MemoryTest.cpp
Log Message:
-----------
[lldb] Fix stale L1 memory cache read after memory write (#208347)
A `memory write` can leave stale bytes in the L1 memory cache, so a later
`memory read` of the address that was just written returns the old value.
The L1 cache (`m_L1_cache`) is a map keyed by each chunk's start address, and
chunks can overlap: a read larger than an L2 cache line
(`target.memory-cache-line-size`, 512 by default) bypasses L2 and is stored
whole in L1, so two large reads can produce two chunks that both cover the same
address.
`Flush()` invalidates the L1 cache on a write. It started at the chunk at or
below the flushed address and walked forward, stopping at the first chunk that
did not intersect. It therefore never inspected a chunk that starts below the
flushed address but is long enough to reach into it, leaving that chunk behind
with the stale byte. A later read fully contained in that chunk is served from
the cache and returns the old value.
Fix `Flush()` to walk the whole L1 cache and erase every chunk that intersects
the flushed range, so a chunk starting below the address is dropped too.
Lookups (`FindL1CacheEntry()`) and inserts (`AddL1CacheData()`) are unaffected:
a lookup that lands on the wrong overlapping chunk simply misses and falls
through to L2 or the inferior, which is not a correctness problem.
Add a unit test covering partial overlaps, containment, disjoint and adjacent
chunks, and a flush that must drop a lower-starting chunk as well as several
overlapping chunks.
Commit: c27b35739d5eaf3e214f639fded1515d72884027
https://github.com/llvm/llvm-project/commit/c27b35739d5eaf3e214f639fded1515d72884027
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M libcxx/include/tuple
Log Message:
-----------
[libc++] Remove SFINAE checks in tuple which are always true (#212765)
We have a specialization for `tuple` with no arguments, so checking
`sizeof...(_Tp) >= 1` in the primary template will never be false.
Commit: 98cdcbae7714396a1d7b4865d0ade80e6450d445
https://github.com/llvm/llvm-project/commit/98cdcbae7714396a1d7b4865d0ade80e6450d445
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M libcxx/include/__chrono/formatter.h
M libcxx/include/__format/formatter_floating_point.h
M libcxx/include/__format/formatter_integral.h
M libcxx/include/__locale
M libcxx/include/__locale_dir/num.h
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
M libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/locale-specific_form.pass.cpp
M libcxx/test/std/utilities/format/format.functions/locale-specific_form.pass.cpp
Log Message:
-----------
[libc++] Move numpunct into <__locale_dir/num.h> (#212465)
`numpunct` is part of the `num` family of facets, so it should live in
`num.h`.
Commit: d3ca4e5011078f04eb974edcfaa00a7c052e3510
https://github.com/llvm/llvm-project/commit/d3ca4e5011078f04eb974edcfaa00a7c052e3510
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M libcxx/include/streambuf
M libcxx/test/std/input.output/stream.buffers/streambuf/streambuf.protected/streambuf.get.area/setg.assert.pass.cpp
M libcxx/test/std/input.output/stream.buffers/streambuf/streambuf.protected/streambuf.put.area/setp.assert.pass.cpp
Log Message:
-----------
[libc++][NFC] Rename the streambuf members (#212277)
This refactors `streambuf` to contain a `_GetArea` and a `_PutArea`.
This makes the code significantly easier to read, since the pointers
belonging together are bundled in a struct.
Commit: ab7bbbbdc7bc0d7813d084898a8f913ca0b40fff
https://github.com/llvm/llvm-project/commit/ab7bbbbdc7bc0d7813d084898a8f913ca0b40fff
Author: jeanPerier <jperier at nvidia.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIRAttr.h
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Optimizer/Transforms/AllocationPlacement.cpp
A flang/test/Integration/allocation-placement-array-result.f90
M flang/test/Lower/HLFIR/array-ctor-index.f90
M flang/test/Lower/HLFIR/custom-intrinsic.f90
M flang/test/Lower/HLFIR/intrinsic-dynamically-optional.f90
M flang/test/Lower/HLFIR/maxloc.f90
M flang/test/Lower/HLFIR/minloc.f90
M flang/test/Lower/submodule.f90
Log Message:
-----------
[flang][AllocationPlacement] prevent promotion of mock result to allocmem (#212825)
Under the new experimental pass that can move automatic arrays to the
heap, "mock" result storage may be promoted to allocmem before
AbstractResult removes them and replace them by a hidden result.
Add a fir.must_be_stack attribute to these mock alloca so they are never
promoted. So that passes dealing with array function results ABI can
expect to find an fir.alloca and remove it.
Commit: 185a931f4b6eb8347cde3346a963541af4bb9b32
https://github.com/llvm/llvm-project/commit/185a931f4b6eb8347cde3346a963541af4bb9b32
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/CStringChecker.cpp
M clang/test/Analysis/string-search-modeling.c
Log Message:
-----------
Reapply "[analyzer] Fix false positive in strchr/strrchr with constant args" (#212124)
Relands #210154
Commit: 840558c5ff53a95efbed5fafacc8fb3b6c377fec
https://github.com/llvm/llvm-project/commit/840558c5ff53a95efbed5fafacc8fb3b6c377fec
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-store-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/store-scalarization-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
Log Message:
-----------
[LV] Only use legacy scalarization costs with replicate regions. (#212738)
The scalarization costs in InstsToScalarize are based on the assumption
that the instructions are scalarized and predicated. There are a number
of VPlan transformations that can simplify/remove replicate regions. If
there are no replicate regions in a plan, nothing is predicated and
scalarized, so the costs in InstsToScalarize will be inaccurate.
Skip the fallback in those cases, using the more accurate VPlan-based
cost info.
PR: https://github.com/llvm/llvm-project/pull/212738
Commit: 2f7a0da7ba3d1de5311118d60e685432238d4e72
https://github.com/llvm/llvm-project/commit/2f7a0da7ba3d1de5311118d60e685432238d4e72
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M lldb/test/API/functionalities/process_save_core_minidump_size_of_image/TestMinidumpSizeOfImage.py
Log Message:
-----------
[lldb][test] Fix TestMinidumpSizeOfImage.py with glibc >= 2.41 (#212972)
Test added by #188363.
In glibc 2.41:
> * dlopen and dlmopen no longer make the stack executable if a shared
> library requires it, either implicitly because of a missing GNU_STACK
> ELF header (and default ABI permission having the executable bit set)
> or explicitly because of the executable bit in GNU_STACK, and the
> stack is not already executable. Instead, loading such objects will
> fail.
https://lists.gnu.org/archive/html/info-gnu/2025-01/msg00014.html
The test program used for this test provides all the PHDRS itself, but
did not include a PT_GNU_STACK entry.
So the loader would assume it wanted exectuable stack. The main program
was not using an executable stack and so the loader refused to change
that, so loading the object fails.
dlopen failed:
lldb-test-build/functionalities/process_save_core_minidump_size_of_image/TestMinidumpSizeOfImage/libtestlib.so:
cannot enable executable stack as shared object requires: Invalid
argument
To fix this provide a PT_GNU_STACK with value 6 aka read and write but
not execute.
Commit: 8212d301fd86709c7965bbeb1d6964bb06c0341c
https://github.com/llvm/llvm-project/commit/8212d301fd86709c7965bbeb1d6964bb06c0341c
Author: Sameer Sahasrabuddhe <sameer.sahasrabuddhe at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/docs/AMDGPUMemoryModel.md
M llvm/docs/AMDGPUUsage.rst
Log Message:
-----------
[Docs][AMDGPU] availability/visibility in addrspace(3) and other cleanups (#212707)
addrspace(3) on AMDGPU corresponds to LDS, which is a fast memory directly
accessed by all threads in a workgroup (there is no intervening cache). Thus,
any accesses to this addrspace have built-in availability and visibility at
"workgroup" scope.
Other cleanups:
- Update the intrinsic names to match the implementation.
- Explain store-available and load-visible.
- Rename to "make-available" and "make-visible" for consistent spelling.
Commit: e477a9950ed219a02f4b33b35c4bee24f4c87b00
https://github.com/llvm/llvm-project/commit/e477a9950ed219a02f4b33b35c4bee24f4c87b00
Author: michaelselehov <michael.selehov at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.cd.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
M llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.modf.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/packed-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
A llvm/test/CodeGen/AMDGPU/sdwa-peephole-lshl-or-hi16pack.ll
A llvm/test/CodeGen/AMDGPU/sdwa-peephole-lshl-or-hi16pack.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
Log Message:
-----------
[AMDGPU] Re-fold masked hi16 pack into v_or_b32_sdwa (#210735)
Follow-up to #206058, which selects the (hi << 16) | (z & 0xffff)
high-half pack to a fused v_lshl_or_b32. When z's high bits are not
known zero this needs an explicit v_and_b32 0xffff, and since
v_lshl_or_b32 has no SDWA form the mask can no longer fold into a single
v_or_b32_sdwa (src1_sel:WORD_0) as it did before -- a small but real
perf hole (~5% on a VALU-bound char4 kernel on gfx942).
Add a SIPeepholeSDWA rewrite of the masked pack back into v_lshlrev_b32
+ v_or_b32_sdwa, erasing the dead v_and. It fires only on the masked
form, so the mask-free #206058 win is preserved, and it never increases
the instruction count.
Assisted-by: Claude Opus
Commit: ba371791db4f9e7ef05f0a1c26529298b2951a4b
https://github.com/llvm/llvm-project/commit/ba371791db4f9e7ef05f0a1c26529298b2951a4b
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
A llvm/include/llvm/ExecutionEngine/Orc/RTBridge/Calls.h
A llvm/include/llvm/ExecutionEngine/Orc/RTBridge/SPS/Calls.h
M llvm/lib/ExecutionEngine/Orc/Shared/OrcRTBridge.cpp
M llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
A llvm/unittests/ExecutionEngine/Orc/SPSCallersTest.cpp
Log Message:
-----------
[ORC] Add rt::sps::MainCaller for running main-like functions. (#212948)
rt::MainCaller is a controller-side interface for running functions with
a main-like signature (int(int argc, char *argv[])) in the executor.
rt::sps::MainCaller is rt::MainCaller's first implementation, which
invokes main functions using on ORC runtime's orc_rt_ci_sps_call_main
entrypoint (using Simple Packed Serialization for argument/return
encoding / decoding).
These utilities live under the ExecutionEngine/Orc/RTBridge directory,
which is intended to hold controller-side utilities for invoking ORC
runtime systems. Subdirectories (e.g. SPS) hold implementations for
specific serialization schemes.
Adds SPSCallersTest with coverage for direct construction, the
synchronous and asynchronous call operators, use through the
rt::MainCaller interface, and the Create / bootstrap-JITDylib lookup
path.
Commit: 18a49751d365d25e2f87a1a418bb5dae6592a0c1
https://github.com/llvm/llvm-project/commit/18a49751d365d25e2f87a1a418bb5dae6592a0c1
Author: Kieran B <kieran.bailey at arm.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
A llvm/test/CodeGen/AArch64/neon-scalar-vcvtfp2fx.ll
Log Message:
-----------
[AArch64][SelectionDAG] Avoid cross-bank copy for NEON vcvtfp2fx result (#210275)
- Add SelectionDAG-only patterns for NEON vcvtfp2fx so integer result
select GPR instead of FPR, avoiding the need for cross-bank copies.
- Bitcast uses still select the FP/SIMD-register forms where available.
- Add testing for GPR-resulting and FPR-resulting patterns.
- Add missing tests in fp16_intrinsic_scalar_2op.ll:
test_vcvth_n_u64_f16_1 and test_vcvth_n_u64_f16_16.
A follow-up patch will also include the fix for GlobalIsel.
Commit: 59691a1f7c907cc492a62ebded8521535974d25a
https://github.com/llvm/llvm-project/commit/59691a1f7c907cc492a62ebded8521535974d25a
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-cmpne.ll
A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-cmp.ll
Log Message:
-----------
[LLVM][InstCombine] Add simplification of SVE compare intrinsics. (#211249)
Extends SVEIntrinsicInfo to accept LLVM IR compare information, which is
then used to call simplifyCmpInst on the data operands of SVE compare
intrinsic calls.
Commit: c6fc14273b9a0b30c7497182b933f580ac11b5f7
https://github.com/llvm/llvm-project/commit/c6fc14273b9a0b30c7497182b933f580ac11b5f7
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/test/CodeGen/AArch64/sve-hadd.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-wide-add.ll
A llvm/test/CodeGen/AArch64/sve2-wide-ops.ll
Log Message:
-----------
[LLVM][CodeGen][SVE] Add isel patterns for add/sub where the second operand is promoted. (#212771)
Commit: 0a1c936ef1427699f72a107f701aa79a92d313e8
https://github.com/llvm/llvm-project/commit/0a1c936ef1427699f72a107f701aa79a92d313e8
Author: Luke Lau <luke at igalia.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll
M llvm/test/Transforms/LoopVectorize/select-cmp-blend-chain.ll
Log Message:
-----------
[VPlan] Mark ComputeReductionResult as not reading or writing from memory (#212982)
Enables some DCE
Commit: f8c1d988e169ee9cd97e514efd07bb90d20ad6db
https://github.com/llvm/llvm-project/commit/f8c1d988e169ee9cd97e514efd07bb90d20ad6db
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/CMakeLists.txt
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/include/mlir/Dialect/Tosa/IR/TosaOpBase.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.h
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaProfileCompliance.h
M mlir/include/mlir/Dialect/Tosa/IR/TosaShapeOps.td
M mlir/lib/Dialect/Tosa/CMakeLists.txt
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
R mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/profile_all_unsupported.mlir
M mlir/test/Dialect/Tosa/profile_pro_fp_unsupported.mlir
M mlir/test/lib/Dialect/Tosa/CMakeLists.txt
R mlir/test/lib/Dialect/Tosa/TestAvailability.cpp
M mlir/tools/mlir-opt/mlir-opt.cpp
M mlir/tools/mlir-tblgen/CMakeLists.txt
R mlir/tools/mlir-tblgen/TosaUtilsGen.cpp
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][tosa] Remove availability interfaces from profile conformance (#207809)
This commit removes the "QueryProfileInterface" and
"QueryExtensionInterface" as they are superfluous in most cases, with
TosaComplianceData.h.inc already providing much of the data we need.
Removing these also helps prevent mistakes as observed in:
https://github.com/llvm/llvm-project/pull/206687
This commit removes these interfaces and updates the profile conformance
to extract supported profile/extension information from
TosaComplianceData.h.inc instead.
One factor that isn't duplicated is operations that rely on extensions,
but do not declare any data type support. This is a small set of
operations, such as tosa.custom, tosa.cond_if, tosa.while_loop and
tosa.const_shape, and we can add them to the TosaComplianceData.h.inc
file as needed.
Commit: 9e1630622de397a3c8d284d15ce25ee62a00b406
https://github.com/llvm/llvm-project/commit/9e1630622de397a3c8d284d15ce25ee62a00b406
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/Orc/BUILD.gn
Log Message:
-----------
[gn build] Port ba371791db4f (#212996)
Commit: a19d7a1c779c05f727ea5d55cd0434bbd39d179b
https://github.com/llvm/llvm-project/commit/a19d7a1c779c05f727ea5d55cd0434bbd39d179b
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 7ded638ea33b (#212995)
Commit: 0af5e8419f4bb6c830f3e2ec4b640830ea63a8b0
https://github.com/llvm/llvm-project/commit/0af5e8419f4bb6c830f3e2ec4b640830ea63a8b0
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M lldb/source/Plugins/ExpressionParser/Clang/IRForTarget.cpp
A lldb/test/API/commands/expression/result-with-destructor/Makefile
A lldb/test/API/commands/expression/result-with-destructor/TestResultWithDestructor.py
A lldb/test/API/commands/expression/result-with-destructor/main.cpp
Log Message:
-----------
[lldb] Fix C++ expression evaluation with the MS C++ ABI (#212521)
IRForTarget didn't correctly handle the Microsoft C++ ABI when preparing
JIT'd expressions:
- `CreateResultVariable` could match a compiler generated dynamic
initializer function instead of the result variable, since both share
the same mangled substring under the MS ABI.
- `RemoveCXAAtExit` only stripped `__cxa_atexit` calls (Itanium ABI). On
the MS ABI, static destructors are registered via plain `atexit`.
Example:
```cpp
struct Foo {
Foo() : x(42) {}
~Foo() {}
int x;
};
void bar() {
static Foo f;
// <breakpoint here>
}
```
Evaluating `f.x` at the breakpoint on Windows previously could resolve
against the wrong symbol or crash, because the MS-ABI-specific dynamic
initializer function and atexit-registered destructor thunk weren't
accounted for.
Changes
- Restrict result variable lookup to GlobalVariables, so the dynamic
initializer function is skipped.
- Strip `atexit` registrations in addition to `__cxa_atexit`.
- Clear the body of any atexit destructor thunk.
This is needed for:
- https://github.com/swiftlang/llvm-project/pull/13517
Commit: 6a932c6041a58a1c352ea65c94810a13d3b453d0
https://github.com/llvm/llvm-project/commit/6a932c6041a58a1c352ea65c94810a13d3b453d0
Author: janr-bay <jrehders at baylibre.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Support/APFloat.cpp
M llvm/unittests/ADT/APFloatTest.cpp
Log Message:
-----------
[APFloat][NFC] Generalize bitcast to also cover x87 semantics (#209781)
This removes the special case code for bitcasting APInt to a float with
x87 semantics in convertF80LongDoubleAPFloatToAPInt. This makes it
consistent with previous removal of special cases and will remove one
more small obstacle to making APFloat extensible.
Commit: fcf4bb1af7450f618504201610ef8c3ef52844d7
https://github.com/llvm/llvm-project/commit/fcf4bb1af7450f618504201610ef8c3ef52844d7
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
M llvm/test/CodeGen/AArch64/misched-fusion-apple-sme-compute.mir
Log Message:
-----------
[AArch64] Relax SDep requirement for AppleSMECompute clustering (#212603)
Do not require RAW dependency for FuseAppleSMECompute.
Commit: 8aeb59eab5eb0bc516628fa42e7698f23eb3f6d5
https://github.com/llvm/llvm-project/commit/8aeb59eab5eb0bc516628fa42e7698f23eb3f6d5
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/X86/reassociate-ops.ll
Log Message:
-----------
[SLP][NFC]Add extra tests for fadd/fsub reordering, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/213002
Commit: 3a687d3b86c44821ae2a013fe3d9f5bf88a471a9
https://github.com/llvm/llvm-project/commit/3a687d3b86c44821ae2a013fe3d9f5bf88a471a9
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M libcxx/docs/Status/Cxx17Papers.csv
M libcxx/docs/Status/Cxx20Papers.csv
Log Message:
-----------
[libc++] Fix incorrect paper statuses (#212827)
These two papers also added parallel algorithm overloads, which were
never implemented but the papers were still marked as implemented. Mark
the papers as Partial instead.
CF #103640 and #104095
Commit: a8cc3d25922b689508dc63487525c73bc2747585
https://github.com/llvm/llvm-project/commit/a8cc3d25922b689508dc63487525c73bc2747585
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M libcxx/include/__config
M libcxx/include/__filesystem/path.h
M libcxx/include/__filesystem/u8path.h
M libcxx/include/__locale
M libcxx/include/__locale_dir/locale_base_api.h
M libcxx/include/__math/gamma.h
M libcxx/include/__ostream/print.h
M libcxx/include/fstream
M libcxx/include/print
M libcxx/include/text_encoding
M libcxx/include/wchar.h
M libcxx/src/chrono.cpp
M libcxx/src/filesystem/directory_iterator.cpp
M libcxx/src/filesystem/error.h
M libcxx/src/filesystem/file_descriptor.h
M libcxx/src/filesystem/filesystem_clock.cpp
M libcxx/src/filesystem/format_string.h
M libcxx/src/filesystem/operations.cpp
M libcxx/src/filesystem/path.cpp
M libcxx/src/filesystem/path_parser.h
M libcxx/src/filesystem/posix_compat.h
M libcxx/src/filesystem/time_utils.h
M libcxx/src/fstream.cpp
M libcxx/src/include/aligned_alloc.h
M libcxx/src/include/config_elast.h
M libcxx/src/iostream.cpp
M libcxx/src/locale.cpp
M libcxx/src/print.cpp
M libcxx/src/std_stream.h
M libcxx/src/system_error.cpp
M libcxx/src/thread.cpp
M libcxx/test/support/count_new.h
Log Message:
-----------
[libc++] Clean up windows macros (#207577)
We have multiple macros for different Windows. However, most of them
don't actually define different things. We can condense the macros to
- `_WIN32` directly if it only depends on windows, or
- `_LIBCPP_MSVCRT`
This patch drops `_LIBCPP_MSVCRT_LIKE` and `_LIBCPP_WIN32API`, since
they are equivalent to `_WIN32`.
Commit: e7b04d7b58941cc9173930871a18d149f0b8a432
https://github.com/llvm/llvm-project/commit/e7b04d7b58941cc9173930871a18d149f0b8a432
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M libcxx/.clang-format
M libcxxabi/.clang-format
Log Message:
-----------
[libc++abi] Use the same .clang-format as libc++ (#208661)
libc++abi is very close to libc++, and even shares some amount of code.
We should keep the formatting style the same between the two libraries.
Commit: 7b463ebd0d5b23a5efc9ffba1363593e6c6745fb
https://github.com/llvm/llvm-project/commit/7b463ebd0d5b23a5efc9ffba1363593e6c6745fb
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/CommonArgs.cpp
A clang/test/Driver/amdgpu-assembler-xnack-sramecc.s
Log Message:
-----------
clang/AMDGPU: Forward xnack/sramecc mode to the assembler (#212955)
When assembling a .s file with no target ID directive, the requested
xnack/sramecc mode has no module flag to carry it. Forward the mode
requested via -mxnack/-msramecc (or the -mcpu target ID modifiers) to
the assembler as a target feature so it is recorded in the object's e_flags.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Commit: 76140a666d18b940597bf73362d4101af0247ea6
https://github.com/llvm/llvm-project/commit/76140a666d18b940597bf73362d4101af0247ea6
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M libcxx/test/extensions/libcxx/input.output/file.streams/fstreams/filebuf.members/xsgetn.buffer.pass.cpp
Log Message:
-----------
[libc++] Switch XFAIL in xsgetn.buffer.pass.cpp to LLVM 23 (#212969)
We want to back-port the fix for xsgetn, so the XFAIL needs to be
updated to reflect that.
Commit: c9c03ed3991035591d2a4529f323ed9e5e345221
https://github.com/llvm/llvm-project/commit/c9c03ed3991035591d2a4529f323ed9e5e345221
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/ARM/non-fp-math-op.ll
Log Message:
-----------
[SLP]Fix a crash on non-fp operator isFast request
isFast should be used only on FPMathOperator kind instructons.
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/213008
Commit: 424d5a7cb36fb4770f4436762b636ded1e035bb0
https://github.com/llvm/llvm-project/commit/424d5a7cb36fb4770f4436762b636ded1e035bb0
Author: fineg74 <61437305+fineg74 at users.noreply.github.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/tools/llvm-gpu-loader/llvm-gpu-loader.cpp
Log Message:
-----------
[OFFLOAD] Fix a platform selection issue for llvm-gpu-loader (#212893)
Currently if an image supplied to llvm-gpu-loader is not properly
detected by its platform detection logic it does not accept it for
execution. The example could be a spirv or bitcode format. This fix
allows it to rely on devices to device if an image will be accepted and
uses its existing platform detection logic as an optimization only
Commit: e9777c58be265687897e04c5d8013d7d6cb43571
https://github.com/llvm/llvm-project/commit/e9777c58be265687897e04c5d8013d7d6cb43571
Author: David Green <david.green at arm.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/arith-overflow.ll
M llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
M llvm/test/Analysis/CostModel/AArch64/arith.ll
M llvm/test/Analysis/CostModel/AArch64/clmul-fixed.ll
M llvm/test/Analysis/CostModel/AArch64/clmul.ll
M llvm/test/Analysis/CostModel/AArch64/cmp.ll
M llvm/test/Analysis/CostModel/AArch64/cttz_elts.ll
M llvm/test/Analysis/CostModel/AArch64/div.ll
M llvm/test/Analysis/CostModel/AArch64/div_cte.ll
M llvm/test/Analysis/CostModel/AArch64/fshl.ll
M llvm/test/Analysis/CostModel/AArch64/fshr.ll
M llvm/test/Analysis/CostModel/AArch64/masked-divrem.ll
M llvm/test/Analysis/CostModel/AArch64/mul.ll
M llvm/test/Analysis/CostModel/AArch64/rem.ll
M llvm/test/Analysis/CostModel/AArch64/sve-arith.ll
M llvm/test/Analysis/CostModel/AArch64/sve-div.ll
M llvm/test/Analysis/CostModel/AArch64/sve-rem.ll
M llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
Log Message:
-----------
[AArch64] Add all cost kinds for integer getArithmeticInstrCost (#210759)
This adds all (CodeSize, Latency, LatSize) costs to
getArithmeticInstrCost integer operations, getting the cost more correct
especially for operations that expand into multiple instructions.
Floating point are left to another commit to limit the impact.
Commit: dc6cd6a29a0831d1a4d607162a1dbd07b556143a
https://github.com/llvm/llvm-project/commit/dc6cd6a29a0831d1a4d607162a1dbd07b556143a
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp
Log Message:
-----------
[mlir] Honor IntrHasSideEffects on IntrNoMem LLVM intrinsics (#212760)
`[IntrNoMem, IntrHasSideEffects]` is a perfectly valid intrinsic trait
combination, and MLIR would CSE/DCE those without checking. This mirrors
how LLVM models this, see getEffectiveME in IntrinsicEmitter.cpp
Commit: 9771205212d9802c9de142335fc8af3bc52a1d85
https://github.com/llvm/llvm-project/commit/9771205212d9802c9de142335fc8af3bc52a1d85
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Record.cpp
M clang/lib/AST/ByteCode/Record.h
Log Message:
-----------
[clang][bytecode] Add Record::findBase() (#212952)
Similar to findField().
Commit: a0c7f8366b8dbbfb25d294541ab9298851cfa65f
https://github.com/llvm/llvm-project/commit/a0c7f8366b8dbbfb25d294541ab9298851cfa65f
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes ba37179 (#212986)
This fixes ba371791db4f9e7ef05f0a1c26529298b2951a4b (#212948).
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=ba371791db4f9e7ef05f0a1c26529298b2951a4b
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 6a898832ff382b1a288f9eb3bc5cd1f37d0fc29f
https://github.com/llvm/llvm-project/commit/6a898832ff382b1a288f9eb3bc5cd1f37d0fc29f
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies-av-constrain.mir
Log Message:
-----------
[AMDGPU] Fix getDestEquivalentVGPRClass narrowing AV-class registers (#212963)
isVGPRClass() rejects AV-class registers, so they were narrowed to
VGPR-only instead of preserved. Same reasoning behind the fix as in
SIPreAllocateWWMRegs (see
https://github.com/llvm/llvm-project/pull/211560)
Commit: 8b36461fb271df4484a375c4b80800fcc8ef8e91
https://github.com/llvm/llvm-project/commit/8b36461fb271df4484a375c4b80800fcc8ef8e91
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/session_helpers.py
M lldb/test/API/tools/lldb-dap/evaluate/TestDAP_evaluate.py
Log Message:
-----------
[lldb-dap] Mirgate TestDAP_evaluate. (#212282)
rewrite the `assertEvaluate` and `assertEvaluateFailure` helpers to use
the already existing `session.verify_evaluate` function. THe helpers are
now inlined functions.
Commit: 179ef900e31ef3b0dfbe762acfa0299551933c8e
https://github.com/llvm/llvm-project/commit/179ef900e31ef3b0dfbe762acfa0299551933c8e
Author: Marc Auberer <marc.auberer at chillibits.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/CommandFlags.h
M llvm/lib/CodeGen/CommandFlags.cpp
Log Message:
-----------
[CodeGen] Remove deprecated createTargetMachineForTriple overload (#212984)
This overload was deprecated in favor of the Triple overload and marked
for removal after llvm 23 branched. All in-tree callers already use the
Triple overload.
Co-authored-by: Claude <noreply at anthropic.com>
Commit: 289a4568f7d18d1d42687f3a2fc2c72bcbadaa28
https://github.com/llvm/llvm-project/commit/289a4568f7d18d1d42687f3a2fc2c72bcbadaa28
Author: Marc Auberer <marc.auberer at chillibits.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M lldb/source/Host/macosx/objcxx/HostInfoMacOSX.mm
M lldb/source/Host/windows/DomainSocketWindows.cpp
M lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm64.cpp
M llvm/include/llvm/ADT/ScopeExit.h
Log Message:
-----------
[ADT] Remove deprecated llvm::make_scope_exit (#212987)
Update remaining call sites in lldb to construct llvm::scope_exit
directly, per the deprecation notice.
---------
Co-authored-by: Claude <noreply at anthropic.com>
Commit: b11722f1d3bd5debac949fe366c1801d39b8a2bb
https://github.com/llvm/llvm-project/commit/b11722f1d3bd5debac949fe366c1801d39b8a2bb
Author: michaelselehov <michael.selehov at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/docs/CommandGuide/index.md
A llvm/docs/CommandGuide/llvm-calc-occupancy.rst
M llvm/test/CMakeLists.txt
M llvm/test/lit.cfg.py
A llvm/test/tools/llvm-calc-occupancy/basic.test
A llvm/tools/llvm-calc-occupancy/CMakeLists.txt
A llvm/tools/llvm-calc-occupancy/llvm-calc-occupancy.cpp
Log Message:
-----------
[llvm-calc-occupancy] Add an AMDGPU occupancy calculator tool (#208727)
Add a command-line utility that reports the occupancy (waves/EU) an
AMDGPU kernel would reach for a given workgroup size, VGPR/SGPR usage
and LDS. It reuses the backend's own occupancy math, so the numbers
match the compiler. Includes a lit test and a CommandGuide man page.
Assisted-by: Claude Opus
---------
Co-authored-by: mselehov <mselehov at amd.com>
Commit: 04536c4984206eb20d93355145f9f4e9a0f0d266
https://github.com/llvm/llvm-project/commit/04536c4984206eb20d93355145f9f4e9a0f0d266
Author: Pradeep Kumar <pradeepku at nvidia.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M mlir/include/mlir-c/BuiltinTypes.h
M mlir/include/mlir/Bindings/Python/IRTypes.h
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/BuiltinTypes.td
M mlir/include/mlir/IR/CommonTypeConstraints.td
M mlir/lib/AsmParser/TokenKinds.def
M mlir/lib/AsmParser/TypeParser.cpp
M mlir/lib/Bindings/Python/IRTypes.cpp
M mlir/lib/CAPI/IR/BuiltinTypes.cpp
M mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
M mlir/lib/IR/AsmPrinter.cpp
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/python/mlir/extras/types.py
M mlir/test/IR/attribute.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/python/ir/builtin_types.py
M mlir/utils/lldb-scripts/mlirDataFormatters.py
M mlir/utils/tree-sitter-mlir/grammar.js
Log Message:
-----------
[MLIR][APFloat] Add Type definitions for UE5M3 type (#212712)
This commit adds UE5M3 type definitions in MLIR based on the Float8E5M3FNU APFloat type
Commit: 31d99ba9e29acbb466380224dbad09eb8cb115ed
https://github.com/llvm/llvm-project/commit/31d99ba9e29acbb466380224dbad09eb8cb115ed
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M flang/docs/ParameterizedDerivedTypes.md
M flang/docs/fstack-arrays.md
M flang/include/flang/Optimizer/Builder/BoxValue.h
R flang/include/flang/Optimizer/Builder/Factory.h
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Optimizer/Builder/FIRBuilder.cpp
R flang/lib/Optimizer/Transforms/ArrayValueCopy.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
R flang/test/Fir/array-copies-pointers.fir
R flang/test/Fir/array-modify.fir
R flang/test/Fir/array-value-copy-2.fir
R flang/test/Fir/array-value-copy-3.fir
R flang/test/Fir/array-value-copy-4.fir
R flang/test/Fir/array-value-copy-cam4.fir
R flang/test/Fir/array-value-copy.fir
M flang/test/Transforms/stack-arrays-hlfir.f90
Log Message:
-----------
[flang] Delete the array-value-copy pass (#212643)
Since the removal of the legacy expression lowering (#210385, #210621,
#210639, #210873) nothing in flang produces the array-value operations
this pass legalizes, and #211816 already removed it from the default
pipeline. Delete the pass and the pieces that existed solely for it:
- ArrayValueCopy.cpp, its Passes.td definition,
createArrayValueCopyPass, and the (duplicated) CMake source entries.
- Optimizer/Builder/Factory.h in its entirety: the pass was its only
includer, and its contents (attrFortranArrayOffsets,
getExtents/getOrigins on shape values, originateIndices) have no other
users.
- The getTypeParams(fir::ArrayLoadOp) overload (sole caller was the
pass) and the ArrayLoadOp forward declaration in BoxValue.h.
- The pass LIT tests (array-value-copy*.fir, array-copies-pointers.fir,
array-modify.fir); stack-arrays-hlfir.f90 drops the --array-value-copy
stage from its RUN pipeline.
- The pass-describing paragraphs in fstack-arrays.md and the stale
ArrayValueCopy TODO entry in ParameterizedDerivedTypes.md.
The array-value operations themselves (fir.array_load and friends; not
fir.array_coor) remain in the dialect and will be deleted in a
follow-up.
Assisted-by: AI
Commit: 938d446f7c1caa33aed9fcfdf350419fe8fb1002
https://github.com/llvm/llvm-project/commit/938d446f7c1caa33aed9fcfdf350419fe8fb1002
Author: Luke Lau <luke at igalia.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/include/llvm/Analysis/ScalarEvolutionPatternMatch.h
M llvm/include/llvm/IR/PatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
Log Message:
-----------
[Support] Don't bring PatternMatchHelpers into top-level scope. NFC (#213016)
Commit: 6e9a51c805878c03fe0813688bd8ad2ef9cb7c6f
https://github.com/llvm/llvm-project/commit/6e9a51c805878c03fe0813688bd8ad2ef9cb7c6f
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/test/src/math/CMakeLists.txt
Log Message:
-----------
[libc][cmake] Make hermetic tests support FLAGS (#212460)
Currently the tests skip themselves because this gets treated as a
(missing) dependency.
I also enable tests that were explicitly skipped with UNIT_TEST_ONLY.
Some of the FP tests are claiming to be failing on GPUs (in 2023). If
that is still true, I'll skip them with if(TARGET_IS_GPU).
Commit: cc623d6e991ffbcf85fe5b7bc637d9070eee0015
https://github.com/llvm/llvm-project/commit/cc623d6e991ffbcf85fe5b7bc637d9070eee0015
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M libc/test/IntegrationTest/CMakeLists.txt
M libc/test/IntegrationTest/test.h
M libc/test/integration/src/pthread/pthread_name_test.cpp
M libc/test/integration/src/stdio/sprintf_size_test.cpp
M libc/test/integration/src/stdlib/CMakeLists.txt
M libc/test/integration/src/stdlib/getenv_test.cpp
M libc/test/integration/src/stdlib/putenv_test.cpp
M libc/test/integration/src/stdlib/setenv_test.cpp
M libc/test/integration/src/stdlib/unsetenv_test.cpp
M libc/test/integration/startup/gpu/args_test.cpp
M libc/test/integration/startup/linux/args_test.cpp
Log Message:
-----------
[libc][test] Add EXPECT_STREQ and ASSERT_STREQ macros for integration tests (#212729)
Add EXPECT_STREQ and ASSERT_STREQ macros to IntegrationTest/test.h using
cpp::string_view. Note that, unlike the unit test macro (but like
googletest), this version treats NULL as distinct from "". The
inconsistency is unfortunate, but I think it's important as the code is
used for testing functions like getenv(), where "" and NULL have very
different meanings.
We should probably follow this up with a change to make the unit test
macro behave the same way.
Update integration tests to use the new macros instead of handrolled
string equality functions (my_streq), strcmp, inline_strcmp, or
string_view wrappers.
Commit: 3122acf9f49012f645ea45e741b81910333a77bc
https://github.com/llvm/llvm-project/commit/3122acf9f49012f645ea45e741b81910333a77bc
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M libc/test/UnitTest/LibcDeathTestExecutors.cpp
M libc/test/UnitTest/LibcTest.cpp
M libc/test/UnitTest/LibcTest.h
M libc/test/src/strings/wide_read_memory_test.cpp
Log Message:
-----------
[libc] Move test macro implementations out of the Test class (#212783)
This is useful for several reasons:
- it makes it possible to use the macros outside of the test methods,
aligning with googletest. Although this isn't recommended, the
alternatives are often not worth it.
- it makes it possible (with additional changes) to expose this
infrastructure to C_TESTs (which currently use the assert() macro, which
is a no-op in release mode)
- it makes it possible to add (and have assertions in) googletest style
SetUp/TearDownTestSuite functions.
I've converted the main assertion macros for now, to test the waters.
I'm planning to handle EXPECT/ASSERT_THAT and EXPECT/ASSERT_EXIT/DEATH
in a follow-up.
Commit: 44840ca0fa1c3cc32278a633dc4fd86c7605392d
https://github.com/llvm/llvm-project/commit/44840ca0fa1c3cc32278a633dc4fd86c7605392d
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-binop.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-shift.ll
Log Message:
-----------
[NFC][LLVM] Cleanup Transforms/InstCombine/AArch64/sve-intrinsic-simplify-*.ll (#213012)
Commit: 0c60c8ad15a0c4255f094bc799c80a683348109c
https://github.com/llvm/llvm-project/commit/0c60c8ad15a0c4255f094bc799c80a683348109c
Author: Diego Novillo <dnovillo at nvidia.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
A llvm/test/CodeGen/SPIRV/debug-info/debug-typedef-nested-drop.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-typedef-skip-base-not-in-regs.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-typedef.ll
Log Message:
-----------
[SPIRV] Emit NonSemantic DebugTypedef (#211883)
This adds `DebugTypedef` emission to the SPIR-V
NonSemantic.Shader.DebugInfo handler.
`SPIRVNonSemanticDebugHandler` now collects `DIDerivedType` nodes tagged
`DW_TAG_typedef` and emits one `DebugTypedef` per node. The emitter
reuses the handler's type-id map and skips a typedef whose base type was
not emitted.
This one has similar limitations to the other type emitters (tracked in
#211850)
1. Typedefs are emitted in one `DebugInfoFinder`-order pass, so a
typedef whose base is another typedef emitted later in that pass is
dropped.
2. The Parent operand uses the enclosing type's id when the typedef's
scope is an emitted `DIType`, otherwise the compile unit. On its own
this PR emits no type that can be a typedef's scope. I'll address this
after debug info for composite types is in mainline.
Tests:
1. `debug-typedef.ll` covers a file-scope typedef of `int` parented to
the compile unit, checking all six operands.
2. `debug-typedef-skip-base-not-in-regs.ll` covers the skip path with a
typedef of a pointer that has no DWARF address space.
3. `debug-typedef-nested-drop.ll`: tests the one-pass limitation: a
two-level typedef emits one `DebugTypedef`, with
`--implicit-check-not=DebugTypedef`.
Commit: cf6335b275a996adff8334cb35245480ece481e1
https://github.com/llvm/llvm-project/commit/cf6335b275a996adff8334cb35245480ece481e1
Author: tfzee <tim.ziegler at intel.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/test/CodeGen/X86/avx10_2bf16-arith-scalar.ll
M llvm/test/CodeGen/X86/avx10_2bf16-fma.ll
Log Message:
-----------
[X86] Lower scalar bf16 arithmetic on AVX10.2 via packed ops (#212245)
Currently basic(fadd/fsub/fmul/fdiv/fsqrt/fma) bf16 operations, as they
are not natively supported, are expanded to f32 operations.
However with AVX10.2 there are packed versions for these operations
which should be used instead and are enabled with this PR.
Since there is no native bf16 register class I instead go through f16
since it matches its size and register class.
This conversion will end up getting optimized away leaving only the
intended packed operation.
I used AI to double check and expand on comments.
Commit: 409b7b49623582da0b5f6a6eb5e607ffe19cd349
https://github.com/llvm/llvm-project/commit/409b7b49623582da0b5f6a6eb5e607ffe19cd349
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
[NFC][AArch64ISelLowering] Use getExtractSubvector and getInsertSubvector helpers. (#213004)
Commit: f30df0953917256142cfbe1172e22ebbca8204b3
https://github.com/llvm/llvm-project/commit/f30df0953917256142cfbe1172e22ebbca8204b3
Author: Fateme Hosseini <Fhossein at qti.qualcomm.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.h
A llvm/test/CodeGen/Hexagon/fmaximum.ll
A llvm/test/CodeGen/Hexagon/fminimum.ll
Log Message:
-----------
[Hexagon] Fix ISel error: LLVM: cannot select -fmaximum (#211283)
This patch adds a custom lowering for FMAXIMUM.
FMAXIMUM is NaN-propagating, and currently, we
don't have any hexagon instruction to support
that behaviour. The patch is also extended to
cover FMINIMUM as well.
Check if any of the inputs are NaN. If so,
propagate the NaN to the output, otherwise
return the maximum/minimum of the inputs,
using ISD::FMINNUM/ISD::FMAXNUM to run
Hexagon's F2_sfmin/F2_sfmax when no operand
is NaN. NaN is propagated (rather than
replaced with a new ConstantFP NaN node) to
avoid triggering a wrong C2_MUX selection in
ISD::SELECT.
Commit: 2d697f8562d7845d5554cc1d2cd2264401b9d68f
https://github.com/llvm/llvm-project/commit/2d697f8562d7845d5554cc1d2cd2264401b9d68f
Author: Zahira Ammarguellat <zahira.ammarguellat at intel.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/include/clang/AST/StmtOpenMP.h
M clang/lib/AST/StmtOpenMP.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/test/OpenMP/fuse_codegen.cpp
M clang/test/OpenMP/interchange_codegen.cpp
A clang/test/OpenMP/loop_transform_final_iv.c
M clang/test/OpenMP/reverse_codegen.cpp
M clang/test/OpenMP/stripe_codegen.cpp
M clang/test/OpenMP/tile_codegen.cpp
Log Message:
-----------
[OpenMP] Restore loop variable values after loop-transformation constructs. (#212853)
This PR relands #208533 which was reverted in #212832 due to test
failures with iterator-based loops.
Original Change:
#208533 fixes loop variable finalization for OpenMP 6.0
loop-transformations constructs: tile, stripe, reverse, interchange and
fuse to comply with spec requirement page 371, lines 19-21. The spec
requires that "After the execution of the loop-transforming construct,
the loop-iteration variables of any of its transformation-affected loops
have the values that they would have without the loop-transforming
directive".
What's Fixed in This Reland:
The original implementation attempted to finalize all loop variables,
including iterators in range-based for loops (CXXForRangeStmt). This
caused issues because the finalization formula `final_value =
lower_bound + num_iterations * step` only applies to arithmetic types
(integers, floats).
Commit: b95468ff04ba648fa637a4c0783b0e2d332b712c
https://github.com/llvm/llvm-project/commit/b95468ff04ba648fa637a4c0783b0e2d332b712c
Author: Paulius Velesko <pvelesko at pglc.io>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/lib/Driver/ToolChains/HIPSPV.cpp
M clang/lib/Driver/ToolChains/HIPSPV.h
M clang/test/Driver/hipspv-link-static-library.hip
M clang/test/Driver/hipspv-pass-plugin.hip
M clang/test/Driver/hipspv-toolchain.hip
M llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
Log Message:
-----------
[HIPSPV] Add in-tree SPIR-V backend support for chipStar (#206910)
Commit: cb0944c34b44c4ceadc891e7ee8fd5013ada8b93
https://github.com/llvm/llvm-project/commit/cb0944c34b44c4ceadc891e7ee8fd5013ada8b93
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M offload/unittests/OffloadAPI/device_code/CMakeLists.txt
M offload/unittests/OffloadAPI/program/olCreateProgram.cpp
Log Message:
-----------
[offload][lit] Add jit unittest (#212860)
Basic test for the JIT path.
Context: https://github.com/llvm/llvm-project/pull/212823
---------
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: 11d7c9c9b4e8ebaf5f9bfb6ba80aecd498aa25ca
https://github.com/llvm/llvm-project/commit/11d7c9c9b4e8ebaf5f9bfb6ba80aecd498aa25ca
Author: michaelselehov <michael.selehov at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/tools/llvm-calc-occupancy/llvm-calc-occupancy.cpp
Log Message:
-----------
[llvm-calc-occupancy] Fix build after SGPR queries moved to TargetParser (#213023)
Urgent buildbot fix for #208727.
That PR was developed before #209848, which moved the SGPR count queries
into TargetParser and removed
`AMDGPU::IsaInfo::getAddressableNumSGPRs()`, so
`llvm-calc-occupancy.cpp` fails to compile on current `main`:
```
llvm-calc-occupancy.cpp:229:41: error: no member named 'getAddressableNumSGPRs' in namespace 'llvm::AMDGPU::IsaInfo'
```
This switches to the equivalent
`GCNSubtarget::getAddressableNumSGPRs()`, which forwards to the
TargetParser version. All other `IsaInfo::*` calls in the file were
checked against the new API and are unaffected.
Verified locally: `ninja llvm-calc-occupancy` builds clean,
`llvm/test/tools/llvm-calc-occupancy` passes, and the reported
addressable SGPR count is unchanged (102 on gfx90a).
Commit: 3b2fe5ae137b845c83a3e435b23f1d9c2abb17f6
https://github.com/llvm/llvm-project/commit/3b2fe5ae137b845c83a3e435b23f1d9c2abb17f6
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/AArch64/trimmed-node-gather-cost.ll
Log Message:
-----------
[SLP][NFC]Add a test with the non-profitable vectorization, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/213028
Commit: e001308a83cace2f133edf4ee08c574ba7c2c702
https://github.com/llvm/llvm-project/commit/e001308a83cace2f133edf4ee08c574ba7c2c702
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M libcxx/src/exception.cpp
M libcxx/src/support/runtime/exception_fallback.ipp
Log Message:
-----------
[libc++] Fix exception_fallback.ipp not compiling (#212961)
Commit: a853e6fcaf602b3c9bdd21a02af2c4f32a2cb5d1
https://github.com/llvm/llvm-project/commit/a853e6fcaf602b3c9bdd21a02af2c4f32a2cb5d1
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M libc/config/linux/aarch64/headers.txt
M libc/config/linux/arm/headers.txt
M libc/config/linux/i386/headers.txt
M libc/config/linux/riscv/headers.txt
M libc/config/linux/x86_64/headers.txt
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/struct_passwd.h
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/struct_passwd.h
A libc/include/pwd.yaml
M libc/src/CMakeLists.txt
A libc/src/pwd/CMakeLists.txt
A libc/src/pwd/pwd_utils.cpp
A libc/src/pwd/pwd_utils.h
M libc/test/src/CMakeLists.txt
A libc/test/src/pwd/CMakeLists.txt
A libc/test/src/pwd/pwd_utils_test.cpp
Log Message:
-----------
[libc] Add struct passwd type, pwd.yaml, and pwd_utils parser (#212421)
Added struct passwd type definition, pwd.yaml header specification, and
parse_passwd_line utility returning ErrorOr<struct passwd> for
colon-separated
password file parsing with hermetic unit tests.
Note: Additional POSIX pwd.h functions (getpwuid, getpwnam, getpwuid_r,
getpwnam_r, fgetpwent) are omitted from this initial change and will be
added in follow-up PRs.
* Added libc/include/llvm-libc-types/struct_passwd.h and proxy header
* Added libc/include/pwd.yaml header specification
* Added pwd_utils.h and pwd_utils.cpp implementing ErrorOr<struct
passwd> parse_passwd_line
* Added pwd.h to target public headers for linux architectures
* Added unit tests in libc/test/src/pwd/pwd_utils_test.cpp
Assisted-by: Automated tooling, human reviewed.
Commit: d7c1e6054fb66a5954a6403d3803f7bc5f1eb449
https://github.com/llvm/llvm-project/commit/d7c1e6054fb66a5954a6403d3803f7bc5f1eb449
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/PhaseOrdering/X86/avg.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/trimmed-node-gather-cost.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-parent-instr-copyable-regular.ll
M llvm/test/Transforms/SLPVectorizer/X86/poor-throughput-seeds.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr46983.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-node-reused-in-later-vector.ll
M llvm/test/Transforms/SLPVectorizer/X86/subvector-minbitwidth-unsigned-value.ll
Log Message:
-----------
[SLP]Recalculate gather costs after tree trimming
Gather node costs are computed against the set of vectorized nodes
available for reuse. Tree trimming changes that set, but the costs were
not recalculated: a gather that reused a trimmed-away vectorized value
kept its 0 cost, and the node transformed to a gather matched the same
sibling gather for a free reuse, so the buildvector cost was lost and
unprofitable trees were vectorized.
Recalculate costs of all gather nodes after trimming.
Fixes #212983
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/213034
Commit: e74432084f392d19bf7f30dfd58d3c47a1a32178
https://github.com/llvm/llvm-project/commit/e74432084f392d19bf7f30dfd58d3c47a1a32178
Author: David Young <davidayoung at meta.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
Log Message:
-----------
[Bazel] Fix Host target's exported headers to include windows (#213018)
When PR# 201283 added windows os select to the build of the Host target,
it missed the exported headers since the CI checks run only linux and
mac (and I hadn't gotten to this in my slow slog of windows bazel lldb
support). I found when translating to BUCK and running into this
compilation error on windows for buck2 built lldb.
Still cannot build and claude tells me the exclude is necessary to avoid
a duplicate.
claude assisted with bazel rule creation
Commit: aa07c1f12d5d7fd61484236fbfdb2c26c81575fe
https://github.com/llvm/llvm-project/commit/aa07c1f12d5d7fd61484236fbfdb2c26c81575fe
Author: Manuel Carrasco <Manuel.Carrasco at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
A llvm/test/CodeGen/SPIRV/debug-info/debug-function-namespace-scope.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-function-with-declaration.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-function.ll
Log Message:
-----------
Implement support for NSDI DebugFunction opcode. (#211760)
Add support for
[DebugFunction](https://github.khronos.org/SPIRV-Registry/nonsemantic/NonSemantic.Shader.DebugInfo.html#DebugFunction).
Commit: 2f08dff5138a4ce908b6d4511a9439e859fedf86
https://github.com/llvm/llvm-project/commit/2f08dff5138a4ce908b6d4511a9439e859fedf86
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/struct_statfs.h
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/fsid_t.h
A libc/include/llvm-libc-types/struct_statfs.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
A libc/src/__support/OSUtil/linux/syscall_wrappers/fstatfs.h
A libc/src/__support/OSUtil/linux/syscall_wrappers/statfs.h
M libc/src/sys/statvfs/linux/CMakeLists.txt
M libc/src/sys/statvfs/linux/fstatvfs.cpp
M libc/src/sys/statvfs/linux/statfs_utils.h
M libc/src/sys/statvfs/linux/statvfs.cpp
M libc/src/unistd/linux/CMakeLists.txt
M libc/src/unistd/linux/fpathconf.cpp
M libc/src/unistd/linux/pathconf.cpp
M libc/src/unistd/linux/pathconf_utils.cpp
M libc/src/unistd/linux/pathconf_utils.h
Log Message:
-----------
[libc] Refactor statfs Linux syscalls and provide 'struct statfs' (#212930)
* Extract statfs/fstatfs Linux syscall wrappers to
`linux/syscall_wrappers` directory;
* Provide our own definition of `struct statfs` type and a corresponding
proxy header (to use system type in overlay mode);
* Migrate callers (e.g. statfs->statvfs translation) to use the new
syscall wrapper.
This would allow us to add Linux-specific (non-POSIX) `<sys/statfs.h>`
header as a next step.
Assisted by: Gemini, human-reviewed
Commit: 11b58f0e4c84437b2c39e0e5cc415077b3fe06d3
https://github.com/llvm/llvm-project/commit/11b58f0e4c84437b2c39e0e5cc415077b3fe06d3
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M libcxx/docs/ReleaseNotes/24.rst
M libcxx/docs/Status/Cxx26Papers.csv
M libcxx/include/__ranges/elements_view.h
M libcxx/include/__ranges/filter_view.h
M libcxx/include/__ranges/iota_view.h
M libcxx/include/__ranges/istream_view.h
M libcxx/include/__ranges/join_view.h
M libcxx/include/__ranges/lazy_split_view.h
M libcxx/include/__ranges/split_view.h
M libcxx/include/__ranges/take_view.h
M libcxx/include/__ranges/take_while_view.h
M libcxx/include/__ranges/transform_view.h
M libcxx/test/std/ranges/range.adaptors/range.elements/iterator/base.pass.cpp
A libcxx/test/std/ranges/range.adaptors/range.elements/iterator/ctor.base.compile.pass.cpp
R libcxx/test/std/ranges/range.adaptors/range.elements/iterator/ctor.base.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.elements/iterator/ctor.other.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.elements/sentinel/base.pass.cpp
A libcxx/test/std/ranges/range.adaptors/range.elements/sentinel/ctor.base.compile.pass.cpp
R libcxx/test/std/ranges/range.adaptors/range.elements/sentinel/ctor.base.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.elements/sentinel/ctor.convert.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.filter/iterator/arrow.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.filter/iterator/base.pass.cpp
A libcxx/test/std/ranges/range.adaptors/range.filter/iterator/ctor.parent.iter.compile.pass.cpp
R libcxx/test/std/ranges/range.adaptors/range.filter/iterator/ctor.parent_iter.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.filter/iterator/deref.pass.cpp
A libcxx/test/std/ranges/range.adaptors/range.filter/sentinel/ctor.parent.compile.pass.cpp
R libcxx/test/std/ranges/range.adaptors/range.filter/sentinel/ctor.parent.pass.cpp
A libcxx/test/std/ranges/range.adaptors/range.join/range.join.sentinel/ctor.parent.compile.pass.cpp
R libcxx/test/std/ranges/range.adaptors/range.join/range.join.sentinel/ctor.parent.pass.cpp
A libcxx/test/std/ranges/range.adaptors/range.lazy.split/range.lazy.split.inner/ctor.outer_iterator.compile.pass.cpp
R libcxx/test/std/ranges/range.adaptors/range.lazy.split/range.lazy.split.inner/ctor.outer_iterator.pass.cpp
A libcxx/test/std/ranges/range.adaptors/range.lazy.split/range.lazy.split.outer/ctor.parent.base.compile.pass.cpp
A libcxx/test/std/ranges/range.adaptors/range.lazy.split/range.lazy.split.outer/ctor.parent.compile.pass.cpp
R libcxx/test/std/ranges/range.adaptors/range.lazy.split/range.lazy.split.outer/ctor.parent.pass.cpp
R libcxx/test/std/ranges/range.adaptors/range.lazy.split/range.lazy.split.outer/ctor.parent_base.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.split/iterator/base.pass.cpp
R libcxx/test/std/ranges/range.adaptors/range.split/iterator/ctor.base.pass.cpp
A libcxx/test/std/ranges/range.adaptors/range.split/iterator/ctor.parent.iter.subrange.compile.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.split/iterator/deref.pass.cpp
A libcxx/test/std/ranges/range.adaptors/range.split/sentinel/ctor.parent.compile.pass.cpp
R libcxx/test/std/ranges/range.adaptors/range.split/sentinel/ctor.parent.pass.cpp
R libcxx/test/std/ranges/range.adaptors/range.take.while/sentinel/ctor.base.pass.cpp
A libcxx/test/std/ranges/range.adaptors/range.take.while/sentinel/ctor.base.pred.compile.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.take.while/sentinel/ctor.convert.pass.cpp
A libcxx/test/std/ranges/range.adaptors/range.take/range.take.sentinel/ctor.base.compile.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.take/range.take.sentinel/ctor.pass.cpp
A libcxx/test/std/ranges/range.adaptors/range.transform/iterator/ctor.parent.iter.compile.pass.cpp
A libcxx/test/std/ranges/range.adaptors/range.transform/sentinel/ctor.base.compile.pass.cpp
A libcxx/test/std/ranges/range.factories/range.iota.view/iterator/ctor.value.compile.pass.cpp
R libcxx/test/std/ranges/range.factories/range.iota.view/iterator/ctor.value.pass.cpp
A libcxx/test/std/ranges/range.factories/range.iota.view/sentinel/ctor.value.compile.pass.cpp
R libcxx/test/std/ranges/range.factories/range.iota.view/sentinel/ctor.value.pass.cpp
M libcxx/test/std/ranges/range.factories/range.istream.view/ctor.pass.cpp
A libcxx/test/std/ranges/range.factories/range.istream.view/iterator/ctor.parent.compile.pass.cpp
R libcxx/test/std/ranges/range.factories/range.istream.view/iterator/ctor.pass.cpp
M libcxx/test/std/ranges/range.factories/range.istream.view/iterator/deref.pass.cpp
Log Message:
-----------
[libc++][ranges] P3059R2: Making user-defined constructors of view iterators/sentinels private (#193891)
Implements https://wg21.link/P3059R2 (DR)
Closes #189599
1. Made constructors of iterator and sentinel types of the following
views private:
- `iota_view`
- `basic_istream_view`
- `filter_view`
- `transform_view`
- `take_view`
- `take_while_view`
- `join_view`
- `lazy_split_view`
- `split_view`
- `elements_view`
2. Updated all relevant tests to fix the usages of the now private
constructor, including:
1. Removed now obsolete tests (files and cases).
2. Updated all relevant tests to get the iterators and the sentinels via
`begin()` and `end()`, wherever applicable .
3. Added test cases to confirm that P3059R2 was implemented properly.
4. Minor other (necessary) tweaks.
---------
Co-authored-by: Hristo Hristov <zingam at outlook.com>
Co-authored-by: A. Jiang <de34 at live.cn>
Commit: 7ccf4e638e3f0106b3c8f36a3e4d9e67c40b8d1d
https://github.com/llvm/llvm-project/commit/7ccf4e638e3f0106b3c8f36a3e4d9e67c40b8d1d
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
Log Message:
-----------
[RISCV] Improve lowerVECTOR_SHUFFLEAsPPair. (#212895)
Allow V1 and V2 to be swapped. Allow V1 or V2 to be used twice.
Assisted-by: Claude
Commit: 66d049cdad21a7ad387f358f7593bee91221bd39
https://github.com/llvm/llvm-project/commit/66d049cdad21a7ad387f358f7593bee91221bd39
Author: Kyungtak Woo <kevinwkt at google.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M libcxx/include/__random/mersenne_twister_engine.h
M libcxx/test/std/numerics/rand/rand.eng/rand.eng.mers/ctor_sseq.pass.cpp
M libcxx/test/std/numerics/rand/rand.eng/rand.eng.mers/seed_sseq.pass.cpp
Log Message:
-----------
[libc++] Fix std::mt19937 seeding with std::seed_seq under vectorized ABI (#209860)
This PR fixes a bug in `std::mersenne_twister_engine::seed(_Sseq&)`
where the initialization twist is bypassed when the vectorized engine
optimization (`_LIBCPP_ABI_VECTORIZED_MERSENNE_TWISTER_ENGINE`) is
enabled.
In the vectorized implementation introduced in #206423, the engine state
must be pre-twisted during initialization by calling
`__update_all_states()` at the end of the `seed` functions.
However, in `seed(_Sseq& __q)`, the all-zero state check contains an
early `return;` when a non-zero state is verified. This early return
bypasses the trailing `__update_all_states()` call. Consequently, the
generator is initialized with raw, untwisted seed values (tempered)
rather than the standard twisted values.
This only manifests when compiled with unstable ABI settings
(`_LIBCPP_ABI_VERSION >= 2`) which enables the vectorized
implementation.
I replaced the early `return;` inside the all-zero state verification
block with a loop break, and conditionalized the zero-state fix using
the loop index `__i`, ensuring `__update_all_states()` is always
executed at the end of the function. Added regression tests to
`seed_sseq.pass.cpp` asserting the exact deterministic outputs for both
32-bit and 64-bit engines.
Commit: e696fb5963f9c9f1e50d1da1bab6430c58ac3da1
https://github.com/llvm/llvm-project/commit/e696fb5963f9c9f1e50d1da1bab6430c58ac3da1
Author: Benedek Kaibas <82393336+benedekaibas at users.noreply.github.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/LifetimeModeling.cpp
M clang/lib/StaticAnalyzer/Checkers/UseAfterLifetimeEnd.cpp
M clang/test/Analysis/lifetime-bound.cpp
Log Message:
-----------
[analyzer] Improve UseAfterLifetimeEnd checker's diagnostic with descriptive names and value tracking (#212158)
Currently the `UseAfterLifetimeEnd` checker used `getString()` for
constructing error message. However, `getString()` is a debug only
stringification and should not be used for emitting reports to the
users. That is why I have changed it to `getDescriptiveName()` and also
implemented the `getRegionName`(#211552) function to return the region's
descriptive name. The `getRegionName()` function got also moved to the
modeling checker since both of the reporting checkers consume it
(#211818). This PR also uses the `trackStoredValue()` for value tracking
path notes, so the report points at where the value's source came from.
Commit: e5bc20b1a810aec0cb7df3f3a834d14a0418ece0
https://github.com/llvm/llvm-project/commit/e5bc20b1a810aec0cb7df3f3a834d14a0418ece0
Author: Ilia Kuklin <ikuklin at accesssoftek.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M lldb/docs/dil-expr-lang.ebnf
M lldb/include/lldb/ValueObject/DILAST.h
M lldb/include/lldb/ValueObject/DILEval.h
M lldb/include/lldb/ValueObject/DILLexer.h
M lldb/include/lldb/ValueObject/DILParser.h
M lldb/source/ValueObject/DILAST.cpp
M lldb/source/ValueObject/DILEval.cpp
M lldb/source/ValueObject/DILLexer.cpp
M lldb/source/ValueObject/DILParser.cpp
M lldb/test/API/commands/frame/var-dil/expr/Bitwise/TestFrameVarDILBitwise.py
M lldb/test/API/commands/frame/var-dil/expr/Bitwise/main.cpp
Log Message:
-----------
[lldb] Add bitwise operators to DIL (#209768)
Add binary bitwise operators `|`, `^`, `&`, and unary bitwise `~`.
Commit: bf4bafc5595b8ed408121e0c5c695b23d52394fc
https://github.com/llvm/llvm-project/commit/bf4bafc5595b8ed408121e0c5c695b23d52394fc
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/test/Analysis/string-search-modeling.c
Log Message:
-----------
[analyzer] Require x86 target for Analysis/string-search-modeling.c (#213048)
This is a fixup to #212124.
The Solaris/sparcv9 build bot failure was reported in:
https://github.com/llvm/llvm-project/pull/212124#issuecomment-5130635364
Build bot failure:
https://lab.llvm.org/buildbot/#/builders/13/builds/14261
```
# RUN: at line 3
/opt/llvm-buildbot/home/solaris11-sparcv9/clang-solaris11-sparcv9/stage1/bin/clang -cc1 -internal-isystem /opt/llvm-buildbot/home/solaris11-sparcv9/clang-solaris11-sparcv9/stage1/lib/clang/24/include -nostdsysteminc -analyze -setup-static-analyzer -std=c17 -verify /opt/llvm-buildbot/home/solaris11-sparcv9/clang-solaris11-sparcv9/llvm/clang/test/Analysis/string-search-modeling.c -analyzer-checker=core,unix -analyzer-checker=debug.ExprInspection -analyzer-config eagerly-assume=false
# executed command: /opt/llvm-buildbot/home/solaris11-sparcv9/clang-solaris11-sparcv9/stage1/bin/clang -cc1 -internal-isystem /opt/llvm-buildbot/home/solaris11-sparcv9/clang-solaris11-sparcv9/stage1/lib/clang/24/include -nostdsysteminc -analyze -setup-static-analyzer -std=c17 -verify /opt/llvm-buildbot/home/solaris11-sparcv9/clang-solaris11-sparcv9/llvm/clang/test/Analysis/string-search-modeling.c -analyzer-checker=core,unix -analyzer-checker=debug.ExprInspection -analyzer-config eagerly-assume=false
# RUN: at line 10
/opt/llvm-buildbot/home/solaris11-sparcv9/clang-solaris11-sparcv9/stage1/bin/clang -cc1 -internal-isystem /opt/llvm-buildbot/home/solaris11-sparcv9/clang-solaris11-sparcv9/stage1/lib/clang/24/include -nostdsysteminc -analyze -setup-static-analyzer -triple x86_64-scei-ps4 -std=c17 -verify /opt/llvm-buildbot/home/solaris11-sparcv9/clang-solaris11-sparcv9/llvm/clang/test/Analysis/string-search-modeling.c -analyzer-checker=core,unix -analyzer-checker=debug.ExprInspection -analyzer-config eagerly-assume=false
# executed command: /opt/llvm-buildbot/home/solaris11-sparcv9/clang-solaris11-sparcv9/stage1/bin/clang -cc1 -internal-isystem /opt/llvm-buildbot/home/solaris11-sparcv9/clang-solaris11-sparcv9/stage1/lib/clang/24/include -nostdsysteminc -analyze -setup-static-analyzer -triple x86_64-scei-ps4 -std=c17 -verify /opt/llvm-buildbot/home/solaris11-sparcv9/clang-solaris11-sparcv9/llvm/clang/test/Analysis/string-search-modeling.c -analyzer-checker=core,unix -analyzer-checker=debug.ExprInspection -analyzer-config eagerly-assume=false
# .---command stderr------------
# | error: 'expected-warning' diagnostics expected but not seen:
# | File /opt/llvm-buildbot/home/solaris11-sparcv9/clang-solaris11-sparcv9/llvm/clang/test/Analysis/string-search-modeling.c Line 528: TRUE
# | File /opt/llvm-buildbot/home/solaris11-sparcv9/clang-solaris11-sparcv9/llvm/clang/test/Analysis/string-search-modeling.c Line 539: TRUE
# | File /opt/llvm-buildbot/home/solaris11-sparcv9/clang-solaris11-sparcv9/llvm/clang/test/Analysis/string-search-modeling.c Line 551: TRUE
# | File /opt/llvm-buildbot/home/solaris11-sparcv9/clang-solaris11-sparcv9/llvm/clang/test/Analysis/string-search-modeling.c Line 565: TRUE
# | error: 'expected-warning' diagnostics seen but not expected:
# | File /opt/llvm-buildbot/home/solaris11-sparcv9/clang-solaris11-sparcv9/llvm/clang/test/Analysis/string-search-modeling.c Line 528: FALSE [debug.ExprInspection]
# | File /opt/llvm-buildbot/home/solaris11-sparcv9/clang-solaris11-sparcv9/llvm/clang/test/Analysis/string-search-modeling.c Line 539: FALSE [debug.ExprInspection]
# | File /opt/llvm-buildbot/home/solaris11-sparcv9/clang-solaris11-sparcv9/llvm/clang/test/Analysis/string-search-modeling.c Line 551: FALSE [debug.ExprInspection]
# | File /opt/llvm-buildbot/home/solaris11-sparcv9/clang-solaris11-sparcv9/llvm/clang/test/Analysis/string-search-modeling.c Line 565: FALSE [debug.ExprInspection]
# | 8 errors generated.
# `-----------------------------
# error: command failed with exit status: 1
```
Commit: 3d6d0457bbc4698cb515f5d68e981a1ebf3d724e
https://github.com/llvm/llvm-project/commit/3d6d0457bbc4698cb515f5d68e981a1ebf3d724e
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-strict_fsub.mir
Log Message:
-----------
AMDGPU/GlobalISel: Switch some FP opcodes to extended LLTs (#212664)
Migrate G_FADD, G_FMUL, G_FMA, and G_FSUB and their strict variants,
along with G_FCANONICALIZE to use extended LLTs.
Also update the relevant MIR tests.
Commit: 0eddedc4e718f05617c8649be78c72eda60d14a2
https://github.com/llvm/llvm-project/commit/0eddedc4e718f05617c8649be78c72eda60d14a2
Author: Ian Li <ian.li at intel.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/lib/Tooling/DependencyScanningTool.cpp
A clang/test/ClangScanDeps/modules-invalid-target.c
Log Message:
-----------
[clang][DependencyScanning] Return failure upon CompilerInstanceWithContext failure to create target (#211607)
This was first pointed out by a static analysis scan: Success/failure
results from `CompilerInstance::createTarget` in
`CompilerInstanceWithContext::initialize` is currently being discarded.
AFAICT, `initialize` should have failed if
`CompilerInstance::createTarget` failed, as I noticed that calls in
`CompilerInstanceWithContext::computeDependencies` (which is ran right
after `initialize`) contains function calls (i.e. `CI.loadModule`) that
make references to `CompilerInstance::getTarget`: `getTarget` then tries
to obtain a reference to the very `TargetInfo` instance that the earlier
`CompilerInstance::createTarget` call failed to create.
AFAIK `createTarget` doesn't actually seem to fail currently, but I
haven't been able to find a good reason as for why success/failure from
`CompilerInstance::createTarget` should be ignored even if it failed.
But please let me know if I am not seeing something here!
Commit: e4c2875c397861ea45a0cca05107d91d7d785d03
https://github.com/llvm/llvm-project/commit/e4c2875c397861ea45a0cca05107d91d7d785d03
Author: Ehren Bendler <143813417+ebendler at users.noreply.github.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/docs/UsersManual.md
M clang/docs/analyzer/user-docs/CommandLineUsage.rst
Log Message:
-----------
[clang][docs] Update CommandLineUsage and UsersManual with some flags (#209519)
The current user-manual is missing implemented options that are useful
for machine-readable output, such as `-fdiagnostics-format=sarif` and
`-fdiagnostics-absolute-paths`.
Commit: 565fdb70e6063e27230f6397d2cbccf1003beaed
https://github.com/llvm/llvm-project/commit/565fdb70e6063e27230f6397d2cbccf1003beaed
Author: Yoonseo Choi <Yoonseo.Choi at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
A llvm/test/CodeGen/AMDGPU/asyncmark-merge-rebase-pregfx12.mir
Log Message:
-----------
[AMDGPU] SIInsertWaitcnts: rebase async marks into the merged frame at CFG joins (#211688)
This PR fixes `WaitcntBrackets::mergeAsyncMarks` to call `mergeScore` at
CFG join block even when one of its predecessors has no AsyncMark
At a CFG join block, the upper bounds of counts from predecessors are
merged. Then,
`mergeScore` rebase each predecessor’s `Score` by the merged upper
bound. Even if a predecessor has no AsyncMark, scores of other
predecessors with AsyncMarks should be rebased by `mergeScore`.
Suppose a predecessor, bb B, without AsyncMark (Score 0) visited later
than another predecessor with AsyncMarks (positive Score), bb A. If
merging upper bounds of bb B into that of bb A increases the new global
upper bounds to UB’ from UB, bb A’s Score should be rebased by the new
UB’. Previously in that case, only UB was merged but Score of bb A was
not updated as `mergeScore` was not called due to bb B’s having zero
score.
Detailed example can be seen in added test,
`llvm/test/CodeGen/AMDGPU/asyncmark-merge-rebase-pregfx12.mir`. Here are
the descriptions on the test.
The join (bb.3) has two predecessors:
- (bb.2) an AsyncMark predecessor: one async LDS DMA + ASYNCMARK, so one
AsyncMark recorded at LOAD_CNT score 1 (small frame, UB = 1).
- (bb.1) a load predecessor: several async LDS DMAs with no ASYNCMARK.
These stay
outstanding (they write LDS, no VGPR result) and extend the frame to UB
= 4,
but contribute no async marks.
si-insert-waitcnts visits the branch target bb.2 before the fall-through
bb.1. So, bb.2 seeds bb.3's incoming state and bb.1 with an empty
AsyncMarks list is merged in.
When UB of LOAD_CNT is still merged to 4 = max(1,4).
If bb.2's Score 1 is not rebased to new UB 4, the vmcnt value wrongly
becomes 3 (= 4 - 1), which was the previous behavior.
Score 1 must be rebased to 4 (= 1 + (4 - 1)) to make correct vmcnt, 0 (=
4 - 4). That rebase logic is already within `mergeScore`. `mergeScore`
should be called even when one of the predecessors has zero Score.
Notice that the bug doesn’t show up if bb.1 was visited before bb.2.
Commit: 75b5df8f0af1000cae8e21fedbc14d0c51a01318
https://github.com/llvm/llvm-project/commit/75b5df8f0af1000cae8e21fedbc14d0c51a01318
Author: Sirraide <aeternalmail at gmail.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/Basic/DiagnosticLexKinds.td
M clang/include/clang/Lex/PPCallbacks.h
M clang/include/clang/Lex/Preprocessor.h
M clang/lib/Frontend/PrintPreprocessedOutput.cpp
M clang/lib/Lex/PPExpressions.cpp
M clang/lib/Lex/Pragma.cpp
M clang/lib/Lex/Preprocessor.cpp
A clang/test/Preprocessor/pragma_set_pp_state.cpp
M clang/test/SemaCXX/libstdcxx_format_kind_hack.cpp
Log Message:
-----------
[Clang] Support libstdc++ workarounds when using `-E` (#210802)
We have a libstdc++ workaround in place to address a hack in libstdc++15
that is used in the definition of `std::format_kind`. GCC accepts the
hack, while Clang does not. libstdc++ was eventually updated to remove
the hack, but we still need the workaround for some versions of
libstdc++15 (see #139560 for more information).
Whether this workaround (and others that address libstdc++ hacks) is
active depends on the value of `__GLIBCXX__`. This stops working if
someone first preprocesses the input (via `-E`) and then attempts to
compile the preprocessed code with Clang (see #160314): since
preprocessing has already happened, `__GLIBCXX__` will be undefined and
the workaround will not be applied.
In case of this particular workaround, this results in `#include
<format>` failing to compile on some versions of libstdc++ if you’re
using separate preprocessing.
To resolve this problem, this patch introduces a new pragma (`#pragma
clang __set_pp_state MACRO_NAME INTEGER`). This is intended as a general
solution to preserving preprocessor state across runs of the
preprocessor.
Currently, the only supported value for `MACRO_NAME`is `__GLIBCXX__`.
When we encounter this form of the pragma, we update
`Preprocessor::CXXStandardLibraryVersion` (we don’t actually define
`__GLIBCXX__` or do anything w/ that macro here). In `-E` mode, the
pragma is retained in the output, and a pragma is emitted for `#define
__GLIBCXX__` if printing macro definitions is disabled.
Things like `#undef __GLIBCXX__` and redefinitions of `__GLIBCXX__` are
deliberately left unhandled (i.e. you get what you get), since users
shouldn’t ever be undefining or redefining this macro anyway (and since
it starts w/ `__`, it would also be UB to do so).
Fixes #160314.
Commit: 7850239749970847955a918d731630b35c540af2
https://github.com/llvm/llvm-project/commit/7850239749970847955a918d731630b35c540af2
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M lldb/docs/use/mcp.md
Log Message:
-----------
[lldb][docs] Rewrite the MCP documentation for lldb-mcp (#212821)
The docs still describe lldb-mcp as a thin stdio-to-socket bridge that
auto-launches an LLDB and exposes a single lldb_command tool. It is now
a full featured multiplexer hosting its own sessions, with four tools
and pid-qualified URIs. Also restructure the documentation around how it
is used, with an explanation of the underlying architecture towards the
end.
Commit: ce7a6f9d239979d9ae7d4c422d830a17dbb4075a
https://github.com/llvm/llvm-project/commit/ce7a6f9d239979d9ae7d4c422d830a17dbb4075a
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi-sat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui-sat.mir
Log Message:
-----------
AMDGPU/GlobalISel: Switch more FP opcodes to extended LLTs (part 2) (#212909)
Migrate G_FPOW, G_FPOWI, G_INTRINSIC_FPTRUNC_ROUND, and FP<->INT
conversions opcodes to extended float LLTs.
Also update the relevant MIR tests.
Commit: f38336987beb7f173e448e50578208b37027c035
https://github.com/llvm/llvm-project/commit/f38336987beb7f173e448e50578208b37027c035
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M lldb/docs/resources/build.md
Log Message:
-----------
[lldb][docs] Document the script interpreter plugin build options (#212655)
Describe LLDB_ENABLE_DYNAMIC_SCRIPTINTERPRETERS and how it interacts
with LLDB_ENABLE_PYTHON_LIMITED_API, including the platform defaults for
both and why the Python Limited API requires dynamic script interpreter
plugins everywhere but Windows.
Commit: 0cfc5bc3aa10274776306e4a4a179974d3fadb4b
https://github.com/llvm/llvm-project/commit/0cfc5bc3aa10274776306e4a4a179974d3fadb4b
Author: Ian Tayler Lessa <ian.taylerlessa at arm.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
Log Message:
-----------
[mlir][tosa][tosa-to-linalg] Use 0 weights at skippable RFFT2D locations (#212293)
The TOSA specifications indicates that when computing the imaginary
output for locations (0,0), (0,W/2), (H/2,0), (H/2, W/2),
implementations may choose to skip the computation entirely and return
0, or compute each accumulation term as `-val_real * 0.0`.
The previous legalizations used `-val_real * sin(a)` but `sin(a)` may
not return exactly 0.0 due to representation error in the input to
`sin`.
This patch updates the legalization to instead check for indices where
`sin(a)` should be replaced by `0.0` and uses a `select` op to match the
expected behaviour according to the Specification when
tosa_extra_multiplies is set to `true`.
Signed-off-by: Ian Tayler Lessa <ian.taylerlessa at arm.com>
Commit: 5e3f4038530f54fa80ef2e2e648dcb399d279b70
https://github.com/llvm/llvm-project/commit/5e3f4038530f54fa80ef2e2e648dcb399d279b70
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/test/CIR/IR/fenv.cir
M clang/test/CIR/IR/invalid-cast.cir
M clang/unittests/CIR/FenvOpTest.cpp
Log Message:
-----------
[CIR] Add fenv attribute to cast operation (#212899)
This adds the optional #cir.fenv attribute to the cir.cast operation and
updates the verifier to enforce the attribute being present only when
the cast involves floating-point values.
Assisted-by: Cursor / various models
Commit: 1dd9687d41e1331996ece0839e58673ab4d8e10f
https://github.com/llvm/llvm-project/commit/1dd9687d41e1331996ece0839e58673ab4d8e10f
Author: Wooseok Lee <wolee at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/AMDGPU/fma_legacy.ll
M llvm/test/Transforms/InstCombine/AMDGPU/fmul_legacy.ll
Log Message:
-----------
[AMDGPU] Fix fmul/fma legacy sign-of-zero miscompile (#203567)
V_MUL_LEGACY_F32 always returns +0.0 when either operand is ±0.0 or a
denormal treated as zero, while IEEE fmul XORs operand signs. This makes
results observably different when one operand is a runtime ±0.0:
fmul.legacy(-2.0, +0.0) = +0.0 (legacy zero clause forces +0.0)
fmul (-2.0, +0.0) = -0.0 (IEEE sign XOR: - * + = -)
The previous code folded whenever one operand matched m_FiniteNonZero()
or both were known never Inf/NaN, without accounting for sign-of-zero
divergence on the other operand.
Restructure the guard:
- Always safe: both operands are known never zero (legacy zero clause
cannot fire). Uses isKnownNeverLogicalZero to correctly account for
denormals flushed to zero under the function's f32 denormal mode.
- With nsz (sign-of-zero is don't-care), two additional cases apply:
1. One operand is not zero or infinity or NaN: zero clause cannot fire
on that side, and 0*Inf/0*NaN (where legacy returns +0.0 but IEEE
returns NaN) is excluded.
2. Neither operand is infinity or NaN: 0*Inf and 0*NaN cases excluded,
nsz covers any sign-of-zero difference from the zero clause.
A single condition captures both cases.
- Compute Known1 lazily: bail before the second computeKnownFPClass call
if Op0 may be zero and nsz is not set, since Op1 cannot help.
Update fmul_legacy.ll and fma_legacy.ll to reflect the corrected
behavior: cases that previously folded without nsz now require it or
require both operands to be provably non-zero.
Commit: 665d200b160d15ef7e8ddeb21c7028d774c7e1b1
https://github.com/llvm/llvm-project/commit/665d200b160d15ef7e8ddeb21c7028d774c7e1b1
Author: Jianhui Li <jian.hui.li at intel.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
M mlir/test/Dialect/XeGPU/propagate-layout.mlir
M mlir/test/Dialect/XeGPU/sg-to-lane-distribute-unit.mlir
Log Message:
-----------
[mlir][xegpu] Handle size-1 broadcast dim in insert_strided_slice layout setup (#211725)
This PR enhance `setupInsertStridedSliceResultLayout` to treat a size-1
source dim as a broadcast dim: keep its lane_data at 1 instead of
requiring divisibility.
Add regression tests for both the layout propagation setup and the
subgroup-to-lane distribution of such an op.
Assisted-by-claude
Co-authored-by: Claude Opus 4.8 <noreply at anthropic.com>
Commit: 33a5fd88736a9f7b7d266c48827a478629d04604
https://github.com/llvm/llvm-project/commit/33a5fd88736a9f7b7d266c48827a478629d04604
Author: Jacob Crawley <jacob.crawley at arm.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/test/CodeGen/AArch64/regalloc-hint-movprfx-streaming.mir
M llvm/test/CodeGen/AArch64/sve-ldst-multi-vec.mir
M llvm/test/CodeGen/AArch64/sve-multivector-load-stores.ll
M llvm/test/CodeGen/AArch64/sve-vector-interleave.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-stores.ll
Log Message:
-----------
[AArch64][SME2] Add stridedorcontiguous pseudos for multi-vector-stores (#211551)
Select strided-or-contiguous psuedos for SME2 multi-vector stores,
allowing register allocation to choose the most profitable tuple layout.
The pseudos can then be expanded to choose the appropriate contiguous or
strided instruction after allocation.
Commit: 188aa82fd8d0b9f322f6d5b3812f8cb4a970b60c
https://github.com/llvm/llvm-project/commit/188aa82fd8d0b9f322f6d5b3812f8cb4a970b60c
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPUDocs.td
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn-s-buffer-load.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsanInstrumentation.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ptr.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.ptr.s.buffer.load.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.ptr.s.buffer.load.subdword.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ptr.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
M llvm/test/CodeGen/AMDGPU/amdgpu-uniform-intrinsic-wwm-single-lane.ll
M llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll
M llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
A llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_ptr_s_buffer_loads.ll
M llvm/test/CodeGen/AMDGPU/group-image-instructions.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.s.buffer.load-gfx12.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.s.buffer.load-mmo.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
A llvm/test/CodeGen/AMDGPU/ptr-s-buffer-load-mmo-offsets.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
M llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll
M llvm/test/CodeGen/AMDGPU/set_kill_i1_for_floation_point_comparison.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/si-scheduler.ll
M llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll
M llvm/test/CodeGen/AMDGPU/si-spill-cf.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
M llvm/test/CodeGen/AMDGPU/wqm.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/Transforms/EarlyCSE/AMDGPU/intrinsics.ll
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts-inseltpoison.ll
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
Log Message:
-----------
[AMDGPU] Add ptr.s.buffer.load intrinsic, use it from Clang (#209243)
This commit adds a version of the existing s_buffer_load intrinsic that
more accurately models the memory semantics of the s_buffer_load
instruction, namely that it is, in fact, a memory load.
To preserve the existing behavior that the "nomem" s.buffer.load
intrinsic was using, Clang and MLIR add !invariant.load metadata when
constructing the intrinsic (matching documented requirements on
scalarazable buffer loads) and a late codegen pass adds the metadata
just to be safe.
Tests that were "about" s.buffer.load have been copied to create
versions that use the new intrinsic, as was done for the other
*.ptr.buffer.* operations.
Other tests have been upgraded to use the new intrinsic. This has mainly
resulted in minor instruction ordering changes in prologues, if any
change at all. However, CodeGen/AMDGPU/dagcombine-fma-fmad.ll has seen a
v_fma => v_mad pattern fail to match in one case, I don't know if this
is a real regression.
While I was here, the s_buffer_load => buffer_load fallback has been
updated to preserve cachepolity.
AI disclosure: Primarily AI-written code, but I have at least looked at
and tried to find the worst of the silliness.
---------
Co-authored-by: Codex <codex at openai.com>
Commit: ce25b1d727308f07355b9f6aad4f6cd70c60db66
https://github.com/llvm/llvm-project/commit/ce25b1d727308f07355b9f6aad4f6cd70c60db66
Author: Jianhui Li <jian.hui.li at intel.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
M mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir
Log Message:
-----------
[mlir][xegpu] Fix DPAS subgroup layout propagation for broadcast K dim (#211695)
This PR fixes an issue in getDpasSubgroupLayouts(): It failed to find
valid subgroup layouts for otherwise-legal DPAS ops. It treated the K
(contraction) dimension as distributed across subgroups — requiring
wgShape % sgLayout == 0 on every dim and gating on a
checkAlignedSgDataAB() equality — when K is actually broadcast: its full
extent stays in every subgroup. This rejected the only valid candidate,
causing layout propagation to bail out.
Update the two affected tests, which now propagate successfully instead
of failing.
assisted-by-claude
Co-authored-by: Claude Opus 4.8 <noreply at anthropic.com>
Commit: 94ef6a696069211685027fe4aa65a31ccfbe3453
https://github.com/llvm/llvm-project/commit/94ef6a696069211685027fe4aa65a31ccfbe3453
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M lld/test/ELF/aarch64-thunk-align.s
M lld/test/ELF/aarch64-thunk-bti-execute-only.s
M lld/test/ELF/aarch64-thunk-bti-multipass.s
M lld/test/ELF/aarch64-thunk-bti.s
M lld/test/ELF/aarch64-thunk-script.s
Log Message:
-----------
[test] Migrate AArch64 thunk tests to the default thunk order (#212691)
Drop -z nosort-thunks (added by #211721 to keep creation order) and
update expectations to the default order: forward thunks sorted by
descending destination.
Commit: 524e0d24b274ad5ae5687558963661196eb1ab87
https://github.com/llvm/llvm-project/commit/524e0d24b274ad5ae5687558963661196eb1ab87
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M lld/test/ELF/arm-bl-v4t.s
M lld/test/ELF/arm-branch-rangethunk.s
M lld/test/ELF/arm-force-pi-thunk.s
M lld/test/ELF/arm-thumb-condbranch-thunk.s
M lld/test/ELF/arm-thumb-interwork-shared.s
M lld/test/ELF/arm-thumb-interwork-thunk.s
M lld/test/ELF/arm-thumb-mix-range-thunk-os.s
M lld/test/ELF/arm-thumb-plt-range-thunk-os.s
M lld/test/ELF/arm-thumb-range-thunk-os-no-ext.s
M lld/test/ELF/arm-thumb-range-thunk-os.s
M lld/test/ELF/arm-thunk-arm-thumb-reuse.s
M lld/test/ELF/arm-thunk-linkerscript-dotexpr.s
M lld/test/ELF/arm-thunk-linkerscript-orphan.s
M lld/test/ELF/arm-thunk-linkerscript.s
M lld/test/ELF/arm-thunk-re-add.s
Log Message:
-----------
[test] Migrate Arm thunk tests to the default thunk order (#212694)
Drop -z nosort-thunks (added by #211721 to keep creation order) and
update expectations to the default order: forward thunks sorted by
descending destination. Backward-only thunk sections keep creation
order and are unchanged.
In arm-thunk-re-add.s, retarget beq.w to imported2: sorting places
imported's pool thunk just within conditional-branch range, so
beq.w imported would reuse it instead of re-adding a thunk.
Commit: 8223635500c61d10820c011371498b96cd4ffbc7
https://github.com/llvm/llvm-project/commit/8223635500c61d10820c011371498b96cd4ffbc7
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-fp.ll
Log Message:
-----------
[AMDGPU] Fix miscompile in performSelectCombine for fcmp one with NaN (#213029)
The fold `select (fcmp one x, K), y, K -> ..., x` returned x instead of
K when x was NaN, changing the result
Commit: 75827f0bdc8895e1059b2dfa4ac5b8efdc413809
https://github.com/llvm/llvm-project/commit/75827f0bdc8895e1059b2dfa4ac5b8efdc413809
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/test/CIR/CodeGen/pointer-to-data-member.cpp
Log Message:
-----------
[CIR] Fix path generation to understand redecls (#213051)
Found this during a self-build, an additional decl was confusing the
check between getParent and the currentClass. This patch generalizes it
to use the 'isSameEntity' function which makes sure they are the same.
Also, as a drive-by, the test had some check-lines that andy submitted a
while back, that were accidentially not being tested, so fixed the
check-title to be actually checked.
Commit: f176fde8c823da74fc9ca1064077056c77846aee
https://github.com/llvm/llvm-project/commit/f176fde8c823da74fc9ca1064077056c77846aee
Author: Alok Kumar Sharma <AlokKumar.Sharma at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Transforms/IPO/MergeFunctions.cpp
A llvm/test/Transforms/MergeFunc/merge-functions-entry-count-imports.ll
Log Message:
-----------
[MergeFunctions] Preserve import GUIDs when folding functions (#207003)
Computes the union of SamplePGO/ThinLTO import GUIDs from both inputs
and attaches it to the surviving function.
Commit: 9e43e04108dddff6476152d0fff672fb4c577925
https://github.com/llvm/llvm-project/commit/9e43e04108dddff6476152d0fff672fb4c577925
Author: Md Abdullah Shahneous Bari <md.abdullah.shahneous.bari at intel.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/Arith/Transforms/Passes.h
M mlir/include/mlir/Dialect/Arith/Transforms/Passes.td
M mlir/lib/Dialect/Arith/Transforms/ExpandOps.cpp
A mlir/test/Dialect/Arith/expand-ops-min-max.mlir
M mlir/test/Dialect/Arith/expand-ops.mlir
M mlir/test/Dialect/EmitC/arith/ops.mlir
Log Message:
-----------
[mlir][arith] Gate min/max expansion in arith-expand behind include-min-max (#211884)
`arith-expand` expanded `arith.maximumf`/`minimumf`/`maxnumf`/`minnumf`
and the signed/unsigned integer max/min ops into `cmpf`/`cmpi` +
`select` sequences. These ops also have a direct arith-to-llvm lowering
to the `llvm.intr.maximum`/`minimum`/... intrinsics, which are a single
hardware instruction on many targets. Pipelines that run arith-to-llvm
after arith-expand (e.g. the GPU-to-XeVM pipeline) therefore paid a
large, avoidable overhead.
Add `include-min-max-f` (the float ops
maximumf/minimumf/maxnumf/minnumf) and `include-min-max-i` (the
signed/unsigned integer ops maxsi/maxui/minsi/minui) option (default `false`, changing the existing
behavior) that controls whether these min/max ops are expanded. The
min/max converters are factored into new
`populateExpandMinMaxFPatterns` and
`populateExpandMinMaxIPatterns`; the ceil/floor-div and scaling ext/trunc
expansions (which have no LLVM lowering) always run.
---------
Co-authored-by: Claude Opus 4.8 <noreply at anthropic.com>
Commit: f8eefd3d9d1b083563b1b095a8cf4513026252e0
https://github.com/llvm/llvm-project/commit/f8eefd3d9d1b083563b1b095a8cf4513026252e0
Author: Zibi Sarbinowski <zibi at ca.ibm.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M libcxx/test/std/ranges/range.adaptors/range.adjacent.transform/iterator/member_types.compile.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.adjacent/iterator/member_types.compile.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.zip.transform/iterator/member_types.compile.pass.cpp
Log Message:
-----------
[libc++] Fix difference_type expectations in range adaptor iterator member_types tests (#201853)
This fixes incorrect expectations in:
```
libcxx/test/std/ranges/range.adaptors/range.adjacent/iterator/member_types.compile.pass.cpp
libcxx/test/std/ranges/range.adaptors/range.zip.transform/iterator/member_types.compile.pass.cpp
libcxx/test/std/ranges/range.adaptors/range.adjacent.transform/iterator/member_types.compile.pass.cpp
```
These iterators define difference_type as `range_difference_t<Base>`.
For `ForwardSizedView` and `InputCommonView`, the `difference_type` of
the underlying iterators is `std::intptr_t` in `test_iterators.h`.
The tests instead assert `std::ptrdiff_t`. That happens to hold on
platforms where `std::intptr_t` and `std::ptrdiff_t` are the same type,
but fails elsewhere.
---------
Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
Commit: af8e570d9009f398473813e8af7e617d40d87199
https://github.com/llvm/llvm-project/commit/af8e570d9009f398473813e8af7e617d40d87199
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
A clang/test/CIR/CodeGen/attr-alias-no-proto.c
Log Message:
-----------
[CIR] Fixup type of no-prototype functions when emitting an alias. (#212308)
If a function is first used through a no-prototype declaration, then
defined later as an alias, we erased the old declaration and created the
new one with the new type. However the earlier references still used the
old type, which caused a verification error.
This patch just makes sure we replace the uses of it similar to how we
do with a similar problem with normal functions.
Note: there is a bit of inconsistency in how we're setting the type of
the function between OGCG and CIR that I'm not sure of the impact of,
but that is prexisting.
Commit: 0cf29309fd12668307f39bd540100618de626e94
https://github.com/llvm/llvm-project/commit/0cf29309fd12668307f39bd540100618de626e94
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/test/CIR/CodeGenBuiltins/builtins-elementwise.c
M clang/test/CIR/CodeGenBuiltins/builtins-floating-point.c
Log Message:
-----------
[CIR]Implement lowering for simple sin/cos/tan/exp10 builtins. (#211614)
Discovered these just looking around, they are pretty simple/trivial
translations to LLVM-IR intrins, and the infrastructure to do so is
already in place, so this is a bit of simple wiring up!
Implements f/h/hl versions of sin/cos/tan. Also implements base-10
exponent, since it is also trivial.
Commit: 3ce0df7ca8027229618de9802eeffe1f0023bf74
https://github.com/llvm/llvm-project/commit/3ce0df7ca8027229618de9802eeffe1f0023bf74
Author: Volodymyr Sapsai <vsapsai at apple.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/Parse/Parser.h
M clang/lib/Interpreter/IncrementalParser.cpp
M clang/lib/Parse/ParseAST.cpp
M clang/lib/Parse/ParseHLSLRootSignature.cpp
M clang/lib/Parse/Parser.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
A clang/test/Modules/decl-attr-merge-explicit-modules.c
A clang/test/Modules/decl-attr-merge2.c
M clang/test/OpenMP/declare_variant_construct_codegen_1.c
M lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
Log Message:
-----------
[Modules] Handle decl attributes on deserialization the same as during parsing. (#208348)
Replace manual handling of 2 attributes with
`Sema::mergeDeclAttributes`, which is called during parsing too. Also
propagate attributes not from a previous redeclaration but from a
previous redeclaration outside of the current module. This is done to
avoid double propagation because attributes from a previous decl in the
same module are already handled when a module is built.
Call `ASTDeclReader::attachLatestDecl` after each decl is added to a
redeclaration chain, not once per `ASTReader::loadPendingDeclChain`
call. This is done to maintain correct redeclaration chain for each
`ASTDeclReader::attachPreviousDecl` call because [newly added]
`mergeDeclAttributes` requires a correct redeclaration chain.
Separated `Parser::Initialize` and `Parser::ConsumeToken` so can move
the initialization earlier, into `Parser` constructor. This way
`Parser::Initialize`, `Sema::Initialize`, `ASTReader::InitializeSema` are
executed before deserialization. This specific case is verified by
"Modules/decl-attr-merge-explicit-modules.c".
The change can cause compilation errors for downstream `Parser` clients.
Instead of calling `Parser::Initialize` now you need to call
`Parser::ConsumeToken`.
rdar://175997317
Commit: 97ff9fc6daee52427f64ba9f11c1c6f268fab4fa
https://github.com/llvm/llvm-project/commit/97ff9fc6daee52427f64ba9f11c1c6f268fab4fa
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/test/CIR/CodeGen/address-space.c
M clang/test/CIR/IR/copy.cir
Log Message:
-----------
[CIR] Allow cir.copy to work across address spaces- (#211873)
LLVM Memcpy supports copying across address spaces, so we should too. IN
C, this is legal, and there are no associated AST nodes to reasonably
put in a cast, so this patch just legalizes it to match the LLVM
behavior.
Note: I've added a 'CopyTypes' printer/parser as well, because it seems
unfortunate to make EVERY copy have to show all of its types.
Commit: 4dd8a2972273d9613b3004516c6bc9d7cf525f68
https://github.com/llvm/llvm-project/commit/4dd8a2972273d9613b3004516c6bc9d7cf525f68
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/AArch64/reassoc-copyable-sched-deps.ll
Log Message:
-----------
[SLP]Release scheduling deps of copyable reassoc operands only once
A flattened reassoc node may have a scalar that is both a modeled
copyable tree operand (child entry) and a direct IR operand of a node
member. Scheduling such a member released its ScheduleCopyableData
dependency twice - in the per-lane operand scan and again in the
reassoc operand cleanup - driving UnscheduledDeps negative. Dedup the
cleanup release through the same Checked set the operand scan uses.
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/213079
Commit: 57a38f251bbb1e443642d4972c88550c750510cb
https://github.com/llvm/llvm-project/commit/57a38f251bbb1e443642d4972c88550c750510cb
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/lib/CodeGen/Targets/PPC.cpp
M llvm/include/llvm/Support/CodeGen.h
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
Log Message:
-----------
IR: Use LongDoubleFormat enum for long-double-type module flag (#213056)
Add parse/print helpers for the LongDoubleFormat enum, and route the
"long-double-type" module flag producers and consumers through them
instead of hardcoded strings in every location. Also clean up some
unnecessary failure checks guaranteed by the verifier.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 2e838bf84da94760fa49e132108e954a62815573
https://github.com/llvm/llvm-project/commit/2e838bf84da94760fa49e132108e954a62815573
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M libc/test/UnitTest/HermeticTestUtils.cpp
Log Message:
-----------
[libc] Fix aligned_alloc used in hermetic tests. (#213041)
Use the provided alignment for the pointer to the returned
memory chunk instead of the size.
This fixes occasional segfaults in `hsearch` tests after
ce62aab97e58c52e6bb0972c49d6fd1aaa6a08a0, since
hash-table bitmask implementation uses SSE2 intrinsics with 16-byte
alignment.
Commit: 056dae16f7d219f0dc943828dccd6cc3773d2674
https://github.com/llvm/llvm-project/commit/056dae16f7d219f0dc943828dccd6cc3773d2674
Author: Ivan R. Ivanov <iivanov at nvidia.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M flang/lib/Optimizer/CodeGen/TargetRewrite.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-gpu-launch-func.mlir
M flang/test/Fir/CUDA/cuda-launch.fir
M flang/test/Fir/CUDA/cuda-stream.mlir
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/lib/Conversion/GPUCommon/GPUToLLVMConversion.cpp
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/lib/Dialect/GPU/Transforms/KernelOutlining.cpp
M mlir/test/Dialect/GPU/invalid.mlir
M mlir/test/Dialect/GPU/ops.mlir
Log Message:
-----------
[mlir][gpu] Add stream-based async mode to gpu.launch (#213031)
Currently, only gpu.launch_func supports stream-based asynchronicity. This
patch adds the same mode to gpu.launch, and makes kernel outlining preserve
that when converting to gpu.launch_func.
This patch also documents the stream-based model in the operations description,
which was previously missing.
This patch changes the builders for the two launch operations:
To retain the current behavior for gpu.launch one needs to add a `nullptr` for
the new `Value asyncObject` argument after the `ValueRange asyncDependencies`,
and make sure to pass a valid type for the `Type asyncTokenType` parameter if
dependency-based async behavior is intended.
For gpu.launch_func, both stream-based and dependency-based async models now go
through the same builders, which take all three `Type asyncTokenType,
ValueRange asyncDependencies, Value asyncObject` arguments. To retain
stream-based behavior, pass `nullptr, {}` to the first two parameters, while to
retain dependency-based behavior, pass `nullptr` to the third parameter.
Assisted-by: Claude Code
Commit: 44cf7e37312967a0538501cc8ac044f6a72c9efb
https://github.com/llvm/llvm-project/commit/44cf7e37312967a0538501cc8ac044f6a72c9efb
Author: Daniel Chen <cdchen at ca.ibm.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/test/DebugInfo/Generic/debug-info-qualifiers.ll
Log Message:
-----------
Fix test case failure due to Commit aa50eb69 DwarfDebug: Move emission of types from beginModule() to endModule() (#212805)
Commit `aa50eb69 ("DwarfDebug: Move emission of types from beginModule()
to endModule()") ` added new CHECK lines
to `debug-info-qualifiers.ll` that broke on XCOFF/AIX in two ways:
(1) `CHECK-NOT: DW_TAG_subprogram` tripped on abbrev table entries
printed before .debug_info, and
(2) the pattern `{{.*}} "g")` had a space/paren mismatch against the AIX
dwarfdump output format
This PR is fix that by adding `; CHECK: .debug_info contents: ` anchor
and changed the pattern to `{{.*}}"g"` in the test file
Commit: 2f238db9da1cec04f7e143fb264aa1c0fd4578ef
https://github.com/llvm/llvm-project/commit/2f238db9da1cec04f7e143fb264aa1c0fd4578ef
Author: Zhen Wang <zhenw at nvidia.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M flang/include/flang/Evaluate/tools.h
M flang/test/Lower/CUDA/cuda-managed-assign.cuf
A flang/test/Lower/CUDA/cuda-unified-assign.cuf
Log Message:
-----------
[flang][cuda] Treat unified data as host data in assignments (#212912)
Unified data was counted as managed data in the data transfer predicate,
so assignments between unified sides, or between unified and host data,
became synchronous copies.
Unified data is host memory that the device can also access, so it now
takes the place of host data there: the assignment is a copy only when
the other side is device or constant data, or a whole managed array, and
is done on the host otherwise.
This matches the reference compiler for whole arrays, sections,
elements, scalars, allocatables, components and expressions.
Commit: c486d28c1ec80f832a0e3cb3173d1940e632742c
https://github.com/llvm/llvm-project/commit/c486d28c1ec80f832a0e3cb3173d1940e632742c
Author: Bar Soloveychik <barsolo at meta.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M lldb/cmake/modules/LLDBConfig.cmake
M lldb/include/lldb/Host/Config.h.cmake
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
M lldb/test/Shell/SymbolFile/DWARF/x86/dwo-not-found-warning.cpp
M lldb/tools/lldb-test/lldb-test.cpp
M llvm/utils/gn/secondary/lldb/include/lldb/Host/BUILD.gn
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
Log Message:
-----------
[lldb] Make missing DWO diagnostics customizable (#212338)
Adds a default-empty `LLDB_DWO_DIAGNOSTIC_SUFFIX` macro and appends it
to both missing-DWO diagnostics.
The idea is companies or build engineers can build with an extra cmake
-D flag to include internal URL links or troubleshooting tips when dwo
files are missing.
tested with:
```
bin/llvm-lit -sv tools/lldb/test/Shell/SymbolFile/DWARF/x86/dwo-not-found-warning.cpp
```
added `GetDwoDiagnosticSuffix()` because a macro has no runtime symbol.
The function lets lldb-test read the exact value compiled into the DWARF
plugin.
---------
Co-authored-by: Bar Soloveychik <barsolo at fb.com>
Commit: 730b803ed05e307d635b6b2764fad833629042c2
https://github.com/llvm/llvm-project/commit/730b803ed05e307d635b6b2764fad833629042c2
Author: Kareem Ergawy <kergawy at nvidia.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
A flang/lib/Optimizer/Transforms/SelectOpsConversion.cpp
M flang/test/Driver/bbc-mlir-pass-pipeline.f90
M flang/test/Driver/mlir-debug-pass-pipeline.f90
M flang/test/Driver/mlir-pass-pipeline.f90
A flang/test/Fir/SelectOpsConversion/select.fir
A flang/test/Fir/SelectOpsConversion/select_case.fir
A flang/test/Fir/SelectOpsConversion/select_rank.fir
M flang/test/Fir/basic-program.fir
M flang/test/Fir/select.fir
M flang/test/Lower/volatile3.f90
Log Message:
-----------
[flang][Transforms] Add `SelectOpsConversion` pass (#212977)
Introduces `--fir-select-ops-conversion`, which lowers `fir.select`,
`fir.select_case`, and `fir.select_rank` to the control-flow dialect
(`cf.switch` / `cf.cond_br` / `cf.br`) while preserving the CFG shape.
`fir.select_case` becomes an if-then-else ladder of `arith.cmpi` +
`cf.cond_br`; Fortran `UNSIGNED` selectors use `ule`. Signed / unsigned
FIR integer values are normalized to signless via `fir.convert` first.
`fir.select_type` is not handled here — it is already lowered by
`--fir-polymorphic-op` (`PolymorphicOpConversion`).
The pass runs in the default FIR optimizer pipeline right after
`PolymorphicOpConversion`. Pipeline-check tests are updated to expect
`SelectOpsConversion` in the sequence; `Fir/select.fir` and
`Lower/volatile3.f90` are relaxed to accept the newly-canonicalized form
of the lowered output.
The main purpose of moving these conversion pattern earlier in the MLIR
pipeline and target `cf` instead of directly `llvm` is to be able to
later on use control-flow to structured-control-flow lifting:
https://github.com/llvm/llvm-project/blob/main/mlir/include/mlir/Conversion/Passes.td#L402.
Co-Authored-By: Claude Sonnet 4.6 (1M context) <noreply at anthropic.com>
PR Stack:
* ▶️ https://github.com/llvm/llvm-project/pull/212977
* https://github.com/llvm/llvm-project/pull/212978
---------
Co-authored-by: Claude Sonnet 4.6 (1M context) <noreply at anthropic.com>
Commit: 4f705acc388ab2c627fb263d89d1d60468f8a97b
https://github.com/llvm/llvm-project/commit/4f705acc388ab2c627fb263d89d1d60468f8a97b
Author: Luke Lau <luke at igalia.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/find-last.ll
Log Message:
-----------
[VPlan] Fix optimizeFindIVReductions not negating condition of blend (#213050)
Fixes #212993
#194729 made the m_Select a m_SelectLike, so FindLastSelect could now be
a blend. However we were checking the first operand to see if the Cond
needed inverted. A select has `select %cond, %true, %false`, a blend is
`blend %false, %cond, %true`, so we were failing to negate the
condition.
Commit: 005b3858f602ec5a193740cb166244d5234ce98f
https://github.com/llvm/llvm-project/commit/005b3858f602ec5a193740cb166244d5234ce98f
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/test/CIR/IR/fenv.cir
A clang/test/CIR/IR/invalid-cmp.cir
M clang/test/CIR/Transforms/vector-cmp-fold.cir
M clang/unittests/CIR/FenvOpTest.cpp
Log Message:
-----------
[CIR] Add fenv attribute to compare operations (#213072)
This adds the #cir.fenv attribute to the cir.cmp and cir.vec.cmp and
adds verfiers to enforce that the attribute is only present when the
comparison involves floating-point values.
The cir.vec.cmp operation has an existing folder which is skipped in
this change when the fenv attribute is present. In most circumstance,
this folding could still be done, but the implementation is
intentionally conservative at this point. Proper checking of the
conditions under which folding would be legal will be added later.
The cir.cmp operation does not currently have a folder.
Assisted-by: Cursor / various models
Commit: b1cf39d2db1fbc644c46e6783d022e274884fda9
https://github.com/llvm/llvm-project/commit/b1cf39d2db1fbc644c46e6783d022e274884fda9
Author: David Green <david.green at arm.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-delayed-stack-protector.ll
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-protector-trap-unreachable.ll
Log Message:
-----------
[GlobalISel] Use integer type for LOAD_STACK_GUARD (#212202)
Commit: 63b3eb10e5f5807bf4c9c0f9ec582f03582c58fe
https://github.com/llvm/llvm-project/commit/63b3eb10e5f5807bf4c9c0f9ec582f03582c58fe
Author: Benedek Kaibas <82393336+benedekaibas at users.noreply.github.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/docs/UsersManual.md
M clang/docs/analyzer/user-docs/CommandLineUsage.rst
Log Message:
-----------
Revert "[clang][docs] Update CommandLineUsage and UsersManual with some flags (#209519)" (#213092)
This PR reverts commit e4c2875c397861ea45a0cca05107d91d7d785d03.
Reverting because of:
https://github.com/llvm/llvm-project/actions/runs/30559163159/job/90927389811#step:10:822
Commit: 6162922a8d7cef0cf2e27b91c980197d371c89b9
https://github.com/llvm/llvm-project/commit/6162922a8d7cef0cf2e27b91c980197d371c89b9
Author: Prabhu Rajasekaran <prabhukr at google.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/lib/Driver/ToolChains/HIPSPV.cpp
M clang/lib/Driver/ToolChains/HIPSPV.h
M clang/test/Driver/hipspv-link-static-library.hip
M clang/test/Driver/hipspv-pass-plugin.hip
M clang/test/Driver/hipspv-toolchain.hip
M llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
Log Message:
-----------
Revert "[HIPSPV] Add in-tree SPIR-V backend support for chipStar" (#213088)
Reverts llvm/llvm-project#206910
which broke buildbot:
https://lab.llvm.org/buildbot/#/builders/144/builds/60707
Commit: 6c5dfef69069230264b3aa7c90656726cc9eac1c
https://github.com/llvm/llvm-project/commit/6c5dfef69069230264b3aa7c90656726cc9eac1c
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/Support/PatternMatchHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[PatternMatchHelpers] Introduce m_Unless (NFC) (#212454)
Introduce m_Unless from PatternMatch, that inverts a match, in
PatternMatchHelpers.
Commit: 5b897d9b57494ef37615cd9af88507a212ab5703
https://github.com/llvm/llvm-project/commit/5b897d9b57494ef37615cd9af88507a212ab5703
Author: vsimion26 <vlad.simion at intel.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M mlir/lib/Dialect/Quant/IR/QuantTypes.cpp
Log Message:
-----------
Fix classof implementation for QuantizedType (#213014)
This PR aims to fix the misleading implementation of `classof` which
accepted as a `QuantizedType` every type registered under the
`QuantDialect.`
The now updated implementation makes the checks more restrictive,
allowing only direct subtypes of `QuantizedType` to be recognized as a
`QuantizedType,` therefore preventing `QuantileType` and other types
that are registered under `QuantDialect` to be seen as a subtype of
`QuantizedType` and wrongfully use its methods which might lead to
potential crashes.
Commit: 0e42c871c2c8a40926ad929cfa334fd1d3c98dfa
https://github.com/llvm/llvm-project/commit/0e42c871c2c8a40926ad929cfa334fd1d3c98dfa
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/lib/Basic/Cuda.cpp
A llvm/include/llvm/TargetParser/NVPTXTargetParser.def
A llvm/include/llvm/TargetParser/NVPTXTargetParser.h
M llvm/lib/TargetParser/CMakeLists.txt
A llvm/lib/TargetParser/NVPTXTargetParser.cpp
M llvm/unittests/TargetParser/CMakeLists.txt
A llvm/unittests/TargetParser/NVPTXTargetParserTest.cpp
M llvm/utils/gn/secondary/llvm/lib/TargetParser/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/TargetParser/BUILD.gn
Log Message:
-----------
NVPTX: Add target names in TargetParser (#212734)
Track the canonical sm name and other target information.
This will eventually be used to reduce the pain of maintaining
OffloadArch in clang; all of the disjoint targets share an
enum which makes target specific covered switches annoying.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 1562871d4191f39de7ed0ae53f8ca48b8e2d4242
https://github.com/llvm/llvm-project/commit/1562871d4191f39de7ed0ae53f8ca48b8e2d4242
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
Log Message:
-----------
clang: Use NVPTX TargetParser for OpenMP unified-addressing check (#212746)
processRequiresDirective enumerated every OffloadArch value in a switch
only to error on nvptx architectures older than sm_60. Replace it with
NVPTX::supportsUnifiedAddressing() applied to the parsed target CPU so
we don't need to keep adding cases here every time a new target is
added.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 6e92d6d0577cbe102bd48f396301ea5cd0ebf247
https://github.com/llvm/llvm-project/commit/6e92d6d0577cbe102bd48f396301ea5cd0ebf247
Author: Rainer Orth <ro at gcc.gnu.org>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
M compiler-rt/lib/tsan/go/buildgo.sh
M compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp
Log Message:
-----------
[tsan] Fix buildgo.sh on FreeBSD/NetBSD (#213047)
This patch fixes the remaining compile errors when running `ninja
check-all` on FreeBSD and NetBSD:
- `sanitizer_linux.cpp` doesn't compile on NetBSD, so this patch adds a
cast:
```
sanitizer_common/sanitizer_linux.cpp:2492:10: error: format specifies
type 'unsigned long long' but the argument has type '__greg_t' (aka
'unsigned long') [-Werror,-Wformat]
```
- `tsan_interface_atomic.cpp` doesn't compile on both FreeBSD and
NetBSD, so this patch disables the warning:
```
tsan_interface_atomic.cpp:353:12: error: unused function template
'NoTsanAtomic' [-Werror,-Wunused-template]
tsan_interface_atomic.cpp:358:12: error: unused function template
'Atomic' [-Werror,-Wunused-template]
tsan_interface_atomic.cpp:389:12: error: unused function template
'NoTsanAtomic' [-Werror,-Wunused-template]
tsan_interface_atomic.cpp:394:12: error: unused function template
'Atomic' [-Werror,-Wunused-template]
tsan_interface_atomic.cpp:401:12: error: unused function template
'NoTsanAtomic' [-Werror,-Wunused-template]
tsan_interface_atomic.cpp:406:12: error: unused function template
'Atomic' [-Werror,-Wunused-template]
```
- `sanitizer_linux_libcdep.cpp` doesn't compile on NetBSD:
```
sanitizer_linux_libcdep.cpp:527:27: error: use of undeclared identifier
'__lwp_getprivate_fast'; did you mean '_lwp_getprivate'?
```
This is the same issue already handled in `tsan_platform_linux.cpp`: to
expose the `__lwp_getprivate_fast` definition in `<machine/mcontext.h>`,
`_RTLD_SOURCE` needs to be defined before `<machine/mcontext.h>` is
included (indirectly from `<signal.h>` in this case). It also needs to
include `<sys/types.h>` to get a definition of the `__aligned` macro.
Tested on `amd64-pc-freebsd15.1` and `amd64-pc-netbsd10.1`.
Commit: 40e33eb35417f565e2ed8a6c0dba63cbd618a926
https://github.com/llvm/llvm-project/commit/40e33eb35417f565e2ed8a6c0dba63cbd618a926
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/hoist-predicated-loads-with-predicated-stores.ll
Log Message:
-----------
[VPlan] Set correct VPIRFlags for FP selects when sinking stores. (#212973)
Selects of floats carry fast-math flags. Update getDefaultFlags to take
the result type and use it to handle selects. I am planning on extending
this to other similar opcodes, including PHIs.
Then update sinkPredicatedStores to pass through the correct default
flags.
This fixes a crash in cse when intersecting common metadata.
Fixes https://github.com/llvm/llvm-project/issues/212811.
PR: https://github.com/llvm/llvm-project/pull/212973
Commit: 5f10bade30ec9e73f19349df7eb833aae323a2e3
https://github.com/llvm/llvm-project/commit/5f10bade30ec9e73f19349df7eb833aae323a2e3
Author: Joel E. Denny <jdenny.ornl at gmail.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
M llvm/test/Transforms/LoopUnroll/branch-weights-freq/unroll-complete.ll
M llvm/test/Transforms/LoopUnroll/branch-weights-freq/unroll-partial-unconditional-latch.ll
Log Message:
-----------
[LoopUnroll] Fix freqs for unconditional latches: N>2, uniform (#182405)
This patch introduces the command-line option `-unroll-uniform-weights`.
When computing probabilities for the remaining N conditional latches in
the unrolled loop after converting some iterations' latches to
unconditional, LoopUnroll now supports the following three strategies:
- A. If N <= 2, use a simple formula to compute a single uniform
probability across those latches.
- B. Otherwise, if `-unroll-uniform-weights` is not specified, apply the
original loop's probability to all N latches and then, as needed, adjust
as few of them as possible.
- C. Otherwise, bisect the range [0,1] to find a single uniform
probability across all N latches. This patch implements this strategy.
An issue with C is that it could impact compiler performance, so this
patch makes it opt-in. Its appeal over B is that it treats all latches
the same given that we have no evidence showing that any latch should
have a higher or lower probability than any other. A has neither
problem, but I do not know how to apply it for N > 2. More experience or
feedback from others might determine that some strategies are not
worthwhile to maintain.
This patch depends on PR #182404.
Commit: 3d94aebde11a6410fc1ee93f12622114c60ace3d
https://github.com/llvm/llvm-project/commit/3d94aebde11a6410fc1ee93f12622114c60ace3d
Author: Rainer Orth <ro at gcc.gnu.org>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M flang/lib/Evaluate/intrinsics-library.cpp
Log Message:
-----------
[flang] Fix POSIX.1/XPG checks in intrinsics-library.cpp (#201072)
PR #201063 breaks the `flang` build on Solaris:
```
flang/lib/Evaluate/intrinsics-library.cpp:225:26: error: address of overloaded function 'acos' does not match required type '__float128 (__float128)'
flang/lib/Evaluate/intrinsics-library.cpp:225:26: error: address of overloaded function 'acos' does not match required type '_Complex __float128 (_Complex __float128)'
```
There are two problems here:
- The `__float128` support in `intrinsics-library.cpp` is guarded by the
POSIX.1 >= 2001/XPG >= 6 check, but only depends on `HAVE_QUADMATHLIB`.
- That check is done incorrectly: it tests for `_POSIX_C_SOURCE >=
200112L` or `_XOPEN_SOURCE >= 600`, which are no longer defined on
Solaris after the PR above. This check is due a misunderstanding of
those feature test macros: as detailed in [The Open Group Base
Specifications Issue 8, 2.2.1 POSIX.1
Symbols](https://pubs.opengroup.org/onlinepubs/9799919799/functions/V2_chap02.html),
those macros are expected to be **defined** by the user to ensure that
the features introduced by a particular version of POSIX.1 or XPG are
enabled, and only be checked by system headers. To test if they actually
are supported, the values of `_POSIX_VERSION` or `_XOPEN_VERSION` need
to be checked instead, as explained in [2.1.3.1 POSIX System
Interfaces](https://pubs.opengroup.org/onlinepubs/9799919799/basedefs/V1_chap02.html).
The feature test macros being defined by the system headers is a
non-portable glibc/AIX extension, it seems.
If the XPG6 features required for `flang` are present by default in a
compilation environment, `_POSIX_VERSION` or `_XOPEN_VERSION` will be
defined to the required values even without defining `_POSIX_C_SOURCE`
or `_XOPEN_SOURCE`.
Tested on `amd64-pc-solaris2.11`, `sparcv9-sun-solaris2.11`, and
`x86_64-pc-linux-gnu`.
Commit: bb7c7d1e2a6b4a3487df8604f94e0b981e873899
https://github.com/llvm/llvm-project/commit/bb7c7d1e2a6b4a3487df8604f94e0b981e873899
Author: satyanarayana reddy janga <satyajanga at gmail.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M lldb/source/Plugins/ObjectFile/Minidump/MinidumpFileBuilder.cpp
A lldb/test/API/functionalities/process_save_core_minidump/size_mismatch/Makefile
A lldb/test/API/functionalities/process_save_core_minidump/size_mismatch/TestProcessSaveCoreMinidumpSizeMismatch.py
A lldb/test/API/functionalities/process_save_core_minidump/size_mismatch/main.cpp
Log Message:
-----------
[lldb][minidump] Fix Memory64List DataSize over-counting on a failed read (#212861)
**Issue:**
save-core records each range's DataSize from the value
ReadMemoryInChunks returns. That value counts bytes read from the
inferior even when the callback dropped them: a chunk that errors
part-way returns Stop before AddData, so the partially-read bytes are
counted but never written.
Because the Memory64List locates every range by the cumulative DataSize
of the preceding ranges, an over-counted DataSize desyncs the shared
data blob: the descriptors claim more bytes than the file holds and
every later range reads back corrupted.
**Fix**
Record the bytes actually written (total_bytes_read) as the range's size
so the descriptor DataSize matches the data in the blob.
**Test**
Add an API test that custom-saves a fully-readable region alongside a
region whose tail is unreadable (a file mapped larger than the file),
and checks the Memory64List does not claim more data than the file holds
and that the readable region round-trips byte-for-byte.
Commit: 50a6209336d9796d26c1e6ecc9553093b074ecb2
https://github.com/llvm/llvm-project/commit/50a6209336d9796d26c1e6ecc9553093b074ecb2
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/clamp.ll
Log Message:
-----------
[AMDGPU] Canonicalize constant CLAMP source (#207902)
CLAMP lowers to v_max_f32, which canonicalizes its result: signaling
NaNs are quieted and denormals are flushed per the function denormal
mode
The constant fold returned the source unchanged, giving a different
result than the hardware. Route the folded constant through
getCanonicalConstantFP so it matches
Commit: dd3a4ed6fbca3696b724b46e2934f3c27534f245
https://github.com/llvm/llvm-project/commit/dd3a4ed6fbca3696b724b46e2934f3c27534f245
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/ne-tightening.ll
Log Message:
-----------
[ConstraintElim] Tighten bounds using inequalities with constants. (#213049)
Update ConstraintElimination to tighten existing bounds using
inequalities. Given an inequality %a != %b and %a >= %b, we can tighten
the fact to %a > %b.
For now this is limited to constant %b.
This helps to remove some checks in practice:
https://github.com/dtcxzyw/llvm-opt-benchmark-nightly/pull/819
Compile-time impact in the noise:
https://llvm-compile-time-tracker.com/compare.php?from=2f08dff5138a4ce908b6d4511a9439e859fedf86&to=fafe1d0d9d012654bc10e2b68d50ffe3b9fdbdcd&stat=instructions:u
PR: https://github.com/llvm/llvm-project/pull/213049
Commit: aae5b3f2a92cc1c08a4bd65ba397fba5e37272fe
https://github.com/llvm/llvm-project/commit/aae5b3f2a92cc1c08a4bd65ba397fba5e37272fe
Author: Michael Jones <michaelrj at google.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M compiler-rt/lib/scudo/standalone/primary64.h
Log Message:
-----------
[scudo] Fix GCC build after 212604 (#212904)
Change #212604 introduced an issue when building with gcc where it
complains there are "too few template-parameter-lists" (see log:
https://lab.llvm.org/buildbot/#/builders/131/builds/51269/steps/6/logs/stdio
)
This PR fixes the build.
Assisted-by: Automated tooling, human reviewed.
Commit: ff95a766e3c5588db19b9c93e1a6f49bd40a2823
https://github.com/llvm/llvm-project/commit/ff95a766e3c5588db19b9c93e1a6f49bd40a2823
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticCommonKinds.td
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/test/OpenMP/requires_codegen.cpp
Log Message:
-----------
clang: Use proper error for unified shared memory openmp error (#212750)
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 4304020b98e20a46dd8f56b361c5f62074e7b8a1
https://github.com/llvm/llvm-project/commit/4304020b98e20a46dd8f56b361c5f62074e7b8a1
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
Log Message:
-----------
[VPlan] Migrate VPBuilder to VPInsertPt fully (NFC) (#209764)
There is already a VPInsertPoint in VPBuilder which is used just with
InsertPointGuard. In order to share code, migrate VPBuilder to fully use
VPInsertPoint as the canonical insertion point.
Commit: b6e3037f6e6283392f306b58c8444e0efe40a23e
https://github.com/llvm/llvm-project/commit/b6e3037f6e6283392f306b58c8444e0efe40a23e
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M offload/unittests/OffloadAPI/program/olCreateProgram.cpp
Log Message:
-----------
[offload][lit] Disable failing olCreateProgram test on AMD (#213126)
Fails with an error about not being able to find `lld`. AMD team is
investigating, but disable the test in the meantime.
Context: https://github.com/llvm/llvm-project/pull/212860
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: b75ab58e83301a56e958ea011fd851c88d976fe5
https://github.com/llvm/llvm-project/commit/b75ab58e83301a56e958ea011fd851c88d976fe5
Author: Patrick Simmons <patrick.simmons at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SOPInstructions.td
A llvm/test/CodeGen/AMDGPU/s_bcnt0.ll
M llvm/test/CodeGen/AMDGPU/s_cmp_0.ll
Log Message:
-----------
[AMDGPU] Match bitsin(typeof(x)) - ctpop(x) to s_bcnt0_i32 (#164847)
This PR optimizes the pattern bitsin(typeof(x)) - popcnt(x) to
s_bcnt0_i32 on AMDGPU. It also creates a Clang builtin for s_bcnt0_i32
so that users can call this instruction directly instead of relying on
the compiler to match this pattern.
Commit: 79f9cdae9dd4502f72f596ff406b0d10ae4cc5a0
https://github.com/llvm/llvm-project/commit/79f9cdae9dd4502f72f596ff406b0d10ae4cc5a0
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M lldb/unittests/Utility/ArchSpecTest.cpp
Log Message:
-----------
[lldb] Add a unit test for Wasm architecture compatibility (#213070)
A Wasm module encodes neither a vendor nor an OS, so ObjectFileWasm
reports a bare wasm32 or wasm64 architecture. That keeps an on-disk
module compatible with the more specific triple a Wasm runtime reports
at launch, which lets the dynamic loader reuse the module instead of
reparsing it from process memory. An over-specified triple, including
one that spells out an unknown vendor and OS, does not match, because an
explicitly specified component still counts as specified.
Commit: cdec735f774869f2949a94a7bf2e446798bf3b8c
https://github.com/llvm/llvm-project/commit/cdec735f774869f2949a94a7bf2e446798bf3b8c
Author: Michael Jones <michaelrj at google.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
A libc/docs/_static/llvm_libc_logo.svg
M libc/docs/index.md
Log Message:
-----------
[libc][docs] Add logo to website (#213120)
Add the excellent new logo drawn by @ajordanr-google to the homepage.
Commit: b05a5d09547bea535b4c26ee522ce310db118c47
https://github.com/llvm/llvm-project/commit/b05a5d09547bea535b4c26ee522ce310db118c47
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M lldb/bindings/python/CMakeLists.txt
M lldb/bindings/python/python-swigsafecast.swig
M lldb/bindings/python/python-wrapper.swig
M lldb/docs/CMakeLists.txt
A lldb/examples/python/templates/scripted_synthetic_children.py
M lldb/include/lldb/API/SBPlatform.h
M lldb/include/lldb/DataFormatters/TypeSynthetic.h
A lldb/include/lldb/Interpreter/Interfaces/ScriptedSyntheticChildrenInterface.h
M lldb/include/lldb/Interpreter/ScriptInterpreter.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/include/lldb/lldb-forward.h
M lldb/source/DataFormatters/TypeSynthetic.cpp
M lldb/source/Interpreter/ScriptInterpreter.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/CMakeLists.txt
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPythonInterface.h
A lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedSyntheticChildrenPythonInterface.cpp
A lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedSyntheticChildrenPythonInterface.h
M lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
M lldb/unittests/ScriptInterpreter/Python/PythonTestSuite.cpp
Log Message:
-----------
[lldb/script] Migrate synthetic children providers onto ScriptedPythonInterface (#210845)
Give `type synthetic add -l` a formal
`ScriptedSyntheticChildrenInterface`, matching the architecture used
elsewhere in this series: a C++ interface header, a Python-backed
implementation, `PluginManager` registration with CLI/API usages, and a
generatable ABC template (`scripted_synthetic_children.py`) wired into
`scripting extension generate`.
Every method goes through the shared `Dispatch<T>()` machinery instead
of hand-rolling its own Locker/raw-SWIG calls. `Dispatch<T>()` is taught
to introspect the target method's arity via
`PythonCallable::GetArgInfo()` and drop trailing args before calling, so
providers that legitimately define an argument as optional
(`num_children(self)` vs. `num_children(self, max_count)`) still work
through the generic dispatch path.
This retires the ad-hoc `LLDBSwigPython_*` synthetic-children bridge
functions entirely.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: f0da3dd9289e1b76da2658a0e6dad0e05842bdfd
https://github.com/llvm/llvm-project/commit/f0da3dd9289e1b76da2658a0e6dad0e05842bdfd
Author: Zahira Ammarguellat <zahira.ammarguellat at intel.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/include/clang/AST/StmtOpenMP.h
M clang/lib/AST/StmtOpenMP.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/test/OpenMP/fuse_codegen.cpp
M clang/test/OpenMP/interchange_codegen.cpp
R clang/test/OpenMP/loop_transform_final_iv.c
M clang/test/OpenMP/reverse_codegen.cpp
M clang/test/OpenMP/stripe_codegen.cpp
M clang/test/OpenMP/tile_codegen.cpp
Log Message:
-----------
Revert "[OpenMP] Restore loop variable values after loop-transformation constructs. (#212853)" (#213127)
Revert "[OpenMP] Restore loop variable values after loop-transformation
constructs. (#212853)"
This reverts commit 2d697f8562d7845d5554cc1d2cd2264401b9d68f.
Reverting this PR. Bot is failing with:
Failed Tests (2):
libomptarget :: spirv64-intel :: offloading/target-tile.c
libomptarget :: x86_64-unknown-linux-gnu :: offloading/target-tile.c
Commit: cc0f33be52a5a04fd809d6e6e6e41c0af794283d
https://github.com/llvm/llvm-project/commit/cc0f33be52a5a04fd809d6e6e6e41c0af794283d
Author: Frank <147031176+frank-suwen at users.noreply.github.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/docs/ClangFormatStyleOptions.rst
M clang/docs/ReleaseNotes.md
M clang/include/clang/Format/Format.h
M clang/lib/Format/BreakableToken.cpp
M clang/lib/Format/Format.cpp
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/FormatTestComments.cpp
Log Message:
-----------
[clang-format] Add SpacesInComments option for block comments (#204727)
Adds a new `SpacesInBlockComments` clang-format option to control
spacing after `/*` and before `*/` in ordinary block comments.
Supported values:
* Always: formats `/*comment*/` as `/* comment */`
* Never: formats `/* comment */` as `/*comment*/`
* Leave: preserves existing spacing
Documentation comments such as `/** ... */` and `/*! ... */`, and
parameter comments such as `/*Arg=*/`, are left unchanged.
Tests added for all option values, multiline block comments, and
excluded parameter/doc comments.
Addresses #160682
Commit: 100e8df6fc863f39e6f3e06862ee9500e859121f
https://github.com/llvm/llvm-project/commit/100e8df6fc863f39e6f3e06862ee9500e859121f
Author: Qiongsi Wu <qiongsiwu at gmail.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/include/clang/Tooling/DependencyScanningTool.h
M clang/lib/Tooling/DependencyScanningTool.cpp
Log Message:
-----------
[clang][DependencyScanning] Extracting a Driver-free CompilerInstaneWithContext Initializer (#211405)
This PR extracts out an initializer of `CompilerInstanceWithContext`
that does not depend on any driver code in preperation of moving the
`CompilerInstanceWithContext` into `DependencyScanningWorker.cpp` as an
implementation detail that is not exposed by any APIs.
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Commit: 7650a43aa8a6dabe890e08d3d482aa25ae31c826
https://github.com/llvm/llvm-project/commit/7650a43aa8a6dabe890e08d3d482aa25ae31c826
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-branch-weights.ll
A llvm/test/Transforms/LoopVectorize/expression-recipe-branch-weights.ll
A llvm/test/Transforms/LoopVectorize/replicate-region-branch-weights-merged-mem-ops.ll
M llvm/test/Transforms/LoopVectorize/replicate-region-branch-weights.ll
Log Message:
-----------
[LV] Add tests for preserving branch weights through VPlan (NFC). (#213131)
Add coverage for carrying the branch weights of a predicated block from
VPlan0 through to the generated IR
Commit: c836b82d088424baa8a60de63136747add192732
https://github.com/llvm/llvm-project/commit/c836b82d088424baa8a60de63136747add192732
Author: Matsu <47756807+khaki3 at users.noreply.github.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M mlir/lib/Dialect/OpenACC/Transforms/ACCCGToGPU.cpp
M mlir/test/Dialect/OpenACC/acc-cg-to-gpu-reduction-array-shared.mlir
Log Message:
-----------
[mlir][OpenACC] Atomicize contended shared array reduction updates (#212971)
Example:
```fortran
!$acc parallel loop gang reduction(+:a)
do i = 1, N
!$acc loop worker reduction(+:a)
do j = 1, M
a(i) = a(i) + b(j,i)
end do
end do
```
In this code, the worker accumulator is block-shared, so every worker
updates
the same element with a plain read-modify-write and all but one partial
is lost.
Fix: make in-place updates of a block-shared array accumulator atomic,
unless
the element index varies per thread, in which case each thread owns its
element
and the plain update is already race-free.
---------
Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
Commit: 21d9869c206e12f1932aecff50d03f06f5a96339
https://github.com/llvm/llvm-project/commit/21d9869c206e12f1932aecff50d03f06f5a96339
Author: yebinchon <86588366+yebinchon at users.noreply.github.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/OpenACC/Passes.td
A flang/lib/Optimizer/OpenACC/Transforms/ACCDevicePtrToCUFKernel.cpp
M flang/lib/Optimizer/OpenACC/Transforms/CMakeLists.txt
A flang/test/Fir/OpenACC/device-ptr-to-cuf-kernel.mlir
Log Message:
-----------
[flang] Add a pass to get OpenACC device ptr for CUDA kernel (#212299)
When a CUDA kernel is launched inside an OpenACC data region, it does
not properly get the device pointers and instead uses host data. This PR
adds a pass to get the device pointers set up by the OpenACC data
construct and pass them explicitly to the CUDA kernel.
Note: A possibly non-contiguous array argument is currently not supported. This pass will skip these cases.
---------
Co-authored-by: Yebin Chon <ychon at nvidia.com>
Commit: 256a6d2807a980c1477df0ed3b6ea6763460b967
https://github.com/llvm/llvm-project/commit/256a6d2807a980c1477df0ed3b6ea6763460b967
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
Log Message:
-----------
[AMDGPU] Use a single SubtargetPredicate for fp8/bf8 -> f32 conversions (#212888)
Add FeatureCvtFP8SDWASrcSel for the form that takes the byte from the SDWA src0_sel field and FeatureCvtFP8ByteSel for the form that takes it from a byte_sel operand. Both imply FeatureFP8ConversionInsts, and a subtarget provides one of them, so the multiclass-generated HasCvtFP8SDWASrcSel and HasCvtFP8ByteSel replace the GFX9 and GFX11Plus predicates outright.
Assisted-By: Claude Opus 5
Commit: f279abcc818a89c2c73c305a1ce5a9a18d2215ec
https://github.com/llvm/llvm-project/commit/f279abcc818a89c2c73c305a1ce5a9a18d2215ec
Author: Kewen Meng <Kewen.Meng at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M offload/test/unit/lit.cfg.py
M offload/test/unit/lit.site.cfg.in
Log Message:
-----------
[Offload][Test] Add llvm bin in the PATH for offload-unit suite (#213149)
This PR makes the offload-unit suite put llvm bin directory on PATH so
that tests need lld can find. It fixes the issue exposed in:
https://github.com/llvm/llvm-project/pull/212860
Commit: 2d0b45bc0a7fcb29aa77242b9262eb7c9eba5333
https://github.com/llvm/llvm-project/commit/2d0b45bc0a7fcb29aa77242b9262eb7c9eba5333
Author: johnnyb2543 <134093951+johnnyb2543 at users.noreply.github.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Prevent re-assigning type on finalized tokens (#210763)
Prevents a finalized token inside modifyContext from being reassigned
through the setType member function by checking if the token is
finalized.
This ensures ill-defined code like does not trigger an assertion failure
during reformatting.
Fixes #210509
Commit: 613154323d2f06b8018065d88c2781529cf77c75
https://github.com/llvm/llvm-project/commit/613154323d2f06b8018065d88c2781529cf77c75
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/OpenACC/Transforms/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 21d9869 (#213147)
This fixes 21d9869c206e12f1932aecff50d03f06f5a96339 (#212299).
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=21d9869c206e12f1932aecff50d03f06f5a96339
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 197e68dbd324fa48d45666a9c95a83303c995356
https://github.com/llvm/llvm-project/commit/197e68dbd324fa48d45666a9c95a83303c995356
Author: Rafael Auler <rafaelauler at meta.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M .github/CODEOWNERS
Log Message:
-----------
Revert "[github] Move BOLT reviewers to team (#211422)" (#213141)
We haven't really being tagged in new PRs anymore, so it looks like this
is not working.
Revert for now until we can fix this, so we don't miss PRs.
This reverts commit 04f124f6151e8c8410e28aba28dc38e590e34c58.
Commit: 7e35cbb1b6f5915ab732a22e83b3afc20e29181a
https://github.com/llvm/llvm-project/commit/7e35cbb1b6f5915ab732a22e83b3afc20e29181a
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXBaseInfo.h
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h
M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.h
Log Message:
-----------
[NVPTX] Cleanup PTX virtual register encoding (NFC) (#212395)
Unify the scheme used to carry PTX virtual registers through
`MCOperand`s. The register class was encoded and decoded
by two hand-written switchtables, one in
`NVPTXAsmPrinter::encodeVirtualRegister` and one in
`NVPTXInstPrinter::printRegName`, kept in sync only by
comment. Both now share a `VirtualRegisterKind` enum and
`getVirtualRegisterPrefix` in `NVPTXBaseInfo.h`, which also
subsumes `getNVPTXRegClassStr` and drops the stale
`%f`/`%fd` cases left over from the typed float register
classes.
Co-Authored by Opus-5.
Commit: 56a48d712006ff7d9a09eef6a86b78d4b2eec3aa
https://github.com/llvm/llvm-project/commit/56a48d712006ff7d9a09eef6a86b78d4b2eec3aa
Author: Thurston Dang <thurston at google.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M compiler-rt/test/msan/vararg_shadow.cpp
Log Message:
-----------
[msan][test] Disable UB cases in vararg_shadow.cpp (#204246)
This patch comments out the tests for char and float, which have
undefined behavior: `warning: second argument to 'va_arg' is of
promotable type 'char'/'float'; this va_arg has undefined behavior
because arguments will be promoted to 'int'/'double' [-Wvarargs]`.
The non-UB way to rewrite the tests is to use `va_arg()` with int and
double types (when the original variables are char and float), but there
are already test cases for int and double.
Note also that the float test makes an assumption that
`cast<float>(cast<double>(float))` will maintain the original shadow,
which MSan need not guarantee. In particular,
https://github.com/llvm/llvm-project/pull/204197 breaks that assumption
(which led to a buildbot breakage and revert).
Commit: 30611cae030a654be821dfc817126568ac6d2baa
https://github.com/llvm/llvm-project/commit/30611cae030a654be821dfc817126568ac6d2baa
Author: Adam Bzowski <adam.bzowski at arm.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/test/AArch64/constant_island_pie_update.s
Log Message:
-----------
[BOLT] Fix RELR addend updates for non-zero image bases (#213000)
This patch fixes an AArch64 BOLT failure exposed by LLVM commit
`fbba327208d7f6994f9a28a51dca3e913e3b444a`, which enabled packed
relative relocations (RELR) globally. BOLT incorrectly used a virtual
relocation address as a file offset when updating RELR addends,
corrupting instrumented executables when their image base was non-zero.
The observed CMake compiler-check failure was only a consequence of the
corrupted BOLT-instrumented Clang executable crashing; the defect itself
is in BOLT, not CMake.
The regression test links an AArch64 PIE with a non-zero image base and
verifies that BOLT updates the RELR addend at the correct file offset.
Assisted-by: Codex
Commit: f68fba7a512c0dd3662540259e032a4a4de653b1
https://github.com/llvm/llvm-project/commit/f68fba7a512c0dd3662540259e032a4a4de653b1
Author: Anshil Gandhi <95053726+gandhi56 at users.noreply.github.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/DependencyGraphTest.cpp
Log Message:
-----------
[SandboxVec][DAG] Fix notifyEraseInstr to skip scheduled neighbors (#212868)
Guard both loops with !PredN->scheduled() so scheduled neighbors are
left untouched, and add a unit test that erases a node with one
scheduled and one unscheduled predecessor to cover the fix.
Commit: 17088c9b104e807ba29a0d115796bc6de23e9f63
https://github.com/llvm/llvm-project/commit/17088c9b104e807ba29a0d115796bc6de23e9f63
Author: Anshil Gandhi <95053726+gandhi56 at users.noreply.github.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/VecUtils.cpp
A llvm/test/Transforms/SandboxVectorizer/topdown_vec.ll
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
Log Message:
-----------
[SandboxVectorizer] Implement topdown/bottomup vectorizers in unison (#205249)
Extend the Sandbox Vectorizer's `bottom-up-vec` pass so a single
implementation can vectorize in either direction, and add the top-down
strategy that walks def-use chains forward from a seed.
Direction selection
--------------------
The pass direction is chosen from the Region's auxiliary pass argument:
"bottom-up" (or empty, the default) and "top-down" map onto a
SchedDirection, and any other value is rejected with a fatal usage
error.
The vectorizer always runs in the same direction as the scheduler.
Top-down traversal
------------------
Bottom-up starts from a seed slice (e.g. stores to consecutive
addresses)
and recurses into operands. Top-down instead starts from a seed of
consecutive loads and recurses into *users*:
- vectorizeRec() registers the current bundle's vector (pre-order)
before
recursing, so instructions are marked vectorized as soon as they are
claimed. This prevents sibling user bundles from claiming the same
instruction and guarantees termination.
- VecUtils::getNextUserBundles() drives the walk. For each user of lane
0
it tries to assemble a matching user for every remaining lane, requiring
the same opcode, type, parent block, and operand-usage indices, and
claiming each instruction at most once. Only complete bundles (one user
per lane) are returned.
- A non-Widen legality result stops the walk down that path: the bundle
is
left scalar and no action is recorded. DiamondReuse results cannot occur
top-down because already-vectorized users are skipped, so a bundle never
contains an instruction already in InstrMaps.
Operand and external-use handling
---------------------------------
Because a user bundle is emitted after its operand bundle, emitVectors()
looks up each operand's vector in InstrMaps and creates a pack when the
operand was not vectorized. emitUnpacksForExternalUses() now redirects
only the genuinely external (non-vectorized) uses via
replaceUsesWithIf(),
instead of a blanket replaceAllUsesWith() that would corrupt the
operands
of user bundles not yet emitted. Scheduling is currently skipped for the
top-down direction (TODO).
Refactoring
-----------
Unify the two strategies to avoid code duplication: introduce a shared
BundleTy alias, move user-bundle collection into VecUtils (with unit
tests), and thread the direction through legality checks and vector
emission.
Depends on #207237
Co-authored-by: Cursor <cursoragent at cursor.com>
Commit: 4912831bc346aa48a3c06475ad8d24f37f84bc8d
https://github.com/llvm/llvm-project/commit/4912831bc346aa48a3c06475ad8d24f37f84bc8d
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M lldb/include/lldb/Target/Target.h
M lldb/source/Target/Target.cpp
M lldb/source/Target/TargetProperties.td
M lldb/test/API/commands/settings/TestSettings.py
Log Message:
-----------
[lldb] Add target.jit-engine setting (#212998)
Add a target.jit-engine setting that lets users choose which LLVM
execution engine (MCJIT or ORC) is used to JIT expressions. Defaults to
MCJIT to preserve current behavior. This is groundwork for migrating
expression evaluation from MCJIT to ORC; IRExecutionUnit does not yet
consult this setting.
Commit: 71af911facd88e41df273a95d658c3293aa4edee
https://github.com/llvm/llvm-project/commit/71af911facd88e41df273a95d658c3293aa4edee
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M lldb/docs/CMakeLists.txt
M lldb/docs/python_extensions.md
Log Message:
-----------
[lldb/docs] Document the remaining scripted-extension plugin categories (#213140)
`python_extensions.md` only covered the first five plugin categories.
This commit adds the missing sections for every plugin category added
since: `ScriptedBreakpointResolver`, `ScriptedHook`,
`ScriptedStackFrameRecognizer`, `ScriptedCommand`, `ParsedCommand`,
`ScriptedStringSummary`, and `ScriptedSyntheticChildren`.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: a1d93f19bed4c73051f9379e2c64d4303b6866ca
https://github.com/llvm/llvm-project/commit/a1d93f19bed4c73051f9379e2c64d4303b6866ca
Author: Abhinav Gaba <abhinav.gaba at intel.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M offload/libomptarget/omptarget.cpp
A offload/test/offloading/firstprivate_packed_buffer_lifetime.c
Log Message:
-----------
[OpenMP][Offload] Fix use-after-free of the packed firstprivate transfer buffer (#212905)
`packAndTransfer()` called `submitData()`, which captured the address of
the data of
the `SmallVector` member of `PrivateArgumentManagerTy`, as the host
source of an
async transfer. The manager was later moved into an `AsyncInfo`
post-processing
lambda, changing the underlying address of the data:
`addPostProcessingFunction()`
copies the closure rather than moving it, but even if it "moved", the
address of the data owned by `SmallVector`'s inline capacity would have
changed.
The AMDGPU plugin read from the stale host source address when doing the
actual transfer.
Fix: allocate the packed buffer via
`getOrCreateSourceBufferForSubmitData()`, so
that `AsyncInfo` owns it. The non-packed
corresponding-pointer-initialization
path in this same class already built its source buffer that way.
Commit: 06361fb2efd0a6818800891d9e410615483fce6c
https://github.com/llvm/llvm-project/commit/06361fb2efd0a6818800891d9e410615483fce6c
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
M clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenStmt.cpp
M clang/lib/CIR/CodeGen/CIRGenVTables.cpp
A clang/test/CIR/CodeGen/attr-musttail.cpp
Log Message:
-----------
[CIR] Implement most of 'musttail' statement attr (#213154)
This implements the basics, and leaves NYI in a few places (particularly
those that require cleanup calculations). There IS some additional work
that needs to be done when the ABI work is put in place as well, and the
thunk 'tail' hint isn't implemented either, and is left as a
missing-feature.
This is necessary for compiling the bytecode interpreter in Clang in a
few places during self-build.
Commit: 8fbdc8cd027176fb54c5fbcd7688fe78eed0154f
https://github.com/llvm/llvm-project/commit/8fbdc8cd027176fb54c5fbcd7688fe78eed0154f
Author: jimingham <jingham at apple.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
Log Message:
-----------
If the address of the isa_pointer is returned as an error don't ask if it is a tagged pointer (#213163)
The answer isn't right and the wrong type might stick and cause
downstream failures.
Note, the correct solution to this is to distinguish between "couldn't
get the address" and "got a real value of LLDB_INVALID_ADDRESS" but
piping an optional all the way down and then through all the uses is an
intrusive change which I don't have time for right now. That only risk
is that this really IS a tagged pointer with the value
LLDB_INVALID_ADDRESS, so this seems an acceptable workaround.
I ran across this when debugging the ObjC test failures in the ObjC
testuite after 8b9cce358bef26ae4cb9275dd6a43f903bafbaa0. This patch
clears up all those testsuite failures, which should stand as a test for
this patch when I resubmit that change.
Commit: 6d9de525456298c7df08d77942d3ec50dddf5eaa
https://github.com/llvm/llvm-project/commit/6d9de525456298c7df08d77942d3ec50dddf5eaa
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/test/CodeGen/AMDGPU/bug-pk-f32-imm-fold.mir
M llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
M llvm/test/CodeGen/AMDGPU/coexec-sched-flavor-classification.mir
Log Message:
-----------
[AMDGPU] Duplicate packed fp32 instructions (#212857)
These have different semantics on gfx9 and gfx12 with respect to
scalar operands.
Commit: 53e16d7708c39ecc03f97d32d1db9afdd355deca
https://github.com/llvm/llvm-project/commit/53e16d7708c39ecc03f97d32d1db9afdd355deca
Author: Akshay K <iit.akshay at gmail.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
A clang/include/clang/CIR/CIRDataLayoutSpec.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
A clang/lib/CIR/CodeGen/CIRDataLayoutSpec.cpp
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
M clang/lib/CIR/CodeGen/CMakeLists.txt
M clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
A clang/test/CIR/CodeGen/pointer-width-32bit.cpp
A clang/test/CIR/IR/pointer-data-layout.cir
A clang/test/CIR/Tools/pointer-width-from-triple.cir
M clang/tools/cir-translate/cir-translate.cpp
Log Message:
-----------
[CIR] Pointer and vptr width from a CIR-native data-layout entry (#204185)
PointerType and VPtrType have hard-coded sizes and alignments of 64/8
bits. On targets with 32-bit pointers (e.g., nvptx, spirv32), this trips
the record layout builder. Any record containing a pointer hit the
insertPadding assertion (offset >= size)
because the pointer was sized at 8 bytes while the following field was
placed at the AST-mandated 4-byte offset.
### Changes:
- CIRGenerator: attaches a CIR-native cir.ptr data-layout entry at
module setup, storing {size-in-bits, abi-align-in-bits} read
from the target DataLayout (only for the default address space).
- CIRTypes: PointerType reads its size/alignment from that entry
(falling back to 64/8 when absent); VPtrType routes through a cir.ptr so
it picks up the same width.
- LowerToLLVM: strips the cir.ptr entry during CIR→LLVM lowering, since
cir.ptr has no meaning in LLVM IR.
- Unit test: checking 4-byte pointer/vptr layout on nvptx, verified
across CIR, CIR→LLVM.
Commit: 0879c1092c66242027065634210692cc06359fee
https://github.com/llvm/llvm-project/commit/0879c1092c66242027065634210692cc06359fee
Author: hulxv <hulxxv at gmail.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/extenddftf2.cpp
A compiler-rt/lib/builtins/extendsfdf2.cpp
A compiler-rt/lib/builtins/extendsftf2.cpp
A compiler-rt/lib/builtins/extendxftf2.cpp
A compiler-rt/lib/builtins/truncdfsf2.cpp
A compiler-rt/lib/builtins/trunctfdf2.cpp
A compiler-rt/lib/builtins/trunctfsf2.cpp
A compiler-rt/lib/builtins/trunctfxf2.cpp
M libc/shared/builtins.h
A libc/shared/builtins/extenddftf2.h
A libc/shared/builtins/extendsfdf2.h
A libc/shared/builtins/extendsftf2.h
A libc/shared/builtins/extendxftf2.h
A libc/shared/builtins/truncdfsf2.h
A libc/shared/builtins/trunctfdf2.h
A libc/shared/builtins/trunctfsf2.h
A libc/shared/builtins/trunctfxf2.h
M libc/src/__support/builtins/CMakeLists.txt
A libc/src/__support/builtins/extenddftf2.h
A libc/src/__support/builtins/extendsfdf2.h
A libc/src/__support/builtins/extendsftf2.h
A libc/src/__support/builtins/extendxftf2.h
A libc/src/__support/builtins/fpconvert_helper.h
A libc/src/__support/builtins/truncdfsf2.h
A libc/src/__support/builtins/trunctfdf2.h
A libc/src/__support/builtins/trunctfsf2.h
A libc/src/__support/builtins/trunctfxf2.h
M libc/test/shared/CMakeLists.txt
M libc/test/shared/shared_builtins_test.cpp
Log Message:
-----------
[compiler-rt][builtins] libc-backed floating-point extend/trunct builtins (#209984)
Add libc-backed floating-point extend/truncate builtins
Part of #197824
Commit: 0142992aea1df89fec8c20bf77520e37bfb69e2a
https://github.com/llvm/llvm-project/commit/0142992aea1df89fec8c20bf77520e37bfb69e2a
Author: Yusuke MINATO <minato.yusuke at fujitsu.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/test/Driver/flang/multiple-inputs-mixed.f90
A clang/test/Driver/flang/runtimes.f90
Log Message:
-----------
Reapply "[NFC][clang][Driver] Add tests for --driver-mode=flang" (#211724)
This reapplies #207658.
Some targets do not support flang_rt or clang_rt.
It seems difficult to create a blocklist, so the tests are now
configured to explicitly specify the known-working targets.
The specified targets are extracted from tests in flang/test/Driver.
-----
The original commit message:
This patch intends to clarify the current behaviors, not to state the
expected/desirable behaviors.
Commit: d9278ad4e640cf04e5fa0bd22898f5aa0351b564
https://github.com/llvm/llvm-project/commit/d9278ad4e640cf04e5fa0bd22898f5aa0351b564
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M lldb/include/lldb/Core/BugReporter.h
M lldb/source/Commands/CommandObjectDiagnostics.cpp
A lldb/source/Core/BugReporter.cpp
M lldb/source/Core/CMakeLists.txt
M lldb/source/Plugins/BugReporter/GitHub/GitHubReporter.cpp
M lldb/test/Shell/Diagnostics/TestReport.test
Log Message:
-----------
[lldb] Ask the reporter what happened in a bug report (#213173)
A diagnostics bundle records the state of the debugger, never what the
user was doing or what they expected instead, so reports arrive with a
generic title and no description of the problem. Pre-fill the report
with the questions only the person filing it can answer, and print a
checklist when the bundle is written so an incomplete report doesn't get
shared as-is.
rdar://183356348
Commit: 2e3f4ef5855e07f4bd2b0a1270e6101beceb1f8c
https://github.com/llvm/llvm-project/commit/2e3f4ef5855e07f4bd2b0a1270e6101beceb1f8c
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
A llvm/test/CodeGen/SPIRV/legalization/matrix-wide-vector-shader.ll
Log Message:
-----------
[SPIRV] Legalize Cast Instructions for Matrix Types (#212619)
fixes #186864
This is a more limited fix. that doesn't require us to change the whole
legalization strategy for SPIR-V.
To get the last fix to work it looks like I would have to have changed
every global opcode to no longer use power of 2 based legalization.
This change with power of 2 fixed the transpose case in the offload
testsuite when we do the conversion of bools to i32s before we call
transpose.
There remains an issue when a i1 makes it into a transpose intrinsic.
That said I can only trigger that case via llvmir and not HLSL so will
move on for now.
Commit: b4d2b2f9a31ba82b5bcbf9060748bde8beae814b
https://github.com/llvm/llvm-project/commit/b4d2b2f9a31ba82b5bcbf9060748bde8beae814b
Author: Michael G. Kazakov <mike.kazakov at gmail.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M libcxx/include/__algorithm/pstl.h
M libcxx/include/__pstl/backend_fwd.h
M libcxx/include/__pstl/backends/default.h
M libcxx/test/libcxx/algorithms/pstl.iterator-requirements.verify.cpp
M libcxx/test/libcxx/algorithms/pstl.nodiscard.verify.cpp
A libcxx/test/std/algorithms/alg.sorting/alg.lex.comparison/pstl.lexicographical_compare.pass.cpp
A libcxx/test/std/algorithms/alg.sorting/alg.lex.comparison/pstl.lexicographical_compare_comp.pass.cpp
M libcxx/test/std/algorithms/pstl.exception_handling.pass.cpp
Log Message:
-----------
[libc++][pstl] Implementation of parallel std::lexicographical_compare() based on std::mismatch() (#212366)
This PR adds an implementation of parallel
`std::lexicographical_compare()` based on parallel `std::mismatch()`.
The implementation is close to a one-liner:
```c++
auto __res = _Mismatch()(__policy, __first1, __last1, __first2, __last2, [&](_Ref1 __lhs, _Ref2 __rhs) {
return !__comp(__lhs, __rhs) && !__comp(__rhs, __lhs);
});
```
Included tests check that:
- Semantics of the iterator-only version is correct.
- Semantics of the predicated version is correct.
- The functions correctly SFINAE out when the first argument is not an
execution policy.
- The `noexcept` policy is followed.
- The `nodiscard` policy is followed.
- `static_assert` verifies iterators' categories.
Part of #99938.
Commit: 71e0359a1acd9ab267c72fcf9dfb683afc59fbea
https://github.com/llvm/llvm-project/commit/71e0359a1acd9ab267c72fcf9dfb683afc59fbea
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/RTBridge/Calls.h
M llvm/include/llvm/ExecutionEngine/Orc/RTBridge/SPS/Calls.h
M llvm/lib/ExecutionEngine/Orc/Shared/OrcRTBridge.cpp
Log Message:
-----------
[ORC] Generalize RTBridge callers over signature types. (#213179)
Recast the RTBridge callers as templates parameterized on the call
signature, so future executor accessors can be added as thin
declarations rather than hand-written classes.
rt::Caller<RetT(ArgTs...)> is the runtime-agnostic caller interface for
a given signature, providing the asynchronous and synchronous call
operators and the associated result types. rt::MainCaller is now an
alias for rt::Caller<int64_t(ArrayRef<std::string>)>.
rt::sps::Caller<BaseT, SPSSigT, CIName> implements any such interface by
invoking an executor-side SPS wrapper in the runtime's controller
interface, deducing the argument and result types from BaseT. A concrete
caller is a typedef supplying the interface, its SPS signature, and the
CI entry-point name; see rt::sps::MainCaller.
MainCaller's observable behavior is unchanged (the existing
SPSCallersTest still passes). The out-of-line destructor anchor in
OrcRTBridge.cpp is dropped, as the templated base now provides an inline
defaulted destructor.
Commit: 5e90b7bad3cc0960a26f46969063c5acf03ac137
https://github.com/llvm/llvm-project/commit/5e90b7bad3cc0960a26f46969063c5acf03ac137
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
A llvm/test/DebugInfo/X86/DW_AT_LLVM_stmt_seq_split_dwarf.ll
Log Message:
-----------
[DebugInfo] Make DW_AT_LLVM_stmt_seq work with split DWARF (#213128)
Before this change, we would end up with a relocation in the dwo, which
would then result in an error.
Commit: 8b04cf374d4ac63edf973eb23b0566c21b6f638f
https://github.com/llvm/llvm-project/commit/8b04cf374d4ac63edf973eb23b0566c21b6f638f
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
Log Message:
-----------
[AMDGPU] Rename packed 64-bit features to include SingleSGPR. NFCI. (#212891)
Commit: 88329c4ad200b71e0cbcc7ac0093c7caf934ddea
https://github.com/llvm/llvm-project/commit/88329c4ad200b71e0cbcc7ac0093c7caf934ddea
Author: Kazu Hirata <kazu at google.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/include/llvm/ADT/SetVector.h
M llvm/lib/Transforms/IPO/Attributor.cpp
Log Message:
-----------
[ADT] Introduce SetVector::reserve (NFC) (#209951)
This patch introduces SetVector::reserve to allocate capacity in the
underlying containers.
We also adopt SetVector::reserve across Attributor.cpp where the exact
number of unique functions being inserted is known ahead of time.
Assisted-by: Antigravity
Commit: ca5549224e06c5ed57332bf1bc89c0ac06c69e60
https://github.com/llvm/llvm-project/commit/ca5549224e06c5ed57332bf1bc89c0ac06c69e60
Author: Thurston Dang <thurston at google.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vcvt.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vcvt_f32_su32.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/vararg_shadow.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/f16c-intrinsics-upgrade.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/vararg_shadow.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/vararg_shadow.ll
Log Message:
-----------
Reland "[msan] Apply handleGenericVectorConvertIntrinsic() to fptrunc/fpext" (#213161)
Reverts llvm/llvm-project#204221 i.e., reapplies
https://github.com/llvm/llvm-project/pull/204197. The original patch was
reverted was due to a buildbot failure in vararg_shadow.cpp that relied
on undefined behavior as well as an unwarranted assumption that the
shadow is preserved when round-tripping from float->double->float. The
UB cases have been disabled in
https://github.com/llvm/llvm-project/pull/204246.
Original commit message:
The current instrumentation uses handleShadowOr(), which effectively
truncates or zero-extends the shadows for fptrunc/fpext respectively;
this is overly lax because floating-point has both mantissa and exponent
components (e.g., if the mantissa is initialized but the exponent is
uninitialized, an fptrunc might end up with a fully initialized shadow,
which is incorrect; conversely, if a floating-point value is fully
uninitialized, we want the fpext'ed shadow to be fully uninitialized,
not zero-extended). This patch strengthens the instrumentation of
fptrunc/fpext by using handleGenericVectorConvertIntrinsic(), which
applies an "all-or-nothing" approach to uninitialized bits of each
scalar.
Note: https://github.com/llvm/llvm-project/pull/203903 auto-upgraded
aarch64_neon_vcvtfp2hf and aarch64_neon_vcvthf2fp to fptrunc and fpext,
which had the effect of weakening MSan's instrumentation for those NEON
intrinsics. This patch restores the stronger instrumentation for them
(and also generalizes it to all instances of fptrunc and fpext).
Commit: 151b53deb836f82fdc068f05d4af1b42e1c4748a
https://github.com/llvm/llvm-project/commit/151b53deb836f82fdc068f05d4af1b42e1c4748a
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/Relocations.cpp
M lld/test/ELF/aarch64-thunk-sort.s
Log Message:
-----------
[ELF] Remove -z sort-thunks (#213074)
The option was added by #211721 (sort forward thunks by descending
destination to prevent convergence failures) as a temporary opt-out.
Tests have been migrated to the default order.
Commit: 4311bccd19e2db25e7c410acd9d77a86d2b779d1
https://github.com/llvm/llvm-project/commit/4311bccd19e2db25e7c410acd9d77a86d2b779d1
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
R llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
R llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
Log Message:
-----------
[NVPTX] Move NVPTXAsmPrinter and NVPTXDAGToDAGISel out of headers (NFC) (#213162)
Both headers were only included by their own `.cpp` file, so move the
class definitions into anonymous namespaces there and delete the
headers.
`getFromTypeWidthForLoad` was the only thing `NVPTXISelLowering.cpp`
needed from the ISel class, so it moves to `NVPTXUtilities` as a free
function.
Commit: 08bfd2e3fd81e6930b12076a670fc9e59ef32a84
https://github.com/llvm/llvm-project/commit/08bfd2e3fd81e6930b12076a670fc9e59ef32a84
Author: Henry Jiang <henry_jiang2 at apple.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/utils/perf-training/perf-helper.py
Log Message:
-----------
[clang] perf_helper.py ignore clang warning/note when parsing cc1 command (#212401)
Parsing cc1 command fails in `perf_helper` when `clang: note:` or
`clang: warning:` due to driver warnings. As an example, harmless macOS
sdk mismatch and `-Wunused-command-line-argument`.
Commit: 1ddfb94fa6c645af9e10ad4946d9b7aea3c46454
https://github.com/llvm/llvm-project/commit/1ddfb94fa6c645af9e10ad4946d9b7aea3c46454
Author: Krisitan Erik Olsen <kristian.erik at outlook.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaChecking.cpp
A clang/test/CodeGenCXX/GH211943.cpp
Log Message:
-----------
[Sema] Fix crash in __builtin_dump_struct with -Werror -Wformat-pedantic (#212377)
`DiagnosticErrorTrap::hasErrorOccurred()` treats warnings promoted to
errors by `-Werror` as real errors, causing `BuiltinDumpStructGenerator`
to bail out before building the `PseudoObjectExpr` wrapper. CodeGen then
encounters the untransformed `CallExpr` with a placeholder builtin type
and hits `llvm_unreachable` in `CodeGenTypes::ConvertType`.
Use `hasUnrecoverableErrorOccurred()` instead, which ignores `-Werror`
promoted warnings and only bails on genuine compilation errors.
Fixes #211943
Commit: 503e7f6a2674bd80490d69670e86e6b8d823215c
https://github.com/llvm/llvm-project/commit/503e7f6a2674bd80490d69670e86e6b8d823215c
Author: Henry Jiang <henry_jiang2 at apple.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/include/module.modulemap
Log Message:
-----------
Module Build Fix: Add NVPTXTargetParser.def as a header (#213194)
Fixes module build `-DLLVM_ENABLE_MODULES=ON` in
https://ci.swift.org/job/llvm.org/job/clang-stage2-Rthinlto/job/main/457
by adding missing header for `NVPTXTargetParser.def`.
rdar://183685761
Commit: c57b2b6103cb4bb6c4c2bee901c1eee2b966e5f0
https://github.com/llvm/llvm-project/commit/c57b2b6103cb4bb6c4c2bee901c1eee2b966e5f0
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
M llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
M llvm/test/CodeGen/X86/merge-store-partially-alias-loads.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
Log Message:
-----------
DAG: Use poison in getLoad/getStore for offsets (#212066)
Commit: 8b1821512db03f0cf0d443ac836f42ab993e9c53
https://github.com/llvm/llvm-project/commit/8b1821512db03f0cf0d443ac836f42ab993e9c53
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/unittests/Target/ARM/InstSizes.cpp
M llvm/unittests/Target/ARM/MachineInstrTest.cpp
Log Message:
-----------
ARM: Thread float ABI through ARMSubtarget (NFC) (#212931)
Commit: 7fc837632399955e281bce975033ff7b389eb790
https://github.com/llvm/llvm-project/commit/7fc837632399955e281bce975033ff7b389eb790
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/test/CodeGenOpenCL/builtins-amdgcn-global-load-store.cl
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
Log Message:
-----------
AMDGPU: Add missing flat-global-insts to gfx13 frontend feature map (#213121)
Commit: cee7b71929312666c5cf48eb79873893811b99a7
https://github.com/llvm/llvm-project/commit/cee7b71929312666c5cf48eb79873893811b99a7
Author: Kirill A. Korinsky <kirill at korins.ky>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/test/CodeGen/SPARC/reserved-regs-named.ll
Log Message:
-----------
[SPARC] Accept named register aliases (#212838)
Handle r0-r31, sp, fp and the optional '%' prefix in llvm.read_register
and llvm.write_register.
Commit: afd4c46353bf77b9f4ebfde664e4fcf8d2ef2fc8
https://github.com/llvm/llvm-project/commit/afd4c46353bf77b9f4ebfde664e4fcf8d2ef2fc8
Author: Kamlesh Kumar <kamlesh.kumar at arm.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/sve-structured-store-memoperands.ll
M llvm/test/CodeGen/AArch64/sve-vector-interleave.ll
Log Message:
-----------
[AArch64] Preserve store memoperand (#210936)
Commit: 5b1539c0fca2e3f9362d100848983a3cc4272764
https://github.com/llvm/llvm-project/commit/5b1539c0fca2e3f9362d100848983a3cc4272764
Author: David Green <david.green at arm.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-addo-zero.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-binop-reassoc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-conflict.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-crash.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-and-mask.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-or-pattern-align.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-or-pattern.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-mulo-zero.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-narrow-binop-feeding-add.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-select-to-fminmax.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-use-vector-truncate.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-ashr-shl-to-sext-inreg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-binop-same-val.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-br.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-bzero.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-commute-shift.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-concat-vectors.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-s1.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-funnel-shifts-to-rotates.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-hoist-same-hands.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-icmp-redundant-trunc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-invert-cmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-not-really-equiv-insts.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-prop-extends-phi.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-ptradd-chain.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-select.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-sextload-from-sextinreg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector-disjoint-mask.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector-undef-rhs.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-simplify-add.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-undef.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-xor-of-and-with-same-reg.mir
Log Message:
-----------
[AArch64][GlobalISel] Update prelegalize tests with concrete types. NFC (#213199)
Commit: 79537625e213b6a5f329da1d5a443de265346a5e
https://github.com/llvm/llvm-project/commit/79537625e213b6a5f329da1d5a443de265346a5e
Author: Kamlesh Kumar <kamlesh.kumar at arm.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/avoid-ld4.ll
Log Message:
-----------
[AArch64] Avoid factor-4 deinterleaved loads feeding uitofp (#210894)
Avoid generating ld4 when all values produced by the deinterleaved load
are fed into uitofp. Keeping the loads separate allows the backend to
optimize them into shifts and masks.
Commit: a7fa385ffa27504240e90e2b857455459dbd11de
https://github.com/llvm/llvm-project/commit/a7fa385ffa27504240e90e2b857455459dbd11de
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx13.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-raw-buffer-atomic-max.cl
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
Log Message:
-----------
AMDGPU: Add missing atomic-fmin-fmax-global to gfx13 feature map (#213119)
fillAMDGCNFeatureMap omitted atomic-fmin-fmax-global-f32 and
atomic-fmin-fmax-global-f64 for gfx1310/gfx13-generic, so clang wrongly
rejected the raw_ptr_buffer_atomic_f{min,max}_f{32,64} builtins on those
targets even though the backend enables the features. Add them to the
gfx13 case.
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: 14192adddc39cb28b7bcb1e6d50dc6ef87f4d54b
https://github.com/llvm/llvm-project/commit/14192adddc39cb28b7bcb1e6d50dc6ef87f4d54b
Author: Peter Rong <peterrong96 at gmail.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/lib/AST/Expr.cpp
M clang/lib/Sema/SemaDecl.cpp
A clang/test/SemaObjC/objc-constant-literal-dict-key-restrictions.m
Log Message:
-----------
[clang][Sema] Fix ObjC file-scope literal diagnostic (#209688)
A non-constant ObjC collection literal used as a file-scope initializer
should get the targeted err_objc_literal_nonconstant_at_file_scope
pointing at the offending element. CheckForConstantInitializer instead
inspected the wrapped Init/Culprit, so under -fobjc-arc, for id-typed
variables, or with parentheses it skipped the per-element loop and fell
back to the generic "initializer element is not a compile-time constant"
on the whole @{...}/@[...] -- or blamed the wrong element (e.g. a valid
string key rather than the non-constant value).
Unwrap the culprit with IgnoreParenImpCasts and drive classification and
per-element reporting off it, mirroring BuildObjC{Array,Dictionary}Literal
(unwrap before each isa<>; keys must be string literals, values/elements
constant object literals). Also treat CK_ARCReclaimReturnedObject as
transparent in Expr::isConstantInitializer so ARC-wrapped literals are
recognized and the reported culprit is the literal itself.
Add objc-constant-literal-dict-key-restrictions.m (macOS no-ARC, iOS ARC,
ObjC++), with each culprit on its own line so -verify checks the caret.
[Assisted-by](https://t.ly/Dkjjk): Opus 4.8
Commit: 6a38e4e0971285ccd7cca1b732f644a49f772d49
https://github.com/llvm/llvm-project/commit/6a38e4e0971285ccd7cca1b732f644a49f772d49
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h
Log Message:
-----------
[BFI] Simplify computeMassInLoops. NFC (#213200)
Iterate backwards with a plain iterator instead of dancing with
prev(base()).
Commit: 0312615e54f021ed2dc400a3ecd6698058490ae6
https://github.com/llvm/llvm-project/commit/0312615e54f021ed2dc400a3ecd6698058490ae6
Author: Mariya Podchishchaeva <mariya.podchishchaeva at intel.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/Maintainers.md
Log Message:
-----------
[clang][doc] Use my private email for now (#213058)
I'm in the middle of changing employers and will loose access to the
current email soon for a while.
Commit: 9f6b782c7a993dedc8fe8b6e69c36c9684191f27
https://github.com/llvm/llvm-project/commit/9f6b782c7a993dedc8fe8b6e69c36c9684191f27
Author: Anutosh Bhat <andersonbhat491 at gmail.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll
Log Message:
-----------
[WebAssembly] Fix legalization of v8f16 insertelement (#212992)
```
define <8 x half> @insert_v8f16(<8 x half> %v, half %x) {
%r = insertelement <8 x half> %v, half %x, i32 3
ret <8 x half> %r
}
```
```
llc \
-mtriple=wasm32-unknown-unknown \
-mattr=+simd128,+fp16 \
-o /dev/null \
/private/tmp/wasm-v8f16-insert-only.ll
```
Would lead to
```
Initial selection DAG: %bb.0 'insert_v8f16:'
SelectionDAG has 10 nodes:
t0: ch,glue = EntryToken
t2: v8f16 = WebAssemblyISD::ARGUMENT TargetConstant:i32<0>
t4: i32 = WebAssemblyISD::ARGUMENT TargetConstant:i32<1>
t5: i16 = truncate t4
t6: f16 = bitcast t5
t8: v8f16 = insert_vector_elt t2, t6, Constant:i32<3>
t9: ch = WebAssemblyISD::RETURN t0, t8
Soft promote half operand 1:
t8: v8f16 = insert_vector_elt t2, t6, Constant:i32<3>
SoftPromoteHalfOperand Op #1:
t8: v8f16 = insert_vector_elt t2, t6, Constant:i32<3>
LLVM ERROR: Do not know how to soft promote this operator's operand!
```
Commit: 652e04312e8c5f4fc90ac16be494c3562c111ab9
https://github.com/llvm/llvm-project/commit/652e04312e8c5f4fc90ac16be494c3562c111ab9
Author: Ramon Munoz Jr <ramon.g.munoz.jr at intel.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/include/llvm/MC/MCSubtargetInfo.h
Log Message:
-----------
[MC] Add default ctor to SubtargetSubTypeAliasKV for zero-alias targets- #38762 (#212919)
Fixes a Windows MSVC 2019-only build break from 02da012 ("TableGen: Use
a compact table for CPU aliases", #211952).
That commit added std::array<SubtargetSubTypeAliasKV, NumAliases> to
SubtargetSubTypeKVStorage. SubtargetSubTypeAliasKV uses relative string
offsets, so it is non-copyable and declares only a two-argument
constructor -
no default constructor. In the MSVC 2019 STL, std::array<T, 0> still
holds a
real _Ty _Elems[1] and value-initializes it, so it requires T to be
default-constructible. Any target that defines no ProcessorAlias records
instantiates std::array<..., 0> and fails to compile. MSVC 2022 changed
this
member to a conditionally-empty type, so only MSVC 2019 is affected.
Fix: add a constexpr default constructor.
Co-Authored-By: Claude Opus 5
Signed-off-by: Munoz Jr, Ramon <ramon.g.munoz.jr at intel.com>
Commit: d91967e13ea281e37930cc592d35dfd3c5447a3f
https://github.com/llvm/llvm-project/commit/d91967e13ea281e37930cc592d35dfd3c5447a3f
Author: David Green <david.green at arm.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/GlobalISel/combine-2-icmps-of-0-and-or.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-add-of-sub.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-addv.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-and-or-disjoint-mask.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-anyext-crash.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-avg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-binop-neg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-binop-undef-left-to-zero.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-build-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-fcmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-icmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-cast.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-const-infinite-loop.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-fp-const-lhs.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-int-const-lhs.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-const-fold-barrier-rhs.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-fma.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-fp-rounding.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-itofp-zero.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-unary-int.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-copy.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ctlz-cttz-zero-poison.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-trunc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ext.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-extract-vec-elt.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fabs.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-flog2.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fminimum-fmaximum.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fminnum-fmaxnum.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fneg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fpowi.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fptrunc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-freeze.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fshl.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fshr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fsqrt.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-of-binop-to-icmp-of-0.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-to-lhs-known-bits.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-inttoptr-ptrtoint.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-logic-of-compare.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-mul-to-shl.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-mul.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-mulo-with-2.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-narrow-binop.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-neg-and-one-to-sext-inreg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-op-trunc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-or-and-xor.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-or-of-and.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-overflow.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-int2ptr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-reassociation.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ptrtoint.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-same-op.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-sdiv.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-debugloc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-trunc-sextload.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-shift-immed-mismatch-crash.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-shifts-undef.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-shufflevector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-srem-by-pow2.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-trunc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-udivrem-use-bug.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-umulh-to-lshr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-unary-undef-to-zero.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge-undef.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-use-vector-truncate-order.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-vscale.mir
Log Message:
-----------
[AArch64][GlobalISel] Update combine tests with concrete types. NFC (#213212)
Commit: 88fb1a93f4dd4e2bc5637b5e30ff0fab9edc21a9
https://github.com/llvm/llvm-project/commit/88fb1a93f4dd4e2bc5637b5e30ff0fab9edc21a9
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
Log Message:
-----------
[clang][bytecode][NFC] Use auto* if we can (#213209)
Instead of just auto.
Commit: e1823e8b1778997d12ba947350190af5ee845ca9
https://github.com/llvm/llvm-project/commit/e1823e8b1778997d12ba947350190af5ee845ca9
Author: Nathaniel McCallum <nathaniel at mccallum.life>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/test/CodeGen/X86/fptosi-sat-scalar-f16.ll
M llvm/test/CodeGen/X86/fptosi-sat-scalar.ll
Log Message:
-----------
[X86] Fix miscompile of fptosi.sat.iN.f16 for NaN under avx512fp16 (#210556)
`X86TargetLowering::LowerFP_TO_INT_SAT` incorrectly lowered
`llvm.fptosi.sat.iN.f16` for N = 13, 14, 15, 16 under `avx512fp16`
codegen: NaN inputs produced the destination type's minimum value
instead of the 0 that the intrinsic's documented semantics require.
Vector forms that scalarize through this lowering are affected under
the same condition, applied per element. See the third commit message
for the full root-cause analysis and fix rationale.
---
Assisted-by: Claude (Anthropic)
Assisted-by: Codex (OpenAI)
The investigation, root-cause analysis, fix, and tests in this PR were
developed with substantial AI assistance (Claude), including four
independent AI-assisted review rounds (Codex). I reviewed and take
responsibility for all code, analysis, and claims in this PR, and can
answer questions about the reasoning above.
Commit: bcf20310bdafd37253c6c849cd9bd3ba5b79752f
https://github.com/llvm/llvm-project/commit/bcf20310bdafd37253c6c849cd9bd3ba5b79752f
Author: Jakob Koschel <jakobkoschel at google.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M compiler-rt/test/cfi/anon-namespace.cpp
M compiler-rt/test/cfi/bad-cast.cpp
M compiler-rt/test/cfi/base-derived-destructor.cpp
M compiler-rt/test/cfi/cross-dso-diagnostic.cpp
M compiler-rt/test/cfi/cross-dso/icall/diag.cpp
M compiler-rt/test/cfi/cross-dso/icall/icall-from-dso.cpp
M compiler-rt/test/cfi/cross-dso/icall/icall.cpp
M compiler-rt/test/cfi/cross-dso/simple-fail.cpp
M compiler-rt/test/cfi/cross-dso/target_out_of_bounds.cpp
M compiler-rt/test/cfi/icall/bad-signature.c
M compiler-rt/test/cfi/lit.cfg.py
M compiler-rt/test/cfi/mfcall.cpp
M compiler-rt/test/cfi/multiple-inheritance.cpp
M compiler-rt/test/cfi/nvcall.cpp
M compiler-rt/test/cfi/overwrite.cpp
M compiler-rt/test/cfi/simple-fail.cpp
M compiler-rt/test/cfi/target_uninstrumented.cpp
M compiler-rt/test/cfi/vdtor.cpp
Log Message:
-----------
[ubsan] Test CFI summaries globally (#206434)
Always enable report_error_type=1 and print_summary=1 for CFI tests, and
update existing tests to check for cfi-bad-type. This allows us to
verify summary output comprehensively across the test suite.
This is a prerequisite for the change to the UBSan summary for CFI in
https://github.com/llvm/llvm-project/pull/203341.
Assisted-by: Automated tooling, human reviewed.
Commit: 5eb4272b04144bded2ca1819c2d93b1cd4f1a26b
https://github.com/llvm/llvm-project/commit/5eb4272b04144bded2ca1819c2d93b1cd4f1a26b
Author: Kareem Ergawy <kergawy at nvidia.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/test/Fir/Todo/select_case_with_character.fir
M flang/test/Fir/convert-to-llvm-invalid.fir
M flang/test/Fir/convert-to-llvm.fir
Log Message:
-----------
[flang][CodeGen] Replace fir.select* FIR-to-LLVM patterns with stubs that emit conversion errors (#212978)
`fir.select`, `fir.select_case`, `fir.select_rank`, and
`fir.select_type` are lowered to cf.* earlier in the pipeline
(`--fir-select-ops-conversion` and `--fir-polymorphic-op`). Their
FIR-to-LLVM conversion patterns are dead in a correct pipeline. Replace
them with a single templated stub
`SelectShouldHaveBeenConvertedStub<OP>` that emits `"'fir.<op>' op
should have already been converted"` and fails legalization, so running
`--fir-to-llvm-ir` standalone on stale IR reports a clear diagnostic
instead of "unable to legalize".
`Fir/convert-to-llvm.fir`'s six select* test blocks are removed (the
lowering no longer runs; CF-level coverage lives in
`Fir/SelectOpsConversion/`). `Fir/convert-to-llvm-invalid.fir` gains a
stub-error test per op. `Fir/Todo/select_case_with_character.fir` is
retargeted to check the equivalent diagnostic now emitted by
`--fir-select-ops-conversion`.
Co-Authored-By: Claude Sonnet 4.6 (1M context) <noreply at anthropic.com>
PR Stack:
* https://github.com/llvm/llvm-project/pull/212977
* ▶️ https://github.com/llvm/llvm-project/pull/212978
Co-authored-by: Claude Sonnet 4.6 (1M context) <noreply at anthropic.com>
Commit: 2897ee1dbbbfb2d28ba23105b85697824b4a98a5
https://github.com/llvm/llvm-project/commit/2897ee1dbbbfb2d28ba23105b85697824b4a98a5
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/docs/AMDGPUMemoryModel.md
Log Message:
-----------
[AMDGPU][Docs] Memory Model: Refactor location-order to cover reads (#213044)
This shouldn't change anything semantically, only make the spec
(a) closer to the Vulkan spec, which includes reads in their location-ordered
relation: https://docs.vulkan.org/spec/latest/appendices/memorymodel.html#memory-model-location-ordered
(b) more uniform: this way, the may-see constraints are the same as the vanilla
LLVM constraints, only with all occurrences of "happens-before" replaced by
"location-ordered before".
Commit: a3ae1e0a8d5edaebe9e934e69fc4df84ed89d365
https://github.com/llvm/llvm-project/commit/a3ae1e0a8d5edaebe9e934e69fc4df84ed89d365
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
Log Message:
-----------
[clang][bytecode][NFC] Enforce internal linkage (#213208)
For a struct and a function.
Commit: 21b0fc84c2f5fac1d3f763cfa581762684ad2a89
https://github.com/llvm/llvm-project/commit/21b0fc84c2f5fac1d3f763cfa581762684ad2a89
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
Log Message:
-----------
[clang][bytecode][NFC] Remove redundant casts (#213210)
Commit: 99b3c767c34a04af0a2bbb1fd41bf1b2cb62b331
https://github.com/llvm/llvm-project/commit/99b3c767c34a04af0a2bbb1fd41bf1b2cb62b331
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
M llvm/test/CodeGen/RISCV/branch-on-zero.ll
M llvm/test/Transforms/IndVarSimplify/ARM/code-size.ll
M llvm/test/Transforms/IndVarSimplify/replace-loop-exit-folds.ll
M llvm/test/Transforms/LoopIdiom/basic.ll
M llvm/test/Transforms/LoopStrengthReduce/AArch64/expand-ptrtoaddr-reuse-ptrtoint.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-metadata.ll
M llvm/test/Transforms/LoopVectorize/opaque-ptr.ll
M llvm/unittests/Transforms/Utils/ScalarEvolutionExpanderTest.cpp
Log Message:
-----------
[Analysis] Optimise mul(const, (udiv %n, const)) during SCEV expansion (#212769)
We sometimes see SCEV expansions like this:
%lshr = lshr i64 %n, 2
%shl = shl i64 %lshr, 2
which originate from SCEV mul and udiv expressions:
mul(4, udiv(%n, 4))
that both share the same multiplicand, divisor. The instcombine pass
normally canonicalises this into
%and = and %n, -4
which is the final IR typically seen by the backend. In the case of SCEV
expansion during a pass like the loop vectoriser, instcombine does clean
this up. However, before this is cleaned up it will lead to
over-estimation of costs of SCEV checks, since the shifts are costed
separately and added up. It doesn't seem like there is an easy way to
look at the use count of a SCEV node in the SCEVExpander code. However,
I think for simple cases like this it's always beneficial to fold them
even if there are multiple uses of the SCEV udiv because we're dropping
both shifts.
Commit: 9d1018038c01d12801ccca9da5e6b5589989750a
https://github.com/llvm/llvm-project/commit/9d1018038c01d12801ccca9da5e6b5589989750a
Author: Lukas Sommer <lukas.sommer at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/RegAllocGreedy.cpp
A llvm/test/CodeGen/AMDGPU/greedy-wwm-copy-prologue-assert.mir
Log Message:
-----------
[RegAlloc] Avoid split past block-prologue interference (#209704)
`leaveIntvAtTop` skips the target-specific block prologue when
determining the insertion point.
If the block prologue itself contains an instruction that interferes
with the interval, we must leave the interval before the block,
otherwise we will hit an assertion in `splitLiveThroughBlock`.
---------
Signed-off-by: Lukas Sommer <lukas.sommer at amd.com>
Commit: 28896ffcde9a773361e5d61191ebc2100abf5bcf
https://github.com/llvm/llvm-project/commit/28896ffcde9a773361e5d61191ebc2100abf5bcf
Author: Benedek Kaibas <82393336+benedekaibas at users.noreply.github.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/test/Analysis/dangling-ptr-deref.cpp
M clang/test/Analysis/lifetime-bound.cpp
Log Message:
-----------
[analyzer][NFC] Add test cases for the lifetime test suite (#212254)
During the development of the lifetime checkers I had many important
test cases saved locally and were never imported to the test files of
the checkers. This PR adds those missing test cases to the test files.
By adding these test cases it helps tracking the state of the lifetime
checkers and what improvements they need in order to have better
coverage and reduce the false positive rate.
*AI policy*: During the development I have consulted with claude sonnet
5 to list me test case scenarios it thinks are useful and then reviewed
its feedback and implemented/wrote those test cases by myself. Since
some of the test cases are edge cases I wanted to make sure the
implementation is on the right track.
Commit: 5eb876fcaf460a9ee1dac9490b4b2871674b80ec
https://github.com/llvm/llvm-project/commit/5eb876fcaf460a9ee1dac9490b4b2871674b80ec
Author: Benedek Kaibas <82393336+benedekaibas at users.noreply.github.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/include/clang/StaticAnalyzer/Core/BugReporter/BugReporterVisitors.h
M clang/include/clang/StaticAnalyzer/Core/BugReporter/Z3CrosscheckVisitor.h
M clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/RetainCountChecker/RetainCountDiagnostics.cpp
M clang/lib/StaticAnalyzer/Checkers/VAListChecker.cpp
M clang/lib/StaticAnalyzer/Core/BugReporter.cpp
M clang/lib/StaticAnalyzer/Core/BugReporterVisitors.cpp
M clang/lib/StaticAnalyzer/Core/Z3CrosscheckVisitor.cpp
Log Message:
-----------
[analyzer][NFC] Match the parameters order of getEndPath and finalizeVisitor with VisitNode (#212883)
Currently the ordering of the parameters in `getEndPath` and
`finalizeVisitor` functions does not match the declaration of the
`VisitNode` function. This PR resolves it by reordering the parameters
among these functions to be consistent.
Commit: 2b4f6c42a7dbc8b28c71a334a9fbecce99b68eaf
https://github.com/llvm/llvm-project/commit/2b4f6c42a7dbc8b28c71a334a9fbecce99b68eaf
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx13.cl
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll
Log Message:
-----------
AMDGPU: Add missing mqsad-pk-insts to gfx13 frontend feature map (#213124)
fillAMDGCNFeatureMap omitted mqsad-pk-insts for gfx1310/gfx13-generic,
so clang wrongly rejected __builtin_amdgcn_mqsad_pk_u16_u8 on those
targets even though the backend enables the feature. Add it to the gfx13 case.
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: df81098826f9b45df3cbe2f29af3c44d69d5851a
https://github.com/llvm/llvm-project/commit/df81098826f9b45df3cbe2f29af3c44d69d5851a
Author: Sergey Shcherbinin <sscherbinin at nvidia.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
A llvm/test/tools/llvm-profgen/X86/first-loadable-address.test
M llvm/tools/llvm-profgen/ProfiledBinary.cpp
Log Message:
-----------
[llvm-profgen] Preserve zero-valued first PT_LOAD address (#212258)
FirstLoadableAddress was initialized with if (!FirstLoadableAddress), so
a valid first PT_LOAD at vaddr 0 was treated as unset and overwritten by
a later segment. Track whether the first loadable segment has been seen
instead.
Assisted by GPT-5
Commit: 4fbad31a8adf437e1d0f1307ff4c26a248462b09
https://github.com/llvm/llvm-project/commit/4fbad31a8adf437e1d0f1307ff4c26a248462b09
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
M mlir/test/Conversion/SPIRVToLLVM/arithmetic-ops-to-llvm.mlir
Log Message:
-----------
[mlir][SPIR-V] Add SPIRVToLLVM conversions for FMod and SMod (#206933)
Commit: 814c0e672dfc81ae02a0772879f993a57bdbc1ad
https://github.com/llvm/llvm-project/commit/814c0e672dfc81ae02a0772879f993a57bdbc1ad
Author: Jeremy Johnson <jeremy.johnson at arm.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
Log Message:
-----------
[mlir][tosa] Switch matmul_t output to bf16 from fp16 (#212970)
Note that this implements the TOSA specification change:
https://github.com/arm/tosa-specification/pull/67
---------
Signed-off-by: Jeremy Johnson <jeremy.johnson at arm.com>
Commit: 9b734e25473bc9e299a4b58575b9b0e618925b78
https://github.com/llvm/llvm-project/commit/9b734e25473bc9e299a4b58575b9b0e618925b78
Author: Siyi Xu <siyix at nvidia.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/BasicPtxBuilderInterface.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/BasicPtxBuilderInterface.cpp
M mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir
Log Message:
-----------
[mlir][NVVM] Add memory clobber support to inline_ptx and BasicPtxBui… (#212937)
PTX with memory side effects (stores, atomics, mbarrier operations with
acquire/release semantics) emitted through `nvvm.inline_ptx` lowers to
`llvm.inline_asm` with register constraints only. Without a `~{memory}`
clobber, LLVM may reorder memory accesses across the inline assembly.
There was no way to express the clobber through this op or the
`BasicPtxBuilderInterface` machinery.
This patch adds, as discussed with @grypp:
- A `hasMemoryClobber` interface method (default `false`) on
`BasicPtxBuilderOpInterface`; when it returns `true`, `PtxBuilder`
appends `~{memory}` to the constraints of the generated inline assembly,
after all register constraints and tied indices.
- An opt-in `memory_clobber` boolean attribute (default `false`) on
`nvvm.inline_ptx` exposing this. Existing behavior is unchanged unless
the attribute is set to `true`.
For example:
```mlir
nvvm.inline_ptx "mbarrier.init.b64 [$0], $1;" ro(%p, %c : !llvm.ptr, i32) memory_clobber = true
```
now lowers to inline assembly with constraints `"l,r,~{memory}"`.
Tests: constraint emission with/without the attribute, combination with
predicate (`"l,r,b,~{memory}"`), read-write operands with tied indices
(`"=f,=f,r,r,0,1,~{memory}"`), and the no-operand case (`"~{memory}"`).
The op documentation's first example (mbarrier.init) is updated to show
correct usage.
Commit: 65cd5388148e798798507dd9301e1dfe564f8ab3
https://github.com/llvm/llvm-project/commit/65cd5388148e798798507dd9301e1dfe564f8ab3
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/VPlan/icmp-uniforms.ll
M llvm/test/Transforms/LoopVectorize/bsd_regex.ll
M llvm/test/Transforms/LoopVectorize/extract-last-veclane.ll
M llvm/test/Transforms/LoopVectorize/float-induction.ll
M llvm/test/Transforms/LoopVectorize/forked-pointers.ll
M llvm/test/Transforms/LoopVectorize/histograms.ll
M llvm/test/Transforms/LoopVectorize/if-conversion-nest.ll
M llvm/test/Transforms/LoopVectorize/if-conversion.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-2.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-pred-stores.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization-2.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/loop-scalars.ll
M llvm/test/Transforms/LoopVectorize/multiple-address-spaces.ll
M llvm/test/Transforms/LoopVectorize/non-const-n.ll
M llvm/test/Transforms/LoopVectorize/phi-cost.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-cond.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
M llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
M llvm/test/Transforms/LoopVectorize/reduction.ll
M llvm/test/Transforms/LoopVectorize/runtime-check.ll
M llvm/test/Transforms/LoopVectorize/scalable-inductions.ll
M llvm/test/Transforms/LoopVectorize/scalar_after_vectorization.ll
M llvm/test/Transforms/LoopVectorize/store-shuffle-bug.ll
M llvm/test/Transforms/LoopVectorize/trunc-reductions.ll
M llvm/test/Transforms/LoopVectorize/vector-geps.ll
Log Message:
-----------
[LV][NFC] Remove almost all remaining instcombine passes in RUN lines (#213067)
Commit: 4120b5f5a3770cea9b26063eaca3d18153307961
https://github.com/llvm/llvm-project/commit/4120b5f5a3770cea9b26063eaca3d18153307961
Author: Yingying Wang <3171290993 at qq.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
A llvm/test/CodeGen/RISCV/frame-base-addr-reuse.mir
M llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv32.mir
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/zdinx-large-spill.mir
Log Message:
-----------
[RISCV] Deduplicate frame base address materializations for large stack frames (#211748)
For large stack frames, `eliminateFrameIndex` materializes the frame
base with a `LUI+ADD` sequence for every frame index access. When
multiple accesses share the same 4096-aligned base, this generates
redundant `LUI+ADD` sequences that `MachineLateInstrsCleanup` cannot
eliminate because it operates on individual instructions.
Introduce `PseudoAddUpperImm` to represent the `LUI+ADD` sequence as a
single pseudo instruction during frame index elimination. This enables
`MachineLateInstrsCleanup` to CSE identical frame base computations
within a basic block. The pseudo is expanded back to `LUI+ADD` in
`RISCVPostRAExpandPseudo`.
This patch improves SPEC CPU2026 `cactus` performance by 18% on the
SpaceMit K3 processor.
### Example
Before :
```assembly
lui a0, 4
add a0, a0, sp
fsd fa3, -1976(a0)
lui a0, 4 # redundant
add a0, a0, sp # redundant
ld s10, -160(a0)
```
After :
```assembly
lui a0, 4
add a0, a0, sp
fsd fa3, -1976(a0)
ld s10, -160(a0) # reuses a0
```
Commit: 6f9c189f738d47c7ad80f6bdf928fea441bfa8d6
https://github.com/llvm/llvm-project/commit/6f9c189f738d47c7ad80f6bdf928fea441bfa8d6
Author: Jakob Koschel <jakobkoschel at google.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M compiler-rt/lib/ubsan/ubsan_checks.inc
M compiler-rt/lib/ubsan/ubsan_handlers.cpp
M compiler-rt/lib/ubsan/ubsan_handlers_cxx.cpp
M compiler-rt/test/cfi/anon-namespace.cpp
M compiler-rt/test/cfi/bad-cast.cpp
M compiler-rt/test/cfi/base-derived-destructor.cpp
M compiler-rt/test/cfi/cross-dso-diagnostic.cpp
M compiler-rt/test/cfi/cross-dso/icall/diag.cpp
M compiler-rt/test/cfi/cross-dso/icall/icall-from-dso.cpp
M compiler-rt/test/cfi/cross-dso/icall/icall.cpp
M compiler-rt/test/cfi/cross-dso/simple-fail.cpp
M compiler-rt/test/cfi/cross-dso/target_out_of_bounds.cpp
M compiler-rt/test/cfi/icall/bad-signature.c
M compiler-rt/test/cfi/mfcall.cpp
M compiler-rt/test/cfi/multiple-inheritance.cpp
M compiler-rt/test/cfi/nvcall.cpp
M compiler-rt/test/cfi/overwrite.cpp
M compiler-rt/test/cfi/simple-fail.cpp
M compiler-rt/test/cfi/target_uninstrumented.cpp
M compiler-rt/test/cfi/vdtor.cpp
Log Message:
-----------
[ubsan] Report specific CFI checks in UBSan summaries (#213224)
Instead of reporting generic `cfi-bad-type` in UBSan summaries for CFI
failures, report the specific CFI check kind (e.g., `cfi-vcall`,
`cfi-nvcall`, `cfi-icall`, `cfi-mfcall`, `cfi-derived-cast`,
`cfi-unrelated-cast`).
This is done by splitting CFIBadType into specific error types in
ubsan_checks.inc, and updating the handlers to report the appropriate
ErrorType based on the check kind. The suppression flag name for all of
them remains `cfi` to maintain backward compatibility.
Also replaces cfi-bad-type expectations in the existing tests.
Assisted-by: Automated tooling, human reviewed.
Commit: 5808b2d513d1baa3355d078193006ab9384a4ee3
https://github.com/llvm/llvm-project/commit/5808b2d513d1baa3355d078193006ab9384a4ee3
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/test/CodeGen/SPIRV/atomicrmw-uinc-udec-wrap.ll
Log Message:
-----------
[SPIR-V] Expand atomicrmw nand through compare-exchange (#213217)
Commit: ed0b5c0a428202f29f1477f1dbc31c1ab6083341
https://github.com/llvm/llvm-project/commit/ed0b5c0a428202f29f1477f1dbc31c1ab6083341
Author: Sean Clarke <sclarke at tenstorrent.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
A llvm/test/Transforms/LoopIdiom/cyclic-redundancy-check-memoryssa.ll
Log Message:
-----------
[LoopIdiom] Update MemorySSA when optimizing CRC with lookup table (#213054)
Although the lookup table optimization of CRC loops inserts a `load`
instruction, MemorySSA is not properly updated, and is oblivious to the
new memory access. Insert a memory use immediately after creating the
`load` instruction, and verify MemorySSA at the end of the optimization
if applicable.
Commit: 55418a582c8ced243b4a6eda9b9d7280499af56c
https://github.com/llvm/llvm-project/commit/55418a582c8ced243b4a6eda9b9d7280499af56c
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/include/llvm/Target/GenericOpcodes.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-region.mir
M llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
Log Message:
-----------
GlobalISel: Don't use GISelMatchGenericTypes for floating point opcodes (#212814)
With GISelMatchGenericTypes, AMDGPU had the same input pattern for
G_ATOMICRMW_FADD that checks for v2s16, so the one that is first
in the tablegen table always fires (it was v2f16 in this case).
Should explicitly check for v2f16/v2bf16.
Commit: 81cd5b6217f12ada97e0f1791ba8545120c13230
https://github.com/llvm/llvm-project/commit/81cd5b6217f12ada97e0f1791ba8545120c13230
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M lldb/source/Utility/Args.cpp
M lldb/test/API/commands/register/register_command/TestRegisters.py
Log Message:
-----------
[lldb] Convert generic register names in a case insensitive way (#213001)
Part of #212778.
There are 3 types of register name:
* The primary name, displayed by default.
* An optional alias, for example AArch64 "lr" is also "x30".
* Generic convenience names like "sp", "ra" and so on.
The first two types are handled case insensitively, but generic names
were not. For example:
(lldb) register read RA
error: Invalid register name 'RA'
(lldb) register read ra
lr = 0x0000fffff7e27400
In this change I've fixed that.
This does close a workaround for #212778, where you could get to the
actual x86_64 "sp" by using "sP". However, this is only known to work on
Linux, and other architectures are negatively impacted by the bug so I'm
fixing it.
Commit: 303ec27d8b231f9fb3078333894fe9813761e566
https://github.com/llvm/llvm-project/commit/303ec27d8b231f9fb3078333894fe9813761e566
Author: antoine moynault <antoine.moynault at linaro.org>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/include/llvm/ProfileData/SampleProfReader.h
M llvm/lib/Transforms/IPO/SampleProfile.cpp
M llvm/lib/Transforms/IPO/SampleProfileMatcher.cpp
M llvm/unittests/ProfileData/SampleProfTest.cpp
Log Message:
-----------
Revert "[ProfileData] Implement contains in SampleProfileNameTable (NFC)" (#213231)
Reverts llvm/llvm-project#211995
Broke arm 32-bit buildbots (narrowing conversion uint64_t -> size_t)
Commit: 9621bedd8a7a09c5e48a12697ff2d0463067e341
https://github.com/llvm/llvm-project/commit/9621bedd8a7a09c5e48a12697ff2d0463067e341
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M lldb/include/lldb/Core/Module.h
M lldb/source/Core/Module.cpp
Log Message:
-----------
[lldb] Only preload a Module's symbols once (#213094)
Creating several targets for the same file concurrently could deadlock.
Targets share Module objects. Therefore, each concurrent
`SBDebugger::CreateTarget()` call creates a `PreloadSymbols()` task for
the *same* Module. The thread pool running those tasks can pick up a
duplicate preload task for the same Module. The mutex used by the Module
is recursive, so the thread starts the task again, enters the same
`std::call_once` and deadlocks.
Preloading only needs to happen once: it does work taht a later lookup
would do anyway. If it's already in progress, skip it. This deduplicate
the task that causes the deadlock.
At desk, this fixes a timeout in
`api/multiple-targets/TestMultipleTargets.py`, roughly 1/40 runs. To
reproduce the issue, I shrunk the thread pool to 2 threads, which makes
it always timeout.
Commit: dcce9de575fdb9f652f38c2ba1b62f4a4da66515
https://github.com/llvm/llvm-project/commit/dcce9de575fdb9f652f38c2ba1b62f4a4da66515
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.td
M clang/test/CodeGen/amdgpu-builtin-is-invocable.c
M clang/test/CodeGen/amdgpu-builtin-processor-is.c
M clang/test/CodeGenCXX/dynamic-cast-address-space.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx13.cl
A clang/test/SemaOpenCL/builtins-amdgcn-cvt-sr-pk-bf16-f32-err.cl
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.pk.bf16.ll
M llvm/test/MC/AMDGPU/gfx950-unsupported.s
Log Message:
-----------
AMDGPU: Give v_cvt_sr_pk_bf16_f32 its own subtarget feature (#213150)
v_cvt_sr_pk_bf16_f32 was gated on bf16-cvt-insts, but that feature is
also present on gfx950 where the (non-sr) v_cvt_pk_bf16_f32 was first
added. The stochastic-rounding v_cvt_sr_pk_bf16_f32 was only added
for gfx1250 and has no gfx950 encoding, so it would mis-select and
later hit the "Invalid opcode" assert. Introduce
cvt-sr-pk-bf16-f32-inst, currently added to gfx13 and 125*
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: 275365f4f94a6e66b933d3d62cb62ac081daa3a9
https://github.com/llvm/llvm-project/commit/275365f4f94a6e66b933d3d62cb62ac081daa3a9
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
Log Message:
-----------
GlobalISel: Fix lowerMergeValues when dst type is float (#212795)
Lowering is done in the integer domain. Similar to the type
mismatch when dst is a pointer, make a bitcast when dst is float.
Commit: 81a8451de62458a29dd5cef6d0c52d0a6271ca30
https://github.com/llvm/llvm-project/commit/81a8451de62458a29dd5cef6d0c52d0a6271ca30
Author: yingopq <115543042+yingopq at users.noreply.github.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsCallingConv.td
M llvm/lib/Target/Mips/MipsRegisterInfo.cpp
A llvm/test/CodeGen/Mips/write_register_gp.ll
Log Message:
-----------
[Mips] Fix $gp was restored when used as global register variable (#201778)
The function `eliminateDeadMI` would check `if (MRI.isReserved(Reg))`,
now we only set GP to reserved when `!Subtarget.isABICalls()`. So
`eliminateDeadMI` delete the `move $gp, $4`. And we would restore $gp
after instr selection through `$gp_64 = LD $sp_64, 8`.
Check the module metadata `llvm.named.register.$28` to detect if $28 is
used as global register. Then append new conditon when set $gp to
reserverd status and return CalleeSavedRegs without $gp.
Fix #176546.
Commit: ea56c331a6afe1334eb3ce3b1bf9974079fb79c3
https://github.com/llvm/llvm-project/commit/ea56c331a6afe1334eb3ce3b1bf9974079fb79c3
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/LocalStackSlotAllocation.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/OptimizePHIs.cpp
M llvm/lib/CodeGen/StackColoring.cpp
M llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/diverged-entry-basic-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/diverged-entry-basic.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_cond.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
M llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-usub_cond.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-usub_sat.ll
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/issue130120-eliminate-frame-index.ll
M llvm/test/CodeGen/AMDGPU/issue139317-bad-opsel-reg-sequence-fold.ll
M llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
M llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
M llvm/test/CodeGen/AMDGPU/memset-pattern.ll
M llvm/test/CodeGen/AMDGPU/sgpr-scavenge-fi-stack-id.ll
M llvm/test/CodeGen/AMDGPU/structurize-hoist.ll
M llvm/test/CodeGen/AMDGPU/valu-i1.ll
M llvm/test/CodeGen/ARM/O3-pipeline.ll
M llvm/test/CodeGen/LoongArch/jr-without-ra.ll
M llvm/test/CodeGen/LoongArch/opt-pipeline.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
M llvm/test/CodeGen/SPIRV/llc-pipeline.ll
M llvm/test/CodeGen/Thumb2/mve-blockplacement.ll
M llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
M llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll
M llvm/test/CodeGen/X86/2011-09-14-valcoalesce.ll
Log Message:
-----------
[MachineLICM] Use `RegisterClassInfo::getRegPressureSetLimit` (#211715)
This recommits #119826, which taught `MachineLICM` to use
`RegisterClassInfo` when computing register pressure limits so
reserved registers are accounted for (#118787).
The original change was reverted by eeac0ff because it increased
compile time by causing repeated `RegisterClassInfo` computations.
This PR is based on #210826, in which `MachineRegisterClassInfo`
analysis pass was added. `MachineRegisterClassInfo` is required
by `MachineLICM` now, but the intervening machine passes that do
not affect `RegisterClassInfo` now preserve it, so the analysis
is reused instead of recomputed.
Assisted-by: TRAE CLI (GPT-5.5)
Commit: 81f89bb526ce322cb4c29196e3c29472bad32e65
https://github.com/llvm/llvm-project/commit/81f89bb526ce322cb4c29196e3c29472bad32e65
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-wide-add.ll
M llvm/test/CodeGen/AArch64/vector-absolute-difference.ll
Log Message:
-----------
[LLVM][CodeGen][SVE] Use pairwise instruction for partial_reduce_[s/u]mla. (#212772)
Commit: 136347be7aac1614000a9072d794d91ca16aa4f1
https://github.com/llvm/llvm-project/commit/136347be7aac1614000a9072d794d91ca16aa4f1
Author: Manasij Mukherjee <manasijm at nvidia.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
Log Message:
-----------
[TableGen] Speed up intrinsic lookups with DenseMap (NFC) (#213198)
Store in DenseMap, avoids linear lookups.
Speeds up NVPTX -gen-dag-isel and -gen-instr-info by 10%.
RISCV shows similar gains.
Neutral or marginally beneficial for other targets.
Commit: 8db13de265a5f12d49147930da6d16a3ad7b40e3
https://github.com/llvm/llvm-project/commit/8db13de265a5f12d49147930da6d16a3ad7b40e3
Author: Luke Lau <luke at igalia.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Remove redundant x && (y && x) -> x && y combine (#213219)
It can be subsumed by making the combine above commutative. In theory
this isn't NFC as it changes the order, in practice it doesn't make a
difference.
Commit: 6ebd9e1a12235fdc42e3e7b157678e6711af9c62
https://github.com/llvm/llvm-project/commit/6ebd9e1a12235fdc42e3e7b157678e6711af9c62
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/RTBridge/Calls.h
M llvm/include/llvm/ExecutionEngine/Orc/RTBridge/SPS/Calls.h
M llvm/unittests/ExecutionEngine/Orc/SPSCallersTest.cpp
Log Message:
-----------
[ORC] Add VoidVoid and IntVoid Callers, with tests. (#213211)
Add rt::VoidVoidCaller (void()) and rt::IntVoidCaller (int64_t())
runtime-agnostic interfaces and their rt::sps implementations, targeting
the orc_rt_ci_sps_call_void_void and orc_rt_ci_sps_call_int_void
controller-interface wrappers. Both are experimental and may be removed.
Extend SPSCallersTest to cover the new callers. VoidVoidCaller is the
first caller instantiated with a void result type, which exposed a
latent bug in sps::Caller::callAsync: its result handler declared a
CalleeRetT parameter, ill-formed when CalleeRetT is void. It now
special-cases void via `if constexpr`.
Commit: 5aec353bd686dbca51755e772971c65ee6ae70f6
https://github.com/llvm/llvm-project/commit/5aec353bd686dbca51755e772971c65ee6ae70f6
Author: Folkert de Vries <folkert at folkertdev.nl>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/test/CodeGen/PowerPC/copysignl.ll
Log Message:
-----------
[NFC][PowerPC] add more `copysign` tests (#213236)
Commit: 090b6569b6ed5cabfc84284542c5ce8b51735015
https://github.com/llvm/llvm-project/commit/090b6569b6ed5cabfc84284542c5ce8b51735015
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M libcxx/include/__memory/array_cookie.h
M libcxx/include/__memory/unique_ptr.h
M libcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.class/unique.ptr.observers/assert.subscript.pass.cpp
Log Message:
-----------
[libc++] Make __has_array_cookie a variable template (#212767)
Using variable templates is slightly faster to compile and more
readable, so we might as well use them.
Commit: e147e5b7d029651554c24ecaaa4086a7cc74e90a
https://github.com/llvm/llvm-project/commit/e147e5b7d029651554c24ecaaa4086a7cc74e90a
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M libcxx/include/__atomic/clear_padding.h
Log Message:
-----------
[libc++] Simplify clear_padding.h a bit (#212426)
Commit: 3a809f644c863a17ac665e19d7dcbf7209688d18
https://github.com/llvm/llvm-project/commit/3a809f644c863a17ac665e19d7dcbf7209688d18
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M libcxx/test/libcxx/clang_tidy.sh.py
A libcxxabi/.clang-tidy
Log Message:
-----------
[libc++abi] Add a clang-tidy config and test (#207324)
This essentially copies the `.clang-tidy` file from libc++ into
libc++abi, except that the naming conventions are updated to not add
underscores and some checks are disabled that don't pass currently. They
will be fixed in follow-ups.
Commit: bcddf2a29177380c62481ee25362064f99ff07d3
https://github.com/llvm/llvm-project/commit/bcddf2a29177380c62481ee25362064f99ff07d3
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/reduction-fadd-reassoc.ll
Log Message:
-----------
[SLP][NFC]Add some extra tests for reductions, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/213257
Commit: 0a1f0aafed6dfce910e18090bfd408838b9a727a
https://github.com/llvm/llvm-project/commit/0a1f0aafed6dfce910e18090bfd408838b9a727a
Author: PushkarSingh <149073046+iitianpushkar at users.noreply.github.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/include/clang/Analysis/AnyCall.h
A clang/unittests/Analysis/AnyCallTest.cpp
M clang/unittests/Analysis/CMakeLists.txt
Log Message:
-----------
[clang][Analysis] Add argument accessors to clang::AnyCall (#212934)
Add APIs to `clang::AnyCall` for accessing expression-backed call
arguments.
`AnyCall` already exposes formal parameters through `parameters()`,
`param_begin()`, `param_end()`, `param_size()`, and `param_empty()`.
This adds the corresponding argument-side helpers:
- `arguments()`
- `arg_begin()`
- `arg_end()`
- `arg_size()`
- `arg_empty()`
- `getArg()`
This lets clients reuse `AnyCall` for callee/argument inspection instead
of
open-coding argument extraction.
Prequel PR to #206337
Commit: e44068cc129912c88dcdeae0d1b5dc5937eb1059
https://github.com/llvm/llvm-project/commit/e44068cc129912c88dcdeae0d1b5dc5937eb1059
Author: Karim Alweheshy <karim.alweheshy at gmail.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M lld/MachO/ObjC.cpp
M lld/test/MachO/objc-category-merging-minimal.s
M lld/test/MachO/objc-category-merging-swift.s
Log Message:
-----------
[lld][MachO] Preserve class-address addends in ObjC category merging (#211431)
Mach-O category merging can encounter Swift class references as an
enclosing
metadata symbol plus a non-zero addend after LTO removes the exact
class-address alias. For example, a category can refer to a `CMf` symbol
plus
the offset of the class object within that metadata record.
`tryGetSymbolAtIsecOffset()` previously resolved such a relocation to
the
enclosing symbol and discarded the residual addend. `getClassRo()` then
read
the class layout at the wrong address. For valid Swift metadata this can
return
null; before the defensive check in the first commit the linker
dereferenced
that result and crashed, while the check alone safely skipped a category
that
could have been merged.
Preserve the class reference as a symbol and residual addend throughout:
- category grouping;
- class and metaclass RO-data lookup;
- source-language detection; and
- relocations synthesized for merged categories.
An exact symbol at the target address is still preferred. When no exact
alias
survives, retain the offset from the closest containing symbol. The
defensive
checks remain in place for genuinely incomplete or unsupported metadata.
The Swift regression now omits the exact class-address alias and points
the
category classlist directly into the enclosing metadata record, matching
the
shape observed after ThinLTO.
Testing:
- Release + assertions AArch64 LLVM/LLD build
- focused `llvm-lit` coverage for the alias-free Swift metadata and
missing-metadata cases
- full Swift 6 application link with `-objc_category_merging`
The application result is integration evidence for correctness and
folding
coverage
Commit: a6a1cb05d247f1fc4414bb6d789f390b2554eac7
https://github.com/llvm/llvm-project/commit/a6a1cb05d247f1fc4414bb6d789f390b2554eac7
Author: Sergey Semenov <sergey.semenov at intel.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M libsycl/src/detail/global_objects.hpp
Log Message:
-----------
[libsycl] Add missing header include to global_objects.hpp (#213020)
Fixes a build error observed on Windows.
Commit: c29bcd45ddd96c5d3ea0d5f7de051b5174966a3b
https://github.com/llvm/llvm-project/commit/c29bcd45ddd96c5d3ea0d5f7de051b5174966a3b
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M lldb/source/Plugins/Platform/Windows/PlatformWindows.cpp
Log Message:
-----------
[lldb][Windows] Don't cut the loader helper off after 250ms (#213010)
`LoadLibraryW` runs on the debuggee with a timeout of 250ms (the
default). On a loaded machine (in CI), this timeout is reached quite
often, causing tests failures.
This patch gives both loader helpers an explicit timeout of 5s (clamped
to half the overall timeout so the two stay consistent).
Commit: e84daa62201acd161c6b77375eb26d0b0ac63ed2
https://github.com/llvm/llvm-project/commit/e84daa62201acd161c6b77375eb26d0b0ac63ed2
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/session_helpers.py
M lldb/test/API/tools/lldb-dap/console/TestDAP_console.py
M lldb/test/API/tools/lldb-dap/console/TestDAP_redirection_to_console.py
M lldb/test/API/tools/lldb-dap/restart/TestDAP_restart.py
M lldb/test/API/tools/lldb-dap/restart/TestDAP_restart_console.py
Log Message:
-----------
[lldb-dap] Migrate console and restart tests (#213019)
Migrated Tests
- TestDAP_console.py
- TestDAP_redirection_to_console.py
- TestDAP_restart.py
- TestDAP_restart_console.py
Commit: b4efecb0379353d51a172209193e500b6cb2a0f2
https://github.com/llvm/llvm-project/commit/b4efecb0379353d51a172209193e500b6cb2a0f2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx13.cl
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.msad.u8.ll
Log Message:
-----------
AMDGPU: Add missing msad-insts to gfx13 frontend feature map (#213122)
fillAMDGCNFeatureMap omitted msad-insts for gfx1310/gfx13-generic, so
clang wrongly rejected __builtin_amdgcn_msad_u8 on those targets even
though the backend enables the feature (FeatureGFX9 generation,
inherited through FeatureGFX13). Add it to the gfx13 case.
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: 3f9b96996cac75b960adf84f5722afe48c20b480
https://github.com/llvm/llvm-project/commit/3f9b96996cac75b960adf84f5722afe48c20b480
Author: Zmicier Prybysh <zprybysh at baylibre.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/ConvertConv2DToImg2Col.cpp
M mlir/test/Dialect/Linalg/convert-conv2d-to-img2col.mlir
Log Message:
-----------
[mlir][linalg] Support non-unit dilations in im2col decomposition (#208424)
The im2col patterns for conv_2d_nhwc_hwcf, conv_2d_nchw_fchw and
conv_2d_nhwc_fhwc avoided non-unit dilations, but the restriction
doesn't seem to be fundamental: dilation only affects the gather step,
which can fold it into its indexing map. Generalize the convolved index
expression from `oh * stride + fh` to `oh * stride + fh * dilation` and
drop the match failures.
Verified by comparing the results of a dilated convolution lowered
directly to loops against the im2col decomposition with mlir-runner.
Assisted-By: Claude Code (for generating tests).
Commit: 2f30bd168ccb47a82a25faba92cae4d6d0b47f0d
https://github.com/llvm/llvm-project/commit/2f30bd168ccb47a82a25faba92cae4d6d0b47f0d
Author: Michael G. Kazakov <mike.kazakov at gmail.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M libcxx/test/std/algorithms/alg.nonmodifying/alg.adjacent.find/pstl.adjacent_find.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.adjacent.find/pstl.adjacent_find_pred.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.find.first.of/pstl.find_first_of.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.find.first.of/pstl.find_first_of_pred.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/mismatch/pstl.mismatch.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/mismatch/pstl.mismatch_pred.pass.cpp
Log Message:
-----------
[libc++][NFC] Make size_t -> int conversions explicit in a few PSTL tests (#213145)
The implicit truncating conversions that were introduced in some PSTL
tests are causing warnings on MSVC. This PR fixes that.
See
https://github.com/llvm/llvm-project/pull/212366#discussion_r3679252259
for more details.
Commit: 4dc60bbb98a8531841383c51a1b7e65a0ec1d05e
https://github.com/llvm/llvm-project/commit/4dc60bbb98a8531841383c51a1b7e65a0ec1d05e
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/tools/llvm-calc-occupancy/CMakeLists.txt
Log Message:
-----------
[Build] Fix llvm-calc-occupancy link errors when using LLVM_LINK_LLVM_DYLIB. (#213262)
Commit: 95ee221ea8fade17576845f12df8c2cd26f85aa5
https://github.com/llvm/llvm-project/commit/95ee221ea8fade17576845f12df8c2cd26f85aa5
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
R flang/docs/FIRArrayOperations.md
M flang/docs/HighLevelFIR.md
M flang/docs/ReleaseNotes.md
M flang/docs/index.md
M flang/include/flang/Optimizer/Builder/MutableBox.h
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/test/Fir/fir-ops.fir
M flang/test/Fir/invalid.fir
M flang/test/HLFIR/inline-elemental.fir
M flang/test/Transforms/loop-versioning.fir
M flang/test/Transforms/simplifyintrinsics.fir
Log Message:
-----------
[flang] Delete the legacy array-value operations from FIR (#213159)
Nothing in flang has produced fir.array_load, fir.array_fetch,
fir.array_update, fir.array_modify, fir.array_access, fir.array_amend,
or fir.array_merge_store since the legacy (non-HLFIR) expression
lowering was deleted (#210385, #210621, #210639, #210873), and the
array-value-copy pass that legalized them is gone (#211816, #212643).
Delete the operations and the surface that existed only for them:
- FIROps.td: the "Array value operations" section including the
copy-in/copy-out design comment; FIROps.cpp: the ops verifiers, effects
and getExtents. fir.array_coor is unrelated and stays, as does the
validTypeParams helper shared with fir.pack_array.
- Tests: the ops roundtrip/verifier blocks in fir-ops.fir and
invalid.fir; scaffolding rewrites in inline-elemental.fir (store via
hlfir.designate; hlfir.apply-in-do_loop coverage preserved),
loop-versioning.fir @test4 (the versioned loops are untouched), and
simplifyintrinsics.fir (inert copy-back loops dropped; no CHECK lines
affected).
- Docs: FIRArrayOperations.md (+ the index.md toctree line); past-tense
updates in HighLevelFIR.md; a stale comment in MutableBox.h; a
release-note entry recording the removal for downstream projects.
FIRLangRef is generated from FIROps.td and follows automatically.
Assisted-by: AI
Commit: 315bbbc18c45079bab55575325b4d4f79aa9a4cd
https://github.com/llvm/llvm-project/commit/315bbbc18c45079bab55575325b4d4f79aa9a4cd
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
M llvm/utils/gn/secondary/llvm/test/BUILD.gn
A llvm/utils/gn/secondary/llvm/tools/llvm-calc-occupancy/BUILD.gn
Log Message:
-----------
[gn] port b11722f1d3bd5de (llvm-calc-occupancy) (#213266)
Commit: f79a8888eb831238423362d004739683e2a20d93
https://github.com/llvm/llvm-project/commit/f79a8888eb831238423362d004739683e2a20d93
Author: Zorojuro <sawantsukumar at gmail.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M libc/src/__support/FPUtil/CMakeLists.txt
M libc/src/__support/FPUtil/dyadic_float.h
M libc/src/__support/FPUtil/float128.h
M libc/test/src/__support/FPUtil/float128_test.cpp
Log Message:
-----------
[libc] Fix float128-to-integer conversion UB (#211593)
https://github.com/llvm/llvm-project/pull/200565#discussion_r3643991194
Fixes the recent issue pointed out in the above comment
about undefined behavior for float128 in the case of extremely large
values and extremely small values.
Commit: f5ffd86a9bd6dd9327669448c3b604ce9b658941
https://github.com/llvm/llvm-project/commit/f5ffd86a9bd6dd9327669448c3b604ce9b658941
Author: Nerixyz <nerixdev at outlook.de>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M lldb/source/Symbol/Variable.cpp
M lldb/test/API/functionalities/scripted_frame_provider/TestScriptedFrameProvider.py
Log Message:
-----------
[lldb] Treat synthetic variables as always in scope (#204177)
When the variables in scope are requested, synthetic variables wouldn't
be returned, because `Variable::IsInScope` would return false. With this
PR, we return true for synthetic variables.
There's still one inconsistency between `frame var` and
`SBFrame::GetVariables` where `frame var` shows "re-exported" variables
from real frames (here: `variable_in_main`). Note that
`IsSyntheticValueType` returns false for `variable_in_main`.
Commit: 5df5e8d9fd6386d99c37cb72ea92c99819c801bc
https://github.com/llvm/llvm-project/commit/5df5e8d9fd6386d99c37cb72ea92c99819c801bc
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
A llvm/test/CodeGen/AMDGPU/arbitrary-fp-from-float-fp8-f16-hw.ll
A llvm/test/CodeGen/AMDGPU/arbitrary-fp-to-float-fp8-hw.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.mir
M llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
Log Message:
-----------
[AMDGPU] Add custom lowering of llvm.convert.from.arbitrary.fp for FP8 (#194144)
Map conversions from FP8 source formats to v_cvt_{,pk_}f32_{fp8,bf8} and v_cvt_{pk_}f16_{fp8,bf8} HW instructions.
Commit: d73beb2ee622eb1aaa13a4bdbe25799031f647f8
https://github.com/llvm/llvm-project/commit/d73beb2ee622eb1aaa13a4bdbe25799031f647f8
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/Builder/FIRBuilder.h
R flang/include/flang/Optimizer/Builder/Runtime/Ragged.h
M flang/include/flang/Runtime/ragged.h
M flang/lib/Optimizer/Builder/CMakeLists.txt
M flang/lib/Optimizer/Builder/FIRBuilder.cpp
R flang/lib/Optimizer/Builder/Runtime/Ragged.cpp
R flang/unittests/Optimizer/Builder/Runtime/RaggedTest.cpp
M flang/unittests/Optimizer/CMakeLists.txt
Log Message:
-----------
[flang] Delete the unused ragged-array runtime builders (#213160)
The ragged-array machinery served the legacy FORALL mask temporaries,
whose lowering was removed with the legacy expression lowering (#210639,
#210873) and the array-value-copy pass (#212643). The builders
(fir::runtime::genRaggedArrayAllocate/Deallocate) and the
getRaggedArrayHeaderType helper have no compiler callers left; only
their own unit test exercised them. Delete the builders, the helper, and
the unit test.
The flang-rt runtime entry points
(RaggedArrayAllocate/RaggedArrayDeallocate in
flang-rt/lib/runtime/ragged.cpp and their declarations in
flang/include/flang/Runtime/ragged.h) are ABI and remain.
Assisted-by: AI
Commit: f6b3f9399e98ef8b79388176e94c910d67669e1f
https://github.com/llvm/llvm-project/commit/f6b3f9399e98ef8b79388176e94c910d67669e1f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
DAG: Use poison for some load/store offsets in legalizer (#167756)
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 7d5dd438b286d4812a8d2e753262cb6db1c3be51
https://github.com/llvm/llvm-project/commit/7d5dd438b286d4812a8d2e753262cb6db1c3be51
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/struct_ucred.h
M libc/include/sys/socket.yaml
Log Message:
-----------
[libc] Add 'struct ucred' definition. (#213152)
This is a Linux extension that allows to obtain credentials of a peer
process connected to a socket, e.g. via passing `SO_PEERCRED` to
`getsockopt` function.
Commit: c325d6fcb6db298f681ae1c450b89b4c255fb3ce
https://github.com/llvm/llvm-project/commit/c325d6fcb6db298f681ae1c450b89b4c255fb3ce
Author: Bryth <matteo.rizza-murgier at sipearl.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M mlir/test/Dialect/Complex/canonicalize.mlir
Log Message:
-----------
[mlir][complex] Fix canonicalize tests (#213259)
Remove trailing spaces and double line breaks, fix variable
re-definitions, make variables match regex consistent.
Commit: fd7993ea2dcc76f915da1baf1b36f5cd560722a8
https://github.com/llvm/llvm-project/commit/fd7993ea2dcc76f915da1baf1b36f5cd560722a8
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/aarch64/headers.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/riscv/headers.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/config/linux/x86_64/headers.txt
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-macros/CMakeLists.txt
M libc/include/llvm-libc-macros/linux/CMakeLists.txt
A libc/include/llvm-libc-macros/linux/sys-statfs-macros.h
A libc/include/llvm-libc-macros/sys-statfs-macros.h
A libc/include/sys/statfs.yaml
M libc/src/sys/CMakeLists.txt
A libc/src/sys/statfs/CMakeLists.txt
A libc/src/sys/statfs/fstatfs.h
A libc/src/sys/statfs/linux/CMakeLists.txt
A libc/src/sys/statfs/linux/fstatfs.cpp
A libc/src/sys/statfs/linux/statfs.cpp
A libc/src/sys/statfs/statfs.h
M libc/test/src/sys/CMakeLists.txt
A libc/test/src/sys/statfs/CMakeLists.txt
A libc/test/src/sys/statfs/linux/CMakeLists.txt
A libc/test/src/sys/statfs/linux/fstatfs_test.cpp
A libc/test/src/sys/statfs/linux/statfs_test.cpp
Log Message:
-----------
[libc] Add <sys/statfs.h> header and entrypoints. (#213108)
Implement `statfs` and `fstatfs` functions on Linux.
We already have `struct statfs` and syscall wrappers defined (to
implement POSIX `<sys/statvfs.h>`). Use them to provide Linux-specific
functions as well.
Commit: 8719d58faf6fb5780bf44fc89df72c951f381f5b
https://github.com/llvm/llvm-project/commit/8719d58faf6fb5780bf44fc89df72c951f381f5b
Author: Sean Clarke <sclarke at tenstorrent.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
M llvm/test/Transforms/LoopIdiom/cyclic-redundancy-check.ll
Log Message:
-----------
[LoopIdiom] Fix miscompile for big-endian sub-byte CRC (#213040)
The Sarwate lookup table optimization shifts the top bits of the
`Indexer` down to the low byte before indexing into the table. Though
uncommon, if the CRC has a sub-byte width, the top bits of `Indexer`
must be shifted *up* to align with the low byte, but this is never
accounted for. Shift `Indexer` either right *or* left depending on CRC
bitwidth.
Commit: 7f29fbaf52b123ddb80745b17df2e73a39006afd
https://github.com/llvm/llvm-project/commit/7f29fbaf52b123ddb80745b17df2e73a39006afd
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M .github/CODEOWNERS
M bolt/include/bolt/Core/DebugData.h
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Core/DIEBuilder.cpp
M bolt/lib/Core/DebugData.cpp
M bolt/lib/Rewrite/DWARFRewriter.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/test/AArch64/constant_island_pie_update.s
M clang-tools-extra/clangd/unittests/PreambleTests.cpp
M clang/Maintainers.md
M clang/cmake/caches/Fuchsia-stage2.cmake
M clang/docs/ClangFormatStyleOptions.rst
M clang/docs/ReleaseNotes.md
M clang/include/clang/AST/StmtOpenMP.h
M clang/include/clang/Analysis/AnyCall.h
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/BuiltinsAMDGPU.td
M clang/include/clang/Basic/BuiltinsAMDGPUDocs.td
M clang/include/clang/Basic/DiagnosticCommonKinds.td
M clang/include/clang/Basic/DiagnosticLexKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/HLSLIntrinsics.td
A clang/include/clang/CIR/CIRDataLayoutSpec.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRDialect.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Dialect/IR/CIRTypeConstraints.td
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
M clang/include/clang/CIR/Interfaces/CIROpInterfaces.h
M clang/include/clang/CIR/Interfaces/CIROpInterfaces.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Format/Format.h
M clang/include/clang/Lex/PPCallbacks.h
M clang/include/clang/Lex/Preprocessor.h
M clang/include/clang/Parse/Parser.h
M clang/include/clang/StaticAnalyzer/Core/BugReporter/BugReporterVisitors.h
M clang/include/clang/StaticAnalyzer/Core/BugReporter/Z3CrosscheckVisitor.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/CoreEngine.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/ExprEngine.h
M clang/include/clang/Tooling/DependencyScanningTool.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Record.cpp
M clang/lib/AST/ByteCode/Record.h
M clang/lib/AST/Expr.cpp
M clang/lib/AST/StmtOpenMP.cpp
M clang/lib/Basic/Cuda.cpp
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/Basic/Targets/OSTargets.h
A clang/lib/CIR/CodeGen/CIRDataLayoutSpec.cpp
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinNVPTX.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
M clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenStmt.cpp
M clang/lib/CIR/CodeGen/CIRGenVTables.cpp
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
M clang/lib/CIR/CodeGen/CMakeLists.txt
M clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
M clang/lib/CIR/Dialect/Transforms/FlattenCFG.cpp
M clang/lib/CIR/Dialect/Transforms/GotoSolver.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CMakeLists.txt
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/lib/CodeGen/Targets/PPC.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/lib/Format/BreakableToken.cpp
M clang/lib/Format/Format.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Frontend/FrontendAction.cpp
M clang/lib/Frontend/PrintPreprocessedOutput.cpp
M clang/lib/Frontend/Rewrite/InclusionRewriter.cpp
M clang/lib/Headers/hlsl/hlsl_intrinsic_helpers.h
M clang/lib/Headers/riscv_packed_simd.h
M clang/lib/Interpreter/IncrementalParser.cpp
M clang/lib/Lex/PPDirectives.cpp
M clang/lib/Lex/PPExpressions.cpp
M clang/lib/Lex/Pragma.cpp
M clang/lib/Lex/Preprocessor.cpp
M clang/lib/Parse/ParseAST.cpp
M clang/lib/Parse/ParseHLSLRootSignature.cpp
M clang/lib/Parse/Parser.cpp
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.h
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/StaticAnalyzer/Checkers/AnalyzerStatsChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/CStringChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/LifetimeModeling.cpp
M clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/RetainCountChecker/RetainCountDiagnostics.cpp
M clang/lib/StaticAnalyzer/Checkers/UseAfterLifetimeEnd.cpp
M clang/lib/StaticAnalyzer/Checkers/VAListChecker.cpp
M clang/lib/StaticAnalyzer/Core/BugReporter.cpp
M clang/lib/StaticAnalyzer/Core/BugReporterVisitors.cpp
M clang/lib/StaticAnalyzer/Core/CoreEngine.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/lib/StaticAnalyzer/Core/Z3CrosscheckVisitor.cpp
M clang/lib/Tooling/DependencyScanningTool.cpp
M clang/test/Analysis/dangling-ptr-deref.cpp
M clang/test/Analysis/lifetime-bound.cpp
M clang/test/Analysis/string-search-modeling.c
M clang/test/CIR/CodeGen/address-space.c
A clang/test/CIR/CodeGen/arithmetic-fence-builtin.c
A clang/test/CIR/CodeGen/attr-alias-no-proto.c
A clang/test/CIR/CodeGen/attr-musttail.cpp
A clang/test/CIR/CodeGen/builtin-cpu-is-cputype.c
A clang/test/CIR/CodeGen/builtin-cpu-is-subtype.c
A clang/test/CIR/CodeGen/builtin-cpu-is-vendor.c
A clang/test/CIR/CodeGen/builtin-cpu-supports.c
A clang/test/CIR/CodeGen/call-conv-lowering-x86_64-indirect.c
M clang/test/CIR/CodeGen/complex.cpp
M clang/test/CIR/CodeGen/enum-bool.cpp
M clang/test/CIR/CodeGen/goto-address-label-table.c
A clang/test/CIR/CodeGen/goto-indirect-cleanup-nyi.c
A clang/test/CIR/CodeGen/goto-indirect-nested.c
M clang/test/CIR/CodeGen/label-values.c
M clang/test/CIR/CodeGen/pointer-to-data-member.cpp
A clang/test/CIR/CodeGen/pointer-width-32bit.cpp
A clang/test/CIR/CodeGenBuiltins/RISCV/riscv-xandesperf-rv32.c
A clang/test/CIR/CodeGenBuiltins/RISCV/riscv-xandesperf-rv64.c
M clang/test/CIR/CodeGenBuiltins/builtins-elementwise.c
M clang/test/CIR/CodeGenBuiltins/builtins-floating-point.c
M clang/test/CIR/CodeGenCUDA/builtins-nvvm-atomic.cu
M clang/test/CIR/IR/cmp.cir
M clang/test/CIR/IR/copy.cir
A clang/test/CIR/IR/fenv.cir
A clang/test/CIR/IR/goto-indirect.cir
M clang/test/CIR/IR/invalid-cast.cir
A clang/test/CIR/IR/invalid-cmp.cir
A clang/test/CIR/IR/pointer-data-layout.cir
A clang/test/CIR/Tools/pointer-width-from-triple.cir
A clang/test/CIR/Transforms/abi-lowering/indirect-call-classification-attr.cir
R clang/test/CIR/Transforms/abi-lowering/indirect-call-nyi.cir
A clang/test/CIR/Transforms/abi-lowering/indirect-call-test-target.cir
A clang/test/CIR/Transforms/abi-lowering/indirect-call.cir
M clang/test/CIR/Transforms/goto_solver.cir
M clang/test/CIR/Transforms/vector-cmp-fold.cir
A clang/test/ClangScanDeps/canonicalize-macros-multiarch.c
A clang/test/ClangScanDeps/modules-async-scan.c
A clang/test/ClangScanDeps/modules-invalid-target.c
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M clang/test/CodeGen/amdgpu-builtin-is-invocable.c
M clang/test/CodeGen/amdgpu-builtin-processor-is.c
A clang/test/CodeGenCXX/GH211943.cpp
M clang/test/CodeGenCXX/dynamic-cast-address-space.cpp
M clang/test/CodeGenHLSL/builtins/cross.hlsl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx13.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-global-load-store.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-raw-buffer-atomic-max.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-s-buffer-load.cl
M clang/test/Driver/aarch64-ptrauth.c
A clang/test/Driver/amdgpu-assembler-xnack-sramecc.s
M clang/test/Driver/amdgpu-mcpu.cl
M clang/test/Driver/flang/multiple-inputs-mixed.f90
A clang/test/Driver/flang/runtimes.f90
M clang/test/Driver/invalid-target-id.cl
M clang/test/Driver/openmp-invalid-target-id.c
M clang/test/Driver/print-supported-extensions-riscv.c
R clang/test/Frontend/linemarker-invalid-escape.c
M clang/test/Frontend/rewrite-includes.c
M clang/test/Misc/target-invalid-cpu-note/amdgcn.c
M clang/test/Misc/target-invalid-cpu-note/r600.c
M clang/test/Modules/cxx20-hu-05.cpp
M clang/test/Modules/cxx20-hu-06.cpp
A clang/test/Modules/decl-attr-merge-explicit-modules.c
A clang/test/Modules/decl-attr-merge2.c
M clang/test/OpenMP/declare_variant_construct_codegen_1.c
M clang/test/OpenMP/fuse_codegen.cpp
M clang/test/OpenMP/interchange_codegen.cpp
R clang/test/OpenMP/loop_transform_final_iv.c
M clang/test/OpenMP/requires_codegen.cpp
M clang/test/OpenMP/reverse_codegen.cpp
M clang/test/OpenMP/stripe_codegen.cpp
M clang/test/OpenMP/tile_codegen.cpp
M clang/test/Parser/cxx11-user-defined-literals.cpp
M clang/test/Preprocessor/line-directive-output.c
M clang/test/Preprocessor/line-directive.c
A clang/test/Preprocessor/pragma_set_pp_state.cpp
M clang/test/Preprocessor/riscv-target-features.c
M clang/test/Sema/darwin-tls.c
M clang/test/SemaCXX/libstdcxx_format_kind_hack.cpp
M clang/test/SemaHLSL/Availability/avail-diag-default-compute.hlsl
M clang/test/SemaHLSL/BuiltIns/cross-errors.hlsl
A clang/test/SemaHLSL/Resources/Textures-derivative-availability.hlsl
A clang/test/SemaHLSL/Resources/Textures-double-element-type-errors.hlsl
A clang/test/SemaHLSL/Resources/Textures-integer-element-type.hlsl
A clang/test/SemaObjC/objc-constant-literal-dict-key-restrictions.m
A clang/test/SemaOpenCL/builtins-amdgcn-cvt-sr-pk-bf16-f32-err.cl
M clang/test/VFS/external-names-multi-overlay.c
M clang/test/VFS/fallback.c
M clang/tools/cir-translate/cir-translate.cpp
A clang/unittests/Analysis/AnyCallTest.cpp
M clang/unittests/Analysis/CMakeLists.txt
M clang/unittests/CIR/CMakeLists.txt
A clang/unittests/CIR/FenvOpTest.cpp
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/FormatTestComments.cpp
M clang/utils/perf-training/perf-helper.py
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/extenddftf2.cpp
A compiler-rt/lib/builtins/extendsfdf2.cpp
A compiler-rt/lib/builtins/extendsftf2.cpp
A compiler-rt/lib/builtins/extendxftf2.cpp
A compiler-rt/lib/builtins/truncdfsf2.cpp
A compiler-rt/lib/builtins/trunctfdf2.cpp
A compiler-rt/lib/builtins/trunctfsf2.cpp
A compiler-rt/lib/builtins/trunctfxf2.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
M compiler-rt/lib/scudo/standalone/combined.h
M compiler-rt/lib/scudo/standalone/primary32.h
M compiler-rt/lib/scudo/standalone/primary64.h
M compiler-rt/lib/scudo/standalone/tests/combined_test.cpp
M compiler-rt/lib/scudo/standalone/tests/primary_test.cpp
M compiler-rt/lib/scudo/standalone/wrappers_c.cpp
M compiler-rt/lib/tsan/go/buildgo.sh
M compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp
M compiler-rt/lib/ubsan/ubsan_checks.inc
M compiler-rt/lib/ubsan/ubsan_handlers.cpp
M compiler-rt/lib/ubsan/ubsan_handlers_cxx.cpp
M compiler-rt/test/cfi/anon-namespace.cpp
M compiler-rt/test/cfi/bad-cast.cpp
M compiler-rt/test/cfi/base-derived-destructor.cpp
M compiler-rt/test/cfi/cross-dso-diagnostic.cpp
M compiler-rt/test/cfi/cross-dso/icall/diag.cpp
M compiler-rt/test/cfi/cross-dso/icall/icall-from-dso.cpp
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M lld/test/ELF/arm-branch-rangethunk.s
M lld/test/ELF/arm-force-pi-thunk.s
M lld/test/ELF/arm-thumb-condbranch-thunk.s
M lld/test/ELF/arm-thumb-interwork-shared.s
M lld/test/ELF/arm-thumb-interwork-thunk.s
M lld/test/ELF/arm-thumb-mix-range-thunk-os.s
M lld/test/ELF/arm-thumb-plt-range-thunk-os.s
M lld/test/ELF/arm-thumb-range-thunk-os-no-ext.s
M lld/test/ELF/arm-thumb-range-thunk-os.s
M lld/test/ELF/arm-thunk-arm-thumb-reuse.s
M lld/test/ELF/arm-thunk-linkerscript-dotexpr.s
M lld/test/ELF/arm-thunk-linkerscript-orphan.s
M lld/test/ELF/arm-thunk-linkerscript.s
M lld/test/ELF/arm-thunk-re-add.s
M lld/test/MachO/objc-category-merging-minimal.s
M lld/test/MachO/objc-category-merging-swift.s
M lldb/bindings/python/CMakeLists.txt
M lldb/bindings/python/python-swigsafecast.swig
M lldb/bindings/python/python-wrapper.swig
M lldb/cmake/modules/LLDBConfig.cmake
M lldb/docs/CMakeLists.txt
M lldb/docs/dil-expr-lang.ebnf
M lldb/docs/python_extensions.md
M lldb/docs/resources/build.md
M lldb/docs/use/mcp.md
A lldb/examples/python/templates/scripted_string_summary.py
A lldb/examples/python/templates/scripted_synthetic_children.py
M lldb/include/lldb/API/SBPlatform.h
M lldb/include/lldb/API/SBTypeSummary.h
M lldb/include/lldb/Core/BugReporter.h
M lldb/include/lldb/Core/Module.h
M lldb/include/lldb/DataFormatters/TypeSummary.h
M lldb/include/lldb/DataFormatters/TypeSynthetic.h
M lldb/include/lldb/Host/Config.h.cmake
M lldb/include/lldb/Host/JSONTransport.h
A lldb/include/lldb/Interpreter/Interfaces/ScriptedStringSummaryInterface.h
A lldb/include/lldb/Interpreter/Interfaces/ScriptedSyntheticChildrenInterface.h
M lldb/include/lldb/Interpreter/ScriptInterpreter.h
M lldb/include/lldb/Protocol/MCP/Transport.h
M lldb/include/lldb/Target/Target.h
M lldb/include/lldb/ValueObject/DILAST.h
M lldb/include/lldb/ValueObject/DILEval.h
M lldb/include/lldb/ValueObject/DILLexer.h
M lldb/include/lldb/ValueObject/DILParser.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/include/lldb/lldb-forward.h
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/session_helpers.py
M lldb/source/API/SBTypeSummary.cpp
M lldb/source/Commands/CommandObjectDiagnostics.cpp
M lldb/source/Commands/CommandObjectType.cpp
A lldb/source/Core/BugReporter.cpp
M lldb/source/Core/CMakeLists.txt
M lldb/source/Core/Module.cpp
M lldb/source/Core/Section.cpp
M lldb/source/DataFormatters/TypeSummary.cpp
M lldb/source/DataFormatters/TypeSynthetic.cpp
M lldb/source/Host/common/JSONTransport.cpp
M lldb/source/Host/macosx/objcxx/HostInfoMacOSX.mm
M lldb/source/Host/windows/DomainSocketWindows.cpp
M lldb/source/Interpreter/ScriptInterpreter.cpp
M lldb/source/Plugins/BugReporter/GitHub/GitHubReporter.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
M lldb/source/Plugins/ExpressionParser/Clang/IRForTarget.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/ObjectFile/Minidump/MinidumpFileBuilder.cpp
M lldb/source/Plugins/ObjectFile/wasm/ObjectFileWasm.cpp
M lldb/source/Plugins/ObjectFile/wasm/ObjectFileWasm.h
A lldb/source/Plugins/ObjectFile/wasm/WasmAddress.h
M lldb/source/Plugins/Platform/Windows/PlatformWindows.cpp
M lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm64.cpp
M lldb/source/Plugins/Process/wasm/ProcessWasm.cpp
M lldb/source/Plugins/Process/wasm/ProcessWasm.h
M lldb/source/Plugins/Protocol/MCP/Tool.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/CMakeLists.txt
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPythonInterface.h
A lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedStringSummaryPythonInterface.cpp
A lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedStringSummaryPythonInterface.h
A lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedSyntheticChildrenPythonInterface.cpp
A lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedSyntheticChildrenPythonInterface.h
M lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
M lldb/source/Protocol/MCP/Transport.cpp
M lldb/source/Symbol/ObjectFile.cpp
M lldb/source/Symbol/Variable.cpp
M lldb/source/Target/Memory.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Target/TargetProperties.td
M lldb/source/Utility/Args.cpp
M lldb/source/ValueObject/DILAST.cpp
M lldb/source/ValueObject/DILEval.cpp
M lldb/source/ValueObject/DILLexer.cpp
M lldb/source/ValueObject/DILParser.cpp
M lldb/test/API/commands/expression/expr-with-fork/TestExprWithFork.py
A lldb/test/API/commands/expression/result-with-destructor/Makefile
A lldb/test/API/commands/expression/result-with-destructor/TestResultWithDestructor.py
A lldb/test/API/commands/expression/result-with-destructor/main.cpp
M lldb/test/API/commands/frame/var-dil/expr/Bitwise/TestFrameVarDILBitwise.py
M lldb/test/API/commands/frame/var-dil/expr/Bitwise/main.cpp
M lldb/test/API/commands/register/register_command/TestRegisters.py
M lldb/test/API/commands/settings/TestSettings.py
M lldb/test/API/functionalities/gdb_remote_client/TestWasm.py
A lldb/test/API/functionalities/process_save_core_minidump/size_mismatch/Makefile
A lldb/test/API/functionalities/process_save_core_minidump/size_mismatch/TestProcessSaveCoreMinidumpSizeMismatch.py
A lldb/test/API/functionalities/process_save_core_minidump/size_mismatch/main.cpp
M lldb/test/API/functionalities/process_save_core_minidump_size_of_image/TestMinidumpSizeOfImage.py
M lldb/test/API/functionalities/scripted_frame_provider/TestScriptedFrameProvider.py
M lldb/test/API/tools/lldb-dap/console/TestDAP_console.py
M lldb/test/API/tools/lldb-dap/console/TestDAP_redirection_to_console.py
M lldb/test/API/tools/lldb-dap/evaluate/TestDAP_evaluate.py
M lldb/test/API/tools/lldb-dap/longpath/TestDAP_launch_longPath.py
M lldb/test/API/tools/lldb-dap/restart/TestDAP_restart.py
M lldb/test/API/tools/lldb-dap/restart/TestDAP_restart_console.py
M lldb/test/API/tools/lldb-dap/stackTrace/subtleFrames/TestDAP_subtleFrames.py
M lldb/test/API/tools/lldb-dap/unknown/TestDAP_unknownRequest.py
M lldb/test/CMakeLists.txt
M lldb/test/Shell/Diagnostics/TestReport.test
A lldb/test/Shell/MCP/TestHelp.test
A lldb/test/Shell/MCP/TestUnknownArgument.test
A lldb/test/Shell/MCP/TestVersion.test
A lldb/test/Shell/ObjectFile/wasm/wasm-globals.yaml
M lldb/test/Shell/SymbolFile/DWARF/x86/dwo-not-found-warning.cpp
M lldb/test/Shell/helper/toolchain.py
M lldb/tools/lldb-mcp/lldb-mcp.cpp
M lldb/tools/lldb-test/lldb-test.cpp
M lldb/unittests/Host/JSONTransportTest.cpp
M lldb/unittests/ScriptInterpreter/Python/PythonTestSuite.cpp
M lldb/unittests/Target/MemoryTest.cpp
M lldb/unittests/Utility/ArchSpecTest.cpp
M llvm/cmake/config-ix.cmake
M llvm/docs/AMDGPUAsyncOperations.md
M llvm/docs/AMDGPUMemoryModel.md
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/CommandGuide/index.md
A llvm/docs/CommandGuide/llvm-calc-occupancy.rst
M llvm/docs/CommandGuide/llvm-readobj.rst
M llvm/docs/LangRef.md
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/docs/_static/custom.css
M llvm/include/llvm/ADT/ScopeExit.h
M llvm/include/llvm/ADT/SetVector.h
M llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h
M llvm/include/llvm/Analysis/ScalarEvolutionPatternMatch.h
M llvm/include/llvm/BinaryFormat/MachO.def
M llvm/include/llvm/BinaryFormat/MachO.h
M llvm/include/llvm/CodeGen/CommandFlags.h
M llvm/include/llvm/CodeGen/MacroFusion.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/ValueTypes.h
M llvm/include/llvm/ExecutionEngine/Orc/MachOBuilder.h
M llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h
A llvm/include/llvm/ExecutionEngine/Orc/RTBridge/Calls.h
A llvm/include/llvm/ExecutionEngine/Orc/RTBridge/SPS/Calls.h
A llvm/include/llvm/Frontend/HLSL/SemanticSignatures.h
M llvm/include/llvm/Frontend/OpenMP/ConstructDecompositionT.h
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/IR/Module.h
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/include/llvm/MC/MCGOFFStreamer.h
M llvm/include/llvm/MC/MCMachObjectWriter.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/include/llvm/MC/MCSubtargetInfo.h
M llvm/include/llvm/Object/MachO.h
M llvm/include/llvm/Support/CodeGen.h
M llvm/include/llvm/Support/DXILABI.h
M llvm/include/llvm/Support/PatternMatchHelpers.h
M llvm/include/llvm/Target/GenericOpcodes.td
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
A llvm/include/llvm/TargetParser/NVPTXTargetParser.def
A llvm/include/llvm/TargetParser/NVPTXTargetParser.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/include/module.modulemap
M llvm/lib/Analysis/BlockFrequencyInfoImpl.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/CommandFlags.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/LocalStackSlotAllocation.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/MacroFusion.cpp
M llvm/lib/CodeGen/OptimizePHIs.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/StackColoring.cpp
M llvm/lib/DWARFLinker/Classic/DWARFLinker.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/OrcRTBridge.cpp
M llvm/lib/Frontend/HLSL/CMakeLists.txt
A llvm/lib/Frontend/HLSL/SemanticSignatures.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/Module.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCGOFFStreamer.cpp
M llvm/lib/MC/MCMachOStreamer.cpp
M llvm/lib/MC/MCParser/DarwinAsmParser.cpp
M llvm/lib/MC/MCParser/MasmParser.cpp
M llvm/lib/MC/MachObjectWriter.cpp
M llvm/lib/ObjCopy/MachO/MachOLayoutBuilder.cpp
M llvm/lib/Object/MachOObjectFile.cpp
M llvm/lib/ObjectYAML/MachOEmitter.cpp
M llvm/lib/ObjectYAML/MachOYAML.cpp
M llvm/lib/Support/APFloat.cpp
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsanInstrumentation.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/GCNProcessors.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
M llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMMacroFusion.cpp
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/lib/Target/CSKY/CSKYAsmPrinter.cpp
M llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.h
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
M llvm/lib/Target/MSP430/MSP430Subtarget.cpp
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/lib/Target/Mips/MipsCallingConv.td
M llvm/lib/Target/Mips/MipsRegisterInfo.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXBaseInfo.h
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
R llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
R llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.h
M llvm/lib/Target/NVPTX/NVPTXUtilities.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCMacroFusion.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
A llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
M llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
M llvm/lib/Target/RISCV/RISCVSchedAndes45.td
M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
M llvm/lib/Target/RISCV/RISCVSchedTTAscalonX.td
M llvm/lib/Target/RISCV/RISCVScheduleV.td
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
M llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
M llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86MacroFusion.cpp
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/lib/TargetParser/CMakeLists.txt
A llvm/lib/TargetParser/NVPTXTargetParser.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/Transforms/IPO/Attributor.cpp
M llvm/lib/Transforms/IPO/MergeFunctions.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCompatibilityAnalysis.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCompatibilityAnalysis.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/VecUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Analysis/CostModel/AArch64/arith-overflow.ll
M llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
M llvm/test/Analysis/CostModel/AArch64/arith.ll
M llvm/test/Analysis/CostModel/AArch64/clmul-fixed.ll
M llvm/test/Analysis/CostModel/AArch64/clmul.ll
M llvm/test/Analysis/CostModel/AArch64/cmp.ll
M llvm/test/Analysis/CostModel/AArch64/cttz_elts.ll
M llvm/test/Analysis/CostModel/AArch64/div.ll
M llvm/test/Analysis/CostModel/AArch64/div_cte.ll
M llvm/test/Analysis/CostModel/AArch64/fshl.ll
M llvm/test/Analysis/CostModel/AArch64/fshr.ll
M llvm/test/Analysis/CostModel/AArch64/masked-divrem.ll
M llvm/test/Analysis/CostModel/AArch64/mul.ll
M llvm/test/Analysis/CostModel/AArch64/rem.ll
M llvm/test/Analysis/CostModel/AArch64/sve-arith.ll
M llvm/test/Analysis/CostModel/AArch64/sve-div.ll
M llvm/test/Analysis/CostModel/AArch64/sve-rem.ll
A llvm/test/Analysis/CostModel/WebAssembly/vector-shift.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/diverged-entry-basic-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/diverged-entry-basic.ll
A llvm/test/Assembler/module-flags-float-abi.ll
M llvm/test/Bitcode/upgrade-ppc-float-abi.ll
M llvm/test/CMakeLists.txt
M llvm/test/CodeGen/AArch64/GlobalISel/combine-2-icmps-of-0-and-or.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-add-of-sub.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-addv.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-and-or-disjoint-mask.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-anyext-crash.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-avg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-binop-neg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-binop-undef-left-to-zero.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-build-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-fcmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-icmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-cast.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-const-infinite-loop.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-fp-const-lhs.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-int-const-lhs.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-const-fold-barrier-rhs.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-fma.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-fp-rounding.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-itofp-zero.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-unary-int.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-copy.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ctlz-cttz-zero-poison.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-trunc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ext.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-extract-vec-elt.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fabs.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-flog2.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fminimum-fmaximum.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fminnum-fmaxnum.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fneg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fpowi.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fptrunc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-freeze.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fshl.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fshr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fsqrt.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-of-binop-to-icmp-of-0.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-to-lhs-known-bits.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-inttoptr-ptrtoint.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-logic-of-compare.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-mul-to-shl.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-mul.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-mulo-with-2.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-narrow-binop.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-neg-and-one-to-sext-inreg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-op-trunc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-or-and-xor.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-or-of-and.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-overflow.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-int2ptr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-reassociation.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ptrtoint.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-same-op.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-sdiv.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-debugloc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-trunc-sextload.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-shift-immed-mismatch-crash.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-shifts-undef.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-shufflevector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-srem-by-pow2.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-trunc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-udivrem-use-bug.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-umulh-to-lshr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-unary-undef-to-zero.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge-undef.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-use-vector-truncate-order.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-vscale.mir
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-delayed-stack-protector.ll
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-protector-trap-unreachable.ll
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-addo-zero.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-binop-reassoc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-conflict.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-crash.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-and-mask.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-or-pattern-align.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-or-pattern.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-mulo-zero.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-narrow-binop-feeding-add.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-select-to-fminmax.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-use-vector-truncate.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-ashr-shl-to-sext-inreg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-binop-same-val.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-br.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-bzero.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-commute-shift.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-concat-vectors.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-s1.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-funnel-shifts-to-rotates.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-hoist-same-hands.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-icmp-redundant-trunc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-invert-cmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-not-really-equiv-insts.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-prop-extends-phi.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-ptradd-chain.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-select.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-sextload-from-sextinreg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector-disjoint-mask.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector-undef-rhs.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-simplify-add.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-undef.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-xor-of-and-with-same-reg.mir
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M llvm/test/CodeGen/AArch64/fmlal-loreg.ll
M llvm/test/CodeGen/AArch64/misched-fusion-apple-sme-compute.mir
A llvm/test/CodeGen/AArch64/neon-scalar-vcvtfp2fx.ll
M llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
M llvm/test/CodeGen/AArch64/regalloc-hint-movprfx-streaming.mir
M llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
M llvm/test/CodeGen/AArch64/sve-hadd.ll
M llvm/test/CodeGen/AArch64/sve-ldst-multi-vec.mir
M llvm/test/CodeGen/AArch64/sve-multivector-load-stores.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-wide-add.ll
A llvm/test/CodeGen/AArch64/sve-structured-store-memoperands.ll
M llvm/test/CodeGen/AArch64/sve-vector-interleave.ll
A llvm/test/CodeGen/AArch64/sve2-wide-ops.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-stores.ll
M llvm/test/CodeGen/AArch64/vector-absolute-difference.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-region.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-strict_fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir
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M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.cd.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ptr.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.ptr.s.buffer.load.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.ptr.s.buffer.load.subdword.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ptr.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi-sat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui-sat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-uniform-intrinsic-wwm-single-lane.ll
A llvm/test/CodeGen/AMDGPU/arbitrary-fp-from-float-fp8-f16-hw.ll
A llvm/test/CodeGen/AMDGPU/arbitrary-fp-to-float-fp8-hw.ll
A llvm/test/CodeGen/AMDGPU/asyncmark-merge-rebase-pregfx12.mir
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_cond.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
M llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
M llvm/test/CodeGen/AMDGPU/bitop3-shared-operand.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-usub_cond.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-usub_sat.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll
M llvm/test/CodeGen/AMDGPU/bug-pk-f32-imm-fold.mir
M llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll
M llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
M llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
M llvm/test/CodeGen/AMDGPU/coexec-sched-flavor-classification.mir
M llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
A llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.ll
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
A llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_ptr_s_buffer_loads.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
A llvm/test/CodeGen/AMDGPU/greedy-wwm-copy-prologue-assert.mir
M llvm/test/CodeGen/AMDGPU/group-image-instructions.ll
M llvm/test/CodeGen/AMDGPU/hsa-default-device.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/issue130120-eliminate-frame-index.ll
M llvm/test/CodeGen/AMDGPU/issue139317-bad-opsel-reg-sequence-fold.ll
M llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.pk.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.msad.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.s.buffer.load-gfx12.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.s.buffer.load-mmo.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.modf.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
M llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
M llvm/test/CodeGen/AMDGPU/memset-pattern.ll
M llvm/test/CodeGen/AMDGPU/packed-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
A llvm/test/CodeGen/AMDGPU/ptr-s-buffer-load-mmo-offsets.ll
A llvm/test/CodeGen/AMDGPU/s_bcnt0.ll
M llvm/test/CodeGen/AMDGPU/s_cmp_0.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll
A llvm/test/CodeGen/AMDGPU/sdwa-peephole-lshl-or-hi16pack.ll
A llvm/test/CodeGen/AMDGPU/sdwa-peephole-lshl-or-hi16pack.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-fp.ll
M llvm/test/CodeGen/AMDGPU/set_kill_i1_for_floation_point_comparison.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/sgpr-scavenge-fi-stack-id.ll
M llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies-av-constrain.mir
M llvm/test/CodeGen/AMDGPU/si-scheduler.ll
M llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll
M llvm/test/CodeGen/AMDGPU/si-spill-cf.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/structurize-hoist.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/valu-i1.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
M llvm/test/CodeGen/AMDGPU/wqm.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/ARM/O3-pipeline.ll
R llvm/test/CodeGen/DirectX/cross.ll
A llvm/test/CodeGen/Hexagon/fmaximum.ll
A llvm/test/CodeGen/Hexagon/fminimum.ll
M llvm/test/CodeGen/LoongArch/jr-without-ra.ll
M llvm/test/CodeGen/LoongArch/opt-pipeline.ll
A llvm/test/CodeGen/Mips/write_register_gp.ll
M llvm/test/CodeGen/PowerPC/copysignl.ll
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/branch-on-zero.ll
A llvm/test/CodeGen/RISCV/epilog-crash.ll
M llvm/test/CodeGen/RISCV/features-info.ll
A llvm/test/CodeGen/RISCV/frame-base-addr-reuse.mir
M llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv32.mir
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
A llvm/test/CodeGen/RISCV/rvv/vlmax-peephole.mir
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/zdinx-large-spill.mir
A llvm/test/CodeGen/RISCV/zilx-opt-w-instrs.mir
A llvm/test/CodeGen/RISCV/zilx.ll
M llvm/test/CodeGen/SPARC/reserved-regs-named.ll
M llvm/test/CodeGen/SPIRV/atomicrmw-uinc-udec-wrap.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-function-namespace-scope.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-function-with-declaration.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-function.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable-skip-type-not-in-regs.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable-static-member.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-type-array-of-composite-drop.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-type-composite-nested-drop.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-type-composite-skip-member-not-in-regs.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-type-composite-static-member-skipped.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-type-composite.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-type-pointer-to-composite-drop.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-typedef-nested-drop.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-typedef-skip-base-not-in-regs.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-typedef.ll
R llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cross.ll
A llvm/test/CodeGen/SPIRV/legalization/matrix-wide-vector-shader.ll
M llvm/test/CodeGen/SPIRV/llc-pipeline.ll
A llvm/test/CodeGen/SystemZ/zos-common-global.ll
M llvm/test/CodeGen/Thumb2/mve-blockplacement.ll
M llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
M llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll
M llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll
M llvm/test/CodeGen/X86/2011-09-14-valcoalesce.ll
A llvm/test/CodeGen/X86/avx10_2bf16-arith-scalar.ll
M llvm/test/CodeGen/X86/avx10_2bf16-fma.ll
M llvm/test/CodeGen/X86/avx512-gather-scatter-intrin-deprecated.ll
M llvm/test/CodeGen/X86/avx512-gather-scatter-intrin.ll
A llvm/test/CodeGen/X86/fptosi-sat-scalar-f16.ll
M llvm/test/CodeGen/X86/fptosi-sat-scalar.ll
M llvm/test/CodeGen/X86/merge-store-partially-alias-loads.ll
M llvm/test/CodeGen/X86/vec_int_to_fp.ll
M llvm/test/CodeGen/X86/win64-eh-unwindv2-errors.mir
M llvm/test/DebugInfo/Generic/debug-info-qualifiers.ll
A llvm/test/DebugInfo/X86/DW_AT_LLVM_stmt_seq_split_dwarf.ll
M llvm/test/ExecutionEngine/JITLink/Generic/Inputs/MachO_Universal_libFoo_dylib.yaml
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vcvt.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vcvt_f32_su32.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/vararg_shadow.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/f16c-intrinsics-upgrade.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/vararg_shadow.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/vararg_shadow.ll
A llvm/test/Linker/module-flags-float-abi.ll
M llvm/test/MC/AMDGPU/gfx950-unsupported.s
M llvm/test/MC/AMDGPU/literals.s
M llvm/test/MC/AMDGPU/mai.s
A llvm/test/MC/MachO/target-triple-padding.s
A llvm/test/MC/MachO/target-triple.s
M llvm/test/MC/Mips/macro-ddiv-bad.s
M llvm/test/MC/Mips/macro-ddivu-bad.s
M llvm/test/MC/Mips/macro-div-bad.s
M llvm/test/MC/Mips/macro-divu-bad.s
M llvm/test/MC/RISCV/rv32d-invalid.s
M llvm/test/MC/RISCV/rv32dc-invalid.s
M llvm/test/MC/RISCV/rv32f-invalid.s
M llvm/test/MC/RISCV/rv32fc-invalid.s
M llvm/test/MC/RISCV/rv32q-invalid.s
M llvm/test/MC/RISCV/rv32zdinx-invalid.s
M llvm/test/MC/RISCV/rv32zfh-invalid.s
M llvm/test/MC/RISCV/rv32zfinx-invalid.s
M llvm/test/MC/RISCV/rv32zhinx-invalid.s
M llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
M llvm/test/MC/RISCV/rv64d-invalid.s
M llvm/test/MC/RISCV/rv64f-invalid.s
M llvm/test/MC/RISCV/rv64q-invalid.s
M llvm/test/MC/RISCV/rv64xtheadfmemidx-invalid.s
M llvm/test/MC/RISCV/rv64zdinx-invalid.s
M llvm/test/MC/RISCV/rv64zfh-invalid.s
M llvm/test/MC/RISCV/rv64zfinx-invalid.s
M llvm/test/MC/RISCV/rv64zhinx-invalid.s
M llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
M llvm/test/MC/RISCV/rvzfbfmin-invalid.s
M llvm/test/MC/RISCV/rvzfhmin-invalid.s
A llvm/test/MC/RISCV/zilx-invalid.s
A llvm/test/MC/RISCV/zilx-valid-rv32.s
A llvm/test/MC/RISCV/zilx-valid-rv64.s
A llvm/test/MC/Sparc/Directives/seg.s
A llvm/test/MC/X86/intel-syntax-data32-16.s
A llvm/test/Object/Inputs/macho-invalid-target-triple-name_offset-toobig.yaml
A llvm/test/Object/Inputs/macho-invalid-target-triple-name_offset-toosmall.yaml
A llvm/test/Object/Inputs/macho-invalid-target-triple-name_toobig.yaml
A llvm/test/Object/Inputs/macho-invalid-target-triple-small.yaml
M llvm/test/Object/macho-invalid.test
A llvm/test/ObjectYAML/MachO/target_triple_command.yaml
M llvm/test/TableGen/AMDGPUTargetDefErrors.td
M llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
M llvm/test/TableGen/MacroFusion.td
R llvm/test/TableGen/RuntimeLibcallEmitter-conflict-warning.td
A llvm/test/TableGen/RuntimeLibcallEmitter-multiple-impls.td
M llvm/test/TableGen/aarch64-register-info-stats.td
M llvm/test/Transforms/ConstraintElimination/ne-tightening.ll
M llvm/test/Transforms/EarlyCSE/AMDGPU/intrinsics.ll
M llvm/test/Transforms/IndVarSimplify/ARM/code-size.ll
M llvm/test/Transforms/IndVarSimplify/replace-loop-exit-folds.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-cmpne.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-binop.ll
A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-cmp.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-shift.ll
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts-inseltpoison.ll
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll
M llvm/test/Transforms/InstCombine/AMDGPU/fma_legacy.ll
M llvm/test/Transforms/InstCombine/AMDGPU/fmul_legacy.ll
M llvm/test/Transforms/LoopIdiom/basic.ll
A llvm/test/Transforms/LoopIdiom/cyclic-redundancy-check-memoryssa.ll
M llvm/test/Transforms/LoopIdiom/cyclic-redundancy-check.ll
M llvm/test/Transforms/LoopStrengthReduce/AArch64/expand-ptrtoaddr-reuse-ptrtoint.ll
M llvm/test/Transforms/LoopUnroll/branch-weights-freq/unroll-complete.ll
M llvm/test/Transforms/LoopUnroll/branch-weights-freq/unroll-partial-unconditional-latch.ll
M llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll
M llvm/test/Transforms/LoopVectorize/VPlan/icmp-uniforms.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-branch-weights.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-store-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/store-scalarization-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
M llvm/test/Transforms/LoopVectorize/bsd_regex.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll
A llvm/test/Transforms/LoopVectorize/expression-recipe-branch-weights.ll
M llvm/test/Transforms/LoopVectorize/extract-last-veclane.ll
M llvm/test/Transforms/LoopVectorize/find-last.ll
M llvm/test/Transforms/LoopVectorize/float-induction.ll
M llvm/test/Transforms/LoopVectorize/forked-pointers.ll
M llvm/test/Transforms/LoopVectorize/histograms.ll
M llvm/test/Transforms/LoopVectorize/hoist-predicated-loads-with-predicated-stores.ll
M llvm/test/Transforms/LoopVectorize/if-conversion-nest.ll
M llvm/test/Transforms/LoopVectorize/if-conversion.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-2.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-metadata.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-pred-stores.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization-2.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/loop-scalars.ll
M llvm/test/Transforms/LoopVectorize/multiple-address-spaces.ll
M llvm/test/Transforms/LoopVectorize/non-const-n.ll
M llvm/test/Transforms/LoopVectorize/opaque-ptr.ll
M llvm/test/Transforms/LoopVectorize/phi-cost.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-cond.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
M llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
M llvm/test/Transforms/LoopVectorize/reduction.ll
A llvm/test/Transforms/LoopVectorize/replicate-region-branch-weights-merged-mem-ops.ll
M llvm/test/Transforms/LoopVectorize/replicate-region-branch-weights.ll
M llvm/test/Transforms/LoopVectorize/runtime-check.ll
M llvm/test/Transforms/LoopVectorize/scalable-inductions.ll
M llvm/test/Transforms/LoopVectorize/scalar_after_vectorization.ll
M llvm/test/Transforms/LoopVectorize/select-cmp-blend-chain.ll
M llvm/test/Transforms/LoopVectorize/store-shuffle-bug.ll
M llvm/test/Transforms/LoopVectorize/trunc-reductions.ll
M llvm/test/Transforms/LoopVectorize/vector-geps.ll
A llvm/test/Transforms/MergeFunc/merge-functions-entry-count-imports.ll
M llvm/test/Transforms/PhaseOrdering/X86/avg.ll
A llvm/test/Transforms/SLPVectorizer/AArch64/extract-fmul-cost.ll
A llvm/test/Transforms/SLPVectorizer/AArch64/reassoc-copyable-sched-deps.ll
A llvm/test/Transforms/SLPVectorizer/AArch64/trimmed-node-gather-cost.ll
A llvm/test/Transforms/SLPVectorizer/ARM/non-fp-math-op.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/external.ll
M llvm/test/Transforms/SLPVectorizer/X86/bv-shuffle-mask.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable-with-non-scheduled-parent-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/extracts-non-extendable.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-parent-instr-copyable-regular.ll
M llvm/test/Transforms/SLPVectorizer/X86/ordering-bug.ll
M llvm/test/Transforms/SLPVectorizer/X86/poor-throughput-seeds.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr46983.ll
M llvm/test/Transforms/SLPVectorizer/X86/reassociate-ops.ll
A llvm/test/Transforms/SLPVectorizer/X86/reduction-fadd-reassoc.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-node-reused-in-later-vector.ll
M llvm/test/Transforms/SLPVectorizer/X86/subvector-minbitwidth-unsigned-value.ll
M llvm/test/Transforms/SLPVectorizer/X86/supernode.ll
A llvm/test/Transforms/SandboxVectorizer/topdown_vec.ll
A llvm/test/Verifier/module-flags-float-abi.ll
M llvm/test/lit.cfg.py
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
A llvm/test/tools/dsymutil/AArch64/lc_target_triple.test
A llvm/test/tools/dsymutil/AArch64/lc_target_triple_duplicate.test
A llvm/test/tools/dsymutil/AArch64/lc_target_triple_universal.test
A llvm/test/tools/dsymutil/Inputs/lc_target_triple.arm64
A llvm/test/tools/dsymutil/Inputs/lc_target_triple_duplicate.arm64
A llvm/test/tools/dsymutil/Inputs/lc_target_triple_universal.arm64
A llvm/test/tools/dsymutil/X86/keep-enumerators.test
A llvm/test/tools/llubi/ptrtoint_cast.ll
A llvm/test/tools/llvm-calc-occupancy/basic.test
A llvm/test/tools/llvm-ml/textequ_expansion.asm
A llvm/test/tools/llvm-objcopy/MachO/lc-target-triple.test
A llvm/test/tools/llvm-objdump/MachO/target-triple.yaml
A llvm/test/tools/llvm-profgen/X86/first-loadable-address.test
A llvm/test/tools/llvm-readobj/MachO/target-triple.test
M llvm/tools/dsymutil/MachOUtils.cpp
M llvm/tools/llubi/lib/Context.cpp
M llvm/tools/llubi/lib/Interpreter.cpp
A llvm/tools/llvm-calc-occupancy/CMakeLists.txt
A llvm/tools/llvm-calc-occupancy/llvm-calc-occupancy.cpp
M llvm/tools/llvm-gpu-loader/llvm-gpu-loader.cpp
M llvm/tools/llvm-objdump/MachODump.cpp
M llvm/tools/llvm-profgen/ProfiledBinary.cpp
M llvm/tools/llvm-readobj/MachODumper.cpp
M llvm/tools/llvm-readobj/ObjDumper.h
M llvm/tools/llvm-readobj/Opts.td
M llvm/tools/llvm-readobj/llvm-readobj.cpp
M llvm/tools/obj2yaml/macho2yaml.cpp
M llvm/unittests/ADT/APFloatTest.cpp
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
M llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
M llvm/unittests/ExecutionEngine/Orc/MachOBuilderTest.cpp
A llvm/unittests/ExecutionEngine/Orc/SPSCallersTest.cpp
M llvm/unittests/Frontend/CMakeLists.txt
A llvm/unittests/Frontend/HLSLSemanticSignatureMetadataTest.cpp
M llvm/unittests/Target/ARM/InstSizes.cpp
M llvm/unittests/Target/ARM/MachineInstrTest.cpp
M llvm/unittests/TargetParser/CMakeLists.txt
A llvm/unittests/TargetParser/NVPTXTargetParserTest.cpp
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/unittests/Transforms/Utils/ScalarEvolutionExpanderTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/DependencyGraphTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
M llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
M llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
M llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp
M llvm/utils/git/github-automation.py
M llvm/utils/gn/secondary/clang/unittests/CIR/BUILD.gn
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/lldb/include/lldb/Host/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Frontend/HLSL/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/TargetParser/BUILD.gn
M llvm/utils/gn/secondary/llvm/test/BUILD.gn
A llvm/utils/gn/secondary/llvm/tools/llvm-calc-occupancy/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/Orc/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Frontend/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/TargetParser/BUILD.gn
M mlir/include/mlir-c/BuiltinTypes.h
M mlir/include/mlir/Bindings/Python/IRTypes.h
M mlir/include/mlir/Dialect/Arith/Transforms/Passes.h
M mlir/include/mlir/Dialect/Arith/Transforms/Passes.td
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/include/mlir/Dialect/LLVMIR/BasicPtxBuilderInterface.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/include/mlir/Dialect/Linalg/Passes.td
M mlir/include/mlir/Dialect/Tosa/IR/CMakeLists.txt
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/include/mlir/Dialect/Tosa/IR/TosaOpBase.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.h
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaProfileCompliance.h
M mlir/include/mlir/Dialect/Tosa/IR/TosaShapeOps.td
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/BuiltinTypes.td
M mlir/include/mlir/IR/CommonTypeConstraints.td
M mlir/lib/AsmParser/TokenKinds.def
M mlir/lib/AsmParser/TypeParser.cpp
M mlir/lib/Bindings/Python/IRTypes.cpp
M mlir/lib/CAPI/IR/BuiltinTypes.cpp
M mlir/lib/Conversion/GPUCommon/GPUToLLVMConversion.cpp
M mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Dialect/Arith/Transforms/ExpandOps.cpp
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/lib/Dialect/GPU/Transforms/KernelOutlining.cpp
M mlir/lib/Dialect/LLVMIR/IR/BasicPtxBuilderInterface.cpp
M mlir/lib/Dialect/Linalg/Transforms/ConvertConv2DToImg2Col.cpp
M mlir/lib/Dialect/Linalg/Transforms/FoldIntoElementwise.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCCGToGPU.cpp
M mlir/lib/Dialect/Quant/IR/QuantTypes.cpp
M mlir/lib/Dialect/Tosa/CMakeLists.txt
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
M mlir/lib/Dialect/Transform/IR/TransformOps.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
M mlir/lib/IR/AsmPrinter.cpp
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/python/mlir/extras/types.py
M mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir
M mlir/test/Conversion/SPIRVToLLVM/arithmetic-ops-to-llvm.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
A mlir/test/Dialect/Arith/expand-ops-min-max.mlir
M mlir/test/Dialect/Arith/expand-ops.mlir
M mlir/test/Dialect/Complex/canonicalize.mlir
M mlir/test/Dialect/EmitC/arith/ops.mlir
M mlir/test/Dialect/GPU/invalid.mlir
M mlir/test/Dialect/GPU/ops.mlir
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Dialect/Linalg/convert-conv2d-to-img2col.mlir
M mlir/test/Dialect/Linalg/elementwise/fold.mlir
M mlir/test/Dialect/OpenACC/acc-cg-to-gpu-reduction-array-shared.mlir
R mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/profile_all_unsupported.mlir
M mlir/test/Dialect/Tosa/profile_pro_fp_unsupported.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
M mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir
M mlir/test/Dialect/XeGPU/propagate-layout.mlir
M mlir/test/Dialect/XeGPU/sg-to-lane-distribute-unit.mlir
M mlir/test/IR/attribute.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
M mlir/test/Target/SPIRV/debug.mlir
M mlir/test/Target/SPIRV/non-uniform-ops.mlir
M mlir/test/lib/Dialect/Tosa/CMakeLists.txt
R mlir/test/lib/Dialect/Tosa/TestAvailability.cpp
M mlir/test/python/ir/builtin_types.py
M mlir/tools/mlir-opt/mlir-opt.cpp
M mlir/tools/mlir-tblgen/CMakeLists.txt
M mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp
R mlir/tools/mlir-tblgen/TosaUtilsGen.cpp
M mlir/utils/lldb-scripts/mlirDataFormatters.py
M mlir/utils/tree-sitter-mlir/grammar.js
M offload/libomptarget/omptarget.cpp
M offload/plugins-nextgen/common/CMakeLists.txt
M offload/plugins-nextgen/common/src/JIT.cpp
A offload/test/offloading/firstprivate_packed_buffer_lifetime.c
M offload/test/unit/lit.cfg.py
M offload/test/unit/lit.site.cfg.in
M offload/unittests/OffloadAPI/device_code/CMakeLists.txt
M offload/unittests/OffloadAPI/program/olCreateProgram.cpp
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/OpenACC/Transforms/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Rebase
Created using spr 1.3.7
Compare: https://github.com/llvm/llvm-project/compare/264f240f5e86...7f29fbaf52b1
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