[all-commits] [llvm/llvm-project] 1a848f: [InlineSpiller][AMDGPU] Implement subreg reload du...

[Aaditya via All-commits]

  Branch: refs/heads/users/cdevadas/subreg-reload
  Home:   https://github.com/llvm/llvm-project
  Commit: 1a848f4a7ae6bcb78e5320aebe55f879124b9e95
      https://github.com/llvm/llvm-project/commit/1a848f4a7ae6bcb78e5320aebe55f879124b9e95
  Author: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
  Date:   2026-07-31 (Fri, 31 Jul 2026)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
    M llvm/lib/CodeGen/InlineSpiller.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
    M llvm/test/CodeGen/AMDGPU/dummy-regalloc-priority-advisor.mir
    M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props.ll
    M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
    M llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir
    M llvm/test/CodeGen/AMDGPU/infloop-subrange-spill-inspect-subrange.mir
    M llvm/test/CodeGen/AMDGPU/infloop-subrange-spill.mir
    M llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir
    M llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
    M llvm/test/CodeGen/AMDGPU/regpressure-mitigation-with-subreg-reload.mir
    A llvm/test/CodeGen/AMDGPU/skip-partial-reload-for-16bit-regaccess.mir
    M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
    M llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
    M llvm/test/CodeGen/AMDGPU/splitkit-nolivesubranges.mir
    M llvm/test/CodeGen/AMDGPU/swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir
    R llvm/test/CodeGen/AMDGPU/use-after-free-after-cleanup-failed-vreg.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll

  Log Message:
  -----------
  [InlineSpiller][AMDGPU] Implement subreg reload during RA spill

Currently, when a virtual register is partially used, the
entire tuple is restored from the spilled location, even if
only a subset of its sub-registers is needed. This patch
introduces support for partial reloads by analyzing actual
register usage and restoring only the required sub-registers.
This improvement enhances register allocation efficiency,
particularly for cases involving tuple virtual registers.
For AMDGPU, this change brings considerable improvements
in workloads that involve matrix operations, large vectors,
and complex control flows.


  Commit: 829c8e9360ece47f2ec76c67ee0f78306e2312cd
      https://github.com/llvm/llvm-project/commit/829c8e9360ece47f2ec76c67ee0f78306e2312cd
  Author: Aaditya <Aaditya.AlokDeshpande at amd.com>
  Date:   2026-07-31 (Fri, 31 Jul 2026)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
    M llvm/lib/CodeGen/InlineSpiller.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.h

  Log Message:
  -----------
  Fix merge conflicts while rebasing on main.


Compare: https://github.com/llvm/llvm-project/compare/070b3e99ac75...829c8e9360ec

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