[all-commits] [llvm/llvm-project] e1823e: [X86] Fix miscompile of fptosi.sat.iN.f16 for NaN ...
Matt Arsenault via All-commits
all-commits at lists.llvm.org
Fri Jul 31 02:07:47 PDT 2026
Branch: refs/heads/users/arsenm/amdgpu/cvt-sr-pk-bf16-distinct-feature
Home: https://github.com/llvm/llvm-project
Commit: e1823e8b1778997d12ba947350190af5ee845ca9
https://github.com/llvm/llvm-project/commit/e1823e8b1778997d12ba947350190af5ee845ca9
Author: Nathaniel McCallum <nathaniel at mccallum.life>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/test/CodeGen/X86/fptosi-sat-scalar-f16.ll
M llvm/test/CodeGen/X86/fptosi-sat-scalar.ll
Log Message:
-----------
[X86] Fix miscompile of fptosi.sat.iN.f16 for NaN under avx512fp16 (#210556)
`X86TargetLowering::LowerFP_TO_INT_SAT` incorrectly lowered
`llvm.fptosi.sat.iN.f16` for N = 13, 14, 15, 16 under `avx512fp16`
codegen: NaN inputs produced the destination type's minimum value
instead of the 0 that the intrinsic's documented semantics require.
Vector forms that scalarize through this lowering are affected under
the same condition, applied per element. See the third commit message
for the full root-cause analysis and fix rationale.
---
Assisted-by: Claude (Anthropic)
Assisted-by: Codex (OpenAI)
The investigation, root-cause analysis, fix, and tests in this PR were
developed with substantial AI assistance (Claude), including four
independent AI-assisted review rounds (Codex). I reviewed and take
responsibility for all code, analysis, and claims in this PR, and can
answer questions about the reasoning above.
Commit: bcf20310bdafd37253c6c849cd9bd3ba5b79752f
https://github.com/llvm/llvm-project/commit/bcf20310bdafd37253c6c849cd9bd3ba5b79752f
Author: Jakob Koschel <jakobkoschel at google.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M compiler-rt/test/cfi/anon-namespace.cpp
M compiler-rt/test/cfi/bad-cast.cpp
M compiler-rt/test/cfi/base-derived-destructor.cpp
M compiler-rt/test/cfi/cross-dso-diagnostic.cpp
M compiler-rt/test/cfi/cross-dso/icall/diag.cpp
M compiler-rt/test/cfi/cross-dso/icall/icall-from-dso.cpp
M compiler-rt/test/cfi/cross-dso/icall/icall.cpp
M compiler-rt/test/cfi/cross-dso/simple-fail.cpp
M compiler-rt/test/cfi/cross-dso/target_out_of_bounds.cpp
M compiler-rt/test/cfi/icall/bad-signature.c
M compiler-rt/test/cfi/lit.cfg.py
M compiler-rt/test/cfi/mfcall.cpp
M compiler-rt/test/cfi/multiple-inheritance.cpp
M compiler-rt/test/cfi/nvcall.cpp
M compiler-rt/test/cfi/overwrite.cpp
M compiler-rt/test/cfi/simple-fail.cpp
M compiler-rt/test/cfi/target_uninstrumented.cpp
M compiler-rt/test/cfi/vdtor.cpp
Log Message:
-----------
[ubsan] Test CFI summaries globally (#206434)
Always enable report_error_type=1 and print_summary=1 for CFI tests, and
update existing tests to check for cfi-bad-type. This allows us to
verify summary output comprehensively across the test suite.
This is a prerequisite for the change to the UBSan summary for CFI in
https://github.com/llvm/llvm-project/pull/203341.
Assisted-by: Automated tooling, human reviewed.
Commit: 5eb4272b04144bded2ca1819c2d93b1cd4f1a26b
https://github.com/llvm/llvm-project/commit/5eb4272b04144bded2ca1819c2d93b1cd4f1a26b
Author: Kareem Ergawy <kergawy at nvidia.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/test/Fir/Todo/select_case_with_character.fir
M flang/test/Fir/convert-to-llvm-invalid.fir
M flang/test/Fir/convert-to-llvm.fir
Log Message:
-----------
[flang][CodeGen] Replace fir.select* FIR-to-LLVM patterns with stubs that emit conversion errors (#212978)
`fir.select`, `fir.select_case`, `fir.select_rank`, and
`fir.select_type` are lowered to cf.* earlier in the pipeline
(`--fir-select-ops-conversion` and `--fir-polymorphic-op`). Their
FIR-to-LLVM conversion patterns are dead in a correct pipeline. Replace
them with a single templated stub
`SelectShouldHaveBeenConvertedStub<OP>` that emits `"'fir.<op>' op
should have already been converted"` and fails legalization, so running
`--fir-to-llvm-ir` standalone on stale IR reports a clear diagnostic
instead of "unable to legalize".
`Fir/convert-to-llvm.fir`'s six select* test blocks are removed (the
lowering no longer runs; CF-level coverage lives in
`Fir/SelectOpsConversion/`). `Fir/convert-to-llvm-invalid.fir` gains a
stub-error test per op. `Fir/Todo/select_case_with_character.fir` is
retargeted to check the equivalent diagnostic now emitted by
`--fir-select-ops-conversion`.
Co-Authored-By: Claude Sonnet 4.6 (1M context) <noreply at anthropic.com>
PR Stack:
* https://github.com/llvm/llvm-project/pull/212977
* ▶️ https://github.com/llvm/llvm-project/pull/212978
Co-authored-by: Claude Sonnet 4.6 (1M context) <noreply at anthropic.com>
Commit: 2897ee1dbbbfb2d28ba23105b85697824b4a98a5
https://github.com/llvm/llvm-project/commit/2897ee1dbbbfb2d28ba23105b85697824b4a98a5
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/docs/AMDGPUMemoryModel.md
Log Message:
-----------
[AMDGPU][Docs] Memory Model: Refactor location-order to cover reads (#213044)
This shouldn't change anything semantically, only make the spec
(a) closer to the Vulkan spec, which includes reads in their location-ordered
relation: https://docs.vulkan.org/spec/latest/appendices/memorymodel.html#memory-model-location-ordered
(b) more uniform: this way, the may-see constraints are the same as the vanilla
LLVM constraints, only with all occurrences of "happens-before" replaced by
"location-ordered before".
Commit: a3ae1e0a8d5edaebe9e934e69fc4df84ed89d365
https://github.com/llvm/llvm-project/commit/a3ae1e0a8d5edaebe9e934e69fc4df84ed89d365
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
Log Message:
-----------
[clang][bytecode][NFC] Enforce internal linkage (#213208)
For a struct and a function.
Commit: 21b0fc84c2f5fac1d3f763cfa581762684ad2a89
https://github.com/llvm/llvm-project/commit/21b0fc84c2f5fac1d3f763cfa581762684ad2a89
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
Log Message:
-----------
[clang][bytecode][NFC] Remove redundant casts (#213210)
Commit: 99b3c767c34a04af0a2bbb1fd41bf1b2cb62b331
https://github.com/llvm/llvm-project/commit/99b3c767c34a04af0a2bbb1fd41bf1b2cb62b331
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
M llvm/test/CodeGen/RISCV/branch-on-zero.ll
M llvm/test/Transforms/IndVarSimplify/ARM/code-size.ll
M llvm/test/Transforms/IndVarSimplify/replace-loop-exit-folds.ll
M llvm/test/Transforms/LoopIdiom/basic.ll
M llvm/test/Transforms/LoopStrengthReduce/AArch64/expand-ptrtoaddr-reuse-ptrtoint.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-metadata.ll
M llvm/test/Transforms/LoopVectorize/opaque-ptr.ll
M llvm/unittests/Transforms/Utils/ScalarEvolutionExpanderTest.cpp
Log Message:
-----------
[Analysis] Optimise mul(const, (udiv %n, const)) during SCEV expansion (#212769)
We sometimes see SCEV expansions like this:
%lshr = lshr i64 %n, 2
%shl = shl i64 %lshr, 2
which originate from SCEV mul and udiv expressions:
mul(4, udiv(%n, 4))
that both share the same multiplicand, divisor. The instcombine pass
normally canonicalises this into
%and = and %n, -4
which is the final IR typically seen by the backend. In the case of SCEV
expansion during a pass like the loop vectoriser, instcombine does clean
this up. However, before this is cleaned up it will lead to
over-estimation of costs of SCEV checks, since the shifts are costed
separately and added up. It doesn't seem like there is an easy way to
look at the use count of a SCEV node in the SCEVExpander code. However,
I think for simple cases like this it's always beneficial to fold them
even if there are multiple uses of the SCEV udiv because we're dropping
both shifts.
Commit: 9d1018038c01d12801ccca9da5e6b5589989750a
https://github.com/llvm/llvm-project/commit/9d1018038c01d12801ccca9da5e6b5589989750a
Author: Lukas Sommer <lukas.sommer at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/RegAllocGreedy.cpp
A llvm/test/CodeGen/AMDGPU/greedy-wwm-copy-prologue-assert.mir
Log Message:
-----------
[RegAlloc] Avoid split past block-prologue interference (#209704)
`leaveIntvAtTop` skips the target-specific block prologue when
determining the insertion point.
If the block prologue itself contains an instruction that interferes
with the interval, we must leave the interval before the block,
otherwise we will hit an assertion in `splitLiveThroughBlock`.
---------
Signed-off-by: Lukas Sommer <lukas.sommer at amd.com>
Commit: 28896ffcde9a773361e5d61191ebc2100abf5bcf
https://github.com/llvm/llvm-project/commit/28896ffcde9a773361e5d61191ebc2100abf5bcf
Author: Benedek Kaibas <82393336+benedekaibas at users.noreply.github.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/test/Analysis/dangling-ptr-deref.cpp
M clang/test/Analysis/lifetime-bound.cpp
Log Message:
-----------
[analyzer][NFC] Add test cases for the lifetime test suite (#212254)
During the development of the lifetime checkers I had many important
test cases saved locally and were never imported to the test files of
the checkers. This PR adds those missing test cases to the test files.
By adding these test cases it helps tracking the state of the lifetime
checkers and what improvements they need in order to have better
coverage and reduce the false positive rate.
*AI policy*: During the development I have consulted with claude sonnet
5 to list me test case scenarios it thinks are useful and then reviewed
its feedback and implemented/wrote those test cases by myself. Since
some of the test cases are edge cases I wanted to make sure the
implementation is on the right track.
Commit: 5eb876fcaf460a9ee1dac9490b4b2871674b80ec
https://github.com/llvm/llvm-project/commit/5eb876fcaf460a9ee1dac9490b4b2871674b80ec
Author: Benedek Kaibas <82393336+benedekaibas at users.noreply.github.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/include/clang/StaticAnalyzer/Core/BugReporter/BugReporterVisitors.h
M clang/include/clang/StaticAnalyzer/Core/BugReporter/Z3CrosscheckVisitor.h
M clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/RetainCountChecker/RetainCountDiagnostics.cpp
M clang/lib/StaticAnalyzer/Checkers/VAListChecker.cpp
M clang/lib/StaticAnalyzer/Core/BugReporter.cpp
M clang/lib/StaticAnalyzer/Core/BugReporterVisitors.cpp
M clang/lib/StaticAnalyzer/Core/Z3CrosscheckVisitor.cpp
Log Message:
-----------
[analyzer][NFC] Match the parameters order of getEndPath and finalizeVisitor with VisitNode (#212883)
Currently the ordering of the parameters in `getEndPath` and
`finalizeVisitor` functions does not match the declaration of the
`VisitNode` function. This PR resolves it by reordering the parameters
among these functions to be consistent.
Commit: 2b4f6c42a7dbc8b28c71a334a9fbecce99b68eaf
https://github.com/llvm/llvm-project/commit/2b4f6c42a7dbc8b28c71a334a9fbecce99b68eaf
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx13.cl
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll
Log Message:
-----------
AMDGPU: Add missing mqsad-pk-insts to gfx13 frontend feature map (#213124)
fillAMDGCNFeatureMap omitted mqsad-pk-insts for gfx1310/gfx13-generic,
so clang wrongly rejected __builtin_amdgcn_mqsad_pk_u16_u8 on those
targets even though the backend enables the feature. Add it to the gfx13 case.
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: df81098826f9b45df3cbe2f29af3c44d69d5851a
https://github.com/llvm/llvm-project/commit/df81098826f9b45df3cbe2f29af3c44d69d5851a
Author: Sergey Shcherbinin <sscherbinin at nvidia.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
A llvm/test/tools/llvm-profgen/X86/first-loadable-address.test
M llvm/tools/llvm-profgen/ProfiledBinary.cpp
Log Message:
-----------
[llvm-profgen] Preserve zero-valued first PT_LOAD address (#212258)
FirstLoadableAddress was initialized with if (!FirstLoadableAddress), so
a valid first PT_LOAD at vaddr 0 was treated as unset and overwritten by
a later segment. Track whether the first loadable segment has been seen
instead.
Assisted by GPT-5
Commit: 4fbad31a8adf437e1d0f1307ff4c26a248462b09
https://github.com/llvm/llvm-project/commit/4fbad31a8adf437e1d0f1307ff4c26a248462b09
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
M mlir/test/Conversion/SPIRVToLLVM/arithmetic-ops-to-llvm.mlir
Log Message:
-----------
[mlir][SPIR-V] Add SPIRVToLLVM conversions for FMod and SMod (#206933)
Commit: 814c0e672dfc81ae02a0772879f993a57bdbc1ad
https://github.com/llvm/llvm-project/commit/814c0e672dfc81ae02a0772879f993a57bdbc1ad
Author: Jeremy Johnson <jeremy.johnson at arm.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
Log Message:
-----------
[mlir][tosa] Switch matmul_t output to bf16 from fp16 (#212970)
Note that this implements the TOSA specification change:
https://github.com/arm/tosa-specification/pull/67
---------
Signed-off-by: Jeremy Johnson <jeremy.johnson at arm.com>
Commit: 9b734e25473bc9e299a4b58575b9b0e618925b78
https://github.com/llvm/llvm-project/commit/9b734e25473bc9e299a4b58575b9b0e618925b78
Author: Siyi Xu <siyix at nvidia.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/BasicPtxBuilderInterface.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/BasicPtxBuilderInterface.cpp
M mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir
Log Message:
-----------
[mlir][NVVM] Add memory clobber support to inline_ptx and BasicPtxBui… (#212937)
PTX with memory side effects (stores, atomics, mbarrier operations with
acquire/release semantics) emitted through `nvvm.inline_ptx` lowers to
`llvm.inline_asm` with register constraints only. Without a `~{memory}`
clobber, LLVM may reorder memory accesses across the inline assembly.
There was no way to express the clobber through this op or the
`BasicPtxBuilderInterface` machinery.
This patch adds, as discussed with @grypp:
- A `hasMemoryClobber` interface method (default `false`) on
`BasicPtxBuilderOpInterface`; when it returns `true`, `PtxBuilder`
appends `~{memory}` to the constraints of the generated inline assembly,
after all register constraints and tied indices.
- An opt-in `memory_clobber` boolean attribute (default `false`) on
`nvvm.inline_ptx` exposing this. Existing behavior is unchanged unless
the attribute is set to `true`.
For example:
```mlir
nvvm.inline_ptx "mbarrier.init.b64 [$0], $1;" ro(%p, %c : !llvm.ptr, i32) memory_clobber = true
```
now lowers to inline assembly with constraints `"l,r,~{memory}"`.
Tests: constraint emission with/without the attribute, combination with
predicate (`"l,r,b,~{memory}"`), read-write operands with tied indices
(`"=f,=f,r,r,0,1,~{memory}"`), and the no-operand case (`"~{memory}"`).
The op documentation's first example (mbarrier.init) is updated to show
correct usage.
Commit: 65cd5388148e798798507dd9301e1dfe564f8ab3
https://github.com/llvm/llvm-project/commit/65cd5388148e798798507dd9301e1dfe564f8ab3
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/VPlan/icmp-uniforms.ll
M llvm/test/Transforms/LoopVectorize/bsd_regex.ll
M llvm/test/Transforms/LoopVectorize/extract-last-veclane.ll
M llvm/test/Transforms/LoopVectorize/float-induction.ll
M llvm/test/Transforms/LoopVectorize/forked-pointers.ll
M llvm/test/Transforms/LoopVectorize/histograms.ll
M llvm/test/Transforms/LoopVectorize/if-conversion-nest.ll
M llvm/test/Transforms/LoopVectorize/if-conversion.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-2.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-pred-stores.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization-2.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/loop-scalars.ll
M llvm/test/Transforms/LoopVectorize/multiple-address-spaces.ll
M llvm/test/Transforms/LoopVectorize/non-const-n.ll
M llvm/test/Transforms/LoopVectorize/phi-cost.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-cond.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
M llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
M llvm/test/Transforms/LoopVectorize/reduction.ll
M llvm/test/Transforms/LoopVectorize/runtime-check.ll
M llvm/test/Transforms/LoopVectorize/scalable-inductions.ll
M llvm/test/Transforms/LoopVectorize/scalar_after_vectorization.ll
M llvm/test/Transforms/LoopVectorize/store-shuffle-bug.ll
M llvm/test/Transforms/LoopVectorize/trunc-reductions.ll
M llvm/test/Transforms/LoopVectorize/vector-geps.ll
Log Message:
-----------
[LV][NFC] Remove almost all remaining instcombine passes in RUN lines (#213067)
Commit: 4120b5f5a3770cea9b26063eaca3d18153307961
https://github.com/llvm/llvm-project/commit/4120b5f5a3770cea9b26063eaca3d18153307961
Author: Yingying Wang <3171290993 at qq.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
A llvm/test/CodeGen/RISCV/frame-base-addr-reuse.mir
M llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv32.mir
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/zdinx-large-spill.mir
Log Message:
-----------
[RISCV] Deduplicate frame base address materializations for large stack frames (#211748)
For large stack frames, `eliminateFrameIndex` materializes the frame
base with a `LUI+ADD` sequence for every frame index access. When
multiple accesses share the same 4096-aligned base, this generates
redundant `LUI+ADD` sequences that `MachineLateInstrsCleanup` cannot
eliminate because it operates on individual instructions.
Introduce `PseudoAddUpperImm` to represent the `LUI+ADD` sequence as a
single pseudo instruction during frame index elimination. This enables
`MachineLateInstrsCleanup` to CSE identical frame base computations
within a basic block. The pseudo is expanded back to `LUI+ADD` in
`RISCVPostRAExpandPseudo`.
This patch improves SPEC CPU2026 `cactus` performance by 18% on the
SpaceMit K3 processor.
### Example
Before :
```assembly
lui a0, 4
add a0, a0, sp
fsd fa3, -1976(a0)
lui a0, 4 # redundant
add a0, a0, sp # redundant
ld s10, -160(a0)
```
After :
```assembly
lui a0, 4
add a0, a0, sp
fsd fa3, -1976(a0)
ld s10, -160(a0) # reuses a0
```
Commit: 6f9c189f738d47c7ad80f6bdf928fea441bfa8d6
https://github.com/llvm/llvm-project/commit/6f9c189f738d47c7ad80f6bdf928fea441bfa8d6
Author: Jakob Koschel <jakobkoschel at google.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M compiler-rt/lib/ubsan/ubsan_checks.inc
M compiler-rt/lib/ubsan/ubsan_handlers.cpp
M compiler-rt/lib/ubsan/ubsan_handlers_cxx.cpp
M compiler-rt/test/cfi/anon-namespace.cpp
M compiler-rt/test/cfi/bad-cast.cpp
M compiler-rt/test/cfi/base-derived-destructor.cpp
M compiler-rt/test/cfi/cross-dso-diagnostic.cpp
M compiler-rt/test/cfi/cross-dso/icall/diag.cpp
M compiler-rt/test/cfi/cross-dso/icall/icall-from-dso.cpp
M compiler-rt/test/cfi/cross-dso/icall/icall.cpp
M compiler-rt/test/cfi/cross-dso/simple-fail.cpp
M compiler-rt/test/cfi/cross-dso/target_out_of_bounds.cpp
M compiler-rt/test/cfi/icall/bad-signature.c
M compiler-rt/test/cfi/mfcall.cpp
M compiler-rt/test/cfi/multiple-inheritance.cpp
M compiler-rt/test/cfi/nvcall.cpp
M compiler-rt/test/cfi/overwrite.cpp
M compiler-rt/test/cfi/simple-fail.cpp
M compiler-rt/test/cfi/target_uninstrumented.cpp
M compiler-rt/test/cfi/vdtor.cpp
Log Message:
-----------
[ubsan] Report specific CFI checks in UBSan summaries (#213224)
Instead of reporting generic `cfi-bad-type` in UBSan summaries for CFI
failures, report the specific CFI check kind (e.g., `cfi-vcall`,
`cfi-nvcall`, `cfi-icall`, `cfi-mfcall`, `cfi-derived-cast`,
`cfi-unrelated-cast`).
This is done by splitting CFIBadType into specific error types in
ubsan_checks.inc, and updating the handlers to report the appropriate
ErrorType based on the check kind. The suppression flag name for all of
them remains `cfi` to maintain backward compatibility.
Also replaces cfi-bad-type expectations in the existing tests.
Assisted-by: Automated tooling, human reviewed.
Commit: 5808b2d513d1baa3355d078193006ab9384a4ee3
https://github.com/llvm/llvm-project/commit/5808b2d513d1baa3355d078193006ab9384a4ee3
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/test/CodeGen/SPIRV/atomicrmw-uinc-udec-wrap.ll
Log Message:
-----------
[SPIR-V] Expand atomicrmw nand through compare-exchange (#213217)
Commit: 2bd28bd97111757b526746f049c9b4411188240e
https://github.com/llvm/llvm-project/commit/2bd28bd97111757b526746f049c9b4411188240e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-31 (Fri, 31 Jul 2026)
Changed paths:
M clang/include/clang/StaticAnalyzer/Core/BugReporter/BugReporterVisitors.h
M clang/include/clang/StaticAnalyzer/Core/BugReporter/Z3CrosscheckVisitor.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/RetainCountChecker/RetainCountDiagnostics.cpp
M clang/lib/StaticAnalyzer/Checkers/VAListChecker.cpp
M clang/lib/StaticAnalyzer/Core/BugReporter.cpp
M clang/lib/StaticAnalyzer/Core/BugReporterVisitors.cpp
M clang/lib/StaticAnalyzer/Core/Z3CrosscheckVisitor.cpp
M clang/test/Analysis/dangling-ptr-deref.cpp
M clang/test/Analysis/lifetime-bound.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx13.cl
M compiler-rt/lib/ubsan/ubsan_checks.inc
M compiler-rt/lib/ubsan/ubsan_handlers.cpp
M compiler-rt/lib/ubsan/ubsan_handlers_cxx.cpp
M compiler-rt/test/cfi/anon-namespace.cpp
M compiler-rt/test/cfi/bad-cast.cpp
M compiler-rt/test/cfi/base-derived-destructor.cpp
M compiler-rt/test/cfi/cross-dso-diagnostic.cpp
M compiler-rt/test/cfi/cross-dso/icall/diag.cpp
M compiler-rt/test/cfi/cross-dso/icall/icall-from-dso.cpp
M compiler-rt/test/cfi/cross-dso/icall/icall.cpp
M compiler-rt/test/cfi/cross-dso/simple-fail.cpp
M compiler-rt/test/cfi/cross-dso/target_out_of_bounds.cpp
M compiler-rt/test/cfi/icall/bad-signature.c
M compiler-rt/test/cfi/lit.cfg.py
M compiler-rt/test/cfi/mfcall.cpp
M compiler-rt/test/cfi/multiple-inheritance.cpp
M compiler-rt/test/cfi/nvcall.cpp
M compiler-rt/test/cfi/overwrite.cpp
M compiler-rt/test/cfi/simple-fail.cpp
M compiler-rt/test/cfi/target_uninstrumented.cpp
M compiler-rt/test/cfi/vdtor.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/test/Fir/Todo/select_case_with_character.fir
M flang/test/Fir/convert-to-llvm-invalid.fir
M flang/test/Fir/convert-to-llvm.fir
M llvm/docs/AMDGPUMemoryModel.md
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
A llvm/test/CodeGen/AMDGPU/greedy-wwm-copy-prologue-assert.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll
M llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/branch-on-zero.ll
A llvm/test/CodeGen/RISCV/frame-base-addr-reuse.mir
M llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv32.mir
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/zdinx-large-spill.mir
M llvm/test/CodeGen/SPIRV/atomicrmw-uinc-udec-wrap.ll
A llvm/test/CodeGen/X86/fptosi-sat-scalar-f16.ll
M llvm/test/CodeGen/X86/fptosi-sat-scalar.ll
M llvm/test/Transforms/IndVarSimplify/ARM/code-size.ll
M llvm/test/Transforms/IndVarSimplify/replace-loop-exit-folds.ll
M llvm/test/Transforms/LoopIdiom/basic.ll
M llvm/test/Transforms/LoopStrengthReduce/AArch64/expand-ptrtoaddr-reuse-ptrtoint.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll
M llvm/test/Transforms/LoopVectorize/VPlan/icmp-uniforms.ll
M llvm/test/Transforms/LoopVectorize/bsd_regex.ll
M llvm/test/Transforms/LoopVectorize/extract-last-veclane.ll
M llvm/test/Transforms/LoopVectorize/float-induction.ll
M llvm/test/Transforms/LoopVectorize/forked-pointers.ll
M llvm/test/Transforms/LoopVectorize/histograms.ll
M llvm/test/Transforms/LoopVectorize/if-conversion-nest.ll
M llvm/test/Transforms/LoopVectorize/if-conversion.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-2.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-metadata.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-pred-stores.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization-2.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/loop-scalars.ll
M llvm/test/Transforms/LoopVectorize/multiple-address-spaces.ll
M llvm/test/Transforms/LoopVectorize/non-const-n.ll
M llvm/test/Transforms/LoopVectorize/opaque-ptr.ll
M llvm/test/Transforms/LoopVectorize/phi-cost.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-cond.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
M llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
M llvm/test/Transforms/LoopVectorize/reduction.ll
M llvm/test/Transforms/LoopVectorize/runtime-check.ll
M llvm/test/Transforms/LoopVectorize/scalable-inductions.ll
M llvm/test/Transforms/LoopVectorize/scalar_after_vectorization.ll
M llvm/test/Transforms/LoopVectorize/store-shuffle-bug.ll
M llvm/test/Transforms/LoopVectorize/trunc-reductions.ll
M llvm/test/Transforms/LoopVectorize/vector-geps.ll
A llvm/test/tools/llvm-profgen/X86/first-loadable-address.test
M llvm/tools/llvm-profgen/ProfiledBinary.cpp
M llvm/unittests/Transforms/Utils/ScalarEvolutionExpanderTest.cpp
M mlir/include/mlir/Dialect/LLVMIR/BasicPtxBuilderInterface.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
M mlir/lib/Dialect/LLVMIR/IR/BasicPtxBuilderInterface.cpp
M mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir
M mlir/test/Conversion/SPIRVToLLVM/arithmetic-ops-to-llvm.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
Log Message:
-----------
Merge branch 'main' into users/arsenm/amdgpu/cvt-sr-pk-bf16-distinct-feature
Compare: https://github.com/llvm/llvm-project/compare/d78ca8ddc295...2bd28bd97111
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