[all-commits] [llvm/llvm-project] 53e16d: [CIR] Pointer and vptr width from a CIR-native dat...
Akshay K via All-commits
all-commits at lists.llvm.org
Thu Jul 30 16:50:34 PDT 2026
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 53e16d7708c39ecc03f97d32d1db9afdd355deca
https://github.com/llvm/llvm-project/commit/53e16d7708c39ecc03f97d32d1db9afdd355deca
Author: Akshay K <iit.akshay at gmail.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
A clang/include/clang/CIR/CIRDataLayoutSpec.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
A clang/lib/CIR/CodeGen/CIRDataLayoutSpec.cpp
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
M clang/lib/CIR/CodeGen/CMakeLists.txt
M clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
A clang/test/CIR/CodeGen/pointer-width-32bit.cpp
A clang/test/CIR/IR/pointer-data-layout.cir
A clang/test/CIR/Tools/pointer-width-from-triple.cir
M clang/tools/cir-translate/cir-translate.cpp
Log Message:
-----------
[CIR] Pointer and vptr width from a CIR-native data-layout entry (#204185)
PointerType and VPtrType have hard-coded sizes and alignments of 64/8
bits. On targets with 32-bit pointers (e.g., nvptx, spirv32), this trips
the record layout builder. Any record containing a pointer hit the
insertPadding assertion (offset >= size)
because the pointer was sized at 8 bytes while the following field was
placed at the AST-mandated 4-byte offset.
### Changes:
- CIRGenerator: attaches a CIR-native cir.ptr data-layout entry at
module setup, storing {size-in-bits, abi-align-in-bits} read
from the target DataLayout (only for the default address space).
- CIRTypes: PointerType reads its size/alignment from that entry
(falling back to 64/8 when absent); VPtrType routes through a cir.ptr so
it picks up the same width.
- LowerToLLVM: strips the cir.ptr entry during CIR→LLVM lowering, since
cir.ptr has no meaning in LLVM IR.
- Unit test: checking 4-byte pointer/vptr layout on nvptx, verified
across CIR, CIR→LLVM.
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