[all-commits] [llvm/llvm-project] cf6335: [X86] Lower scalar bf16 arithmetic on AVX10.2 via ...

[tfzee via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cf6335b275a996adff8334cb35245480ece481e1
      https://github.com/llvm/llvm-project/commit/cf6335b275a996adff8334cb35245480ece481e1
  Author: tfzee <tim.ziegler at intel.com>
  Date:   2026-07-30 (Thu, 30 Jul 2026)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    A llvm/test/CodeGen/X86/avx10_2bf16-arith-scalar.ll
    M llvm/test/CodeGen/X86/avx10_2bf16-fma.ll

  Log Message:
  -----------
  [X86] Lower scalar bf16 arithmetic on AVX10.2 via packed ops (#212245)

Currently basic(fadd/fsub/fmul/fdiv/fsqrt/fma) bf16 operations, as they
are not natively supported, are expanded to f32 operations.
However with AVX10.2 there are packed versions for these operations
which should be used instead and are enabled with this PR.

Since there is no native bf16 register class I instead go through f16
since it matches its size and register class.
This conversion will end up getting optimized away leaving only the
intended packed operation.


I used AI to double check and expand on comments.



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