[all-commits] [llvm/llvm-project] f08211: [AArch64] Remove assembler-only register classes (...

[Cullen Rhodes via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f08211e71e8fec39ff64facef84cb104ea8119e7
      https://github.com/llvm/llvm-project/commit/f08211e71e8fec39ff64facef84cb104ea8119e7
  Author: Cullen Rhodes <cullen.rhodes at arm.com>
  Date:   2026-07-30 (Thu, 30 Jul 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/test/CodeGen/AArch64/fmlal-loreg.ll
    M llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
    M llvm/test/TableGen/aarch64-register-info-stats.td

  Log Message:
  -----------
  [AArch64] Remove assembler-only register classes (#211527)

ZPRMul2, ZPRMul4 and PPRMul2 register classes are used solely by the asm
parser to validate other register classes (ZPR2Mul2, ZPR4Mul4,
PPR2Mul2). Since they're real register classes TableGen synthesizes
numerous intersection classes and pressure sets from them.

Removing them and validating the constraint directly in the assembly
parser reduces:

- generated register classes: 521 -> 403 (~22%)
- generated pressure sets: 188 -> 60 (68%)
- generated register-info size: 11.9 MB -> 9.1 MB (23%)

Also improves CTMark geomean -0.23% on stage1-aarch64-O3.

https://llvm-compile-time-tracker.com/compare.php?from=a90dbb43cd67856f681feba82d51a0d5fbcae3c2&to=5565d4907cdf960cc142a7507f16e551f51919b0&stat=instructions%3Au

Assisted-by: codex



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