[all-commits] [llvm/llvm-project] 806935: AMDGPU: Handle more TargetParser queries in tableg...
Pengcheng Wang via All-commits
all-commits at lists.llvm.org
Wed Jul 29 23:52:04 PDT 2026
Branch: refs/heads/users/wangpc-pp/spr/riscv-support-codegen-of-zilx-extension
Home: https://github.com/llvm/llvm-project
Commit: 806935948ba3532ba559d614f97cc7688d9cb2ee
https://github.com/llvm/llvm-project/commit/806935948ba3532ba559d614f97cc7688d9cb2ee
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/test/Driver/amdgpu-mcpu.cl
M clang/test/Misc/target-invalid-cpu-note/amdgcn.c
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td
M llvm/lib/Target/AMDGPU/GCNProcessors.td
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/test/CodeGen/AMDGPU/hsa-default-device.ll
M llvm/test/TableGen/AMDGPUTargetDefErrors.td
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
Log Message:
-----------
AMDGPU: Handle more TargetParser queries in tablegen (#212357)
Previously we had various enum switches. Start generated tables
indexed by enums. Avoid some special cases by defining the dummy
"generic" and "generic-hsa" targets as real processors.
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: e1f93b045410f3872d3524d91d71ba5eceda0030
https://github.com/llvm/llvm-project/commit/e1f93b045410f3872d3524d91d71ba5eceda0030
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/lib/Target/MSP430/MSP430Subtarget.cpp
Log Message:
-----------
MSP430: Mark more generic libgcc functions as available (#212927)
The generic soft-float, conversion, comparison and integer helper
routines (__addsf3, __divli's __divsi3, __ashlsi3, ...) exist in the
MSP430 libgcc port alongside the preferred __mspabi_* variants. They
were previously removed to force selection of the __mspabi_* names, back
when only one implementation per libcall could be recorded.
Stop hiding them: only __lshrsi3 stays excluded, since the MSP430 libgcc
port provides the 32-bit logical right shift solely under __mspabi_srll
and never defines a generic __lshrsi3.
Repost of #210962
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 7330a8ddc106483031a67d5a74215fc3e1509905
https://github.com/llvm/llvm-project/commit/7330a8ddc106483031a67d5a74215fc3e1509905
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td
M llvm/lib/Target/AMDGPU/GCNProcessors.td
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
Log Message:
-----------
AMDGPU: TableGen subarch to major subarch table (#212605)
Replace the hand-written AMDGPUMajorFamilies array with a
generated lookup table. Adds a special case for the major
arches missing a concrete generic target definition (we probably
should just define those to avoid this).
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: 26d08c22c68bbb9e644012c4e5cae32f68d897cb
https://github.com/llvm/llvm-project/commit/26d08c22c68bbb9e644012c4e5cae32f68d897cb
Author: saloni-shinde-Q <saloshin at qti.qualcomm.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
M llvm/test/MC/RISCV/rv32d-invalid.s
M llvm/test/MC/RISCV/rv32dc-invalid.s
M llvm/test/MC/RISCV/rv32f-invalid.s
M llvm/test/MC/RISCV/rv32fc-invalid.s
M llvm/test/MC/RISCV/rv32q-invalid.s
M llvm/test/MC/RISCV/rv32zdinx-invalid.s
M llvm/test/MC/RISCV/rv32zfh-invalid.s
M llvm/test/MC/RISCV/rv32zfinx-invalid.s
M llvm/test/MC/RISCV/rv32zhinx-invalid.s
M llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
M llvm/test/MC/RISCV/rv64d-invalid.s
M llvm/test/MC/RISCV/rv64f-invalid.s
M llvm/test/MC/RISCV/rv64q-invalid.s
M llvm/test/MC/RISCV/rv64xtheadfmemidx-invalid.s
M llvm/test/MC/RISCV/rv64zdinx-invalid.s
M llvm/test/MC/RISCV/rv64zfh-invalid.s
M llvm/test/MC/RISCV/rv64zfinx-invalid.s
M llvm/test/MC/RISCV/rv64zhinx-invalid.s
M llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
M llvm/test/MC/RISCV/rvzfbfmin-invalid.s
M llvm/test/MC/RISCV/rvzfhmin-invalid.s
Log Message:
-----------
[RISCV][MC] Improve FPR Error Messages (#212492)
This patch improves the error messages for the following register classes:
1. FPR RegClasses (FPR16, FPR32, FPR64, FPR128, FPR256)
2. Compressed FPR RegClasses (FPR16C, FPR32C, FPR64C)
3. GPR-as-FPR classes used by Zfinx/Zdinx extensions (GPRAsFPR16, GPRAsFPR32, GPRF64AsFPR, GPRPairAsFPR).
---------
Co-authored-by: Saloni Shinde <saloshin at qti.qualcomm.com>
Commit: b42621f842571a92cec2961fa5c4fc518d4ca91a
https://github.com/llvm/llvm-project/commit/b42621f842571a92cec2961fa5c4fc518d4ca91a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
Log Message:
-----------
AMDGPU: TableGen the subarch to processor name mapping table (#212606)
Replace the hand-written AMDGPUSubArchNames array (SubArch -> canonical
GPU name) with a generated table.
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: 23a22244b099a9950a5f265460e392bc44beb3b4
https://github.com/llvm/llvm-project/commit/23a22244b099a9950a5f265460e392bc44beb3b4
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
A llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/features-info.ll
A llvm/test/MC/RISCV/zilx-invalid.s
A llvm/test/MC/RISCV/zilx-valid-rv32.s
A llvm/test/MC/RISCV/zilx-valid-rv64.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV][MC] Support experimental Zilx extension
This adds the MC support for `Zilx` (Indexed Integer Load Instructions)
extension.
Doc: https://github.com/riscv/riscv-zilx
Reviewers: topperc, tclin914, kito-cheng
Pull Request: https://github.com/llvm/llvm-project/pull/209419
Commit: 1f7706ec49bab6a638d64e39cc14071c50792e28
https://github.com/llvm/llvm-project/commit/1f7706ec49bab6a638d64e39cc14071c50792e28
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/test/Driver/amdgpu-mcpu.cl
M clang/test/Misc/target-invalid-cpu-note/amdgcn.c
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td
M llvm/lib/Target/AMDGPU/GCNProcessors.td
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/MSP430/MSP430Subtarget.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/test/CodeGen/AMDGPU/hsa-default-device.ll
M llvm/test/MC/RISCV/rv32d-invalid.s
M llvm/test/MC/RISCV/rv32dc-invalid.s
M llvm/test/MC/RISCV/rv32f-invalid.s
M llvm/test/MC/RISCV/rv32fc-invalid.s
M llvm/test/MC/RISCV/rv32q-invalid.s
M llvm/test/MC/RISCV/rv32zdinx-invalid.s
M llvm/test/MC/RISCV/rv32zfh-invalid.s
M llvm/test/MC/RISCV/rv32zfinx-invalid.s
M llvm/test/MC/RISCV/rv32zhinx-invalid.s
M llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
M llvm/test/MC/RISCV/rv64d-invalid.s
M llvm/test/MC/RISCV/rv64f-invalid.s
M llvm/test/MC/RISCV/rv64q-invalid.s
M llvm/test/MC/RISCV/rv64xtheadfmemidx-invalid.s
M llvm/test/MC/RISCV/rv64zdinx-invalid.s
M llvm/test/MC/RISCV/rv64zfh-invalid.s
M llvm/test/MC/RISCV/rv64zfinx-invalid.s
M llvm/test/MC/RISCV/rv64zhinx-invalid.s
M llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
M llvm/test/MC/RISCV/rvzfbfmin-invalid.s
M llvm/test/MC/RISCV/rvzfhmin-invalid.s
M llvm/test/TableGen/AMDGPUTargetDefErrors.td
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
Commit: 4a18e9d0d045068cb3f41d433addc849d5cd50d6
https://github.com/llvm/llvm-project/commit/4a18e9d0d045068cb3f41d433addc849d5cd50d6
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2026-07-30 (Thu, 30 Jul 2026)
Changed paths:
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/test/Driver/amdgpu-mcpu.cl
M clang/test/Misc/target-invalid-cpu-note/amdgcn.c
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td
M llvm/lib/Target/AMDGPU/GCNProcessors.td
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/MSP430/MSP430Subtarget.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/test/CodeGen/AMDGPU/hsa-default-device.ll
M llvm/test/MC/RISCV/rv32d-invalid.s
M llvm/test/MC/RISCV/rv32dc-invalid.s
M llvm/test/MC/RISCV/rv32f-invalid.s
M llvm/test/MC/RISCV/rv32fc-invalid.s
M llvm/test/MC/RISCV/rv32q-invalid.s
M llvm/test/MC/RISCV/rv32zdinx-invalid.s
M llvm/test/MC/RISCV/rv32zfh-invalid.s
M llvm/test/MC/RISCV/rv32zfinx-invalid.s
M llvm/test/MC/RISCV/rv32zhinx-invalid.s
M llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
M llvm/test/MC/RISCV/rv64d-invalid.s
M llvm/test/MC/RISCV/rv64f-invalid.s
M llvm/test/MC/RISCV/rv64q-invalid.s
M llvm/test/MC/RISCV/rv64xtheadfmemidx-invalid.s
M llvm/test/MC/RISCV/rv64zdinx-invalid.s
M llvm/test/MC/RISCV/rv64zfh-invalid.s
M llvm/test/MC/RISCV/rv64zfinx-invalid.s
M llvm/test/MC/RISCV/rv64zhinx-invalid.s
M llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
M llvm/test/MC/RISCV/rvzfbfmin-invalid.s
M llvm/test/MC/RISCV/rvzfhmin-invalid.s
M llvm/test/TableGen/AMDGPUTargetDefErrors.td
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
Log Message:
-----------
Rebase
Created using spr 1.3.6-beta.1
Compare: https://github.com/llvm/llvm-project/compare/36f00d050ab7...4a18e9d0d045
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