[all-commits] [llvm/llvm-project] d982be: [AMDGPU] Limit register pressure of pipelined loops

[hjagasiaAMD via All-commits]

  Branch: refs/heads/users/hjagasiaAMD/swp-4-rp-limit
  Home:   https://github.com/llvm/llvm-project
  Commit: d982be9a856be3bf508554d0684639b09ae3d2c4
      https://github.com/llvm/llvm-project/commit/d982be9a856be3bf508554d0684639b09ae3d2c4
  Author: Harsha Jagasia <harsha.jagasia at amd.com>
  Date:   2026-07-29 (Wed, 29 Jul 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    A llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-regpressure-retry.mir

  Log Message:
  -----------
  [AMDGPU] Limit register pressure of pipelined loops

Opt AMDGPU into the generic MachinePipeliner register-pressure detector via
shouldLimitRegPressure(), and supply an occupancy-aware verdict in
isScheduleRegPressureTooHigh(): reject a schedule whose SGPR or VGPR/AGPR
pressure would drop the kernel below its target occupancy, or exceed a
register class's addressability cap. On gfx90a+ VGPRs and AGPRs share one
register file, so their combined footprint is bounded together. These match
the limits GCNSchedStrategy enforces.



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