[all-commits] [llvm/llvm-project] 9cd13c: [X86] Remove TuningFastSHLDRotate from BMI2 target...

[222rohan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9cd13c11bacc9a5b83640a7168ab0f51160e4ee0
      https://github.com/llvm/llvm-project/commit/9cd13c11bacc9a5b83640a7168ab0f51160e4ee0
  Author: 222rohan <rohanshenoy405 at gmail.com>
  Date:   2026-07-29 (Wed, 29 Jul 2026)

  Changed paths:
    M llvm/lib/Target/X86/X86.td

  Log Message:
  -----------
  [X86] Remove TuningFastSHLDRotate from BMI2 targets (#211217)

This flag has no effect at `x86-64-v3` or `v4`. It only enables a pseudo
that lowers `rotl`/`rotr` by immediate to `shld $imm, %reg, %reg`, but a
higher-priority `RORX` pattern matches the same case and always wins the
iSel tie.

Both patterns match `rotl(GR64, imm)`; only their `AddedComplexity`
differs:

```
// X86InstrShiftRotate.td:507 -- SHLD-rotate pseudo, complexity 5
let Predicates = [HasFastSHLDRotate], AddedComplexity = 5, ... in {
  def SHLDROT64ri : ... [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$shamt)))]>;
}

// X86InstrShiftRotate.td:602 -- RORX pattern, complexity 10, only needs BMI2
let AddedComplexity = 10 in {
  def : Pat<(rotl GR64:$src, (i8 imm:$shamt)),
            (RORX64ri GR64:$src, (ROT64L2R_imm8 imm:$shamt))>;
}
```
LLVM's iSel always picks `RORX`, and it only requires BMI2, which is
part of `x86-64-v3` and up, so it is picked unconditionally on every
v3/v4 build regardless of `TuningFastSHLDRotate`.

No codegen change; existing lit tests unaffected.



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