[all-commits] [llvm/llvm-project] 1cfc77: [MIR2Vec] Handle registers without a register clas...

[Petr Kurapov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1cfc77fdd6368dd6527c620645ec6f351e1c658f
      https://github.com/llvm/llvm-project/commit/1cfc77fdd6368dd6527c620645ec6f351e1c658f
  Author: Petr Kurapov <petr.kurapov at gmail.com>
  Date:   2026-07-28 (Tue, 28 Jul 2026)

  Changed paths:
    M llvm/include/llvm/CodeGen/MIR2Vec.h
    M llvm/lib/CodeGen/MIR2Vec.cpp
    A llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_classless_vocab.json
    A llvm/test/CodeGen/MIR2Vec/classless-physreg.mir
    A llvm/test/CodeGen/MIR2Vec/classless-vreg.mir

  Log Message:
  -----------
  [MIR2Vec] Handle registers without a register class (#212280)

getRegisterOperandIndex() hit an llvm_unreachable for registers in no
register class. That is a supported outcome, not an error: tablegen
emits InvalidRegClassID for such registers and getMinimalPhysRegClass()
returns nullptr. It hits classless physregs (X86 $mxcsr/$fpcw, AMDGPU
$mode), which crashed any function with FP math, and generic vregs
before ISel, where MRI.getRegClass() asserts -- so use
getRegClassOrNull().

Return std::nullopt instead. Both callers already handle the analogous
NoRegister and stack-slot cases, so the vocabulary layout is unchanged.

We could avoid the special casing by adding a special value for such
registers. It would actually hold some meaningful information for
models. I didn't include it in this patch since it would require seed
vocab re-generation.



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