[all-commits] [llvm/llvm-project] 144595: [SelectionDAG][AArch64][X86] Don't scalarize vecto...

[guyfischman via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 144595f400eaa08691c8fda82b80e83329c779ed
      https://github.com/llvm/llvm-project/commit/144595f400eaa08691c8fda82b80e83329c779ed
  Author: guyfischman <138163913+guyfischman at users.noreply.github.com>
  Date:   2026-07-23 (Thu, 23 Jul 2026)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AArch64/smul_fix_sat.ll
    M llvm/test/CodeGen/AArch64/umul_fix_sat.ll
    M llvm/test/CodeGen/X86/smul_fix_sat.ll
    M llvm/test/CodeGen/X86/umul_fix_sat.ll
    M llvm/test/CodeGen/X86/vector-mulfix-legalize.ll

  Log Message:
  -----------
  [SelectionDAG][AArch64][X86] Don't scalarize vector smul.fix.sat/umul.fix.sat (#209351)

Vector SMULFIXSAT/UMULFIXSAT were not handled by expandFixedPointMul in
the vector legalizer (a FIXME) and were unrolled to per-lane scalar
code: a single <8 x i16> smul.fix.sat was ~100 instructions on both
AArch64 and x86.

Expand the saturating variants like the non-saturating ones, and build
the saturation clamp with SETCC + VSELECT for vector types so it stays
vectorized instead of being scalarized by SELECT_CC legalization. Scalar
lowering is unchanged: the clamp change is guarded on isVector(), so
scalar fixed-point codegen on every target is bit-identical.

Additionally custom-lower SMULFIXSAT on AArch64 for scale == eltbits-1,
which is exactly sqdmulh, to a single instruction.

To the FIXME note - results in a ~12x speedup over the unroll fallback.

AI was used in the making of this PR, and if its feedback is to be
believed, this PR is a masterpiece of engineering.

Fixes #209334



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