[all-commits] [llvm/llvm-project] a64f74: [SPIR-V][NewPM] Register SPIRVStructurizer with th...
Matt Arsenault via All-commits
all-commits at lists.llvm.org
Mon Jul 20 11:05:30 PDT 2026
Branch: refs/heads/users/arsenm/runtime-libcalls/composable-predicates
Home: https://github.com/llvm/llvm-project
Commit: a64f7412551ae63a49dd8617f93ab89878288879
https://github.com/llvm/llvm-project/commit/a64f7412551ae63a49dd8617f93ab89878288879
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp
M llvm/test/CodeGen/SPIRV/structurizer/HLSLControlFlowHint-pass-check.ll
Log Message:
-----------
[SPIR-V][NewPM] Register SPIRVStructurizer with the new pass manager (#209965)
Commit: 9d2e7e6836beadbe63380f64c716df2c086ff2ea
https://github.com/llvm/llvm-project/commit/9d2e7e6836beadbe63380f64c716df2c086ff2ea
Author: Lukas <43409484+hertelukas at users.noreply.github.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
M llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
M llvm/lib/Transforms/Utils/FixIrreducible.cpp
M llvm/lib/Transforms/Utils/UnifyLoopExits.cpp
M llvm/test/Transforms/FixIrreducible/bug45623.ll
M llvm/test/Transforms/FixIrreducible/multiedge.ll
M llvm/test/Transforms/FixIrreducible/nested.ll
M llvm/test/Transforms/FixIrreducible/switch.ll
M llvm/test/Transforms/FixIrreducible/unreachable.ll
M llvm/test/Transforms/FixIrreducible/unsupported-terminator.ll
M llvm/test/Transforms/UnifyLoopExits/basic.ll
M llvm/test/Transforms/UnifyLoopExits/integer_guards.ll
M llvm/test/Transforms/UnifyLoopExits/multiedge.ll
M llvm/test/Transforms/UnifyLoopExits/nested.ll
M llvm/test/Transforms/UnifyLoopExits/restore-ssa.ll
M llvm/test/Transforms/UnifyLoopExits/switch.ll
M llvm/test/Transforms/UnifyLoopExits/undef-phis.ll
Log Message:
-----------
[FixIrreducible][UnifyLoopExits] Support switch statements (#206567)
This builds on #149308, which implemented `callbr` support.
The same approach of splitting multi-branch edges entering irreducible
loops can be used for switches. It does not introduce any new switch
statements, but alleviates the requirement of having to run the
`LowerSwitch` pass first. This makes the pass usable for users other
than AMDGPU, which can handle switch statements (e.g., WebAssembly, see
[here](https://github.com/llvm/llvm-project/pull/181755#issuecomment-3936316307)).
I'm also implementing a flag into the `ControlFlowHub` to support
switches as well, for which I will open a separate PR. Currently the
`ControlFlowHub` creates a branch-sled, mimicking a `switch` (a series
of blocks consisting only of conditional branches, selectively entering
an irreducible loop at a certain point or continuing to the next
potential entry point). If the target can support switches, that should
be the clear goal here, as shown in the image below. This PR implements
the step from (a) to (b), whereas extending the `ControlFlowHub`
represents the step from (b) to (c). ((c) to (d) already exists through
`SwitchToLookup` and `SwitchToArithmetic`).
<img width="1055" height="432" alt="image"
src="https://github.com/user-attachments/assets/780b7894-1895-4137-8148-b2bbc7f73a8f"
/>
The test cases in `switch.ll` were adapted from the `callbr.ll` tests
using an LLM to ensure equivalent coverage. I've manually reviewed the
control flow and conditions for every case, and the final assertions
were generated using `update_test_checks.py`.
Commit: c34d2c30e86358bfe308558b5e0719e9f5305153
https://github.com/llvm/llvm-project/commit/c34d2c30e86358bfe308558b5e0719e9f5305153
Author: Aayush Shrivastava <iamaayushrivastava at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
M mlir/test/Dialect/LLVMIR/mem2reg.mlir
Log Message:
-----------
[mlir] Fix mem2reg crash on scalable vector store/load with matching type (#209426)
Fixes #209065
`createInsertAndCast/createExtractAndCast` in `LLVMMemorySlot.cpp`
queried the bit size of the source/target types before checking whether
they were already identical. For scalable vector types (e.g.
`vector<[4]xi1>`), this size query implicitly converts a scalable
TypeSize to a scalar, which aborts. `mem2reg` hits this path for any
store or load whose value type exactly matches the slot's element type,
since `getStored/removeBlockingUses` run even when no cast is needed.
This fix adds an early return when the types are already equal, skipping
the size query, consistent with the existing short-circuit in
`areConversionCompatible/castSameSizedTypes`.
Commit: e2572b883f0b2bc7a7a3808e484039f9382aa898
https://github.com/llvm/llvm-project/commit/e2572b883f0b2bc7a7a3808e484039f9382aa898
Author: Ming-Yi Lai <ming-yi.lai at mediatek.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M lld/ELF/Arch/RISCV.cpp
M lld/test/ELF/riscv-feature-zicfilp-unlabeled.s
Log Message:
-----------
[LLD][RISCV][Zicfilp] Generate unlabeled landing pad-style PLT (#145461)
To support dynamic linking when Zicfilp is enabled, lpad insns are
inserted into PLTs. This patch generates the unlabeled landing pad-style
PLT, in which all the lpads have label `0`, when ZICFILP-unlabeled is
enabled:
--- PLT Header:
```
1: auipc t3, %pcrel_hi(.got.plt)
sub t1, t1, t2
l[w|d] t2, %pcrel_lo(1b)(t3)
addi t1, t1, -(hdr size + 16)
addi t0, t3, %pcrel_lo(1b)
srli t1, t1, log2(16/PTRSIZE)
l[w|d] t0, PTRSIZE(t0)
jr t2
```
--- PLT Entry:
```
lpad 0
1: auipc t2, %pcrel_hi(function at .got.plt)
l[w|d] t2, %pcrel_lo(1b)(t2)
jalr t1, t2
```
(The PLT format is specified in the psABI draft at
<https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/417>)
---------
Co-authored-by: Piyou Chen <piyou.chen at sifive.com>
Co-authored-by: Kito Cheng <npickito at gmail.com>
Commit: 21d537e48677c6c9f3fe679694bba7bcaece90ce
https://github.com/llvm/llvm-project/commit/21d537e48677c6c9f3fe679694bba7bcaece90ce
Author: Mel Chen <mel.chen at sifive.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
Log Message:
-----------
[LV][Test] Rename conflicting IR values to avoid FileCheck conflicts. nfc (#210293)
Commit: 99789ca18a7982a0b8d63e681d957590f67455c4
https://github.com/llvm/llvm-project/commit/99789ca18a7982a0b8d63e681d957590f67455c4
Author: A. Jiang <de34 at live.cn>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M libcxx/docs/Status/Cxx23Issues.csv
M libcxx/test/std/ranges/range.adaptors/range.adjacent.transform/helpers.h
M libcxx/test/std/ranges/range.adaptors/range.adjacent.transform/iterator/member_types.compile.pass.cpp
Log Message:
-----------
[libc++] Add tests for LWG3798 and mark it as Complete (#210640)
Commit: 9e2e9b33e14808541c0470b92ade34bee6608bf6
https://github.com/llvm/llvm-project/commit/9e2e9b33e14808541c0470b92ade34bee6608bf6
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/test/UnitTest/CMakeLists.txt
M libc/test/UnitTest/ExecuteFunctionUnix.cpp
M libc/test/UnitTest/HermeticTestUtils.cpp
M libc/test/UnitTest/LibcDeathTestExecutors.cpp
M libc/test/src/stdlib/CMakeLists.txt
M utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel
Log Message:
-----------
[libc] Port process utilities to hermetic mode and enable some tests (#209999)
This is achieved by calling internal libc functions in hermetic mode. In
the overlay mode I keep calling the system functions so that the tests
work even on systems which don't have these implemented.
I also needed to implement the delete operators as both the libc proper
and the test framework uses them nowadays.
This is sufficient to enable all stdlib tests in hermetic mode, except
for one, which actually exposes a bug in the implementation. I'll deal
with that in a separate patch.
Commit: ba9a115e3ba30699cafe7815d851f89f02f821ea
https://github.com/llvm/llvm-project/commit/ba9a115e3ba30699cafe7815d851f89f02f821ea
Author: Adam Scott <adamscott200322 at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/vselect-masked-shift.ll
Log Message:
-----------
[AArch64] Fold vector shifts guarded against oversized amounts into USHL (#207628)
`select(icmp ult(amt, EltSize), shl(x, amt), 0)`, where EltSize is the
{8, 16, 32, 64} lane size, is the usual way to guard a variable vector
shift against shl poison. On AArch64 the guard is unnecessary because
USHL already returns zero once the shift amount reaches the lane size.
For v4i32:
Before:
```
movi v2.4s, #63
movi v3.4s, #32
and v1.16b, v1.16b, v2.16b
ushl v0.4s, v0.4s, v1.4s
cmhi v1.4s, v3.4s, v1.4s
and v0.16b, v1.16b, v0.16b
```
After:
```
movi v2.4s, #63
and v1.16b, v1.16b, v2.16b
ushl v0.4s, v0.4s, v1.4s
```
USHL reads each lane's shift amount as a signed value from its low byte
so amounts above 127 would be misread. The fold applies directly when
known bits can prove the amounts are at most 127 and otherwise the
amounts are clamped to EltSize with umin first, which is still one
instruction cheaper than the select.
NEON has no umin for 64-bit lanes so unbounded v2i64 amounts use the SVE
umin when available and otherwise keep the select.
lshr gets the same fold since it already lowers to ushl with a negated
amount.
This is the AArch64 counterpart of #86922, which added the same folds
for AVX2's variable shifts. This does the select(shift) half; the
shift(select) form will be a follow-up.
Closes #200698.
Commit: 92aded9ac802ed85971627bfa651697f960eefbf
https://github.com/llvm/llvm-project/commit/92aded9ac802ed85971627bfa651697f960eefbf
Author: Kareem Ergawy <kergawy at nvidia.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M flang/include/flang/Lower/PFTBuilder.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/PFTBuilder.cpp
M flang/lib/Lower/Runtime.cpp
M flang/test/HLFIR/assumed_shape_with_value_keyword.f90
M flang/test/HLFIR/optional_dummy.f90
M flang/test/Integration/OpenMP/parallel-private-reduction-worstcase.f90
M flang/test/Lower/HLFIR/intrinsic-subroutines.f90
M flang/test/Lower/MIF/change_team2.f90
M flang/test/Lower/OpenACC/Todo/acc-unstructured-combined-construct.f90
M flang/test/Lower/OpenACC/Todo/do-loops-to-acc-loops-todo.f90
M flang/test/Lower/OpenACC/acc-terminator.f90
M flang/test/Lower/OpenACC/acc-unstructured.f90
M flang/test/Lower/OpenMP/loop-compound.f90
M flang/test/Lower/OpenMP/parallel-reduction3.f90
M flang/test/Lower/OpenMP/stop-stmt-in-region.f90
M flang/test/Lower/OpenMP/unstructured.f90
M flang/test/Lower/OpenMP/wsloop-unstructured.f90
M flang/test/Lower/branching-directive.f90
A flang/test/Lower/do_loop_execute_region_wrap.f90
M flang/test/Lower/do_loop_unstructured.f90
M flang/test/Lower/fail_image.f90
A flang/test/Lower/if_construct_execute_region_wrap.f90
M flang/test/Lower/ifconvert.f90
M flang/test/Lower/mixed_loops.f90
M flang/test/Lower/nsw.f90
M flang/test/Lower/pre-fir-tree02.f90
M flang/test/Lower/while_loop.f90
Log Message:
-----------
[flang][PFT-to-MLIR] Wrap unstructured Fortran constructs in scf.execute_region (#208635)
Extend the PFT-to-MLIR (HLFIR/FIR) lowering so unstructured DO and IF
constructs are emitted inside scf.execute_region, hiding their
multi-block CFG behind a single op. OpenACC lowerings that reject
multi-block content (e.g. the "unstructured do loop in combined acc
construct" TODO in OpenACC.cpp) now see a structured op instead.
The main goal is to prevent propagating the "unstructured" property up
the evaluation tree just because one nested evaluation is unstructured;
which is the current behavior.
Flag: -mmlir --wrap-unstructured-constructs-in-execute-region (default
on).
An evaluation is wrappable iff all of the following hold:
* wrap flag on
* eval is parser::DoConstruct or parser::IfConstruct
* eval.isUnstructured
* branchesAreInternal(eval) -- every controlSuccessor in the subtree
targets a nested eval or the constructExit
* !hasIncomingBranch(eval) -- no outside eval branches into the body
(PFT's synthetic IfConstruct around `if(c) goto X` absorbs label targets
between the IF and X; the incoming-branch check excludes such wrappers
when an outer GOTO names one of those labels)
* does not contain a ReturnStmt -- its lowering creates the function's
final block in the current region, which would mis-parent func.return
* not an infinite DO and does not contain one (no LoopControl in any
nested DO): the wrap's yield is unreachable and the body has no
write-shaped side effects, so RegionDCE treats the wrap as trivially
dead and drops it. Excluding the whole enclosing construct keeps such
infinite loops visible in the parent CFG.
* not the body DO of an enclosing OpenACCLoopConstruct or
OpenACCCombinedConstruct -- nor one of the N collapsed iterator DOs
reached by walking down through `collapse(N)`. Such DOs are driven
directly into acc.loop by the OpenACC lowering, so wrapping them would
hide the iteration from the acc.loop op.
Diagnostics
-----------
Emit per-wrap and per-function diagnostics on stderr so the wrapping is
observable from a single compile invocation:
[wrap-unstructured] wrapped DO at <loc>
[wrap-unstructured] wrapped IF at <loc>
[wrap-unstructured] summary: N execute_region(s) wrapping unstructured
constructs at <loc>
The counter is reset per function and the summary is suppressed when no
wraps fire.
Co-authored-by: Claude Opus 4.7 <noreply at anthropic.com>
---------
Co-authored-by: Claude Opus 4.7 <noreply at anthropic.com>
Commit: 751fca6c06e4d29b8d2a62c307afce8ba6a0a101
https://github.com/llvm/llvm-project/commit/751fca6c06e4d29b8d2a62c307afce8ba6a0a101
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M clang/test/Driver/freebsd-mips-as.c
M clang/test/Driver/freebsd.c
Log Message:
-----------
[Driver][test] Unwrap freebsd-mips-as.c RUN lines (#210658)
Collapse 3-line RUN blocks to 2 lines and move -### immediately after
%clang, matching the prevailing style for new tests.
Commit: a4ca7f3a670c84196cad4c739114b316fed6d8f1
https://github.com/llvm/llvm-project/commit/a4ca7f3a670c84196cad4c739114b316fed6d8f1
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M libc/hdr/CMakeLists.txt
Log Message:
-----------
[libc][cmake] Remove proxy header XXX_macros -> XXX.h deps (#210008)
In the full build mode, these headers do not include the main XXX.h
header, which makes sense, because they exist to allow us only to expose
a part of it. They do include it in the overlay mode, but in this case,
they are referring to the header from the libc being overlaid, which
exists outside of the build system.
Also fix float_macros by moving
libc.include.llvm-libc-macros.float_macros from DEPENDS to
FULL_BUILD_DEPENDS, as llvm-libc-macros/float-macros.h is only included
under LIBC_FULL_BUILD.
Commit: f214ce6b0a9a6af9b1d899895e29cbba68ee2726
https://github.com/llvm/llvm-project/commit/f214ce6b0a9a6af9b1d899895e29cbba68ee2726
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/arpa/inet/BUILD.bazel
Log Message:
-----------
[libc][bazel] Add missing arpa/inet functions and tests (#210310)
Add bazel build targets for the remaining arpa/inet functions
(inet_addr, inet_aton, inet_ntoa, and inet_ntop) along with their unit
tests and supporting targets (__support_net_address, headers, and proxy
types).
Assisted by Gemini.
Commit: 72e0b55f9b1fd69030d7e9853a708bfd2fba36ec
https://github.com/llvm/llvm-project/commit/72e0b55f9b1fd69030d7e9853a708bfd2fba36ec
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/include/llvm/Analysis/ConstraintSystem.h
M llvm/lib/Analysis/ConstraintSystem.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/gep-arithmetic-signed-predicates.ll
Log Message:
-----------
[ConstraintSys] Solve sub-system with variables needed for query (#210432)
Update ConstraintSystem to only solve the sub-system containing all
variables relevant to a given query.
The sub-system contains the transitive closure of all variables in rows
involving the variables in the constraint to prove.
The iterative collection loop only needs very few iterations to
complete. The pruned system can significantly speed up Fourier–Motzkin
elimination and reduce the cost of copying the system.
This helps to notably decrease compile-time in cases when there are
larger numbers of variables & rows (especially during (Thin)LTO).
Highlights include
* stage1-ReleaseThinLTO: -0.16%
* stage1-ReleaseLTO-g: -0.19%
* stage1-aarch64-O3: -0.04%
https://llvm-compile-time-tracker.com/compare.php?from=1f2772f8e26beb909c2a559f1fb08697e3e06909&to=77fbe7926609da96a193254e44efd1d6f8a097de&stat=instructions%3Au
Note that we will now stop to simplify conditions in code we proved
dead/unreachable earlier; previously, unrelated constraints in the
system that form contradictions would allow proving any unrelated fact.
After pruning, unrelated facts will no longer contribute.
Commit: 4234ff65326237102157875f6ddf098355864178
https://github.com/llvm/llvm-project/commit/4234ff65326237102157875f6ddf098355864178
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M libcxx/include/__functional/function.h
Log Message:
-----------
Reapply "[libc++][NFC] Inline std::function members into the class body" (#209555) (#210260)
This caused LLDB to fail, which has been fixed now.
This reverts commit 7618426138aae95561da676a1d1e10ee0392bf78.
Commit: 1ad0e6989597f550e1a5b53abd889366b65aa6c7
https://github.com/llvm/llvm-project/commit/1ad0e6989597f550e1a5b53abd889366b65aa6c7
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M clang/lib/Driver/ToolChains/FreeBSD.cpp
M clang/lib/Driver/ToolChains/Serenity.cpp
M clang/test/Driver/freebsd.c
Log Message:
-----------
[Driver,FreeBSD] Fix -pie for -r and -no-pie links (#210663)
Port Gnu.cpp changes ae623d16d50c and cac82e26c642 to FreeBSD and
Serenity: -r should suppress -pie. -nopie, OpenBSD specific, should not
be used by other OSes.
Group the options selecting the link mode and place them after -m, as
gnutools::Linker does, so that -r suppresses -export-dynamic and
--hash-style as well, and -no-pie overrides the -fsanitize PIE default.
Drop --enable-new-dtags: default in modern linkers.
Change -Bstatic to -static to follow Gnu.cpp (identical in lld and older
GNU ld).
Commit: 37a2803740cc9df3d605431b2410c9d9c0bc5731
https://github.com/llvm/llvm-project/commit/37a2803740cc9df3d605431b2410c9d9c0bc5731
Author: Kamlesh Kumar <kamleshbhalui at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
M llvm/test/CodeGen/AArch64/scalable_masked_interleaved_stores.ll
M llvm/test/CodeGen/AArch64/sve-ldst-sext.ll
M llvm/test/CodeGen/AArch64/sve-ldst-zext.ll
A llvm/test/CodeGen/AArch64/vector-deinterleave-load.ll
A llvm/test/CodeGen/AArch64/vector-interleave-store.ll
Log Message:
-----------
[AArch64] Add combine for interleave deinterleave (#208414)
These combines now can emit ldN/stN without interleaved access pass.
Commit: 6fb8d5fd507d976cb8072a7aa245c225c25ee08a
https://github.com/llvm/llvm-project/commit/6fb8d5fd507d976cb8072a7aa245c225c25ee08a
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M lldb/source/Plugins/TraceExporter/docs/htr.md
Log Message:
-----------
[lldb][docs] Remove image links from trace doc (#210664)
The document was first added in https://reviews.llvm.org/D105741 but
that did not include the images (they were not in the RFC or discussions
either).
Commit: 03b5c5285eaf0acdc1dc30c5be6e0a7cefeab16f
https://github.com/llvm/llvm-project/commit/03b5c5285eaf0acdc1dc30c5be6e0a7cefeab16f
Author: Nathan Gauër <brioche at google.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/docs/LangRef.md
M llvm/include/llvm/IR/IntrinsicInst.h
M llvm/include/llvm/InitializePasses.h
A llvm/include/llvm/Transforms/Scalar/LogicalSROA.h
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Transforms/Scalar/CMakeLists.txt
A llvm/lib/Transforms/Scalar/LogicalSROA.cpp
A llvm/test/Transforms/LSROA/array.ll
A llvm/test/Transforms/LSROA/basictest.ll
A llvm/test/Transforms/LSROA/escaping.ll
A llvm/test/Transforms/LSROA/nesting.ll
A llvm/test/Transforms/LSROA/normal-gep.ll
A llvm/test/Transforms/LSROA/phi.ll
A llvm/test/Transforms/LSROA/select.ll
Log Message:
-----------
[LSROA] Add logical SROA pass (#192058)
This commit adds a logical-pointer compatible SROA pass. As-is, the pass
does not optimizes nested structs, arrays, or usages of structured
alloca with non-structured GEP instructions.
Adding support for both is not complex, but increase the size of the PR,
hence we can start with this.
Next step will be to allow mem2reg to apply on logical alloca/ptr, and
to add support for nesting/arrays.
---------
Co-authored-by: Nikita Popov <npopov at redhat.com>
Commit: b8300a76659d65fd9738de1c1e4bf5b71e9ef72b
https://github.com/llvm/llvm-project/commit/b8300a76659d65fd9738de1c1e4bf5b71e9ef72b
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/Scalar/GVN.h
M llvm/lib/Transforms/Scalar/GVN.cpp
Log Message:
-----------
[GVN] Remove the "private" `llvm::gvn` namespace (NFC) (#210323)
Move `AvailableValue` and `AvailableValueInBlock` into GVNPass, similar
to other helper types.
Retain `llvm::gvn::GVNLegacyPass` as just `llvm::GVNLegacyPass` -
"legacy" is already a sufficent hint and it is not going to become more
"private" by stacking "gvn" prefixes to the name.
Ideally, `GVNLegacyPass` should be defined in an anonymous namespace,
but that is not possible because it is declared as a friend of GVNPass.
Commit: b9b454166eaa92d2e6e129f6c21ad59639d8364e
https://github.com/llvm/llvm-project/commit/b9b454166eaa92d2e6e129f6c21ad59639d8364e
Author: Hongyu Chen <xxs_chy at outlook.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvp-zip.ll
Log Message:
-----------
[RISCV][P-ext] Generalize lowerVECTOR_SHUFFLEAsRV32PNarrowingShift (#210522)
The previous implementation only matches
`shuffle(extract_subvector(src), extract_subvector(src), mask)`.
This patch generalizes it to `shuffle(a, b, mask)`, so we can now lower
it to `PNSRL(concat(a,b), element_bits)` if it is a deinterleave
shuffle. And we use `foldConcatVector` to handle the original pattern
with `extract_subvector`.
Commit: 023361f8ef6aa47d10cd839515c58322890367c3
https://github.com/llvm/llvm-project/commit/023361f8ef6aa47d10cd839515c58322890367c3
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
Log Message:
-----------
[lldb][AArch64][Linux][NFC] Move RegisterSetType enum into header (#207145)
I will be using this later to replace all the register specific
functions this class has (WriteSVE/ReadSVE and so on) with single
functions that use RegisterSetType to decide what to do.
While I'm here, I've made some sizeof and casts use RegisterSetType in
case the underlying type changes later.
Commit: 975c8f5a7b25f84a257ddfaf9605c62147a0913d
https://github.com/llvm/llvm-project/commit/975c8f5a7b25f84a257ddfaf9605c62147a0913d
Author: Raphael Isemann <rise at apple.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M lldb/include/lldb/Core/ModuleSpec.h
M lldb/source/API/SBAddressRangeList.cpp
M lldb/source/API/SBMemoryRegionInfo.cpp
M lldb/source/Breakpoint/Breakpoint.cpp
M lldb/source/Breakpoint/BreakpointLocation.cpp
M lldb/source/Breakpoint/BreakpointLocationList.cpp
M lldb/source/Breakpoint/BreakpointOptions.cpp
M lldb/source/Breakpoint/BreakpointResolverName.cpp
M lldb/source/Breakpoint/Watchpoint.cpp
M lldb/source/Breakpoint/WatchpointList.cpp
M lldb/source/Core/Disassembler.cpp
M lldb/source/Core/DumpDataExtractor.cpp
M lldb/source/Core/DynamicLoader.cpp
M lldb/source/Core/FormatEntity.cpp
M lldb/source/Core/IOHandler.cpp
M lldb/source/Core/IOHandlerCursesGUI.cpp
M lldb/source/Core/Mangled.cpp
M lldb/source/Core/SearchFilter.cpp
M lldb/source/Core/SourceManager.cpp
M lldb/source/DataFormatters/FormattersHelpers.cpp
M lldb/source/DataFormatters/StringPrinter.cpp
M lldb/source/DataFormatters/TypeCategory.cpp
M lldb/source/DataFormatters/TypeSynthetic.cpp
M lldb/source/DataFormatters/ValueObjectPrinter.cpp
M lldb/source/DataFormatters/VectorType.cpp
M lldb/source/Expression/IRInterpreter.cpp
M lldb/source/Expression/Materializer.cpp
M lldb/source/Expression/REPL.cpp
M lldb/source/Host/common/ProcessLaunchInfo.cpp
M lldb/source/Symbol/SymbolContext.cpp
M lldb/source/Symbol/Type.cpp
M lldb/source/Symbol/UnwindPlan.cpp
M lldb/source/Utility/Event.cpp
M lldb/source/Utility/ProcessInfo.cpp
M lldb/source/Utility/StructuredData.cpp
M lldb/source/ValueObject/ValueObject.cpp
Log Message:
-----------
[lldb][NFC] Remove various Stream::Printf calls with constants (#210294)
`Stream::Printf` needs to call various other (variadic) functions, needs
to parse the input string and potentially handle too-long format
outputs. Calling in with a constant string is wasting a lot of
instruction on doing nothing.
assisted-by: claude
Commit: 1c1c0657f990b92d23067cb7367772f4c91ea32b
https://github.com/llvm/llvm-project/commit/1c1c0657f990b92d23067cb7367772f4c91ea32b
Author: Abhay Kanhere <a_kanhere at apple.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
A llvm/test/Transforms/ConstraintElimination/lshr.ll
Log Message:
-----------
[ConstraintElim] LSHR x, n <= x when n< bitwidth (#209583)
A logical right shift never increases an unsigned value:
for %r = lshr %x, %n, add the fact %r u<= %x when LSHR is not poison.
This extends the existing udiv/urem fact modeling to lshr.
https://alive2.llvm.org/ce/z/RUTMwe proof shown with constant value <
bit size
Commit: ead8fd8e29fbf3774b7a08bf7b991c2ada30112b
https://github.com/llvm/llvm-project/commit/ead8fd8e29fbf3774b7a08bf7b991c2ada30112b
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M libcxx/include/__ranges/lazy_split_view.h
Log Message:
-----------
[libc++][ranges][NFC] Format `lazy_split_view` (#210644)
Pre-requisite for: https://github.com/llvm/llvm-project/pull/193891
Commit: eec2f0916d44c33beac52f4396c7a9c98b0c9cf6
https://github.com/llvm/llvm-project/commit/eec2f0916d44c33beac52f4396c7a9c98b0c9cf6
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M libcxx/include/__configuration/availability.h
Log Message:
-----------
[libc++][NFC] Removed duplicated `_LIBCPP_INTRODUCED_IN_LLVM_23` macros (#210602)
Removed the redundant macros, which apparently were added by two
different patches.
Commit: 39a2c6a695f9d045b05fd5798a7cb99f3c7425a7
https://github.com/llvm/llvm-project/commit/39a2c6a695f9d045b05fd5798a7cb99f3c7425a7
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M libcxx/test/libcxx/atomics/builtin_clear_padding.pass.cpp
M libcxx/test/std/numerics/numeric.ops/numeric.ops.sat/saturating.bitint.pass.cpp
Log Message:
-----------
[libc++][test][NFC] Removed unsupported compilers from tests (#210413)
Commit: 9cb6db4e3814fba503389aa0af16960847295fd2
https://github.com/llvm/llvm-project/commit/9cb6db4e3814fba503389aa0af16960847295fd2
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/Scalar/GVN.h
M llvm/lib/Transforms/Scalar/GVN.cpp
Log Message:
-----------
Revert "[GVN] Remove the "private" `llvm::gvn` namespace (NFC)" (#210666)
Reverts llvm/llvm-project#210323
FAILED: lib/Transforms/Scalar/CMakeFiles/LLVMScalarOpts.dir/GVN.cpp.o
/var/llvm-compile-time-tracker/llvm-project/llvm/lib/Transforms/Scalar/GVN.cpp:4001:27:
error: qualified name does not name a class before ‘:’ token
4001 | class llvm::GVNLegacyPass : public FunctionPass {
Commit: ded79d9ddea47eb3a42da740353c16d21e890354
https://github.com/llvm/llvm-project/commit/ded79d9ddea47eb3a42da740353c16d21e890354
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
A llvm/test/CodeGen/SPIRV/constant/fp128-unsupported.ll
Log Message:
-----------
[SPIR-V] Reject fp128 and ppc_fp128 types with a diagnostic (#208397)
Introduced as a part of discussion in
https://github.com/llvm/llvm-project/pull/208219
Commit: 4caba63c698121203eea9280a392159dc6328e68
https://github.com/llvm/llvm-project/commit/4caba63c698121203eea9280a392159dc6328e68
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M lldb/test/API/commands/gui/spawn-threads/TestGuiSpawnThreads.py
Log Message:
-----------
[lldb][test] Double the timeout for TestGuiSpawnThreads.py (#210043)
If the host machine is overloaded, spawning threads may be delayed due
to lack of resources. I'm pretty sure this is the cause of failures in
GitHub CI reported in
https://github.com/llvm/llvm-project/issues/209874.
For what the test is doing, we unfortunately cannot get around needing
to wait on the test program.
We could perhaps come up with a lit mode that runs some tests in serial,
but this is a larger project than I want to get into now.
For now, let's try doubling the timeout. This test is unlikely to fail
for real, so if it's taking a long time, it'll be due to system
resources. In 99% of cases, it'll pass in a few seconds still.
Commit: 35c8e920cdd5b53dccfd669ebd92f3e06f534aae
https://github.com/llvm/llvm-project/commit/35c8e920cdd5b53dccfd669ebd92f3e06f534aae
Author: Valery Pykhtin <valery.pykhtin at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
Log Message:
-----------
[NFC][AMDGPU] Use SIInstrFlags predicates in SIMemoryLegalizer and AMDGPUBaseInfo. (#209821)
Part of a series following the introduction of SIInstrFlags predicates.
Commit: 195df3d4654b43ecf35927e574a8061bfaecbb78
https://github.com/llvm/llvm-project/commit/195df3d4654b43ecf35927e574a8061bfaecbb78
Author: Matsu <47756807+khaki3 at users.noreply.github.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsCG.cpp
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-worker-reduction-private.mlir
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsCGTest.cpp
Log Message:
-----------
[mlir][OpenACC] Privatize worker reduction accumulators per worker (#210456)
Example:
```fortran
!$acc parallel
!$acc loop gang reduction(+:sum)
do k = 1, p
!$acc loop worker reduction(+:sum)
do j = 1, n
!$acc loop vector reduction(+:sum)
do i = 1, m
sum = sum + a(i,j,k)
end do
end do
end do
```
In this code, the worker accumulator is both gang- and worker-scoped.
Shared
memory allocated only one copy, so workers raced while updating the same
value.
Fix: allocate one shared-memory accumulator per worker whenever worker
parallelism is present.
Commit: 91ad9f0ce9655eb3715c937f7d64d329bac63817
https://github.com/llvm/llvm-project/commit/91ad9f0ce9655eb3715c937f7d64d329bac63817
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fcmp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmad.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fract.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.frexp.mant.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.cd.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/add-max.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-sin-cos-f16-f32.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bitop3.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-return-types.ll
M llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll
M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll
M llvm/test/CodeGen/AMDGPU/float-sopc-vopc.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaxnum.ll
M llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminnum.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fsub-as-fneg-src-modifier.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/literal64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.flat.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.store.async.from.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.modf.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/lround.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/memset-pattern.ll
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-global.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-smem.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
Log Message:
-----------
AMDGPU/GlobalISel: Handle G_BITCAST for 16 bit extendedLLTs (#208750)
Handle bitcast between i16 and f16/bf16.
For true16 this was already legal, make it legal in regbanklegalize as well.
For non-true16 widen it using G_ANYEXT to i32 and G_TRUNC to dst.
The "i32 G_ANYEXT f16/bf16" and "f16/bf16 G_TRUNC i32" are already legal,
for example these are generated by common CallLowering argument lowering.
Commit: 5ec4a236305f18f2d2d8646902ab166655f1b7f1
https://github.com/llvm/llvm-project/commit/5ec4a236305f18f2d2d8646902ab166655f1b7f1
Author: Matsu <47756807+khaki3 at users.noreply.github.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M flang-rt/lib/cuda/allocator.cpp
M flang/include/flang/Lower/AbstractConverter.h
M flang/include/flang/Lower/Bridge.h
M flang/include/flang/Optimizer/Builder/Runtime/CUDA/Descriptor.h
M flang/include/flang/Runtime/CUDA/descriptor.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Optimizer/Builder/Runtime/CUDA/Descriptor.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/test/Fir/CUDA/cuda-code-gen.mlir
M flang/test/Lower/CUDA/cuda-allocatable.cuf
M flang/test/Lower/CUDA/cuda-derived.cuf
M flang/test/Lower/CUDA/cuda-return01.cuf
M flang/test/Lower/CUDA/cuda-return02.cuf
Log Message:
-----------
[flang][cuda] Fix device-variable leaks and reset-safe cleanup (#209865)
Example:
```fortran
program main
use cudafor
integer, allocatable, device :: b(:)
integer :: istat
allocate(b(1024))
b = 2
istat = cudaDeviceReset()
end program
```
Managed descriptors and main-program allocatable data could leak. After
`cudaDeviceReset()`, compiler-generated scope-exit cleanup could also
access
stale descriptors or recreate a CUDA context.
Fix: free device data and descriptors in the correct order, and avoid
unnecessary
managed temporary descriptors. Each routine’s CUDA scope-exit cleanup is
grouped
under one `CUFDeviceIsActive()` check using
`cuDevicePrimaryCtxGetState`.
Routines without CUDA cleanup—and individual runtime frees—incur no
query.
Commit: f6b1a575b4076281cd67cf3f3a626d70363f1b9b
https://github.com/llvm/llvm-project/commit/f6b1a575b4076281cd67cf3f3a626d70363f1b9b
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-legalize-range-metadata.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector-pointer-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-weird-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/trunc-brc.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll
Log Message:
-----------
AMDGPU/GlobalISel: Switch legalizer intrinsic lowering to extended LLTs (#209200)
Affects various buffer intrinsics.
Commit: 9428725fa09113905847decc48e8b5a731ad0ae6
https://github.com/llvm/llvm-project/commit/9428725fa09113905847decc48e8b5a731ad0ae6
Author: Ryan Thomas Lynch <me at ryanlyn.ch>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M mlir/test/mlir-tblgen/op-result.td
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
Log Message:
-----------
[mlir-tblgen] Emit named result indices (#210542)
similar to https://github.com/llvm/llvm-project/pull/146839
useful for cases such as being able to programmatically update the
result segment sizes or clone an operation via `OperationState` while
editing just a few results, programmatically
Commit: 085ecff1ecc69ad022b614cfa4dc020540b6296b
https://github.com/llvm/llvm-project/commit/085ecff1ecc69ad022b614cfa4dc020540b6296b
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlanValue.h
Log Message:
-----------
[VPlan] Assert VPRegionValues are not used in VPTransformState::get(NFC) (#199420)
VPRegionValues must be replaced with concrete VPValues before execute
and never passed to VPTransformState::get. Add assert to guard against
violations.
Commit: 79e05f4aff2e5b9f0513c0539d146e44cc80193c
https://github.com/llvm/llvm-project/commit/79e05f4aff2e5b9f0513c0539d146e44cc80193c
Author: Jacob Crawley <jacob.crawley at arm.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleave-low-vf-cost.ll
Log Message:
-----------
[AArch64][LV] Adjust costs for low-VF interleaved access (#209441)
Addressing regression introduced by #205844 in which a significantly
slower SVE tail loop is generated.
The cost model for the case where the interleave factor is larger than
the VF has been adjusted to more accurately reflect the cost of the uzp
instructions generated by the deinterleave tree, and the cost of
legalizing the type of each subvector.
Commit: d9fff42ccd58cb3d95cff60641011d72d38dc300
https://github.com/llvm/llvm-project/commit/d9fff42ccd58cb3d95cff60641011d72d38dc300
Author: Matsu <47756807+khaki3 at users.noreply.github.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Lower/Bridge.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Transforms/AffinePromotion.cpp
M flang/lib/Optimizer/Transforms/ControlFlowConverter.cpp
M flang/lib/Optimizer/Transforms/FIRToSCF.cpp
M flang/test/Fir/FirToSCF/do-loop.fir
M flang/test/Fir/loop01.fir
M flang/test/Integration/ivdep.f90
M flang/test/Lower/OpenACC/acc-cache.f90
M flang/test/Lower/OpenACC/acc-declare.f90
M flang/test/Lower/OpenMP/default-clause.f90
M flang/test/Lower/OpenMP/hlfir-seqloop-parallel.f90
M flang/test/Lower/OpenMP/parallel-private-clause-fixes.f90
M flang/test/Lower/OpenMP/sections-predetermined-private.f90
M flang/test/Lower/OpenMP/shared-loop.f90
M flang/test/Lower/OpenMP/unstructured.f90
M flang/test/Lower/OpenMP/wsloop-reduction-allocatable-array-minmax.f90
M flang/test/Lower/OpenMP/wsloop-variable.f90
M flang/test/Lower/allocatable-polymorphic.f90
M flang/test/Lower/dispatch.f90
M flang/test/Lower/do_concurrent_loop_in_nested_block.f90
M flang/test/Lower/do_loop.f90
M flang/test/Lower/do_loop_execute_region_wrap.f90
M flang/test/Lower/do_loop_unstructured.f90
M flang/test/Lower/infinite_loop.f90
M flang/test/Lower/inline_directive.f90
M flang/test/Lower/ivdep.f90
M flang/test/Lower/loops.f90
M flang/test/Lower/loops2.f90
M flang/test/Lower/mixed_loops.f90
M flang/test/Lower/nsw.f90
M flang/test/Transforms/DoConcurrent/skip_all_nested_loops.f90
Log Message:
-----------
[flang] Lower plain DO loops without a secondary-induction iter_arg (#207816)
Example:
```fortran
do i = lb, ub, step
...
end do
```
Flang lowers this with the DO variable as a redundant `iter_arg`, which
hides memory recurrences from later analyses. Simply removing it would
require converting the `index` IV to the source integer type each
iteration, potentially blocking vectorization.
Fix: allow `fir.do_loop` to use the DO variable’s integer type directly.
Trip-count and post-loop calculations remain in `index`. This removes
the redundant `iter_arg` without introducing per-iteration conversions.
`do concurrent` and unstructured loops are unaffected.
Commit: 334708eb100204edc677a546bfa77ef10df71ec9
https://github.com/llvm/llvm-project/commit/334708eb100204edc677a546bfa77ef10df71ec9
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Transforms/Scalar/BUILD.gn
Log Message:
-----------
[gn build] Port 03b5c5285eaf (#210688)
Commit: 41d76f2763a53517f273c87a1a703f00cb965f09
https://github.com/llvm/llvm-project/commit/41d76f2763a53517f273c87a1a703f00cb965f09
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctls.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaximum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminimum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx7.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx8-plus.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.modf.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
Log Message:
-----------
AMDGPU/GlobalISel: Fix G_UNMERGE_VALUES lowering for extended LLTs (#209201)
Use integer type for bit twiddling instead of scalar.
Commit: b21fb937f165898c727030760f0a8ab685ef08eb
https://github.com/llvm/llvm-project/commit/b21fb937f165898c727030760f0a8ab685ef08eb
Author: Benedek Kaibas <82393336+benedekaibas at users.noreply.github.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt
A clang/lib/StaticAnalyzer/Checkers/DanglingPtrDeref.cpp
R clang/lib/StaticAnalyzer/Checkers/ReportDanglingPtrDeref.cpp
Log Message:
-----------
[analyzer][NFC] Correct the DanglingPtrDeref checker's filename (#209862)
The alpha `DanglingPtrDeref` checker got implemented in #209278. Since
it is under heavy development and subject to change significantly in the
near future it is in alpha stage. During the development of the
`DanglingPtrDeref` checker its name got changed from
`ReportDanglingPtrDeref` to `DanglingPtrDeref` based on the conversation
here:
https://github.com/llvm/llvm-project/pull/209278#discussion_r3578604913
While the checker's registration got updated in `Checkers.td` the same
change did not get applied to the `
clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt` and the checker's
filename. This PR addresses this issue.
Commit: 2ec66d76fde71265be83c216d0be3d16bb131fc7
https://github.com/llvm/llvm-project/commit/2ec66d76fde71265be83c216d0be3d16bb131fc7
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt/Session.h
M orc-rt/lib/executor/Session.cpp
M orc-rt/test/unit/SessionTest.cpp
Log Message:
-----------
[orc-rt] Fix wrapper-call managed-code token lifetime (#210686)
d199b284c7d established that ManagedCodeTaskGroup tokens must bracket a
single span of execution on a stack, not a chain of asynchronous
operations (see orc-rt/docs/Design.md's "Managed code execution and
shutdown" section). Session::handleWrapperCall and sendWrapperResult
predated that policy and didn't conform to it: the token was acquired in
handleWrapperCall but only released in sendWrapperResult, holding it for
the whole call/response chain. If Fn deferred sending its result
asynchronously, Session shutdown would incorrectly wait on that deferred
completion instead of proceeding as soon as Fn's stack unwound.
Acquire the token as a TaskGroup::Token scoped to the dispatched call,
and let it release when Fn returns rather than when its result is sent.
Commit: d90634dc185da79a8eb6a993c28614f4788e368e
https://github.com/llvm/llvm-project/commit/d90634dc185da79a8eb6a993c28614f4788e368e
Author: 311Volt <41923095+311Volt at users.noreply.github.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M offload/liboffload/API/Memory.td
M offload/plugins-nextgen/level_zero/include/L0Device.h
M offload/plugins-nextgen/level_zero/include/L0Queue.h
M offload/plugins-nextgen/level_zero/src/L0Device.cpp
M offload/plugins-nextgen/level_zero/src/L0Queue.cpp
M offload/unittests/OffloadAPI/memory/olMemFill.cpp
Log Message:
-----------
[offload] support arbitrary memoryFill pattern sizes in L0 plugin (#209724)
Even though L0, CUDA and HSA do not directly support filling memory
regions with non-power-of-two-sized patterns, plugins explicitly allow
for such fills by falling back to a slow path whenever a direct API call
is not possible.
The Level Zero plugin is the odd one out, forwarding directly to
`zeCommandListAppendMemoryFill`. This fails for non-power-of-two
patterns, causing unit tests for `olMemFill` to fail when run on L0.
This PR adds fallbacks in L0 plugin's `memoryFill` implementation to
support arbitrary pattern sizes:
- if all pattern bytes are the same, substitute `1` for `patternSize`
and proceed with the native fill
- if memory is host-accessible (host or shared alloc), then simply
`std::copy_n` the pattern
- if memory is device-only, upload a seed to the device, and
`memoryCopy` O(log n) times, doubling the pattern each time, until the
entire region is filled. The seed is the input pattern, but extended on
the host to 1-2KiB to potentially eliminate several small `memoryCopy`
calls that would otherwise be almost pure overhead.
Conceptually, this approach has better worst-case overhead than the one
found in the CUDA plugin (decompose the pattern to then run multiple
strided memsets) and the AMDGPU one (call `pushMemoryCopyH2DAsync` with
the pattern, setting `NumTimes`). Aligning the fallback fill approaches
is outside the scope of this PR, however - the main intent is to fix the
unit test failures.
Commit: a8ffce42477c909908d6f45511a48fd01a24837d
https://github.com/llvm/llvm-project/commit/a8ffce42477c909908d6f45511a48fd01a24837d
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/test/SemaCXX/cxx2c-fold-exprs.cpp
Log Message:
-----------
[Clang] Fix evaluation of fold expanded constraints for NTTP (#210005)
This is a rework of #200185 and also reflects what we did for TTP in
C++26 fold expression constraints (adc64c6e1745)
Fixes https://github.com/llvm/llvm-project/issues/199569
Commit: 14f6b9f0a3976f85d3ef509c8361991ae3702002
https://github.com/llvm/llvm-project/commit/14f6b9f0a3976f85d3ef509c8361991ae3702002
Author: Deepak Shirke <deepakshirke509 at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
A llvm/test/Transforms/VectorCombine/AArch64/bitreverse-v8i8-to-gpr.ll
Log Message:
-----------
[VectorCombine] Fold bitcast(bitreverse.v8i8(bitcast(IntTy))) into bswap+bitreverse (#209037)
Add reverse direction to `foldBitOrderReverseAndSwap`:
`bitcast(bitreverse(<N x i8>)(bitcast(IntTy X)))` -->
`bitreverse(bswap(X))`
This avoids GPR<=>vector register crossings when integer ops are
cheaper. On AArch64 for example:
Before:
```asm
fmov d0, x0 ; GPR → vector crossing
rbit v0.8b, v0.8b
fmov x0, d0 ; vector → GPR crossing
```
After:
```asm
rev x8, x0 ; stays in integer registers
rbit x0, x8
```
The fold is cost-model driven and only fires when the integer version is
cheaper, so targets like X86+GFNI that prefer the vector form (single
`vgf2p8affineqb` instruction) are unaffected.
A new call site for `BitCast` instructions is added alongside the
existing `Call` instruction call site in the dispatch loop.
Fixes #201760
Commit: 06e3180cd141d9a8efdb9e9867b4a32300679038
https://github.com/llvm/llvm-project/commit/06e3180cd141d9a8efdb9e9867b4a32300679038
Author: Barbara Mitic <Barbara.Mitic at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
Log Message:
-----------
[AMDGPU] Accept extractelement of a widening cast when folding image ops to a16 (#208207)
canSafelyConvertTo16Bit() recognizes a scalar coordinate that is a
direct sext/zext/fpext from a 16-bit value (sext gated on AllowI16SExt).
Per-dimension coordinates can instead arrive as an extractelement of a
widening vector cast (extractelement((s|z|fp)ext <N x i16/half> Vec),
Idx). When the cast has more than one use, the extractelement(cast) ->
cast(extractelement) canonicalization does not fire, so the cast is left
in place and the coordinate is not recognized.
Strip a leading extractelement before the cast check so the same logic
handles scalar and per-lane coordinates, and mirror this in
convertTo16Bit() by re-extracting from the narrow vector, allowing the
widening cast to be removed once it has no other uses.
Commit: bd38dd0ace19c3b9512da2b37bb9690ee6c9e97f
https://github.com/llvm/llvm-project/commit/bd38dd0ace19c3b9512da2b37bb9690ee6c9e97f
Author: AntonyCJ30 <cj6186609 at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/test/CodeGen/X86/avx512-vpternlog-commute.ll
Log Message:
-----------
[X86] Fix swapped VPTERNLOG231_imm8/VPTERNLOG312_imm8 SDNodeXForm bodies (#209782)
Fixes #157929
VPTERNLOG231_imm8 and VPTERNLOG312_imm8 had their bodies swapped,
causing ISel to emit the wrong truth-table immediate whenever operand
reordering was needed (-O1+, not -O0).
Test changes:
- **avx512-vpternlog-commute.ll: regenerated with
update_llc_test_checks.py**
(accounts for the large diff)
- Added 4 new cases: vpternlog231_rmik, vpternlog312_rmik,
vpternlog231_rmbik, vpternlog312_rmbik
Tested: llvm-lit on llvm/test/CodeGen/X86 (no regressions), original
repro verified correct at -O0 through -O3, -Os, -Oz.
Commit: 60f8b4624badab6bec5e2600d82cf98b6a4e303b
https://github.com/llvm/llvm-project/commit/60f8b4624badab6bec5e2600d82cf98b6a4e303b
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-cse-leaves-dead-cast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def-s1025.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx8-plus.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/no-ctlz-from-umul-to-lshr-in-postlegalizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/umed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fmaxnum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fminnum.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
Log Message:
-----------
AMDGPU/GlobalISel: Fix G_MERGE_VALUES lowering for extended LLTs (#209202)
Use integer type for bit twiddling instead of scalar.
Commit: 648aec12e5e5242c93aa73a21714553c6341ddc3
https://github.com/llvm/llvm-project/commit/648aec12e5e5242c93aa73a21714553c6341ddc3
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
Log Message:
-----------
[AArch64] NFC: Factor out code from FP_TO_INT (SVE). (#207200)
This just moves out some of the SVE lowering code from
LowerVectorFP_TO_INT into a separate function, so that we can reuse that
in LowerVectorFP_TO_INT_SAT.
Commit: 25b75a1e41c5fe71ed1f832c36c8bfb1bca1ab35
https://github.com/llvm/llvm-project/commit/25b75a1e41c5fe71ed1f832c36c8bfb1bca1ab35
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
M llvm/test/CodeGen/AMDGPU/lrint.ll
M llvm/test/CodeGen/AMDGPU/lround.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
Log Message:
-----------
AMDGPU/GlobalISel: Stop using changeTo in legalizer actions (#209203)
Use changeElementSizeTo or changeElementCountTo to preserve extended LLT.
Commit: 8abc26930cf9ee0f059228acdbd1d22cd1c325e3
https://github.com/llvm/llvm-project/commit/8abc26930cf9ee0f059228acdbd1d22cd1c325e3
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/test/CodeGen/X86/pr209714.ll
Log Message:
-----------
[X86] combineShiftRightLogical - fold srl(vecreduce_umax(x),bw-1) as MOVMSK signbit reduction (#210281)
VectorCombine may have folded:
icmp_eq(vecreduce_or(splatsign(x)),0) --> icmp_sgt(vecreduce_umax(x),-1)
which DAG folds to:
srl(vecreduce_umax(x),bw-1).
This match attempts to lower:
srl(vecreduce_umax(x),bw-1) --> icmp_ne(movmsk(x),0) "any_of negative"
srl(not(vecreduce_umax(x)),bw-1) --> icmp_eq(movmsk(x),0) "none_of negative"
The correct fix would be to improve vecreduce_or costs to prevent
VectorCombine doing this, but that change is far too big to be merged
into 23.x - so I've created the narrow backend fix.
Fixes #209714
Commit: d9c88062ecf9dc8ece4bb1482b0f1789979e3da5
https://github.com/llvm/llvm-project/commit/d9c88062ecf9dc8ece4bb1482b0f1789979e3da5
Author: rdevshp <rdevshp at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/SMTConstraintManager.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/SMTConv.h
M clang/lib/StaticAnalyzer/Core/ExprEngineC.cpp
M clang/lib/StaticAnalyzer/Core/SValBuilder.cpp
M clang/test/Analysis/logical-ops.c
A clang/test/Analysis/z3/z3-bitint-arithmetic.c
M clang/test/Analysis/z3/z3-logicalexpr-eval.c
M llvm/lib/Support/Z3Solver.cpp
Log Message:
-----------
[analyzer] Fix _BitInt support & casting behavior for Z3 symbolic execution (#210525)
Forces symbolic cast to be enabled for z3 symbolic execution, and
switches away from Ctx.getTypeSize for getting the bit width of integral
types.
The current patch might be a bit problematic for z3 cross-check, as this
relies on symbolic integer cast to be always on. I am not sure if
turning on ShouldSupportSymbolicIntegerCasts would cause issues for the
supported range-based solver, so I only kept it turned on when
AnalysisConstraintsOpt == Z3ConstraintsModel.
Assisted-by: Codex
Commit: 27fe16dcf920c92bcb7050e5abf4164ed3b496d1
https://github.com/llvm/llvm-project/commit/27fe16dcf920c92bcb7050e5abf4164ed3b496d1
Author: Dan Blackwell <dan_blackwell at apple.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
A llvm/test/Instrumentation/AddressSanitizer/darwin-mte-tag-stripping.ll
Log Message:
-----------
[Darwin][ASan] Strip MTE-tags for inlined shadow translations (#204827)
https://github.com/llvm/llvm-project/pull/166453 stripped these tags
when the runtime performed the mem-to-shadow translation, but did not
account for ASan's inline translations. When an MTE-tagged address gets
translated, the tag bits are right-shifted too, resulting in a very high
address that faults when accessed.
This patch strips the MTE-tag bits before applying the translation on
Apple platforms.
rdar://180032780
Commit: 1caf9e1ef68ef85f1976e82bfc33befe1edc6eff
https://github.com/llvm/llvm-project/commit/1caf9e1ef68ef85f1976e82bfc33befe1edc6eff
Author: Federico Bruzzone <federico.bruzzone.i at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/pack-unpack-mmt4d.mlir
Log Message:
-----------
[mlir][ArmSVE] Fix comment inconsistency for `pack_lhs` in `ArmSVE/pack-unpack-mmt4d.mlir` (NFC) (#210502)
This PR simply fix a comment inconsistency for `pack_lhs` in
[ArmSVE/pack-unpack-mmt4d.mlir](https://github.com/llvm/llvm-project/compare/main...FedericoBruzzone:nfc-armsve?expand=1#diff-7be071860c440806b8dad954ed61946e7e9f27e032ed6044a704f0c0f70e4407)
as identified in #208226.
Signed-off-by: Federico Bruzzone <federico.bruzzone.i at gmail.com>
Commit: c30b1fa7a08e36346f80b1798ae587bc1d5e032b
https://github.com/llvm/llvm-project/commit/c30b1fa7a08e36346f80b1798ae587bc1d5e032b
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Checkers/BUILD.gn
Log Message:
-----------
[gn build] Port b21fb937f165 (#210698)
Commit: 2cdd343022d4c5848281f4bb3670213f535884a2
https://github.com/llvm/llvm-project/commit/2cdd343022d4c5848281f4bb3670213f535884a2
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
M llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-flat.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-global.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-local.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
Log Message:
-----------
AMDGPU/GlobalISel: Fix legalizer lowering for G_EXTRACT/INSERT_VECTOR_ELT (#210094)
Use LLT::integer in bit twiddling lowering for extract/insert vector element.
Commit: ca276b4822b1c748aaf9ef631d887143cb03a217
https://github.com/llvm/llvm-project/commit/ca276b4822b1c748aaf9ef631d887143cb03a217
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Transforms/Scalar/ExpandMemCmp.cpp
M llvm/test/CodeGen/RISCV/memcmp-optsize.ll
M llvm/test/CodeGen/RISCV/memcmp.ll
A llvm/test/Transforms/ExpandMemCmp/RISCV/lit.local.cfg
A llvm/test/Transforms/ExpandMemCmp/RISCV/memcmp-strict-align.ll
Log Message:
-----------
[ExpandMemCmp][RISCV] Expand memcmp/bcmp for aligned pointers on strict-align targets (#209738)
`RISCVTTIImpl::enableMemCmpExpansion` previously disabled `memcmp`/`bcmp`
expansion whenever the target lacks unaligned scalar memory access. This is
too conservative: when both pointers are statically known to be
sufficiently aligned (e.g. `bcmp(ptr align 8, ptr align 8, 32)`), only
naturally aligned loads are needed, which are fine on strict-align
targets.
`ExpandMemCmp` now keeps a candidate load size only if, given the known
common alignment of the two pointers, the access is naturally aligned or
the target reports it via `allowsMisalignedMemoryAccesses`; otherwise it
falls back to the libcall. The query tests whether the access is
*allowed* (not *fast*), so it is a no-op for targets that already allow
unaligned access (X86, AArch64, ...).
The known alignment now also folds in the `align` attributes on the call
arguments (`CallBase::getParamAlign`), not just the pointer value.
RISCV drops the early return and only offers overlapping loads / tail
expansions when unaligned scalar access is supported.
Fixes #209511.
Assisted-by: TRAE CLI (DeepSeek V4 Pro)
Commit: 0000fd1fc63dcc7f0fe87091fe2e5a0daf5ec727
https://github.com/llvm/llvm-project/commit/0000fd1fc63dcc7f0fe87091fe2e5a0daf5ec727
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
A llvm/test/Transforms/VectorCombine/AArch64/load-widening.ll
M llvm/test/Transforms/VectorCombine/X86/load-widening.ll
Log Message:
-----------
[VectorCombine] load-widening.ll - add test coverage for all 4 x86-64 cpu levels and aarch64 endian test coverage (#210690)
Removed x86 endianess tests which makes no sense (and are likely to misbehave) and add equivalent test coverage to aarch64
Noticed while reviewing #209775
Commit: ac41c58f7b3b26a4bd4260d05afd7c3b2ccc3c72
https://github.com/llvm/llvm-project/commit/ac41c58f7b3b26a4bd4260d05afd7c3b2ccc3c72
Author: BohdanYehorov <yehorovbohdan.work at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M clang/docs/InternalsManual.rst
Log Message:
-----------
[clang][docs] Fix include path in InternalsManual (#209458)
The paths `include/Basic/StmtNodes.td` and `include/AST/Expr*.h` in the
Clang Internals Manual are incorrect.
Commit: a35bcaef8c1a0867af4c3b547422b4783c88fc96
https://github.com/llvm/llvm-project/commit/a35bcaef8c1a0867af4c3b547422b4783c88fc96
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-store-s16-true16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-weird-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/call-return-types.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
Log Message:
-----------
AMDGPU/GlobalISel: Explicitly widen scalar to i32 for load and store (#210095)
Affects f16 and bf16. Earlier, they were widened to f32 and s32 respectively.
The actual error was the artifact combiner creating a copy between f32/i32
which fails in the machine verifier. Maybe we could create a bitcast there.
However i32 is more efficient for us and matches well with how argument
lowering keeps f16 and bf16 in i32 copies to/from physical registers.
Also starting from f16 store, G_STORE %0(f16), %1(p1) :: (store (f16),
and doing widen scalar to 32 bit type, i32 makes more sense since store
will store 16 least significant bits G_STORE %0(i32), %1(p1) :: (store (f16)
compared to G_STORE %0(f32), %1(p1) :: (store (f16), which looks incorrect if
we assume input was really in f32 format.
Commit: 16e213f7dd3b8a2ec93b3015268efb8f59c9b52d
https://github.com/llvm/llvm-project/commit/16e213f7dd3b8a2ec93b3015268efb8f59c9b52d
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.shuffle.ll
Log Message:
-----------
[AMDGPU][GlobalISel] Fix wrong half selection in wave.shuffle lowering (#210661)
selectWaveShuffleIntrin XORed ThreadID with the shifted index instead of
the original index, picking the wrong lane half on wave64 targets
without wave wide bpermute (GFX10/GFX11)
Commit: 75ee393652ca86f5d9b3670be5fa04d2bd8bb95a
https://github.com/llvm/llvm-project/commit/75ee393652ca86f5d9b3670be5fa04d2bd8bb95a
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-weird-size.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
Log Message:
-----------
AMDGPU/GlobalISel: Use integer as MMO type for loads and stores lowering (#210096)
We could get away with just the type from MMO in most cases, but MMO splitting
creates MMO with LLT::scalar and we prefer integer.
Commit: 112aac39131f7fdc8b4a50cb3fb13ef293e1c620
https://github.com/llvm/llvm-project/commit/112aac39131f7fdc8b4a50cb3fb13ef293e1c620
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll
Log Message:
-----------
AMDGPU/GlobalISel: Fix extending load narrow scalar (#210097)
isAnyScalar is explicit LLT::scalar check but we want to narrow scalar
integer types as well.
Commit: 88a19bdee051ef4ce15fc4e29f50a328b80b0166
https://github.com/llvm/llvm-project/commit/88a19bdee051ef4ce15fc4e29f50a328b80b0166
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.inst.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll
Log Message:
-----------
AMDGPU/GlobalISel: Use integers for read-any-lane split type (#210098)
Commit: 92873559f90a35f89ebc5ac94a6d7e4c3a419ecb
https://github.com/llvm/llvm-project/commit/92873559f90a35f89ebc5ac94a6d7e4c3a419ecb
Author: Raphael Isemann <rise at apple.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbutil.py
M lldb/test/API/macosx/simulator/TestSimulatorPlatform.py
M lldb/test/API/macosx/simulator/hello.cpp
M lldb/test/API/tools/lldb-server/apple-simulator/TestAppleSimulatorOSType.py
Log Message:
-----------
[lldb][test] Bump safety timeout in simulator tests to fix flakyness (#209180)
On really slow machines, the current 10 second timeout can expire and
cause the test to randomly fail. Bump the timeout to 10 minutes which 60
times the current value and should be unreachable even on the slowest of
machines.
To avoid making the tests run for 10 minutes, we now consistently kill
the test process on shutdown using the subprocess list in lldbtest which
gets killed on tearDown.
Commit: 1e18a0f4d758ff796acbb3987c2d01c02bb223a1
https://github.com/llvm/llvm-project/commit/1e18a0f4d758ff796acbb3987c2d01c02bb223a1
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/test/Transforms/MemCpyOpt/callslot.ll
Log Message:
-----------
[MemCpyOpt] Precommit tests for PR210667 (NFC) (#210708)
Commit: 92539cf3a83e22dd589fa97d223da06339dc304a
https://github.com/llvm/llvm-project/commit/92539cf3a83e22dd589fa97d223da06339dc304a
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/test/Transforms/MemCpyOpt/callslot.ll
Log Message:
-----------
[MemCpyOpt] Ensure call slot optz does not lower destination alloca alignment (#210667)
A destination alloca's alignment could have been unconditionally
overwritten, letting a lower-aligned source incorrectly undo a
previous alignment increase. This issue has been addressed by
considering the maximum alignment between the new source target
and current destination, adhering to what the existing comment
already promises.
Fixes: https://github.com/llvm/llvm-project/issues/208092.
Commit: 4f939577de61ffdf85087499b99aa3686ed362cd
https://github.com/llvm/llvm-project/commit/4f939577de61ffdf85087499b99aa3686ed362cd
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
Log Message:
-----------
GlobalISel: Use extended LLTs in f64 to f16 fptrunc lowering (#210099)
Commit: e3016ce1a9a14c690c90a343849d45837d9d95d7
https://github.com/llvm/llvm-project/commit/e3016ce1a9a14c690c90a343849d45837d9d95d7
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
Log Message:
-----------
GlobalISel: Use extended LLTs in extract lowering (#210100)
Commit: e8969304fe0ca32088120702267772a622f5f746
https://github.com/llvm/llvm-project/commit/e8969304fe0ca32088120702267772a622f5f746
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
Log Message:
-----------
AMDGPU/GlobalISel: Use integers for clamp i64 to i16 prelegalizer combine (#210101)
Commit: 066fba24b425211e80deb4486ba56ddf70472c37
https://github.com/llvm/llvm-project/commit/066fba24b425211e80deb4486ba56ddf70472c37
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
Log Message:
-----------
AMDGPU/GlobalISel: Use extended LLTs in AMDGPUCombinerHelper (#210102)
Here we also had to change comparisons to extended LLTs to avoid
matching bfloats. In the old scalar version, before the switch to extended
LLTs, s16 was treated as f16 and bf16 was combined as if it were f16.
Commit: 499fd10534993eec4aefc8f06026fc4876bbd371
https://github.com/llvm/llvm-project/commit/499fd10534993eec4aefc8f06026fc4876bbd371
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M .github/workflows/libcxx-build-and-test.yaml
Log Message:
-----------
[libc++] Run macOS CI on self-hosted runners instead of Github ones (#210124)
This should increase our capacity and allow better turn around times,
and potentially unblock additional test coverage.
Note that this change implies that the self-hosted runners provide a
version of Xcode that is supported by libc++ (the latest released one),
which is currently the case.
Commit: 03b780679bdb5152aef0182dfc8b2f1d182a94e0
https://github.com/llvm/llvm-project/commit/03b780679bdb5152aef0182dfc8b2f1d182a94e0
Author: Thurston Dang <thurston at google.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M libcxx/test/libcxx-03/strings/basic.string/string.capacity/allocation_size.pass.cpp
M libcxx/test/libcxx-03/strings/basic.string/string.capacity/max_size.pass.cpp
Log Message:
-----------
[libc++][test] Fix build failure from typo in #171785 (#210552)
If `__STDCPP_DEFAULT_NEW_ALIGNMENT__` is not defined, these tests will
fail to build due to a typo that was added in #171785.
Commit: 8888665966f14abfac4f2c352846abfc1212d8e5
https://github.com/llvm/llvm-project/commit/8888665966f14abfac4f2c352846abfc1212d8e5
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
Log Message:
-----------
AMDGPU/GlobalISel: Fix type mismatch in regbank combiner for applyD16Load (#210103)
Commit: 743813d10023a0616833062f5d448284022b8063
https://github.com/llvm/llvm-project/commit/743813d10023a0616833062f5d448284022b8063
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs-i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
Log Message:
-----------
GlobalISel: Use extended LLTs in lshr narrow combine (#210298)
Commit: a8617034c4a7cc733676a31b736d3118fec34259
https://github.com/llvm/llvm-project/commit/a8617034c4a7cc733676a31b736d3118fec34259
Author: Hubert Tong <hubert.reinterpretcast at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
A libcxx/test/selftest/if-else.sh.cpp
M libcxx/utils/libcxx/test/format.py
Log Message:
-----------
[libc++][utils] Fix LIT `%if` substitution support (#209358)
Update the applySubstitutions call in `libcxx/utils/libcxx/test/format.py` to match the
change to `llvm/utils/lit/lit/TestRunner.py` done in 1041a9642ba0.
Commit: 3fc6711ccaf60c15371402c3ee7776fde5f01b4f
https://github.com/llvm/llvm-project/commit/3fc6711ccaf60c15371402c3ee7776fde5f01b4f
Author: zhijian lin <zhijian at ca.ibm.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
M llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
M llvm/test/CodeGen/PowerPC/aix-crspill.ll
M llvm/test/CodeGen/PowerPC/aix32-crsave.mir
M llvm/test/CodeGen/PowerPC/cc.ll
M llvm/test/CodeGen/PowerPC/crsave.ll
M llvm/test/CodeGen/PowerPC/p10-spill-creq.ll
M llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll
M llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
M llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
M llvm/test/CodeGen/PowerPC/ppc64-rop-protection-aix.ll
M llvm/test/CodeGen/PowerPC/ppc64-rop-protection.ll
Log Message:
-----------
[PowerPC]optimize the epilogue for restore non volatile cr fields (#202339)
For AIX and ELFv2 ABI,
1. When we only spill one non-volatile CR field , using one
mfocrf/mtocrf instruction.
2. when spill two or more non-volatile CR fields, using one mfcr/mtcr
instead of multi mfocrf/mtocrf instructions
Commit: faf7261308da236627ae8f813d17d6e1ef1e9d68
https://github.com/llvm/llvm-project/commit/faf7261308da236627ae8f813d17d6e1ef1e9d68
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M libcxx/test/std/algorithms/alg.nonmodifying/alg.all_of/all_of.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.any_of/any_of.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.none_of/none_of.pass.cpp
Log Message:
-----------
[libc++] Bring std::{any,all,none}_of tests up to current standards (#209266)
The tests for these algorithms were minimal, didn't test all iterator
categories, and the constexpr coverage didn't follow our current
practice. This patch brings all three tests (which are very similar) up
to our current standards.
Assisted by Claude
Commit: 44e37579d19c7d0965166808c77f9e7ebf407df9
https://github.com/llvm/llvm-project/commit/44e37579d19c7d0965166808c77f9e7ebf407df9
Author: Kareem Ergawy <kergawy at nvidia.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M flang/lib/Lower/Bridge.cpp
M flang/test/Lower/if_construct_execute_region_wrap.f90
Log Message:
-----------
[flang][PFT-to-MLIR] reset Evaluation blocks between entry-point passes (#210681)
A subprogram with an alternate ENTRY is lowered by walking the shared
PFT once per entry. Evaluation::block is populated during each walk
(top-level createEmptyBlocks and inside wrapUnstructuredConstruct's own
createEmptyBlocks), but the second pass previously inherited stale
pointers into the first entry's function/wrap regions. For a wrappable
IfConstruct nested inside a structured container, the entry block that
genFIR(IfConstruct) starts before creating its scf.execute_region then
sent the builder into the previous entry's region, and the wrap plus its
inner load ended up in the wrong func:
subroutine foo(a)
integer a
entry bar(a)
if (a .eq. 1) then
if (a .ne. 3) stop
end if
end subroutine
produced both scf.execute_region ops in _QPfoo, with an inner fir.load
referencing bar's %arg0 — 'fir.load' op using value defined outside the
region.
Fix: null every Evaluation::block in the shared PFT at the start of each
entry-point pass, so createEmptyBlocks fills a clean tree and later
reads (in particular the landing-pad reposition in genFIR(IfConstruct))
never see a pointer from a prior pass.
Co-authored-by: Claude Opus 4.7 <noreply at anthropic.com>
Commit: 2a33792a2ec1a980259bd9388834e3c1fa53af3d
https://github.com/llvm/llvm-project/commit/2a33792a2ec1a980259bd9388834e3c1fa53af3d
Author: Matthias Wippich <mfwippich at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M clang/include/clang/AST/TypeBase.h
M clang/include/clang/Basic/CMakeLists.txt
M clang/include/clang/Basic/ExpressionTraits.h
M clang/include/clang/Basic/Specifiers.h
M clang/include/clang/Basic/TokenKinds.def
A clang/include/clang/Basic/Traits.td
R clang/include/clang/Basic/TransformTypeTraits.def
M clang/include/clang/Basic/TypeTraits.h
M clang/include/clang/Sema/DeclSpec.h
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/AST/TypePrinter.cpp
M clang/lib/ASTMatchers/Dynamic/Marshallers.cpp
M clang/lib/ASTMatchers/Dynamic/Marshallers.h
M clang/lib/Basic/ExpressionTraits.cpp
M clang/lib/Basic/TypeTraits.cpp
M clang/lib/Format/FormatToken.h
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Lex/Lexer.cpp
M clang/lib/Lex/PPMacroExpansion.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Parse/ParseExpr.cpp
M clang/lib/Parse/ParseExprCXX.cpp
M clang/lib/Parse/ParseStmt.cpp
M clang/lib/Parse/ParseTentative.cpp
M clang/lib/Sema/DeclSpec.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaTemplateVariadic.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Sema/SemaTypeTraits.cpp
M clang/utils/TableGen/CMakeLists.txt
A clang/utils/TableGen/ClangTraitsEmitter.cpp
M clang/utils/TableGen/TableGen.cpp
M clang/utils/TableGen/TableGenBackends.h
Log Message:
-----------
[clang][NFC] move traits to tablegen (#201491)
This patch moves all traits to a tablegen file.
The motivation for this change is a review comment in
https://github.com/llvm/llvm-project/pull/142341 - since then about a
year has passed and we've accumulated 9 standard names that are
maintained separately from their corresponding trait definitions. For
transform type traits we keep the standard names around as well. While
this is still a reasonably low number, it is definitely going to keep
increasing.
Commit: 0549fbe55ba4f9fc172591a61b04700d4ff5045e
https://github.com/llvm/llvm-project/commit/0549fbe55ba4f9fc172591a61b04700d4ff5045e
Author: Daemon <daemonpilot at hotmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/knownbits-maxdepth.mir
Log Message:
-----------
[GlobalISel] Synchronize GISelValueTrackingAnalysis behavior across Legacy and New PM paths (#207013)
This patch aligns the New Pass Manager (NPM) implementation of
`GISelValueTrackingAnalysis::run()` with the Legacy pass manager by
dynamically adjusting the maximum search depth based on the optimization
level. This eliminates behavioral discrepancies between the two code
paths, reducing migration risks and ensuring consistent compilation
performance and code generation quality across both code paths.
Commit: 97a105f8e681e8e9e5778b6f8bf95a8c365a05f6
https://github.com/llvm/llvm-project/commit/97a105f8e681e8e9e5778b6f8bf95a8c365a05f6
Author: Sergio Afonso <safonsof at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M flang/include/flang/Semantics/openmp-directive-sets.h
A flang/test/Semantics/OpenMP/teams_loop.f90
Log Message:
-----------
[Flang][OpenMP] Allow `parallel loop` inside of `teams` (#210679)
A missing `parallel_loop` directive in the `nestedTeamsAllowedSet`
currently causes code like the following to report a semantics issue:
```f90
!$omp teams
!$omp parallel loop
do i=1, 10
end do
!$omp end teams
```
This patch makes sure to accept it, since `parallel` is an allowed
construct to be immediately nested inside of `teams`, even when combined
with another construct.
Commit: e16e6077cbc2b0ab6335dd4dc67e3a6318b1ad3a
https://github.com/llvm/llvm-project/commit/e16e6077cbc2b0ab6335dd4dc67e3a6318b1ad3a
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
Log Message:
-----------
[SCEV] Use m_scev_AffineAddRec in get{Zero,Sign}ExtendExprImpl (NFC) (#210082)
It's a small win in number of lines, and reduces the nesting level a
bit.
Suggested in https://github.com/llvm/llvm-project/pull/208805
PR: https://github.com/llvm/llvm-project/pull/210082
Commit: 35aa7b529ebeafc9767a4c5398047a92b86bd4a8
https://github.com/llvm/llvm-project/commit/35aa7b529ebeafc9767a4c5398047a92b86bd4a8
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/test/SemaCXX/attr-no-specializations.cpp
Log Message:
-----------
Ensure that we properly propagate template decl attributes to redecls (#209873)
Variable and class templates weren't forwarding their declaration
attributes that were attached directly to them (at the moment, the only
one I could find that had this issue is the no_specialization attr). The
result was that intermediate redeclarations would prevent the
diagnostics from happening.
This patch ensures we propagate them properly for variable and class
templates. It seems our function templates already do the right thing.
Fixes: #209812
Commit: b16c5f7cc88c9f41d904cc73d5618cc7453ac862
https://github.com/llvm/llvm-project/commit/b16c5f7cc88c9f41d904cc73d5618cc7453ac862
Author: yinghao <73093416+andreww0210 at users.noreply.github.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXProxyRegErasure.cpp
A llvm/test/CodeGen/NVPTX/proxy-reg-erasure-kill-flag.mir
M llvm/test/CodeGen/NVPTX/proxy-reg-erasure.mir
Log Message:
-----------
[NVPTX] Clear unsafe kill flags in NVPTXProxyRegErasure (#198143)
Fixes #198142
After replacing regsiter, stale `killed` flags my leave on non-terminal
uses, breaking liveness and triggering MachineVerifier errors.
Fix this by conservatively dropping the `killed` flag on `ToReg`.
Commit: bb5c8d5bea4817a2447d9acfdb7ef11c4323ddac
https://github.com/llvm/llvm-project/commit/bb5c8d5bea4817a2447d9acfdb7ef11c4323ddac
Author: Ömer Sinan Ağacan <omeragacan at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/docs/LangRef.md
Log Message:
-----------
[LangRef] Add immarg attributes to memcpy, memset, memmove isvolatile args (#210669)
Commit: 1ed1ca59245bfa949919f31cef5fd5c87c20c6ec
https://github.com/llvm/llvm-project/commit/1ed1ca59245bfa949919f31cef5fd5c87c20c6ec
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/Scalar/GVN.h
M llvm/lib/Transforms/Scalar/GVN.cpp
Log Message:
-----------
Re-commit: [GVN] Remove the "private" `llvm::gvn` namespace (NFC) (#210712)
Re-commit of https://github.com/llvm/llvm-project/pull/210323 after
adding
a forward declaration for GVNLegacyPass class to work around GCC
compilation
failure.
Move `AvailableValue` and `AvailableValueInBlock` into GVNPass, similar
to other helper types.
Retain `llvm::gvn::GVNLegacyPass` as just `llvm::GVNLegacyPass` -
"legacy" is already a sufficent hint and it is not going to become more
"private" by stacking "gvn" prefixes to the name.
Ideally, `GVNLegacyPass` should be defined in an anonymous namespace,
but
that is not possible because it is declared as a friend of GVNPass.
Commit: 6998fd59e16026a00fee8e83243c0ec91047fee3
https://github.com/llvm/llvm-project/commit/6998fd59e16026a00fee8e83243c0ec91047fee3
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
A llvm/test/Transforms/Inline/AMDGPU/inline-max-bb-debug.ll
Log Message:
-----------
[AMDGPU] Print max-BB inline rejections
Commit: 6f744fb04cf1cf30b45ff73883566eeebb7eeb7d
https://github.com/llvm/llvm-project/commit/6f744fb04cf1cf30b45ff73883566eeebb7eeb7d
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 2a33792 (#210726)
This fixes 2a33792a2ec1a980259bd9388834e3c1fa53af3d.
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=2a33792a2ec1a980259bd9388834e3c1fa53af3d
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 4c5b4f40c4ac77f1b50a90451fd040356748ac6a
https://github.com/llvm/llvm-project/commit/4c5b4f40c4ac77f1b50a90451fd040356748ac6a
Author: Sergey Semenov <sergey.semenov at intel.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M libsycl/test/basic/platform_get_devices.cpp
M libsycl/test/lit.cfg.py
M libsycl/test/usm/alloc_functions.cpp
Log Message:
-----------
[libsycl][E2E] Compile all E2E tests with -fsycl (#204115)
Commit: 2549a2c39b4b86b035df052948bd3f867728b075
https://github.com/llvm/llvm-project/commit/2549a2c39b4b86b035df052948bd3f867728b075
Author: Sergey Semenov <sergey.semenov at intel.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M libsycl/CMakeLists.txt
Log Message:
-----------
[libsycl][NFC] Move the cmake msvc DLL check (#193485)
Addresses a review comment from
https://github.com/llvm/llvm-project/pull/188770
Commit: 7bbed7999de1a60c790a3b0f01d965c18fd832e8
https://github.com/llvm/llvm-project/commit/7bbed7999de1a60c790a3b0f01d965c18fd832e8
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/test/Fir/array-coor-canonicalization.fir
A flang/test/Fir/box-dims-folding.fir
M flang/test/Fir/boxaddr-folding.fir
Log Message:
-----------
[flang] Fold reads of fir.create_box components (#210388)
Fold fir.box_addr and constant-dimension fir.box_dims of a descriptor
built by fir.create_box back to the operands that built it, so the
create_box can die when nothing consumes it as a real descriptor.
fir.array_coor is intentionally not folded through create_box, since
that would drop its explicit byte strides.
Assisted-by: Cursor
Commit: b2d3db9bfb01ceb821b38dfc57f7965b09f602cf
https://github.com/llvm/llvm-project/commit/b2d3db9bfb01ceb821b38dfc57f7965b09f602cf
Author: Jinsong Ji <jinsong.ji at intel.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
A llvm/test/Analysis/Delinearization/multidim_pointer_addrspace.ll
Log Message:
-----------
[SCEV] Derive element size from the access's own pointer address space (#209824)
ScalarEvolution::getElementSize always derived the element-size SCEV
using a generic address-space-0 pointer index type. On targets whose
data layout uses different pointer index widths per address space (for
example, where some address spaces use 32-bit pointers and others
64-bit), a load/store through a narrow address space produced an access
function SCEV of one width but an element-size SCEV of another.
Delinearization then called SCEVDivision::divide with numerator and
denominator of mismatched types, tripping the assertion added in
a9d295d615a8 once the implicit sign-extension was removed in
23a32bcedb91.
Derive the index type from the memory access's actual pointer operand
address space so the element-size SCEV matches the width of the access
function's SCEV.
Commit: 9c024f3a83cf2469b27ae42c1a8d3ab635da3dc1
https://github.com/llvm/llvm-project/commit/9c024f3a83cf2469b27ae42c1a8d3ab635da3dc1
Author: YongKang Zhu <yongzhu at fb.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M bolt/lib/Passes/Instrumentation.cpp
R bolt/test/X86/instrument-funcs-file.s
Log Message:
-----------
[BOLT] Drop option --instrument-funcs-file (#210217)
Commit: 34aefe9744fa83fa222d7f28e073c693c2c4ff5b
https://github.com/llvm/llvm-project/commit/34aefe9744fa83fa222d7f28e073c693c2c4ff5b
Author: Brian Cain <brian.cain at oss.qualcomm.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M clang/cmake/caches/hexagon-unknown-linux-musl-clang-dist.cmake
M clang/cmake/caches/hexagon-unknown-linux-musl-clang-dylib-dist.cmake
Log Message:
-----------
[Hexagon] Fix compiler-rt install dir type, scope sanitizers (#209375)
COMPILER_RT_INSTALL_LIBRARY_DIR must be CACHE STRING, not CACHE PATH: a
relative PATH-typed cache entry resolves against the runtimes sub-build
directory instead of CMAKE_INSTALL_PREFIX, misplacing sanitizer libs.
Replace the explicit COMPILER_RT_BUILD_* ON list with
COMPILER_RT_SANITIZERS_TO_BUILD=all, since those options already default
ON upstream and infeasible sanitizers self-exclude via their own
ALL_<X>_SUPPORTED_ARCH lists.
Add FORCE to the dylib overrides so they take effect after
hexagon-unknown-linux-musl-clang-dist.cmake has already cached them OFF.
Commit: c84d20b18026fc230a7957c8faf3cf3a40d9cb55
https://github.com/llvm/llvm-project/commit/c84d20b18026fc230a7957c8faf3cf3a40d9cb55
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M libc/test/src/sys/socket/linux/CMakeLists.txt
M libc/test/src/sys/socket/linux/sockatmark_test.cpp
M utils/bazel/llvm-project-overlay/libc/test/src/sys/socket/BUILD.bazel
Log Message:
-----------
[libc] Fix sockatmark test (#210655)
When writing the test, I assumed that (linux) domain sockets do not
support OOB data, and that sockatmark returns 0, because it can never
read it.
In fact, as of 2021, linux does support OOB on domain sockets, but this
feature can be turned off at build time (CONFIG_AF_UNIX_OOB). In this
case (or in the case of older kernels), the kernel returns an error (and
the test fails).
Armed with this knowledge, I modify the test to test both "1" (OOB
present) and "0" (no OOB data) cases by actually sending OOB data into
the socket. I use the send call to determine the presence of OOB
support, and have the test skip itself if it is absent. OOB data only
makes sense on stream sockets, so change the socketpair type to that.
---------
Co-authored-by: Jeff Bailey <jbailey at raspberryginger.com>
Commit: 5a19a3a4b9915d19fff1b8298e723ee2b24ebc6a
https://github.com/llvm/llvm-project/commit/5a19a3a4b9915d19fff1b8298e723ee2b24ebc6a
Author: Nerixyz <nerixdev at outlook.de>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M lldb/cmake/modules/LLDBConfig.cmake
M lldb/docs/resources/build.md
Log Message:
-----------
[lldb][Windows] Only embed Python home in Debug config (#209464)
On Windows, we used to embed `PYTHONHOME` by default on Windows. In the
documentation, we say
> This is most useful for developers who simply want to run LLDB after
they build it.
Since we use the limited/stable API now, we're less restricted in the
Python version, so I think it's less of an issue that LLDB won't find
Python. The only configuration where it might cause issues is the debug
configuration, since, when installing Python, you usually don't include
the debug libraries. Thus, you might not have the debug version
(`python3_d.py`) of Python in your PATH.
Commit: 0c0d9ff3b01b5709bda34198a01da2f19b88650e
https://github.com/llvm/llvm-project/commit/0c0d9ff3b01b5709bda34198a01da2f19b88650e
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/fmuladd-copyable-add-part.ll
Log Message:
-----------
[SLP][NFC]Add a test with fmuladd copyables candidates, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/210744
Commit: b7810e97d6281f65e255b36af7b39af18d3d2006
https://github.com/llvm/llvm-project/commit/b7810e97d6281f65e255b36af7b39af18d3d2006
Author: Tom Stellard <tstellar at redhat.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M .github/workflows/release-documentation.yml
Log Message:
-----------
workflows/release-documentation: Add missing secrets (#210421)
Commit: 9ba8a3c8ebf0dee73c7e3e1aa8ae0a81dd6439c7
https://github.com/llvm/llvm-project/commit/9ba8a3c8ebf0dee73c7e3e1aa8ae0a81dd6439c7
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Log Message:
-----------
[AMDGPU] Use simpler form of applyWaitcnt. NFC. (#210736)
Commit: 95f39100f1c1dab2aefbdc42d6e9ca26955535d1
https://github.com/llvm/llvm-project/commit/95f39100f1c1dab2aefbdc42d6e9ca26955535d1
Author: Caroline Newcombe <caroline.newcombe at hpe.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M flang/include/flang/Semantics/openmp-utils.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Semantics/check-omp-loop.cpp
M flang/lib/Semantics/openmp-utils.cpp
A flang/test/Lower/OpenMP/collapse-imperfect-nest.f90
A flang/test/Lower/OpenMP/collapse-labeled-do-host-eval.f90
A flang/test/Lower/OpenMP/collapse-loop-transform.f90
A flang/test/Lower/OpenMP/collapse-target-intervening-todo.f90
M flang/test/Semantics/OpenMP/do-collapse.f90
M flang/test/Semantics/OpenMP/do-concurrent-collapse-60.f90
M flang/test/Semantics/OpenMP/do-concurrent-collapse.f90
M flang/test/Semantics/OpenMP/do08.f90
M flang/test/Semantics/OpenMP/do10.f90
M flang/test/Semantics/OpenMP/do13.f90
M flang/test/Semantics/OpenMP/do15.f90
M flang/test/Semantics/OpenMP/do16.f90
M flang/test/Semantics/OpenMP/do22.f90
A flang/test/Semantics/OpenMP/doacross-nesting-omp60.f90
M flang/test/Semantics/OpenMP/metadirective-loop-applicability.f90
M flang/test/Semantics/OpenMP/metadirective-loop-nest.f90
A flang/test/Semantics/OpenMP/ordered-nesting-omp50.f90
A flang/test/Semantics/OpenMP/ordered-nesting-omp51.f90
Log Message:
-----------
Redo [flang][OpenMP] Implement collapse for imperfectly nested loops (#208528)
Relands https://github.com/llvm/llvm-project/pull/202435, reverted in
https://github.com/llvm/llvm-project/pull/208456 because it broke
lowering of labeled DO loops under collapse with host-evaluated bounds.
Commit: bf2c381c6f9609428f1bfcc8e572cadefdf7e5c9
https://github.com/llvm/llvm-project/commit/bf2c381c6f9609428f1bfcc8e572cadefdf7e5c9
Author: parya03 <34556720+parya03 at users.noreply.github.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/test/CodeGen/ARM/fp-intrinsics-vector.ll
M llvm/test/CodeGen/ARM/fp16-fullfp16.ll
M llvm/test/CodeGen/ARM/strict-fp-int-promote.ll
Log Message:
-----------
[ARM] Add strict uint to FP conversion handling during operation legalization (#208554)
Currently, strict uint to FP conversions for the ARM backend end up
falling through to software emulation.
This commit allows them to be correctly handled using the corresponding
vcvt instruction.
Commit: 65bd2df84bb9e6ee8513a313840d8e2096c82e4d
https://github.com/llvm/llvm-project/commit/65bd2df84bb9e6ee8513a313840d8e2096c82e4d
Author: Aleksandr Popov <42888396+aleks-tmb at users.noreply.github.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll
M llvm/test/Transforms/LoopUnroll/ARM/multi-blocks.ll
M llvm/test/Transforms/LoopUnroll/WebAssembly/basic-unrolling.ll
M llvm/test/Transforms/LoopUnroll/runtime-loop5.ll
M llvm/test/Transforms/LoopUnrollAndJam/unroll-and-jam.ll
Log Message:
-----------
[SCEV] Tighten loop guards range check idiom (#210387)
Previously, the idiom matcher derived the clamp range only from the raw
`(LHS + C1) u< C2` form and rejected wrapped or full ranges.
Intersect the derived range with the known unsigned range of `LHSUnknown`.
This can reduce wrapped or full ranges to a usable interval and allows the
matcher to extract clamps in more cases.
Related to https://github.com/llvm/llvm-project/issues/208778
Commit: 53136bd4b70071169edbae1fd9149a9f4fca6c8c
https://github.com/llvm/llvm-project/commit/53136bd4b70071169edbae1fd9149a9f4fca6c8c
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M flang/lib/Lower/Bridge.cpp
Log Message:
-----------
[flang][NFC] Remove unreachable legacy FORALL/WHERE lowering code from Bridge.cpp (#210639)
The HLFIR lowering migration left a cluster of legacy, now-unreachable
code in Bridge.cpp behind. None of it has a live caller (FORALL is
lowered by genForallNest; DO CONCURRENT by getConcurrentControl):
- forceControlVariableBinding and the old DoLoopOp-based genFIR(const
parser::ConcurrentHeader &) FORALL-nest lowering (the ConcurrentHeader
is not a PFT evaluation node and is never visited).
- The member genInitializerExprValue, implicitIterationSpace/
explicitIterationSpace, genArrayAssignment, and the NDEBUG-only
isFuncResultDesignator.
- The analyzeExplicitSpace overload set, analyzeExplicitSpacePop, and
addMaskVariable.
- The explicitIterSpace / implicitIterSpace members.
These were the only Bridge.cpp users of the legacy expression lowering
(createSome*Assignment / createSomeInitializerExpression) and of
IterationSpace, so their includes (ConvertExpr.h, IterationSpace.h, and
Runtime/Ragged.h, used only by addMaskVariable) are removed as well.
Assisted-by: AI
Commit: 4158229224381e8038617d9e25b8e152551f5e08
https://github.com/llvm/llvm-project/commit/4158229224381e8038617d9e25b8e152551f5e08
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M clang/lib/Sema/SemaCXXScopeSpec.cpp
M clang/test/SemaTemplate/destructor-template.cpp
Log Message:
-----------
[clang] fix a crash for uses of a pseudo-destructor of enum without definition (#210424)
Lookup for the destuctor name in the object type only applies to record
types.
Since this will be backported, there are no release notes.
Fixes #209808
Commit: 272378ef3ce1cbddb37b5c2b1ffe595a123e04fd
https://github.com/llvm/llvm-project/commit/272378ef3ce1cbddb37b5c2b1ffe595a123e04fd
Author: Matthias Wippich <mfwippich at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaOverload.cpp
Log Message:
-----------
[clang][NFC] Extract LookupOverloadedUnaryOp (#210567)
This patch extracts `LookupOverloadedUnaryOp` from
`CreateOverloadedUnaryOp` for consistency with
`LookupOverloadedBinOp`/`CreateOverloadedBinOp`.
Commit: bdfcef52762c746d82326b2e4ce9b2ba470551f4
https://github.com/llvm/llvm-project/commit/bdfcef52762c746d82326b2e4ce9b2ba470551f4
Author: Matthias Wippich <mfwippich at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/AST/PrettyPrinter.h
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/Frontend/ASTConsumers.cpp
M clang/test/AST/ast-print-enum-decl.c
M clang/test/Misc/diag-template-diffing-cxx11.cpp
M clang/test/SemaCXX/static-assert.cpp
Log Message:
-----------
[clang] improve diagnostics for enums (#204682)
This patch makes clang attempt printing enumerator names rather than
C-style cast expressions in more diagnostics (notably static_assert) iff
the value matches an enumerator exactly.
For example, consider a static assertion `static_assert(E ==
TestEnum::B);` where `E` is a constant template argument. Assuming
`(TestEnum)1 == TestEnum::A`, this changes emitted diagnostics as
follows:
```
// old
static assertion failed due to requirement '(TestEnum)1 == TestEnum::B'
// new
static assertion failed due to requirement 'TestEnum::A == TestEnum::B'
```
Commit: b80af9cc2d856e211fa6ac58959e46b5707e9d71
https://github.com/llvm/llvm-project/commit/b80af9cc2d856e211fa6ac58959e46b5707e9d71
Author: Nishant Patel <nishant.b.patel at intel.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
M mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
Log Message:
-----------
[MLIR][XeGPU] Enhance unrolling of convert layout (#209822)
This PR adds rewriteWithRegrouping to unroll ConvertLayoutOp by
extracting at the input inst_data granularity and inserting at the
target inst_data granularity for cancellation during canonicalization.
Assisted by Claude
Commit: 160f9c15b9f1627364d33d56cd7d30fdcb0225ed
https://github.com/llvm/llvm-project/commit/160f9c15b9f1627364d33d56cd7d30fdcb0225ed
Author: Ron Green [NVIDIA] <rogreen at nvidia.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M flang/lib/Parser/openacc-parsers.cpp
M flang/test/Parser/acc-unparse.f90
Log Message:
-----------
[flang][OpenACC] Allow blanks around ':' in more clause separators (#210446)
Several OpenACC clause parsers glue a keyword directly to its `:`
separator in the token string (`"DEVNUM:"`, `"QUEUES:"`, `"FORCE:"`,
`"ZERO:"`, `"READONLY:"`). A blank in a `TokenStringMatch` pattern is
the only place a blank is accepted between characters of the token, so
these spellings rejected an otherwise valid separating space, e.g.
```fortran
!$acc wait(devnum : 1 : 2, 3)
!$acc loop collapse(force : 2)
!$acc data copyin(readonly : a) create(zero : b)
```
This moves the blank in each token string to before the `:` so zero or
more blanks are accepted on either side of the separator, matching
free-form Fortran's treatment of blanks and the spec grammar (which
writes these with spaces around the `:`). It mirrors the earlier fix for
the gang `static`/`dim`/`num` arguments.
Parser/unparse coverage is added for the spaced spellings of the wait
`devnum`/`queues` argument, the collapse `force` modifier, and the
`zero` and `readonly` data modifiers.
Assisted-by: AI
Commit: cfddcac22dabf01901424b746c94d3b6c9bddc4a
https://github.com/llvm/llvm-project/commit/cfddcac22dabf01901424b746c94d3b6c9bddc4a
Author: Caroline Newcombe <caroline.newcombe at hpe.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M flang/test/Semantics/OpenMP/metadirective-loop-nest.f90
Log Message:
-----------
[flang][OpenMP] Fix new metadirective-loop-nest.f90 test expectation with collapse changes in #208528 (#210753)
Commit: 331e5641480d24de1951d30ef6b10362ab3b6acf
https://github.com/llvm/llvm-project/commit/331e5641480d24de1951d30ef6b10362ab3b6acf
Author: Bhavesh M <85327930+beamandala at users.noreply.github.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/include/mlir/Dialect/EmitC/Transforms/Passes.h
M mlir/include/mlir/Dialect/EmitC/Transforms/Passes.td
M mlir/include/mlir/Dialect/EmitC/Transforms/Transforms.h
M mlir/lib/Dialect/EmitC/Transforms/CMakeLists.txt
A mlir/lib/Dialect/EmitC/Transforms/MLGOAddReflectionMap.cpp
A mlir/test/Dialect/EmitC/mlgo-add-reflection-map.mlir
A mlir/test/Target/Cpp/mlgo-add-reflection-map.mlir
Log Message:
-----------
[mlir][EmitC] Create a pass to add a reflection map to a class (#205464)
This creates the `add-reflection-map` pass to add a reflection map and a
helper method to EmitC classes for runtime field lookup.
Details:
- Add headers to import `map` and `string` if not already present.
- For every `ClassOp`:
- Collect all the `FieldOp`s that contain the attribute whose value we
want as the reflection map key. We ignore all `FieldOp`s that contain an
attribute present in `excludedFieldAttrs` and if there's a `FieldOp`
that neither has the attribute we're looking for and isn't excluded by
the presence of one of the `excludedFieldAttrs`, emit and error.
- Create the reflection map where the key is the value of the attribute
in each applicable `FieldOp`'s attribute dictionary and the value is a
pointer to the field's contents.
- Create a `getBufferForName` method which serves as a getter method for
the reflection map.
Based on PR #150572. Key differences:
- Adds a `excluded-field-attrs` option which is a list of attributes
that if present on a field exclude it from the reflection map.
- Adds a helper method called `getBufferForName` which given a string
key returns a pointer to the field's buffer.
Co-authored-by: Jaden Angella <jadenangela8 at gmail.com>
Commit: 83ba8addf60668a971453eed207f9bfdaa379f97
https://github.com/llvm/llvm-project/commit/83ba8addf60668a971453eed207f9bfdaa379f97
Author: Andrew Haberlandt <ahaberlandt at apple.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
M compiler-rt/lib/CMakeLists.txt
M compiler-rt/lib/asan/CMakeLists.txt
R compiler-rt/lib/asan/asan_ignorelist.txt
M compiler-rt/lib/cfi/CMakeLists.txt
R compiler-rt/lib/cfi/cfi_ignorelist.txt
M compiler-rt/lib/hwasan/CMakeLists.txt
R compiler-rt/lib/hwasan/hwasan_ignorelist.txt
M compiler-rt/lib/msan/CMakeLists.txt
R compiler-rt/lib/msan/msan_ignorelist.txt
A compiler-rt/lib/sanitizer_ignorelists/CMakeLists.txt
A compiler-rt/lib/sanitizer_ignorelists/asan_ignorelist.txt
A compiler-rt/lib/sanitizer_ignorelists/cfi_ignorelist.txt
A compiler-rt/lib/sanitizer_ignorelists/hwasan_ignorelist.txt
A compiler-rt/lib/sanitizer_ignorelists/msan_ignorelist.txt
Log Message:
-----------
[compiler-rt] Move sanitizer ignorelists to sanitizer-ignorelists target (#200518)
This adds a `sanitizer-ignorelists` target to compiler-rt, allowing the
ignorelists to be built independently of the sanitizer runtimes. The
ignorelists are still built by default, but this change is not quite
NFC: when any of the sanitizers are built, all of the ignorelists will
be included (rather than the individual runtime ignorelists being built
with their respective runtimes).
For _why_ we want to be able to build these independently of the
runtimes, see
https://github.com/llvm/llvm-project/pull/195690#issuecomment-4384573223
I did not move the dfsan abilist to this new target because it is not as
straightforward as a copying a static file.
Assisted-by: Claude
rdar://175962064
Commit: d2e70aa7e546f7f2bbcf398b42151e464ce1098e
https://github.com/llvm/llvm-project/commit/d2e70aa7e546f7f2bbcf398b42151e464ce1098e
Author: Alex Langford <alangford at apple.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderDarwin.cpp
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderDarwin.h
Log Message:
-----------
[lldb] Remove unused method DynamicLoaderDarwin::ImageInfo::FindSegment (#210155)
This method is unused.
Commit: b559a53427f926a603a1755f60d98e06e2b7e1d2
https://github.com/llvm/llvm-project/commit/b559a53427f926a603a1755f60d98e06e2b7e1d2
Author: A. Jiang <de34 at live.cn>
Date: 2026-07-21 (Tue, 21 Jul 2026)
Changed paths:
M libcxx/docs/Status/Cxx17Papers.csv
M libcxx/docs/Status/Cxx23Papers.csv
M libcxx/docs/Status/Cxx26Issues.csv
M libcxx/docs/Status/Cxx26Papers.csv
Log Message:
-----------
[libc++][docs] Avoid talking about other implementations on DR status (#210637)
Standard library implementations consistently treat (or will
consistently treat) some LWG papers as Defect Reports that are also
applied to old modes, despite that they are not officially listed as
Defect Reports in WG21 meeting minutes. We used to say "other
implementations (namely MSVC STL and libstdc++) will do the same" for
some of them.
However, such sentences will become outdated soon when other
implementations actually do so. It is possibly better to avoid saying
so, which potentially requires synchronizing our documentation with
other implementations.
Commit: eb7677457c1611c02a6362d9eae043987c02ea25
https://github.com/llvm/llvm-project/commit/eb7677457c1611c02a6362d9eae043987c02ea25
Author: Prabhu Rajasekaran <prabhukr at google.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/test/tools/llvm-readobj/ELF/call-graph-info-warn-malformed.test
M llvm/test/tools/llvm-readobj/ELF/call-graph-info.test
M llvm/tools/llvm-readobj/ELFDumper.cpp
Log Message:
-----------
[llvm-readobj] Print all callgraph sections (#198929)
Ensure that `llvm-readobj` / `llvm-readelf` processes and dumps all
SHT_LLVM_CALL_GRAPH sections present in an object file, rather
than just the first one.
**Motivation:**
Consider this `foo.s` file
```
.pushsection .text, "axG", %progbits, foo
.globl foo
foo:
ret
.pushsection .llvm.callgraph, "?", %llvm_call_graph
.byte 0, 0
.dc.a foo
.quad 0
.popsection
.popsection
.pushsection .text, "axG", %progbits, bar
.globl foo
bar:
ret
.pushsection .llvm.callgraph, "?", %llvm_call_graph
.byte 0, 0
.dc.a bar
.quad 0
.popsection
.popsection
```
`clang -c foo.s && llvm-readelf --elf-output-style=JSON --pretty-print
--call-graph-info foo.o` on that shows that there is only one record
reported because the current implementation just looked at the first
SHT_LLVM_CALL_GRAPH section and then ignored all others. This patch will
address this gap by iterating over all the SHT_LLVM_CALL_GRAPH sections.
Commit: c5204abb4ee22b720528b8c9263d9bf1a5b10d34
https://github.com/llvm/llvm-project/commit/c5204abb4ee22b720528b8c9263d9bf1a5b10d34
Author: Gang Chen <gangc at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
A llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/amdgpu-scattered-filter.mir
A llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/amdgpu-scattered-filter.mir.filter.expected
M llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-filter.mir.filter-out.expected
M llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-filter.mir.filter.expected
A llvm/test/tools/UpdateTestChecks/update_mir_test_checks/amdgpu-filter.test
M llvm/utils/UpdateTestChecks/mir.py
Log Message:
-----------
[llvm-utils][Tools] fix mir-check filter to handle scattered check-lines (#209226)
When filtered output was not consecutive, the auto-update script was not
able to generate working checklines.
Commit: 3ec4c1783b7dd490d68594e4e46fe309c5fbfbeb
https://github.com/llvm/llvm-project/commit/3ec4c1783b7dd490d68594e4e46fe309c5fbfbeb
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/include/llvm/BinaryFormat/ELFRelocs/AArch64.def
M llvm/test/tools/llvm-readobj/ELF/reloc-types-aarch64.test
Log Message:
-----------
[PAC][llvm-readobj][ELF][AArch64] Define R_AARCH64_AUTH_TLSDESC_CALL reloc (#199503)
See specification https://github.com/ARM-software/abi-aa/pull/395
Commit: c4026e4350fd4d70692f205aff8764055a8b4ce1
https://github.com/llvm/llvm-project/commit/c4026e4350fd4d70692f205aff8764055a8b4ce1
Author: Zachary Yedidia <zyedidia at gmail.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M libunwind/src/DwarfInstructions.hpp
M libunwind/src/UnwindRegistersSave.S
Log Message:
-----------
[LFI][libunwind] Omit unsuppported stg/za instructions for LFI target (#209392)
Under the LFI target the SVE `za` are not currently supported, and
neither is the `stg` instruction. When included in an LFI program they
cause verification failures due to being unsupported instructions. This
patch omits them from compilation when targeting LFI.
Commit: 33b9e91b76073bdce71951199c7ed0efcf41d14c
https://github.com/llvm/llvm-project/commit/33b9e91b76073bdce71951199c7ed0efcf41d14c
Author: Justin Fargnoli <jfargnoli at nvidia.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/Scalar/LoopUnrollPass.h
M llvm/include/llvm/Transforms/Utils/UnrollLoop.h
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
M llvm/test/Other/new-pm-print-pipeline.ll
M llvm/test/Other/print-passes.ll
A llvm/test/Transforms/LoopUnroll/prepare-for-lto.ll
Log Message:
-----------
[LoopUnroll] Add `prepare-for-lto` pass option (#192153)
Expose `UnrollCostEstimator`'s `PrepareForLTO` flag as a pass option for
`LoopUnrollPass` and `LoopFullUnrollPass`. When enabled, loops
containing calls that may be inlined during the LTO post-link phase are
left rolled in the pre-link phase, deferring the decision until LTO
post-link inlining has completed.
Commit: a6b49df4454ae85b8fc500d549d4b614f4c6d535
https://github.com/llvm/llvm-project/commit/a6b49df4454ae85b8fc500d549d4b614f4c6d535
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M lld/ELF/SymbolTable.cpp
M lld/ELF/SymbolTable.h
M lld/ELF/Symbols.cpp
M lld/test/ELF/version-script-symver-extern.s
M lld/test/ELF/version-script-symver.s
Log Message:
-----------
[ELF] Apply version script patterns to name-versioned definitions by node (#208882)
Like GNU ld, a definition whose name specifies a version (foo@@v1 or
foo at v1) should be governed solely by its own version node, with global
patterns checked before local ones and no exact-over-wildcard
precedence. Also fix #202259 (`local: foo*` does not localize defined
`foo@@v1`)
```
old new (= GNU ld)
symbol foo@@v1
v1 { local: foo; } (own node) localized localized
v2 { local: foo; } (other node) localized exported
v1 { local: foo*; } (own node) exported localized
v1 { local: *; } (own node) exported localized
v1 { global: foo*; local: foo; } localized exported
symbol foo3 at v1
v1 { global: foo3*; local: foo3; } localized exported
v1 { global: *; local: foo3*; } localized exported
```
assignExactVersion now skips name-versioned symbols, and the
synthesized "pat at v1" patterns and includeNonDefault parameters are
removed. Instead, parseSymbolVersion matches the version-less name
(demangled for extern "C++" patterns) against the symbol's own node,
localizing the symbol if a local: pattern matches and no global:
pattern does. An exact pattern still performs a "pat at v1" lookup so that
a pattern matching only foo at v1 is not reported as undefined. "attempt
to reassign" diagnostics no longer apply to name-versioned symbols.
Commit: a04f87fdd9b59c6089bf731c669c6f149208363c
https://github.com/llvm/llvm-project/commit/a04f87fdd9b59c6089bf731c669c6f149208363c
Author: Haowei <haowei at google.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M clang/cmake/modules/ClangConfig.cmake.in
M compiler-rt/cmake/Modules/CompilerRTUtils.cmake
M llvm/cmake/modules/LLVMConfig.cmake.in
M runtimes/CMakeLists.txt
Log Message:
-----------
Reapply "Skipping host target exports during cross-compilation" (#210… (#210496)
This reverts commit 42eb7db188f23625872b6f1d722979a3100d170e. This
reland 3fbb037d03e7ff1ef1cd9156363e895af7caaf98 (#209922).
Under CMake 4+, calling add_library(... SHARED IMPORTED) on a target
platform that lacks dynamic linking support triggers a fatal error. This
becomes an issue when building LLVM and runtimes for baremetal targets
like armv6m-none-eabi. This patch adds the option
"LLVM_OMIT_EXPORTS_FROM_CONFIG" in LLVM. When used in sub builds like
LLVM runtimes, it makes CMake to skip including the LLVM and Clang
exports. This mitigates the CMake 4 errors on baremetal runtimes.
42eb7db188f23625872b6f1d722979a3100d170e originally
apply this flag on all runtimes build and causing issues on runtimes
like intel-sycl-gpu, amdgpu-offload-ubuntu-22-cmake-build-only.
This PR only set this flag when the target platform lacks shared library
support.
Commit: 1020bbfc6e9e93f304ddb1329e2fa58ef26831c5
https://github.com/llvm/llvm-project/commit/1020bbfc6e9e93f304ddb1329e2fa58ef26831c5
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M lld/test/ELF/amdgpu-abi-version-err.s
M lld/test/ELF/amdgpu-abi-version.s
M lld/test/ELF/amdgpu-duplicate-sym.s
M lld/test/ELF/amdgpu-elf-flags-err.s
M lld/test/ELF/amdgpu-elf-flags.s
M lld/test/ELF/amdgpu-globals.s
M lld/test/ELF/amdgpu-relocs.s
M lld/test/ELF/amdgpu-relocs2.s
M lld/test/ELF/amdgpu-tid.s
M lld/test/ELF/emulation-amdgpu.s
M lld/test/ELF/lto/amdgcn-oses.ll
A lld/test/ELF/lto/amdgpu.ll
Log Message:
-----------
lld: Migrate amdgpu tests to use subarch triples (#210114)
Commit: 7b9ab3a48198aa6bb2130e4302b0dcb66e980f90
https://github.com/llvm/llvm-project/commit/7b9ab3a48198aa6bb2130e4302b0dcb66e980f90
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/include/clang/Basic/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn
M llvm/utils/gn/secondary/clang/utils/TableGen/BUILD.gn
Log Message:
-----------
[gn build] Port 2a33792a2ec1 (#210772)
Commit: 55e5cc2ab21be2ef375e5235a961def0e27a2e1a
https://github.com/llvm/llvm-project/commit/55e5cc2ab21be2ef375e5235a961def0e27a2e1a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/test/Analysis/CostModel/AMDGPU/fsub.ll
M llvm/test/Analysis/CostModel/AMDGPU/fused_costs.ll
M llvm/test/Analysis/DotMachineCFG/AMDGPU/functions.mir
M llvm/test/Analysis/DotMachineCFG/AMDGPU/irreducible.mir
M llvm/test/Analysis/Lint/const-store.ll
M llvm/test/Analysis/MemorySSA/ptr-const-mem.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/atomics-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/atomics.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-diverge-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-loop-diverge.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/branch-outside-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/diverged-entry-basic-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/exit-divergence-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/irreducible-2-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/join-loopexit-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/loads-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/never-uniform-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/temporal-divergence.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/deprecated/hidden-diverge.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/deprecated/irreducible-1.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/irreducible-2.ll
M llvm/test/Assembler/amdgpu-image-atomic-attributes.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extendedLLTs-err.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extendedLLTs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.offset-split.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/merge-values-s16-true16.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_dpp_lds_expected_active_lanes.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
M llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir
M llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir
M llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
M llvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir
M llvm/test/CodeGen/AMDGPU/coexec-rewrite-mfma.ll
M llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-flat-scratch-svs.mir
M llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr-hsa.ll
M llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr-rel32.mir
M llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr.ll
M llvm/test/CodeGen/AMDGPU/expand-variadic-call.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll
M llvm/test/CodeGen/AMDGPU/finalize-isel-kill-scc-vcc.mir
M llvm/test/CodeGen/AMDGPU/flat-error-unsupported-gpu-hsa.ll
M llvm/test/CodeGen/AMDGPU/issue196582-late-codegenprepare-crash-non-po2.ll
M llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load-exported.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.format.i8.xfail.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-calls.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-constants.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-contents-legalization-alignment.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-control-flow.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-mem-transfer.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-memops.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-p7-in-memory.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-pointer-ops.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-unoptimized-debug-data.ll
M llvm/test/CodeGen/AMDGPU/mcinstlower-external-symbol-reloc.mir
M llvm/test/CodeGen/AMDGPU/noop-shader-O0.ll
M llvm/test/CodeGen/AMDGPU/pack-half-to-lshl-or.ll
M llvm/test/CodeGen/AMDGPU/packed_shl64_combine.ll
M llvm/test/CodeGen/AMDGPU/phi-elimination-assertion.mir
M llvm/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir
M llvm/test/CodeGen/AMDGPU/rewrite-out-arguments-2.ll
M llvm/test/CodeGen/AMDGPU/s-barrier-signal-var-gep.ll
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-dead-def-join.mir
M llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwwmregs-dbg-noreg.mir
M llvm/test/CodeGen/AMDGPU/strict_fptrunc_bf16.ll
M llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
M llvm/test/CodeGen/AMDGPU/v_mov_b64-isel.ll
M llvm/test/CodeGen/AMDGPU/vgpr-setreg-pred-block.mir
M llvm/test/CodeGen/Generic/GlobalISel/irtranslator-byte-type.ll
M llvm/test/CodeGen/Generic/bfloat-op.ll
M llvm/test/CodeGen/Generic/bfloat.ll
M llvm/test/CodeGen/Generic/half-op.ll
M llvm/test/CodeGen/Generic/half.ll
M llvm/test/CodeGen/Generic/live-debug-label.ll
M llvm/test/CodeGen/MIR/AMDGPU/empty-custom-regmask.mir
M llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
M llvm/test/CodeGen/MIR/AMDGPU/intrinsics.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-fixed-stack.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-stack.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-no-stack.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index2.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
M llvm/test/CodeGen/MIR/AMDGPU/llc-target-cpu-attr-from-cmdline-ir.mir
M llvm/test/CodeGen/MIR/AMDGPU/llc-target-cpu-attr-from-cmdline.mir
M llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll
M llvm/test/CodeGen/MIR/AMDGPU/lr-split-flag.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-dynlds-align-invalid-case.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir
M llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi-def.mir
M llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
M llvm/test/CodeGen/MIR/AMDGPU/noconvergent-invalid.mir
M llvm/test/CodeGen/MIR/AMDGPU/noconvergent.mir
M llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-empty-lanemask.mir
M llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-lanemask.mir
M llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-missing-lparen.mir
M llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-missing-rparen.mir
M llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand.mir
M llvm/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_wait_alu_missing_operand_crash.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_waitcnt_missing_operand_crash.mir
M llvm/test/CodeGen/MIR/AMDGPU/sgpr-for-exec-copy-invalid-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-invalid.mir
M llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-not-a-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir
M llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir
M llvm/test/CodeGen/MIR/AMDGPU/stack-id.mir
M llvm/test/CodeGen/MIR/AMDGPU/target-flags.mir
M llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
M llvm/test/CodeGen/MIR/AMDGPU/target-memoperands.mir
M llvm/test/CodeGen/MIR/AMDGPU/vgpr-for-agpr-copy-invalid-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-invalid-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-not-a-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs.mir
M llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_do_not_internalize.ll
M llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_mem_intrinsics.ll
M llvm/test/Instrumentation/InstrProfiling/amdgpu-3d-grid.ll
M llvm/test/Instrumentation/InstrProfiling/amdgpu-contiguous-counters.ll
M llvm/test/Instrumentation/InstrProfiling/amdgpu-instrumentation.ll
M llvm/test/Instrumentation/InstrProfiling/amdgpu-uniform-counters.ll
M llvm/test/Instrumentation/InstrProfiling/amdgpu-wave32.ll
M llvm/test/Instrumentation/InstrProfiling/amdgpu-wave64.ll
M llvm/test/Instrumentation/InstrProfiling/platform.ll
M llvm/test/LTO/AMDGPU/closed-world-assumption.ll
M llvm/test/MachineVerifier/AMDGPU/undef-virt-reg-entry-block.mir
M llvm/test/MachineVerifier/AMDGPU/verifier-implicit-virtreg-invalid-physreg-liveness.mir
M llvm/test/MachineVerifier/AMDGPU/verify-implicit-def.mir
M llvm/test/MachineVerifier/AMDGPU/writelane_m0.mir
M llvm/test/MachineVerifier/convergencectrl/AMDGPU/cycles.mir
M llvm/test/MachineVerifier/convergencectrl/AMDGPU/mixed2.mir
M llvm/test/MachineVerifier/convergencectrl/AMDGPU/region-nesting.mir
M llvm/test/MachineVerifier/stack-protector-offset.mir
M llvm/test/ThinLTO/AMDGPU/force-import-all.ll
M llvm/test/Transforms/Attributor/heap_to_stack_gpu.ll
M llvm/test/Transforms/Attributor/memory_locations_gpu.ll
M llvm/test/Transforms/Attributor/reduced/openmp_opt_constant_type_crash.ll
M llvm/test/Transforms/Attributor/value-simplify-gpu.ll
M llvm/test/Transforms/FunctionAttrs/make-buffer-rsrc.ll
M llvm/test/Transforms/IndVarSimplify/AMDGPU/addrspace-7-doesnt-crash.ll
M llvm/test/Transforms/InstCombine/AMDGPU/phi-with-incoming-from-load.ll
M llvm/test/Transforms/InstCombine/AMDGPU/select-from-load.ll
M llvm/test/Transforms/LICM/AMDGPU/buffer-rsrc-ptrs.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/dont-adjust-globalobj-alignment.ll
M llvm/test/Transforms/LoopLoadElim/pr46854-adress-spaces.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-icmpzero-mixed-ptr-width.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-void-inseltpoison.ll
M llvm/test/Transforms/LoopUnroll/AMDGPU/scev-mul-expansion-cost.ll
M llvm/test/Transforms/OpenMP/add_attributes_amdgcn.ll
M llvm/test/Transforms/OpenMP/barrier_removal.ll
M llvm/test/Transforms/OpenMP/indirect_call_kernel_info_crash.ll
M llvm/test/Transforms/OpenMP/spmdization_constant_prop.ll
M llvm/test/Transforms/OpenMP/spmdization_kernel_env_dep.ll
M llvm/test/Transforms/OpenMP/value-simplify-openmp-opt.ll
M llvm/test/Transforms/PGOProfile/amdgpu-disable-value-profiling.ll
M llvm/test/Transforms/PhaseOrdering/varargs.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/lower-gep.ll
M llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/pr23975.ll
M llvm/test/Transforms/StructurizeCFG/hoist-zerocost-nested.ll
M llvm/test/Transforms/StructurizeCFG/rebuild-ssa-infinite-loop-inseltpoison.ll
M llvm/test/Transforms/StructurizeCFG/rebuild-ssa-infinite-loop.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_no_merge_comments.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_no_merge_comments.ll.expected
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/source-lines.ll
M llvm/test/tools/llvm-objdump/Offloading/Inputs/binary.yaml
M llvm/test/tools/llvm-objdump/Offloading/coff.test
M llvm/test/tools/llvm-objdump/Offloading/elf.test
Log Message:
-----------
AMDGPU: Migrate more tests to amdgpu triples (#210113)
These were missed in previous conversions for whatever reason.
Some are new tests added after I did the bulk migration, some
are special cases.
Commit: 6665357608334ed956517d8aa3df472b0553e50d
https://github.com/llvm/llvm-project/commit/6665357608334ed956517d8aa3df472b0553e50d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/include/llvm/IR/RuntimeLibcallsImpl.td
M llvm/test/TableGen/RuntimeLibcallEmitter-bad-system-library-entry-error.td
M llvm/test/TableGen/RuntimeLibcallEmitter-calling-conv.td
M llvm/test/TableGen/RuntimeLibcallEmitter-conflict-warning.td
M llvm/test/TableGen/RuntimeLibcallEmitter-nested-predicates-error.td
M llvm/test/TableGen/RuntimeLibcallEmitter-predicate-cc-sort.td
M llvm/test/TableGen/RuntimeLibcallEmitter.td
M llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp
Log Message:
-----------
RuntimeLibcalls: Rename RuntimeLibcallPredicate to RuntimeLibcallAvailability (#210648)
Rename to avoid confusing partial name collisions in future changes.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 69baca13234a29ff02a685c6082e40aec1682c65
https://github.com/llvm/llvm-project/commit/69baca13234a29ff02a685c6082e40aec1682c65
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-20 (Mon, 20 Jul 2026)
Changed paths:
M .github/workflows/libcxx-build-and-test.yaml
M .github/workflows/release-documentation.yml
M bolt/lib/Passes/Instrumentation.cpp
R bolt/test/X86/instrument-funcs-file.s
M clang/cmake/caches/hexagon-unknown-linux-musl-clang-dist.cmake
M clang/cmake/caches/hexagon-unknown-linux-musl-clang-dylib-dist.cmake
M clang/cmake/modules/ClangConfig.cmake.in
M clang/docs/InternalsManual.rst
M clang/docs/ReleaseNotes.md
M clang/include/clang/AST/PrettyPrinter.h
M clang/include/clang/AST/TypeBase.h
M clang/include/clang/Basic/CMakeLists.txt
M clang/include/clang/Basic/ExpressionTraits.h
M clang/include/clang/Basic/Specifiers.h
M clang/include/clang/Basic/TokenKinds.def
A clang/include/clang/Basic/Traits.td
R clang/include/clang/Basic/TransformTypeTraits.def
M clang/include/clang/Basic/TypeTraits.h
M clang/include/clang/Sema/DeclSpec.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/SMTConstraintManager.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/SMTConv.h
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/AST/TypePrinter.cpp
M clang/lib/ASTMatchers/Dynamic/Marshallers.cpp
M clang/lib/ASTMatchers/Dynamic/Marshallers.h
M clang/lib/Basic/ExpressionTraits.cpp
M clang/lib/Basic/TypeTraits.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/Driver/ToolChains/FreeBSD.cpp
M clang/lib/Driver/ToolChains/Serenity.cpp
M clang/lib/Format/FormatToken.h
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Frontend/ASTConsumers.cpp
M clang/lib/Lex/Lexer.cpp
M clang/lib/Lex/PPMacroExpansion.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Parse/ParseExpr.cpp
M clang/lib/Parse/ParseExprCXX.cpp
M clang/lib/Parse/ParseStmt.cpp
M clang/lib/Parse/ParseTentative.cpp
M clang/lib/Sema/DeclSpec.cpp
M clang/lib/Sema/SemaCXXScopeSpec.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaTemplateVariadic.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Sema/SemaTypeTraits.cpp
M clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt
A clang/lib/StaticAnalyzer/Checkers/DanglingPtrDeref.cpp
R clang/lib/StaticAnalyzer/Checkers/ReportDanglingPtrDeref.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineC.cpp
M clang/lib/StaticAnalyzer/Core/SValBuilder.cpp
M clang/test/AST/ast-print-enum-decl.c
M clang/test/Analysis/logical-ops.c
A clang/test/Analysis/z3/z3-bitint-arithmetic.c
M clang/test/Analysis/z3/z3-logicalexpr-eval.c
M clang/test/Driver/freebsd-mips-as.c
M clang/test/Driver/freebsd.c
M clang/test/Misc/diag-template-diffing-cxx11.cpp
M clang/test/SemaCXX/attr-no-specializations.cpp
M clang/test/SemaCXX/cxx2c-fold-exprs.cpp
M clang/test/SemaCXX/static-assert.cpp
M clang/test/SemaTemplate/destructor-template.cpp
M clang/utils/TableGen/CMakeLists.txt
A clang/utils/TableGen/ClangTraitsEmitter.cpp
M clang/utils/TableGen/TableGen.cpp
M clang/utils/TableGen/TableGenBackends.h
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
M compiler-rt/cmake/Modules/CompilerRTUtils.cmake
M compiler-rt/lib/CMakeLists.txt
M compiler-rt/lib/asan/CMakeLists.txt
R compiler-rt/lib/asan/asan_ignorelist.txt
M compiler-rt/lib/cfi/CMakeLists.txt
R compiler-rt/lib/cfi/cfi_ignorelist.txt
M compiler-rt/lib/hwasan/CMakeLists.txt
R compiler-rt/lib/hwasan/hwasan_ignorelist.txt
M compiler-rt/lib/msan/CMakeLists.txt
R compiler-rt/lib/msan/msan_ignorelist.txt
A compiler-rt/lib/sanitizer_ignorelists/CMakeLists.txt
A compiler-rt/lib/sanitizer_ignorelists/asan_ignorelist.txt
A compiler-rt/lib/sanitizer_ignorelists/cfi_ignorelist.txt
A compiler-rt/lib/sanitizer_ignorelists/hwasan_ignorelist.txt
A compiler-rt/lib/sanitizer_ignorelists/msan_ignorelist.txt
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M flang-rt/lib/cuda/allocator.cpp
M flang/include/flang/Lower/AbstractConverter.h
M flang/include/flang/Lower/Bridge.h
M flang/include/flang/Lower/PFTBuilder.h
M flang/include/flang/Optimizer/Builder/Runtime/CUDA/Descriptor.h
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/include/flang/Runtime/CUDA/descriptor.h
M flang/include/flang/Semantics/openmp-directive-sets.h
M flang/include/flang/Semantics/openmp-utils.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/PFTBuilder.cpp
M flang/lib/Lower/Runtime.cpp
M flang/lib/Optimizer/Builder/Runtime/CUDA/Descriptor.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Transforms/AffinePromotion.cpp
M flang/lib/Optimizer/Transforms/ControlFlowConverter.cpp
M flang/lib/Optimizer/Transforms/FIRToSCF.cpp
M flang/lib/Parser/openacc-parsers.cpp
M flang/lib/Semantics/check-omp-loop.cpp
M flang/lib/Semantics/openmp-utils.cpp
M flang/test/Fir/CUDA/cuda-code-gen.mlir
M flang/test/Fir/FirToSCF/do-loop.fir
M flang/test/Fir/array-coor-canonicalization.fir
A flang/test/Fir/box-dims-folding.fir
M flang/test/Fir/boxaddr-folding.fir
M flang/test/Fir/loop01.fir
M flang/test/HLFIR/assumed_shape_with_value_keyword.f90
M flang/test/HLFIR/optional_dummy.f90
M flang/test/Integration/OpenMP/parallel-private-reduction-worstcase.f90
M flang/test/Integration/ivdep.f90
M flang/test/Lower/CUDA/cuda-allocatable.cuf
M flang/test/Lower/CUDA/cuda-derived.cuf
M flang/test/Lower/CUDA/cuda-return01.cuf
M flang/test/Lower/CUDA/cuda-return02.cuf
M flang/test/Lower/HLFIR/intrinsic-subroutines.f90
M flang/test/Lower/MIF/change_team2.f90
M flang/test/Lower/OpenACC/Todo/acc-unstructured-combined-construct.f90
M flang/test/Lower/OpenACC/Todo/do-loops-to-acc-loops-todo.f90
M flang/test/Lower/OpenACC/acc-cache.f90
M flang/test/Lower/OpenACC/acc-declare.f90
M flang/test/Lower/OpenACC/acc-terminator.f90
M flang/test/Lower/OpenACC/acc-unstructured.f90
A flang/test/Lower/OpenMP/collapse-imperfect-nest.f90
A flang/test/Lower/OpenMP/collapse-labeled-do-host-eval.f90
A flang/test/Lower/OpenMP/collapse-loop-transform.f90
A flang/test/Lower/OpenMP/collapse-target-intervening-todo.f90
M flang/test/Lower/OpenMP/default-clause.f90
M flang/test/Lower/OpenMP/hlfir-seqloop-parallel.f90
M flang/test/Lower/OpenMP/loop-compound.f90
M flang/test/Lower/OpenMP/parallel-private-clause-fixes.f90
M flang/test/Lower/OpenMP/parallel-reduction3.f90
M flang/test/Lower/OpenMP/sections-predetermined-private.f90
M flang/test/Lower/OpenMP/shared-loop.f90
M flang/test/Lower/OpenMP/stop-stmt-in-region.f90
M flang/test/Lower/OpenMP/unstructured.f90
M flang/test/Lower/OpenMP/wsloop-reduction-allocatable-array-minmax.f90
M flang/test/Lower/OpenMP/wsloop-unstructured.f90
M flang/test/Lower/OpenMP/wsloop-variable.f90
M flang/test/Lower/allocatable-polymorphic.f90
M flang/test/Lower/branching-directive.f90
M flang/test/Lower/dispatch.f90
M flang/test/Lower/do_concurrent_loop_in_nested_block.f90
M flang/test/Lower/do_loop.f90
A flang/test/Lower/do_loop_execute_region_wrap.f90
M flang/test/Lower/do_loop_unstructured.f90
M flang/test/Lower/fail_image.f90
A flang/test/Lower/if_construct_execute_region_wrap.f90
M flang/test/Lower/ifconvert.f90
M flang/test/Lower/infinite_loop.f90
M flang/test/Lower/inline_directive.f90
M flang/test/Lower/ivdep.f90
M flang/test/Lower/loops.f90
M flang/test/Lower/loops2.f90
M flang/test/Lower/mixed_loops.f90
M flang/test/Lower/nsw.f90
M flang/test/Lower/pre-fir-tree02.f90
M flang/test/Lower/while_loop.f90
M flang/test/Parser/acc-unparse.f90
M flang/test/Semantics/OpenMP/do-collapse.f90
M flang/test/Semantics/OpenMP/do-concurrent-collapse-60.f90
M flang/test/Semantics/OpenMP/do-concurrent-collapse.f90
M flang/test/Semantics/OpenMP/do08.f90
M flang/test/Semantics/OpenMP/do10.f90
M flang/test/Semantics/OpenMP/do13.f90
M flang/test/Semantics/OpenMP/do15.f90
M flang/test/Semantics/OpenMP/do16.f90
M flang/test/Semantics/OpenMP/do22.f90
A flang/test/Semantics/OpenMP/doacross-nesting-omp60.f90
M flang/test/Semantics/OpenMP/metadirective-loop-applicability.f90
M flang/test/Semantics/OpenMP/metadirective-loop-nest.f90
A flang/test/Semantics/OpenMP/ordered-nesting-omp50.f90
A flang/test/Semantics/OpenMP/ordered-nesting-omp51.f90
A flang/test/Semantics/OpenMP/teams_loop.f90
M flang/test/Transforms/DoConcurrent/skip_all_nested_loops.f90
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/hdr/CMakeLists.txt
M libc/test/UnitTest/CMakeLists.txt
M libc/test/UnitTest/ExecuteFunctionUnix.cpp
M libc/test/UnitTest/HermeticTestUtils.cpp
M libc/test/UnitTest/LibcDeathTestExecutors.cpp
M libc/test/src/stdlib/CMakeLists.txt
M libc/test/src/sys/socket/linux/CMakeLists.txt
M libc/test/src/sys/socket/linux/sockatmark_test.cpp
M libcxx/docs/Status/Cxx17Papers.csv
M libcxx/docs/Status/Cxx23Issues.csv
M libcxx/docs/Status/Cxx23Papers.csv
M libcxx/docs/Status/Cxx26Issues.csv
M libcxx/docs/Status/Cxx26Papers.csv
M libcxx/include/__configuration/availability.h
M libcxx/include/__functional/function.h
M libcxx/include/__ranges/lazy_split_view.h
M libcxx/test/libcxx-03/strings/basic.string/string.capacity/allocation_size.pass.cpp
M libcxx/test/libcxx-03/strings/basic.string/string.capacity/max_size.pass.cpp
M libcxx/test/libcxx/atomics/builtin_clear_padding.pass.cpp
A libcxx/test/selftest/if-else.sh.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.all_of/all_of.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.any_of/any_of.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.none_of/none_of.pass.cpp
M libcxx/test/std/numerics/numeric.ops/numeric.ops.sat/saturating.bitint.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.adjacent.transform/helpers.h
M libcxx/test/std/ranges/range.adaptors/range.adjacent.transform/iterator/member_types.compile.pass.cpp
M libcxx/utils/libcxx/test/format.py
M libsycl/CMakeLists.txt
M libsycl/test/basic/platform_get_devices.cpp
M libsycl/test/lit.cfg.py
M libsycl/test/usm/alloc_functions.cpp
M libunwind/src/DwarfInstructions.hpp
M libunwind/src/UnwindRegistersSave.S
M lld/ELF/Arch/RISCV.cpp
M lld/ELF/SymbolTable.cpp
M lld/ELF/SymbolTable.h
M lld/ELF/Symbols.cpp
M lld/test/ELF/amdgpu-abi-version-err.s
M lld/test/ELF/amdgpu-abi-version.s
M lld/test/ELF/amdgpu-duplicate-sym.s
M lld/test/ELF/amdgpu-elf-flags-err.s
M lld/test/ELF/amdgpu-elf-flags.s
M lld/test/ELF/amdgpu-globals.s
M lld/test/ELF/amdgpu-relocs.s
M lld/test/ELF/amdgpu-relocs2.s
M lld/test/ELF/amdgpu-tid.s
M lld/test/ELF/emulation-amdgpu.s
M lld/test/ELF/lto/amdgcn-oses.ll
A lld/test/ELF/lto/amdgpu.ll
M lld/test/ELF/riscv-feature-zicfilp-unlabeled.s
M lld/test/ELF/version-script-symver-extern.s
M lld/test/ELF/version-script-symver.s
M lldb/cmake/modules/LLDBConfig.cmake
M lldb/docs/resources/build.md
M lldb/include/lldb/Core/ModuleSpec.h
M lldb/packages/Python/lldbsuite/test/lldbutil.py
M lldb/source/API/SBAddressRangeList.cpp
M lldb/source/API/SBMemoryRegionInfo.cpp
M lldb/source/Breakpoint/Breakpoint.cpp
M lldb/source/Breakpoint/BreakpointLocation.cpp
M lldb/source/Breakpoint/BreakpointLocationList.cpp
M lldb/source/Breakpoint/BreakpointOptions.cpp
M lldb/source/Breakpoint/BreakpointResolverName.cpp
M lldb/source/Breakpoint/Watchpoint.cpp
M lldb/source/Breakpoint/WatchpointList.cpp
M lldb/source/Core/Disassembler.cpp
M lldb/source/Core/DumpDataExtractor.cpp
M lldb/source/Core/DynamicLoader.cpp
M lldb/source/Core/FormatEntity.cpp
M lldb/source/Core/IOHandler.cpp
M lldb/source/Core/IOHandlerCursesGUI.cpp
M lldb/source/Core/Mangled.cpp
M lldb/source/Core/SearchFilter.cpp
M lldb/source/Core/SourceManager.cpp
M lldb/source/DataFormatters/FormattersHelpers.cpp
M lldb/source/DataFormatters/StringPrinter.cpp
M lldb/source/DataFormatters/TypeCategory.cpp
M lldb/source/DataFormatters/TypeSynthetic.cpp
M lldb/source/DataFormatters/ValueObjectPrinter.cpp
M lldb/source/DataFormatters/VectorType.cpp
M lldb/source/Expression/IRInterpreter.cpp
M lldb/source/Expression/Materializer.cpp
M lldb/source/Expression/REPL.cpp
M lldb/source/Host/common/ProcessLaunchInfo.cpp
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderDarwin.cpp
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderDarwin.h
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
M lldb/source/Plugins/TraceExporter/docs/htr.md
M lldb/source/Symbol/SymbolContext.cpp
M lldb/source/Symbol/Type.cpp
M lldb/source/Symbol/UnwindPlan.cpp
M lldb/source/Utility/Event.cpp
M lldb/source/Utility/ProcessInfo.cpp
M lldb/source/Utility/StructuredData.cpp
M lldb/source/ValueObject/ValueObject.cpp
M lldb/test/API/commands/gui/spawn-threads/TestGuiSpawnThreads.py
M lldb/test/API/macosx/simulator/TestSimulatorPlatform.py
M lldb/test/API/macosx/simulator/hello.cpp
M lldb/test/API/tools/lldb-server/apple-simulator/TestAppleSimulatorOSType.py
M llvm/cmake/modules/LLVMConfig.cmake.in
M llvm/docs/LangRef.md
M llvm/include/llvm/Analysis/ConstraintSystem.h
M llvm/include/llvm/BinaryFormat/ELFRelocs/AArch64.def
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
M llvm/include/llvm/IR/IntrinsicInst.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Transforms/Scalar/GVN.h
A llvm/include/llvm/Transforms/Scalar/LogicalSROA.h
M llvm/include/llvm/Transforms/Scalar/LoopUnrollPass.h
M llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
M llvm/include/llvm/Transforms/Utils/UnrollLoop.h
M llvm/lib/Analysis/ConstraintSystem.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Support/Z3Solver.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXProxyRegErasure.cpp
M llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
M llvm/lib/Transforms/Scalar/CMakeLists.txt
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/ExpandMemCmp.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
A llvm/lib/Transforms/Scalar/LogicalSROA.cpp
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
M llvm/lib/Transforms/Utils/FixIrreducible.cpp
M llvm/lib/Transforms/Utils/UnifyLoopExits.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlanValue.h
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Analysis/CostModel/AMDGPU/fsub.ll
M llvm/test/Analysis/CostModel/AMDGPU/fused_costs.ll
A llvm/test/Analysis/Delinearization/multidim_pointer_addrspace.ll
M llvm/test/Analysis/DotMachineCFG/AMDGPU/functions.mir
M llvm/test/Analysis/DotMachineCFG/AMDGPU/irreducible.mir
M llvm/test/Analysis/Lint/const-store.ll
M llvm/test/Analysis/MemorySSA/ptr-const-mem.ll
M llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/atomics-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/atomics.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-diverge-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-loop-diverge.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/branch-outside-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/diverged-entry-basic-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/exit-divergence-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/irreducible-2-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/join-loopexit-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/loads-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/never-uniform-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/temporal-divergence.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/deprecated/hidden-diverge.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/deprecated/irreducible-1.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/irreducible-2.ll
M llvm/test/Assembler/amdgpu-image-atomic-attributes.ll
A llvm/test/CodeGen/AArch64/GlobalISel/knownbits-maxdepth.mir
M llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
M llvm/test/CodeGen/AArch64/scalable_masked_interleaved_stores.ll
M llvm/test/CodeGen/AArch64/sve-ldst-sext.ll
M llvm/test/CodeGen/AArch64/sve-ldst-zext.ll
A llvm/test/CodeGen/AArch64/vector-deinterleave-load.ll
A llvm/test/CodeGen/AArch64/vector-interleave-store.ll
A llvm/test/CodeGen/AArch64/vselect-masked-shift.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-cse-leaves-dead-cast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fcmp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmad.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extendedLLTs-err.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extendedLLTs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctls.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaximum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminimum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def-s1025.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-store-s16-true16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx7.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx8-plus.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fract.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.frexp.mant.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.cd.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.offset-split.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-legalize-range-metadata.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/merge-values-s16-true16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs-i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/no-ctlz-from-umul-to-lshr-in-postlegalizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector-pointer-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-weird-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/trunc-brc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/umed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll
M llvm/test/CodeGen/AMDGPU/add-max.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-sin-cos-f16-f32.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_dpp_lds_expected_active_lanes.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bitop3.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-return-types.ll
M llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir
M llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir
M llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
M llvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
M llvm/test/CodeGen/AMDGPU/coexec-rewrite-mfma.ll
M llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll
M llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-flat-scratch-svs.mir
M llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr-hsa.ll
M llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr-rel32.mir
M llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr.ll
M llvm/test/CodeGen/AMDGPU/expand-variadic-call.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/finalize-isel-kill-scc-vcc.mir
M llvm/test/CodeGen/AMDGPU/flat-error-unsupported-gpu-hsa.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll
M llvm/test/CodeGen/AMDGPU/float-sopc-vopc.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaxnum.ll
M llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminnum.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/fsub-as-fneg-src-modifier.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/issue196582-late-codegenprepare-crash-non-po2.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
M llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll
M llvm/test/CodeGen/AMDGPU/literal64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.flat.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.store.async.from.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load-exported.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.inst.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.format.i8.xfail.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.shuffle.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.modf.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-flat.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-global.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-local.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-calls.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-constants.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-contents-legalization-alignment.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-control-flow.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-mem-transfer.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-memops.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-p7-in-memory.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-pointer-ops.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-unoptimized-debug-data.ll
M llvm/test/CodeGen/AMDGPU/lrint.ll
M llvm/test/CodeGen/AMDGPU/lround.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/mcinstlower-external-symbol-reloc.mir
M llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
M llvm/test/CodeGen/AMDGPU/memset-pattern.ll
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/noop-shader-O0.ll
M llvm/test/CodeGen/AMDGPU/pack-half-to-lshl-or.ll
M llvm/test/CodeGen/AMDGPU/packed_shl64_combine.ll
M llvm/test/CodeGen/AMDGPU/phi-elimination-assertion.mir
M llvm/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/rewrite-out-arguments-2.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/s-barrier-signal-var-gep.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-global.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-smem.ll
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-dead-def-join.mir
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwwmregs-dbg-noreg.mir
M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fptrunc_bf16.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
M llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
M llvm/test/CodeGen/AMDGPU/v_mov_b64-isel.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
M llvm/test/CodeGen/AMDGPU/vgpr-setreg-pred-block.mir
M llvm/test/CodeGen/ARM/fp-intrinsics-vector.ll
M llvm/test/CodeGen/ARM/fp16-fullfp16.ll
M llvm/test/CodeGen/ARM/strict-fp-int-promote.ll
M llvm/test/CodeGen/Generic/GlobalISel/irtranslator-byte-type.ll
M llvm/test/CodeGen/Generic/bfloat-op.ll
M llvm/test/CodeGen/Generic/bfloat.ll
M llvm/test/CodeGen/Generic/half-op.ll
M llvm/test/CodeGen/Generic/half.ll
M llvm/test/CodeGen/Generic/live-debug-label.ll
M llvm/test/CodeGen/MIR/AMDGPU/empty-custom-regmask.mir
M llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
M llvm/test/CodeGen/MIR/AMDGPU/intrinsics.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-fixed-stack.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-stack.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-no-stack.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index2.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
M llvm/test/CodeGen/MIR/AMDGPU/llc-target-cpu-attr-from-cmdline-ir.mir
M llvm/test/CodeGen/MIR/AMDGPU/llc-target-cpu-attr-from-cmdline.mir
M llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll
M llvm/test/CodeGen/MIR/AMDGPU/lr-split-flag.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-dynlds-align-invalid-case.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir
M llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi-def.mir
M llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
M llvm/test/CodeGen/MIR/AMDGPU/noconvergent-invalid.mir
M llvm/test/CodeGen/MIR/AMDGPU/noconvergent.mir
M llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-empty-lanemask.mir
M llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-lanemask.mir
M llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-missing-lparen.mir
M llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-missing-rparen.mir
M llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand.mir
M llvm/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_wait_alu_missing_operand_crash.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_waitcnt_missing_operand_crash.mir
M llvm/test/CodeGen/MIR/AMDGPU/sgpr-for-exec-copy-invalid-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-invalid.mir
M llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-not-a-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir
M llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir
M llvm/test/CodeGen/MIR/AMDGPU/stack-id.mir
M llvm/test/CodeGen/MIR/AMDGPU/target-flags.mir
M llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
M llvm/test/CodeGen/MIR/AMDGPU/target-memoperands.mir
M llvm/test/CodeGen/MIR/AMDGPU/vgpr-for-agpr-copy-invalid-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-invalid-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-not-a-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs.mir
A llvm/test/CodeGen/NVPTX/proxy-reg-erasure-kill-flag.mir
M llvm/test/CodeGen/NVPTX/proxy-reg-erasure.mir
M llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
M llvm/test/CodeGen/PowerPC/aix-crspill.ll
M llvm/test/CodeGen/PowerPC/aix32-crsave.mir
M llvm/test/CodeGen/PowerPC/cc.ll
M llvm/test/CodeGen/PowerPC/crsave.ll
M llvm/test/CodeGen/PowerPC/p10-spill-creq.ll
M llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll
M llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
M llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
M llvm/test/CodeGen/PowerPC/ppc64-rop-protection-aix.ll
M llvm/test/CodeGen/PowerPC/ppc64-rop-protection.ll
M llvm/test/CodeGen/RISCV/memcmp-optsize.ll
M llvm/test/CodeGen/RISCV/memcmp.ll
M llvm/test/CodeGen/RISCV/rvp-zip.ll
A llvm/test/CodeGen/SPIRV/constant/fp128-unsupported.ll
M llvm/test/CodeGen/SPIRV/structurizer/HLSLControlFlowHint-pass-check.ll
M llvm/test/CodeGen/X86/avx512-vpternlog-commute.ll
A llvm/test/CodeGen/X86/pr209714.ll
M llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_do_not_internalize.ll
M llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_mem_intrinsics.ll
A llvm/test/Instrumentation/AddressSanitizer/darwin-mte-tag-stripping.ll
M llvm/test/Instrumentation/InstrProfiling/amdgpu-3d-grid.ll
M llvm/test/Instrumentation/InstrProfiling/amdgpu-contiguous-counters.ll
M llvm/test/Instrumentation/InstrProfiling/amdgpu-instrumentation.ll
M llvm/test/Instrumentation/InstrProfiling/amdgpu-uniform-counters.ll
M llvm/test/Instrumentation/InstrProfiling/amdgpu-wave32.ll
M llvm/test/Instrumentation/InstrProfiling/amdgpu-wave64.ll
M llvm/test/Instrumentation/InstrProfiling/platform.ll
M llvm/test/LTO/AMDGPU/closed-world-assumption.ll
M llvm/test/MachineVerifier/AMDGPU/undef-virt-reg-entry-block.mir
M llvm/test/MachineVerifier/AMDGPU/verifier-implicit-virtreg-invalid-physreg-liveness.mir
M llvm/test/MachineVerifier/AMDGPU/verify-implicit-def.mir
M llvm/test/MachineVerifier/AMDGPU/writelane_m0.mir
M llvm/test/MachineVerifier/convergencectrl/AMDGPU/cycles.mir
M llvm/test/MachineVerifier/convergencectrl/AMDGPU/mixed2.mir
M llvm/test/MachineVerifier/convergencectrl/AMDGPU/region-nesting.mir
M llvm/test/MachineVerifier/stack-protector-offset.mir
M llvm/test/Other/new-pm-print-pipeline.ll
M llvm/test/Other/print-passes.ll
M llvm/test/ThinLTO/AMDGPU/force-import-all.ll
M llvm/test/Transforms/Attributor/heap_to_stack_gpu.ll
M llvm/test/Transforms/Attributor/memory_locations_gpu.ll
M llvm/test/Transforms/Attributor/reduced/openmp_opt_constant_type_crash.ll
M llvm/test/Transforms/Attributor/value-simplify-gpu.ll
M llvm/test/Transforms/ConstraintElimination/gep-arithmetic-signed-predicates.ll
A llvm/test/Transforms/ConstraintElimination/lshr.ll
A llvm/test/Transforms/ExpandMemCmp/RISCV/lit.local.cfg
A llvm/test/Transforms/ExpandMemCmp/RISCV/memcmp-strict-align.ll
M llvm/test/Transforms/FixIrreducible/bug45623.ll
M llvm/test/Transforms/FixIrreducible/multiedge.ll
M llvm/test/Transforms/FixIrreducible/nested.ll
M llvm/test/Transforms/FixIrreducible/switch.ll
M llvm/test/Transforms/FixIrreducible/unreachable.ll
M llvm/test/Transforms/FixIrreducible/unsupported-terminator.ll
M llvm/test/Transforms/FunctionAttrs/make-buffer-rsrc.ll
M llvm/test/Transforms/IndVarSimplify/AMDGPU/addrspace-7-doesnt-crash.ll
A llvm/test/Transforms/Inline/AMDGPU/inline-max-bb-debug.ll
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
M llvm/test/Transforms/InstCombine/AMDGPU/phi-with-incoming-from-load.ll
M llvm/test/Transforms/InstCombine/AMDGPU/select-from-load.ll
M llvm/test/Transforms/LICM/AMDGPU/buffer-rsrc-ptrs.ll
A llvm/test/Transforms/LSROA/array.ll
A llvm/test/Transforms/LSROA/basictest.ll
A llvm/test/Transforms/LSROA/escaping.ll
A llvm/test/Transforms/LSROA/nesting.ll
A llvm/test/Transforms/LSROA/normal-gep.ll
A llvm/test/Transforms/LSROA/phi.ll
A llvm/test/Transforms/LSROA/select.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/dont-adjust-globalobj-alignment.ll
M llvm/test/Transforms/LoopLoadElim/pr46854-adress-spaces.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-icmpzero-mixed-ptr-width.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-void-inseltpoison.ll
M llvm/test/Transforms/LoopUnroll/AMDGPU/scev-mul-expansion-cost.ll
M llvm/test/Transforms/LoopUnroll/ARM/multi-blocks.ll
M llvm/test/Transforms/LoopUnroll/WebAssembly/basic-unrolling.ll
A llvm/test/Transforms/LoopUnroll/prepare-for-lto.ll
M llvm/test/Transforms/LoopUnroll/runtime-loop5.ll
M llvm/test/Transforms/LoopUnrollAndJam/unroll-and-jam.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleave-low-vf-cost.ll
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
M llvm/test/Transforms/MemCpyOpt/callslot.ll
M llvm/test/Transforms/OpenMP/add_attributes_amdgcn.ll
M llvm/test/Transforms/OpenMP/barrier_removal.ll
M llvm/test/Transforms/OpenMP/indirect_call_kernel_info_crash.ll
M llvm/test/Transforms/OpenMP/spmdization_constant_prop.ll
M llvm/test/Transforms/OpenMP/spmdization_kernel_env_dep.ll
M llvm/test/Transforms/OpenMP/value-simplify-openmp-opt.ll
M llvm/test/Transforms/PGOProfile/amdgpu-disable-value-profiling.ll
M llvm/test/Transforms/PhaseOrdering/varargs.ll
A llvm/test/Transforms/SLPVectorizer/X86/fmuladd-copyable-add-part.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/lower-gep.ll
M llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/pr23975.ll
M llvm/test/Transforms/StructurizeCFG/hoist-zerocost-nested.ll
M llvm/test/Transforms/StructurizeCFG/rebuild-ssa-infinite-loop-inseltpoison.ll
M llvm/test/Transforms/StructurizeCFG/rebuild-ssa-infinite-loop.ll
M llvm/test/Transforms/UnifyLoopExits/basic.ll
M llvm/test/Transforms/UnifyLoopExits/integer_guards.ll
M llvm/test/Transforms/UnifyLoopExits/multiedge.ll
M llvm/test/Transforms/UnifyLoopExits/nested.ll
M llvm/test/Transforms/UnifyLoopExits/restore-ssa.ll
M llvm/test/Transforms/UnifyLoopExits/switch.ll
M llvm/test/Transforms/UnifyLoopExits/undef-phis.ll
A llvm/test/Transforms/VectorCombine/AArch64/bitreverse-v8i8-to-gpr.ll
A llvm/test/Transforms/VectorCombine/AArch64/load-widening.ll
M llvm/test/Transforms/VectorCombine/X86/load-widening.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_no_merge_comments.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_no_merge_comments.ll.expected
A llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/amdgpu-scattered-filter.mir
A llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/amdgpu-scattered-filter.mir.filter.expected
M llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-filter.mir.filter-out.expected
M llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-filter.mir.filter.expected
A llvm/test/tools/UpdateTestChecks/update_mir_test_checks/amdgpu-filter.test
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/source-lines.ll
M llvm/test/tools/llvm-objdump/Offloading/Inputs/binary.yaml
M llvm/test/tools/llvm-objdump/Offloading/coff.test
M llvm/test/tools/llvm-objdump/Offloading/elf.test
M llvm/test/tools/llvm-readobj/ELF/call-graph-info-warn-malformed.test
M llvm/test/tools/llvm-readobj/ELF/call-graph-info.test
M llvm/test/tools/llvm-readobj/ELF/reloc-types-aarch64.test
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/utils/UpdateTestChecks/mir.py
M llvm/utils/gn/secondary/clang/include/clang/Basic/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Checkers/BUILD.gn
M llvm/utils/gn/secondary/clang/utils/TableGen/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Transforms/Scalar/BUILD.gn
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/include/mlir/Dialect/EmitC/Transforms/Passes.h
M mlir/include/mlir/Dialect/EmitC/Transforms/Passes.td
M mlir/include/mlir/Dialect/EmitC/Transforms/Transforms.h
M mlir/lib/Dialect/EmitC/Transforms/CMakeLists.txt
A mlir/lib/Dialect/EmitC/Transforms/MLGOAddReflectionMap.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsCG.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
A mlir/test/Dialect/EmitC/mlgo-add-reflection-map.mlir
M mlir/test/Dialect/LLVMIR/mem2reg.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-worker-reduction-private.mlir
M mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/pack-unpack-mmt4d.mlir
A mlir/test/Target/Cpp/mlgo-add-reflection-map.mlir
M mlir/test/mlir-tblgen/op-result.td
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsCGTest.cpp
M offload/liboffload/API/Memory.td
M offload/plugins-nextgen/level_zero/include/L0Device.h
M offload/plugins-nextgen/level_zero/include/L0Queue.h
M offload/plugins-nextgen/level_zero/src/L0Device.cpp
M offload/plugins-nextgen/level_zero/src/L0Queue.cpp
M offload/unittests/OffloadAPI/memory/olMemFill.cpp
M orc-rt/include/orc-rt/Session.h
M orc-rt/lib/executor/Session.cpp
M orc-rt/test/unit/SessionTest.cpp
M runtimes/CMakeLists.txt
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/arpa/inet/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/socket/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/arsenm/runtime-libcalls/composable-predicates
Compare: https://github.com/llvm/llvm-project/compare/87febc44fb75...69baca13234a
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