[all-commits] [llvm/llvm-project] c34d2c: [mlir] Fix mem2reg crash on scalable vector store/...

[Aayush Shrivastava via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c34d2c30e86358bfe308558b5e0719e9f5305153
      https://github.com/llvm/llvm-project/commit/c34d2c30e86358bfe308558b5e0719e9f5305153
  Author: Aayush Shrivastava <iamaayushrivastava at gmail.com>
  Date:   2026-07-20 (Mon, 20 Jul 2026)

  Changed paths:
    M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
    M mlir/test/Dialect/LLVMIR/mem2reg.mlir

  Log Message:
  -----------
  [mlir] Fix mem2reg crash on scalable vector store/load with matching type (#209426)

Fixes #209065

`createInsertAndCast/createExtractAndCast` in `LLVMMemorySlot.cpp`
queried the bit size of the source/target types before checking whether
they were already identical. For scalable vector types (e.g.
`vector<[4]xi1>`), this size query implicitly converts a scalable
TypeSize to a scalar, which aborts. `mem2reg` hits this path for any
store or load whose value type exactly matches the slot's element type,
since `getStored/removeBlockingUses` run even when no cast is needed.

This fix adds an early return when the types are already equal, skipping
the size query, consistent with the existing short-circuit in
`areConversionCompatible/castSameSizedTypes`.



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