[all-commits] [llvm/llvm-project] 24c002: [AMDGPU] Enabled GCNTrackers in GCNMaxOccupancySch...
Dhruva Chakrabarti via All-commits
all-commits at lists.llvm.org
Sat Jul 18 13:53:06 PDT 2026
Branch: refs/heads/users/dhruvachak/max_occ_gcn_trackers_enabled
Home: https://github.com/llvm/llvm-project
Commit: 24c00270c548953b566698e425cbf207900dd52a
https://github.com/llvm/llvm-project/commit/24c00270c548953b566698e425cbf207900dd52a
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-07-18 (Sat, 18 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/clmul.ll
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector.ll
M llvm/test/CodeGen/AMDGPU/fceil64.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-args.ll
M llvm/test/CodeGen/AMDGPU/function-returns.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.large.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.small.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.single.2c.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
M llvm/test/CodeGen/AMDGPU/load-local-i16.ll
M llvm/test/CodeGen/AMDGPU/machine-scheduler-rematerialization-scoring.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
M llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
M llvm/test/CodeGen/AMDGPU/packed-u64.ll
M llvm/test/CodeGen/AMDGPU/pr51516.mir
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/rewrite-mfma-form-spill-cost-reset.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
M llvm/test/CodeGen/AMDGPU/rsq.f64.ll
M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir
M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_cost.mir
M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_diff_types.mir
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-ilp-metric-spills.mir
M llvm/test/CodeGen/AMDGPU/schedule-relaxed-occupancy.ll
M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/sema-v-unsched-bundle.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/sibling-call.ll
M llvm/test/CodeGen/AMDGPU/spill-agpr.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
Log Message:
-----------
[AMDGPU] Enabled GCNTrackers in GCNMaxOccupancySchedStrategy.
https://github.com/llvm/llvm-project/pull/169616 introduced scheduling
strategy specific GCNTrackers. This PR follows that template and
enables GCNTrackers for the max-occupancy strategy.
Depends on https://github.com/llvm/llvm-project/pull/184275.
Assisted-by: Cursor/Claude Opus
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