[all-commits] [llvm/llvm-project] e4308c: [AMDGPU][GlobalISel] Fold trivial uniform G_AMDGPU...

[Anshil Gandhi via All-commits]

  Branch: refs/heads/users/gandhi56/globalisel/fold-trivial-uniform-readanylane
  Home:   https://github.com/llvm/llvm-project
  Commit: e4308c7b927c8c27a4b94b084afb5cf7f479848d
      https://github.com/llvm/llvm-project/commit/e4308c7b927c8c27a4b94b084afb5cf7f479848d
  Author: Anshil Gandhi <Anshil.Gandhi at amd.com>
  Date:   2026-07-17 (Fri, 17 Jul 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCombine.td
    M llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-redundant-readanylane.mir
    M llvm/test/CodeGen/AMDGPU/packed-fp32.ll

  Log Message:
  -----------
  [AMDGPU][GlobalISel] Fold trivial uniform G_AMDGPU_READANYLANE

Eliminate redundant G_AMDGPU_READANYLANE (selected as v_readfirstlane_b32)
that only round-trips a uniform value through the VGPR/SGPR banks.

Two complementary changes:

- AMDGPURegBankCombiner: add a combine that replaces a
  G_AMDGPU_READANYLANE whose source is already uniform (an sgpr value
  merely copied into a vgpr) with the original sgpr value.

- AMDGPURegBankLegalize: extend tryMatchMergeReadAnyLane to handle
  merges with mixed sources. When at least one source is a readanylane,
  the merge is rebuilt entirely in the vgpr bank, using each
  readanylane's vgpr operand directly and copying the plain uniform
  sources into vgpr. This removes the sgpr -> vgpr -> sgpr -> vgpr
  round trip for patterns like build_vector(readanylane(x), uniform_y)
  feeding a vector ALU op.

Regenerate affected check lines in packed-fp32.ll and mul.ll and add a
MIR test for the new combine.

Co-authored-by: Cursor <cursoragent at cursor.com>



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