[all-commits] [llvm/llvm-project] a4d12b: [lldb][Windows] Enforce Python 3.11 (#209759)
Slava Zakharin via All-commits
all-commits at lists.llvm.org
Fri Jul 17 13:16:10 PDT 2026
Branch: refs/heads/users/boomanaiden154/main.lit-delete-the-external-shell
Home: https://github.com/llvm/llvm-project
Commit: a4d12bf0c2ab2acfd772a8fd6ad216e3a17e5c49
https://github.com/llvm/llvm-project/commit/a4d12bf0c2ab2acfd772a8fd6ad216e3a17e5c49
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lldb/cmake/modules/FindPythonAndSwig.cmake
Log Message:
-----------
[lldb][Windows] Enforce Python 3.11 (#209759)
https://github.com/llvm/llvm-project/pull/191159 recommended Python 3.11
or later. Now that llvm 23 has branched, we can enforce Python 3.11 as
the minimum requirement.
Commit: 25682c3470410534c59708d7d3e2c9248802485f
https://github.com/llvm/llvm-project/commit/25682c3470410534c59708d7d3e2c9248802485f
Author: Access <ShootingStarDragons at protonmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang-tools-extra/clangd/SemanticHighlighting.cpp
M clang-tools-extra/clangd/unittests/PrerequisiteModulesTest.cpp
Log Message:
-----------
[clangd] highlight import and export keywords for C++20 modules (#204511)
Add syntax highlighting for C++20 module `import` and `export` keywords.
Note: Highlighting of the `export` keyword in a module export statement is not possible, because such statements don't appear in the AST
Commit: 9a4deccf90ae914aa6d99acfff44b24bc5dfcb5c
https://github.com/llvm/llvm-project/commit/9a4deccf90ae914aa6d99acfff44b24bc5dfcb5c
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/CMakeLists.txt
A llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
A llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
Log Message:
-----------
[WebAssembly] Introduce CodeGenPassBuilder
This is the equivalent of TargetPassConfig for the NewPM. This currently
mirrors the existing TargetPassConfig as close as possible, but with
TODOs for passes that have not been ported to the NewPM.
Reviewers: aheejin, sbc100, dschuff
Pull Request: https://github.com/llvm/llvm-project/pull/208983
Commit: f4452848f0a5e827f5732ab390099d7d90084ca0
https://github.com/llvm/llvm-project/commit/f4452848f0a5e827f5732ab390099d7d90084ca0
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyAddMissingPrototypes.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/test/CodeGen/WebAssembly/add-prototypes.ll
Log Message:
-----------
[WebAssembly] Port WebAssemblyAddMissingPrototypesPass to NewPM
Standard pass porting.
Reviewers: dschuff, aheejin, sbc100
Pull Request: https://github.com/llvm/llvm-project/pull/208985
Commit: f69748cd80db74bcd81834b4bba8749fc508f99f
https://github.com/llvm/llvm-project/commit/f69748cd80db74bcd81834b4bba8749fc508f99f
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyFixFunctionBitcasts.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[WebAssembly] Port WebAssemblyFixFunctionBitcastsPass to NewPM
Standard pass porting.
Reviewers: aheejin, dschuff, sbc100
Pull Request: https://github.com/llvm/llvm-project/pull/208986
Commit: 80314ec06f15e7a0bb4b55380e50b2e529c5b0f7
https://github.com/llvm/llvm-project/commit/80314ec06f15e7a0bb4b55380e50b2e529c5b0f7
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/fenv/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/mman/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 36c6568 (#209689)
This fixes 36c6568b04aff4e1cf00a60570ab4a4344692920.
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=36c6568b04aff4e1cf00a60570ab4a4344692920
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 491539a8b801aad5706cc32fc54a319791d57a91
https://github.com/llvm/llvm-project/commit/491539a8b801aad5706cc32fc54a319791d57a91
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyOptimizeReturned.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[WebAssembly] Port WebAssemblyOptimizeReturnedPass
Standard pass porting for the NewPM.
Reviewers: sbc100, dschuff, aheejin
Pull Request: https://github.com/llvm/llvm-project/pull/209036
Commit: 0d93f2aec0b4847761bd8458b7847ce37b85cf03
https://github.com/llvm/llvm-project/commit/0d93f2aec0b4847761bd8458b7847ce37b85cf03
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/test/SemaCXX/enable_if.cpp
Log Message:
-----------
Fix references to complete types in attribute references (#209537)
This is a regression from #197215.
Attributes are not REALLY in the body of a function (though the name of
said function is... awkwardly inaccurate at best), but still need to pay
attention to the completeness of their references. As a result, we
weren't marking the expression as invalid, but were also trying to
evaluate it.
This patch fixes this in 2 ways. First, we re-add the
CXXThisTypeOverride check, but except constant substitution, since that
has some additional 'this' behavior from #197215. x
Secondly, we also make the constant evaluator give up on incomplete
types when handling an L value member. This stops us from trying to
evaluate the value if it is incomplete during template instantiation,
when the type is incomplete. We don't diagnose, since it is still
potentially a constant expression, but isn't currently one.
Fixes: #199527
Commit: 5fcfb4d168eae3e78da8d0f7649bf08a338eff42
https://github.com/llvm/llvm-project/commit/5fcfb4d168eae3e78da8d0f7649bf08a338eff42
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/test/CodeGen/WebAssembly/lower-em-exceptions-allowed.ll
Log Message:
-----------
[WebAssembly] Port WebAssemblyLowerEmscriptenEHSjLjImpl
Standard NewPM pass porting.
Reviewers: dschuff, sbc100, aheejin
Pull Request: https://github.com/llvm/llvm-project/pull/209040
Commit: c2da010159cc318b5fdba4a1fc7deef9438e749d
https://github.com/llvm/llvm-project/commit/c2da010159cc318b5fdba4a1fc7deef9438e749d
Author: David Young <davidayoung at meta.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/test/src/string/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/mman/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/resource/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/socket/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/unistd/BUILD.bazel
Log Message:
-----------
[libc][bazel] Add missing hdr/*_macros deps to test targets (#209761)
Commit b790c5cd2679 (#209449) switched several libc tests to include the
hdr/*_macros.h proxy headers and updated the CMake build accordingly,
but did not update the Bazel overlay. As a result, the Bazel libc test
targets include hdr/*_macros.h (and, via shared headers,
hdr/sys_mman_macros.h) without declaring the corresponding
//libc:hdr_*_macros dependencies, breaking the Bazel build with 'file
not found' / module layering errors.
Mirror the CMake dependency additions into the Bazel overlay so each
test target that includes an hdr macro header depends on the matching
//libc:hdr_*_macros (and //libc:types_struct_rlimit) target.
First found trying to land (#209747).
bazel changes assisted with: claude
cannot build with bazel locally so relying on CI to confirm green
Commit: 044f8a1f151f935d2e718faa5b1d7cb8e8f52bec
https://github.com/llvm/llvm-project/commit/044f8a1f151f935d2e718faa5b1d7cb8e8f52bec
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyReduceToAnyAllTrue.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[WebAssembly] Port WebAssemblyReduceToAnyAllTruePass
Standard NewPM pass porting. Made a little bit annoying by the module
caching that I'm not sure helps much, but I've left it in.
Reviewers: aheejin, dschuff, sbc100
Pull Request: https://github.com/llvm/llvm-project/pull/209043
Commit: 868e3b898dcf243f97885ce0d857a2827f4d1fa3
https://github.com/llvm/llvm-project/commit/868e3b898dcf243f97885ce0d857a2827f4d1fa3
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.chain.arg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
Log Message:
-----------
[AMDGPU] Fix set_inactive known bits to intersect both operands (#201817)
SimplifyDemandedBitsForTargetNode grouped amdgcn_set_inactive with the
single-source readfirstlane/readlane/wwm, taking known bits from operand
1 only
Handle the data from the operand 2 inactive lanes as well
Commit: 8396c758875a11a57a4b6a2b6b06b719c1b2ab1b
https://github.com/llvm/llvm-project/commit/8396c758875a11a57a4b6a2b6b06b719c1b2ab1b
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyRefTypeMem2Local.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[WebAssembly] Port WebAssemblyRefTypeMem2LocalPass
Standard NewPM pass porting.
Reviewers: sbc100, aheejin, dschuff
Pull Request: https://github.com/llvm/llvm-project/pull/209044
Commit: 7e80bca9c9130a49ded8ac500d19942928c3564b
https://github.com/llvm/llvm-project/commit/7e80bca9c9130a49ded8ac500d19942928c3564b
Author: Kseniya Tikhomirova <kseniya.tikhomirova at intel.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M libsycl/test/basic/parallel_for_indexers.cpp
Log Message:
-----------
[libsycl] Add missing include to test (#209722)
Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
Commit: 8a41c1f77732d18eae12409b572fc926df29062b
https://github.com/llvm/llvm-project/commit/8a41c1f77732d18eae12409b572fc926df29062b
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
Log Message:
-----------
[mlir][tosa] Add support for MXFP reshape (#207944)
Adds profile compliance support for MXFP reshape.
Commit: 2375505c7c19cf521b9ed5acaf7f359ddd9f216b
https://github.com/llvm/llvm-project/commit/2375505c7c19cf521b9ed5acaf7f359ddd9f216b
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/CMakeLists.txt
M llvm/lib/Target/WebAssembly/WebAssembly.h
A llvm/lib/Target/WebAssembly/WebAssemblyCoalesceFeaturesAndStripAtomics.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[NFC][WebAssembly] Move WebAssemblyCoalesceFeaturesAndStripAtomics
Move WebAssemblyCoalesceFeaturesAndStripAtomics to a separate file.
Having a pass implemented directly in the TargetMachine file is a bit
weird.
Reviewers: dschuff, sbc100, aheejin
Pull Request: https://github.com/llvm/llvm-project/pull/209046
Commit: a2b6a1bae7904be696d8283b9bb34331c39a54ef
https://github.com/llvm/llvm-project/commit/a2b6a1bae7904be696d8283b9bb34331c39a54ef
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyCoalesceFeaturesAndStripAtomics.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[WebAssembly] Port WebAssemblyCoalesceFeaturesAndStripAtomicsPass
Standard NewPM pass porting.
Reviewers: sbc100, aheejin, dschuff
Pull Request: https://github.com/llvm/llvm-project/pull/209054
Commit: 9d28ea2432d4ac2d4f79d5c2a87117a678b74720
https://github.com/llvm/llvm-project/commit/9d28ea2432d4ac2d4f79d5c2a87117a678b74720
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyNullifyDebugValueLists.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[WebAssembly] Port WebAssemblyNullifyDebugValueListsPass
Standard NewPM pass porting.
Reviewers: sbc100, aheejin, dschuff
Pull Request: https://github.com/llvm/llvm-project/pull/209055
Commit: 66766179575d3193139df7f0c9fc36c414cc84c6
https://github.com/llvm/llvm-project/commit/66766179575d3193139df7f0c9fc36c414cc84c6
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[WebAssembly] Port WebAssemblyFixIrreducibleControlFlowPass
Standard NewPM pass porting.
Reviewers: aheejin, sbc100, dschuff
Pull Request: https://github.com/llvm/llvm-project/pull/209077
Commit: 8bc9dae5c79d418ee96d920eef9a858f58e71530
https://github.com/llvm/llvm-project/commit/8bc9dae5c79d418ee96d920eef9a858f58e71530
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyArgumentMove.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[WebAssembly] Port WebAssemblyArgumentMovePass
Standard NewPM pass porting.
Reviewers: aheejin, sbc100, dschuff
Pull Request: https://github.com/llvm/llvm-project/pull/209368
Commit: 543e714713566ca08c2701973f2c1eafb9757b1a
https://github.com/llvm/llvm-project/commit/543e714713566ca08c2701973f2c1eafb9757b1a
Author: David Young <davidayoung at meta.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
Log Message:
-----------
[lldb][bazel] Add the lldb-mcp binary to the Bazel overlay (#209498)
#143628 added the lldb-mcp tool (an MCP server multiplexer for LLDB),
built by lldb/tools/lldb-mcp/CMakeLists.txt. The Bazel overlay already
models the ProtocolMCP library and the MCP protocol-server plugin, but
not the lldb-mcp executable itself, so it is missing from the Bazel
build.
Add an lldb-mcp cc_binary modeled on the existing lldb-dap target: glob
tools/lldb-mcp/**, expand the macOS Info.plist via expand_template, and
depend on liblldb.wrapper, Host, Utility, ProtocolMCP, and the LLVM
Option/Support libraries. lldb-mcp has no Options.td, so unlike lldb-dap
no gentbl_cc_library is needed.
This properly translates into BUCk internally at Meta and then builds
with buck2, but I cannot validate the bazel build of this new target
directly.
bazel rule generation assisted with: claude
Commit: 426a44a7780c72e523e29218ec89155f97bf5c78
https://github.com/llvm/llvm-project/commit/426a44a7780c72e523e29218ec89155f97bf5c78
Author: Deric C. <cheung.deric at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
R clang/test/AST/HLSL/Texture2D-AST.hlsl
R clang/test/AST/HLSL/Texture2D-scalar-AST.hlsl
R clang/test/AST/HLSL/Texture2D-shorthand-AST.hlsl
R clang/test/AST/HLSL/Texture2D-vector-AST.hlsl
R clang/test/AST/HLSL/Texture2DArray-scalar-AST.hlsl
R clang/test/AST/HLSL/Texture2DArray-shorthand-AST.hlsl
R clang/test/AST/HLSL/Texture2DArray-vector-AST.hlsl
A clang/test/AST/HLSL/Textures-AST.hlsl
A clang/test/AST/HLSL/Textures-scalar-AST.hlsl
A clang/test/AST/HLSL/Textures-shorthand-AST.hlsl
A clang/test/AST/HLSL/Textures-vector-AST.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-CalculateLevelOfDetail.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-Gather.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-GetDimensions.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-Load.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-Mips.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-Sample.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-SampleBias.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-SampleCmp.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-SampleCmpLevelZero.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-SampleGrad.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-SampleLevel.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-Subscript.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-default-explicit-binding.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-default.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-shorthand-contexts.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-CalculateLevelOfDetail.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-Gather.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-Load.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-Mips.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-Sample.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-SampleBias.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-SampleCmp.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-SampleCmpLevelZero.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-SampleGrad.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-SampleLevel.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-Subscript.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-default-explicit-binding.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-default.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-shorthand-contexts.hlsl
A clang/test/CodeGenHLSL/resources/Textures-CalculateLevelOfDetail.hlsl
A clang/test/CodeGenHLSL/resources/Textures-Gather.hlsl
A clang/test/CodeGenHLSL/resources/Textures-GetDimensions.hlsl
A clang/test/CodeGenHLSL/resources/Textures-Load.hlsl
A clang/test/CodeGenHLSL/resources/Textures-Mips.hlsl
A clang/test/CodeGenHLSL/resources/Textures-Sample.hlsl
A clang/test/CodeGenHLSL/resources/Textures-SampleBias.hlsl
A clang/test/CodeGenHLSL/resources/Textures-SampleCmp.hlsl
A clang/test/CodeGenHLSL/resources/Textures-SampleCmpLevelZero.hlsl
A clang/test/CodeGenHLSL/resources/Textures-SampleGrad.hlsl
A clang/test/CodeGenHLSL/resources/Textures-SampleLevel.hlsl
A clang/test/CodeGenHLSL/resources/Textures-Subscript.hlsl
A clang/test/CodeGenHLSL/resources/Textures-default-explicit-binding.hlsl
A clang/test/CodeGenHLSL/resources/Textures-default.hlsl
A clang/test/CodeGenHLSL/resources/Textures-shorthand-contexts.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-CalculateLevelOfDetail.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-GetDimensions.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-Load-errors.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-SampleBias.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-SampleCmp.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-SampleCmpLevelZero.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-SampleGrad.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-SampleLevel.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-Sema.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-Subscript.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-CalculateLevelOfDetail.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-GetDimensions.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-SampleBias.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-SampleCmp.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-SampleCmpLevelZero.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-SampleGrad.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-SampleLevel.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-Sema.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-Subscript.hlsl
A clang/test/SemaHLSL/Resources/Textures-CalculateLevelOfDetail.hlsl
A clang/test/SemaHLSL/Resources/Textures-GetDimensions.hlsl
A clang/test/SemaHLSL/Resources/Textures-Load-errors.hlsl
A clang/test/SemaHLSL/Resources/Textures-SampleBias.hlsl
A clang/test/SemaHLSL/Resources/Textures-SampleCmp.hlsl
A clang/test/SemaHLSL/Resources/Textures-SampleCmpLevelZero.hlsl
A clang/test/SemaHLSL/Resources/Textures-SampleGrad.hlsl
A clang/test/SemaHLSL/Resources/Textures-SampleLevel.hlsl
A clang/test/SemaHLSL/Resources/Textures-Sema.hlsl
A clang/test/SemaHLSL/Resources/Textures-Subscript.hlsl
R clang/test/SemaHLSL/Texture2D-Gather.hlsl
R clang/test/SemaHLSL/Texture2D-GatherCmp-Vulkan.hlsl
R clang/test/SemaHLSL/Texture2D-mips-errors.hlsl
R clang/test/SemaHLSL/Texture2DArray-Gather.hlsl
R clang/test/SemaHLSL/Texture2DArray-GatherCmp-Vulkan.hlsl
R clang/test/SemaHLSL/Texture2DArray-mips-errors.hlsl
A clang/test/SemaHLSL/Textures-Gather.hlsl
A clang/test/SemaHLSL/Textures-GatherCmp-Vulkan.hlsl
A clang/test/SemaHLSL/Textures-mips-errors.hlsl
Log Message:
-----------
[HLSL] Consolidate texture tests (#209348)
Fixes #205878
This PR consolidates all the current texture tests into files that all
texture types can extend by adding new RUN lines.
This should greatly reduce the amount of effort required to implement
and review tests for new texture types.
Assisted by: Claude Opus 4.8
Commit: 43394198cf089eb054c25e141ddb293f502f9948
https://github.com/llvm/llvm-project/commit/43394198cf089eb054c25e141ddb293f502f9948
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[bazel][libc] Add missing header deps (#209767)
For stat/ioctl/size headers
Not sure which commit exactly broke this, maybe #209449
Commit: 469794e66f86f11ae50015f6199179ca83efc58b
https://github.com/llvm/llvm-project/commit/469794e66f86f11ae50015f6199179ca83efc58b
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/MPI-Checker/MPIFunctionClassifier.cpp
M clang/test/Analysis/MPIMock.h
M clang/test/Analysis/mpichecker.cpp
Log Message:
-----------
[analyzer] Recognize missing MPI collectives in MPI-Checker (#209263)
Fixes a false positive in the `optin.mpi.MPI-Checker` where legitimate
code was flagged with "Request 'X' has no matching nonblocking call."
Background for reviewers unfamiliar with MPI or this checker
------------------------------------------------------------
MPI (Message Passing Interface) is the standard API for communication
between processes in HPC/cluster programs (C/C++/Fortran). Many MPI
operations come in a *nonblocking* form, prefixed with "I" (for
"immediate"): e.g. `MPI_Isend`, `MPI_Iscatter`. A nonblocking call
returns immediately and hands back an `MPI_Request` handle; the caller
must later complete it with `MPI_Wait` (or `MPI_Waitall`). Forgetting to
wait, or reusing a request before waiting, are real bugs (buffer reuse
races, leaked requests).
The MPI-Checker (originally contributed as a GSoC 2016 project, and is a
domain-specific check - hence it's in "optin").
It tracks each `MPI_Request` region through a small state machine and
reports: three misuse patterns:
* **missing wait**: a nonblocking call whose request is never waited on
* **double nonblocking**: a request reused by a second nonblocking call
before being waited on
* **unmatched wait**: `MPI_Wait` on a request with no originating
nonblocking call
Root cause
----------
`MPIFunctionClassifier` maintains a hand-written list of known MPI
functions. That list was incomplete: several standard collectives --
notably the vector variants (`MPI_Iscatterv`, `MPI_Igatherv`, ...), the
scans, the reduce-scatter family, and `MPI_Ibarrier` -- were entirely
absent. Because `isNonBlockingType()` returned `false` for them,
`checkDoubleNonblocking()` never recorded the request as Nonblocking, so
the matching `MPI_Wait` looked unmatched and produced a FP.
Note that only
`isNonBlockingType()`/`isWaitType()`/`isMPI_Wait()`/`isMPI_Waitall()`
actually drive the checker; the per-shape predicates (`isScatterType`,
`isGatherType`, `isCollToColl`, etc.) and their backing containers are
currently unused. `checkDoubleNonblocking()` also reads the request from
the *last* argument, which is generic since every nonblocking MPI
function places `MPI_Request*` last -- so no per-function argument
handling is needed.
Fix
---
Register the remaining standard collectives and mark the nonblocking
("I") variants as nonblocking:
* **vector variants**: `MPI_Scatterv`/`Iscatterv`,
`MPI_Gatherv`/`Igatherv`, `MPI_Allgatherv`/`Iallgatherv`,
`MPI_Alltoallv`/`Ialltoallv`, `MPI_Alltoallw`/`Ialltoallw`
* **nonblocking barrier**: `MPI_Ibarrier`
* **scans**: `MPI_Scan`/`Iscan`, `MPI_Exscan`/`Iexscan`
* **reduce-scatter**: `MPI_Reduce_scatter`/`Ireduce_scatter`,
`MPI_Reduce_scatter_block`/`Ireduce_scatter_block`
These functions are not referenced by any per-shape predicate, so they
are added directly to the classification containers without a dedicated
`IdentifierInfo` member. Neighborhood collectives (`MPI_Ineighbor_*`)
and the wait-family beyond `Wait`/`Waitall`
(`Waitany`/`Waitsome`/`Test*`) remain out of scope.
Adds regression tests covering the reported repro (no warning), and
confirms double-nonblocking and missing-wait are still detected for the
new functions.
Fixes #208107
---------
Co-authored-by: Claude Opus 4.8 <noreply at anthropic.com>
Commit: 00f263b209a834eca2092d4a91d25b5413caea39
https://github.com/llvm/llvm-project/commit/00f263b209a834eca2092d4a91d25b5413caea39
Author: Marcos Maronas <mmaronas at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/test/Driver/spirv-amd-toolchain.c
Log Message:
-----------
[HIP][SPIR-V] Enable -spirv-preserve-auxdata (#209520)
Function attributes such as `convergent` are only kept through SPIRV if
`-spirv-preserve-auxdata` is enabled. This is important to keep the
translation as accurate as possible. Also, this aligns with the
translator path.
Commit: 0d6013c30572faddfb03d165cfb33f658c313716
https://github.com/llvm/llvm-project/commit/0d6013c30572faddfb03d165cfb33f658c313716
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-store-s16-true16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptr-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrmask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sbfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-constant-32bit.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-s16-true16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-strict_fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trap-gfx11.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ubfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx7.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx8-plus.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-constant-32bit.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.dispatch.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fract.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.frexp.mant.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
Log Message:
-----------
AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (44) (#209734)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 957b6635060d85200d985797eaac8c4dccfd8825
https://github.com/llvm/llvm-project/commit/957b6635060d85200d985797eaac8c4dccfd8825
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.cd.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.p1.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.live.mask.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mul24.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.queue.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.integer-minmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.setreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.sleep.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.softwqm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.strictwqm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_32.ll
Log Message:
-----------
AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (45) (#209753)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: f8f37a65d472e65561994fb7ae55f6b539c357d4
https://github.com/llvm/llvm-project/commit/f8f37a65d472e65561994fb7ae55f6b539c357d4
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
A mlir/lib/Dialect/OpenACC/Transforms/ACCCGToGPU.cpp
M mlir/lib/Dialect/OpenACC/Transforms/CMakeLists.txt
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-barrier-gang-private-init.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-launch-mapping.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-predicate-region-reuse-barrier.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-predicate-region.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-private-local-gang-redundant.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-privatize-local.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-privatize-routine-seq.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-privatize-threadprivate.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-reduction-array-shared.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-reduction-array.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-reduction-block-combine-no-reload.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-reduction-combine-region-private-dest.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-reuse-barrier-sibling-region-privatize.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-routine-call-nested-if.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-routine-worker-call-with-thread-y-reduction.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-worker-private-dynamic-nw.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-worker-vector-reuse-barrier.mlir
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-worker-vector-subgroup-align.mlir
Log Message:
-----------
[mlir][acc] Introduce acc to gpu codegen pass (#209606)
Introduce pass that lowers `acc.compute_region` to the GPU dialect. For
host-side kernels it wraps the region in `gpu.launch`; for specialized
ACC routines already inside a `gpu.func`, the body is lowered in place.
The pass maps nested `scf.parallel` / `scf.for` loops carrying
`acc.par_dims` to GPU block and thread parallelism, materializes
privatization and reductions for the device, and handles
synchronization.
Example input IR:
```
func.func @two_sibling_loops() {
%c4 = arith.constant 4 : index
%c32 = arith.constant 32 : index
%grid = acc.par_width %c4 {par_dim = #acc.par_dim<block_x>}
%block = acc.par_width %c32 {par_dim = #acc.par_dim<thread_x>}
acc.kernel_environment {
%priv = acc.privatize [#acc<par_dims[block_x]>] : () ->
!acc.private_type<memref<32xi32>>
acc.compute_region launch(%g = %grid, %t = %block) ins(%p = %priv)
: (!acc.private_type<memref<32xi32>>) {
%slot = acc.private_local %p : (!acc.private_type<memref<32xi32>>)
-> memref<32xi32>
%c0 = arith.constant 0 : index
%c1 = arith.constant 1 : index
%c32_len = arith.constant 32 : index
scf.parallel (%tx) = (%c0) to (%t) step (%c1) {
scf.parallel (%i) = (%c0) to (%c32_len) step (%c1) {
%v = arith.index_cast %i : index to i32
memref.store %v, %slot[%i] : memref<32xi32>
scf.reduce
} {acc.par_dims = #acc<par_dims[sequential]>}
scf.reduce
} {acc.par_dims = #acc<par_dims[thread_x]>}
scf.parallel (%bx) = (%c0) to (%g) step (%c1) {
scf.parallel (%tx2) = (%c0) to (%t) step (%c1) {
scf.parallel (%j) = (%c0) to (%c32_len) step (%c1) {
%loaded = memref.load %slot[%j] : memref<32xi32>
memref.store %loaded, %slot[%j] : memref<32xi32>
scf.reduce
} {acc.par_dims = #acc<par_dims[sequential]>}
scf.reduce
} {acc.par_dims = #acc<par_dims[thread_x]>}
scf.reduce
} {acc.par_dims = #acc<par_dims[block_x]>}
acc.yield
} {origin = "acc.parallel"}
}
return
}
```
Output IR:
```
module {
func.func @two_sibling_loops() {
%c4 = arith.constant 4 : index
%c32 = arith.constant 32 : index
acc.kernel_environment {
%0 = acc.privatize [#acc<par_dims[block_x]>] : () ->
!acc.private_type<memref<32xi32>>
%c1 = arith.constant 1 : index
gpu.launch blocks(%arg0, %arg1, %arg2) in (%arg6 = %c4, %arg7 =
%c1, %arg8 = %c1)
threads(%arg3, %arg4, %arg5) in (%arg9 = %c32, %arg10
= %c1, %arg11 = %c1) {
%grid_dim_x = gpu.grid_dim x
%grid_dim_y = gpu.grid_dim y
%grid_dim_z = gpu.grid_dim z
%block_dim_x = gpu.block_dim x
%block_dim_y = gpu.block_dim y
%block_dim_z = gpu.block_dim z
%1 = acc.gpu_shared_memory {num_copies = 1 : i64,
static_upper_bound_bytes = 128 : i64}
: () -> memref<32xi32, #gpu.address_space<workgroup>>
%memspacecast = memref.memory_space_cast %1
: memref<32xi32, #gpu.address_space<workgroup>> to
memref<32xi32>
%c0 = arith.constant 0 : index
%c1_0 = arith.constant 1 : index
%c32_1 = arith.constant 32 : index
scf.parallel (%arg12) = (%c0) to (%c32_1) step (%c1_0) {
%2 = arith.index_cast %arg12 : index to i32
memref.store %2, %memspacecast[%arg12] : memref<32xi32>
scf.reduce
} {acc.par_dims = #acc<par_dims[sequential]>}
gpu.barrier
scf.parallel (%arg12) = (%c0) to (%c32_1) step (%c1_0) {
%2 = memref.load %memspacecast[%arg12] : memref<32xi32>
memref.store %2, %memspacecast[%arg12] : memref<32xi32>
scf.reduce
} {acc.par_dims = #acc<par_dims[sequential]>}
gpu.barrier
gpu.terminator
}
}
return
}
}
```
---------
Co-authored-by: Matsu <kmatsumura at nvidia.com>
Commit: f829df1bf55e674aad2d90390b7b53dd141c2c8b
https://github.com/llvm/llvm-project/commit/f829df1bf55e674aad2d90390b7b53dd141c2c8b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wwm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.atomic.cmpxchg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant32bit.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-divergent.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-legalize-range-metadata.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-divergent.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer-wrong-insert-point.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/min3-max3-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs-i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mmra.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/no-cse-nonlocal-convergent-instrs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/no-ctlz-from-umul-to-lshr-in-postlegalizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/no-ctlz-from-umul-to-lshr-in-postlegalizer.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/no-legalize-atomic.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/or.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-buildvector-identities.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-divrem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-sextload-from-sextinreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-trunc-bitcast-buildvector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-unmerge-undef.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-zextload-from-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-load-and-mask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-sbfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-ubfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-divrem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-fptrunc_fpext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-redundant-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-sext_inreg-to-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-shuffle.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/promote-dependency-on-invariant-result.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-minmax-const.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-fmed3-minmax-const.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-redundant-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-umed3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.subdword.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
Log Message:
-----------
AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (46) (#209754)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 703e9b3b79f1520d05fceebabfacf31af4ad4e14
https://github.com/llvm/llvm-project/commit/703e9b3b79f1520d05fceebabfacf31af4ad4e14
Author: Phoebe Linck <phoebe.linck at hpe.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
R flang/test/Lower/OpenMP/Todo/taskwait-depend.f90
A flang/test/Lower/OpenMP/taskwait-depend.f90
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/test/Target/LLVMIR/openmp-taskwait-depend.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[Flang][OpenMP] Implement DEPEND clause for TASKWAIT directive (#193568)
Implements support for the `DEPEND` clause on `TASKWAIT`, added in
OpenMP 5.0.
Commit: f1cb3d330c03827247468b4c0437e86ad0b286ad
https://github.com/llvm/llvm-project/commit/f1cb3d330c03827247468b4c0437e86ad0b286ad
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx942.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.v2f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-minmax-uminmax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-uinc-udec-wrap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi-sat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui-sat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
Log Message:
-----------
AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (47) (#209755)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: c78147a9198c45ac1020dfc1d5524d158470309e
https://github.com/llvm/llvm-project/commit/c78147a9198c45ac1020dfc1d5524d158470309e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-merge.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbankselect.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-whole-wave-functions.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sbfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/select-merge-values-build-vector-s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shader-epilogs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-divergent-addr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-uniform-addr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-weird-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/true16-merge-values-s16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/trunc-brc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/trunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/twoaddr-extract-dyn-v7f64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ubfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/umed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-ptr-add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/v_bfe_i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll
Log Message:
-----------
AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (48) (#209756)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 649466a54f920970e99574d0d982b8ed35465c8f
https://github.com/llvm/llvm-project/commit/649466a54f920970e99574d0d982b8ed35465c8f
Author: Scott Manley <rscottmanley at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCCGOps.td
Log Message:
-----------
[NFC][OpenACC] fix doc formatting for reduction ops (#209739)
Was not printing correctly due to the matching `$`
Commit: 1725c53752c84cc19c656413b0e75e1dbe9e154b
https://github.com/llvm/llvm-project/commit/1725c53752c84cc19c656413b0e75e1dbe9e154b
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCCGAttributes.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsCG.h
M mlir/lib/Dialect/OpenACC/Transforms/ACCCGToGPU.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsCG.cpp
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-block-redundant.mlir
Log Message:
-----------
[mlir][acc] Add attribute for redundant execution marking (#209784)
Adds `acc.gpu_block_redundant` attribute for correct gang-redundant
lowering.
OpenACC gang-redundant regions execute on every gang rather than
partitioning work across gangs. When lowering to the GPU dialect, such
regions must not be assigned block-level par dims; only thread-level
parallelism applies. This marks loops with this attribute to ensure
proper execution and to avoid incorrect predication.
Co-authored-by: Delaram Talaashrafi <dtalaashrafi at nvidia.com>
Commit: 15a20079696696162af6aa532bd95f8cd010aaa5
https://github.com/llvm/llvm-project/commit/15a20079696696162af6aa532bd95f8cd010aaa5
Author: Ayokunle Amodu <ayokunle321 at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx1250.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-vi-f16.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
Log Message:
-----------
[CIR][AMDGPU] Add support for AMDGCN sqrt builtins (#197342)
Adds codegen for the following AMDGCN square root builtins:
- __builtin_amdgcn_sqrt (double)
- __builtin_amdgcn_sqrtf (float)
- __builtin_amdgcn_sqrth (half)
- __builtin_amdgcn_sqrt_bf16 (bfloat16)
These are lowered to the corresponding `llvm.amdgcn.sqrt` intrinsic calls.
Commit: 35182ec363a6943bd4c6c4158b0de17f7799b6b7
https://github.com/llvm/llvm-project/commit/35182ec363a6943bd4c6c4158b0de17f7799b6b7
Author: David Young <davidayoung at meta.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
Log Message:
-----------
[lldb][bazel] Add PlatformWasm plugin library to the Bazel overlay (#209749)
Adds the PluginPlatformWasm cc_library plus its PlatformWasmProperties
gentbl_cc_library (settings .td, modeled on PlatformQemuUserProperties)
to the lldb Bazel overlay. Deps mirror
source/Plugins/Platform/WebAssembly/CMakeLists.txt (lldbCore, lldbHost,
lldbTarget, lldbUtility, Support) plus the :PluginPlatformGDB and
:PluginProcessWasm plugin deps its GDB-remote/Web-Inspector sources use.
The library is intentionally left out of DEFAULT_PLUGINS.
bazel rule assisted with: claude
Can confirm this library will convert to BUCK internally at Meta and
build with buck2 where we do have in the default plugin list. I left it
out here, unless there's a desire to add it in.
Commit: 78c8cf7ef90cb0bca766d07a221977fbe2a2a69f
https://github.com/llvm/llvm-project/commit/78c8cf7ef90cb0bca766d07a221977fbe2a2a69f
Author: David Young <davidayoung at meta.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
Log Message:
-----------
[lldb][bazel] Add ObjectFileXCOFF plugin library to the Bazel overlay (#209747)
Adds the PluginObjectFileXCOFF cc_library to the lldb Bazel overlay,
modeled on PluginObjectFileELF/PluginObjectFileCOFF and mirroring
source/Plugins/ObjectFile/XCOFF/CMakeLists.txt (lldbCore, lldbHost,
lldbSymbol, lldbTarget; llvm BinaryFormat/Object/Support). The library
is intentionally left out of DEFAULT_PLUGINS.
bazel rule assisted with: claude
Can confirm this library will convert to BUCK internally at Meta and
build with buck2 where we do have in the default plugin list. I left it
out here, unless there's a desire to add it in.
Commit: 6526c5ba127123f2c81b21b3f27bfa69dd623f9e
https://github.com/llvm/llvm-project/commit/6526c5ba127123f2c81b21b3f27bfa69dd623f9e
Author: LU-JOHN <John.Lu at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/test/CodeGen/AMDGPU/div-rem-fast-path.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdivrem24.ll
M llvm/test/CodeGen/AMDGPU/sdivrem64.r600.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udivrem24.ll
M llvm/test/CodeGen/AMDGPU/udivrem64.r600.ll
Log Message:
-----------
[AMDGPU] Avoid errors with 24-bit div/rem (#209711)
Avoid errors when using floating-point reciprocal to calculate Y/X when
Y = (0x7FFFFF/X)*X-1. Limit expansion to 23-bit signed and 22-bit
unsigned to avoid this issue.
This change is analogous to the change done in
https://github.com/llvm/llvm-project/pull/202753, but in
AMDGPUISelLowering.cpp.
Signed-off-by: John Lu <John.Lu at amd.com>
Commit: 4b415b168494b2cbf814db3305ec236aae1562c6
https://github.com/llvm/llvm-project/commit/4b415b168494b2cbf814db3305ec236aae1562c6
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/Driver/ToolChain.cpp
A clang/test/Driver/Inputs/resource_dir_with_amdgpu_per_target_subdir/lib/amdgpu-amd-amdhsa/libclang_rt.profile.a
M clang/test/Driver/amdgpu-toolchain.c
Log Message:
-----------
[Clang][AMDGPU] Search both amdgcn and amdgpu libraries (#209770)
Summary:
Temporary workaround as we transition triples from amdgcn to amdgpu.
Commit: 2cd090afbe1eddfe8f781d5ccae391e1f69e8ee4
https://github.com/llvm/llvm-project/commit/2cd090afbe1eddfe8f781d5ccae391e1f69e8ee4
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/cmake/Modules/CompilerRTUtils.cmake
M compiler-rt/cmake/base-config-ix.cmake
M compiler-rt/cmake/builtin-config-ix.cmake
M compiler-rt/lib/builtins/CMakeLists.txt
Log Message:
-----------
[compiler-rt] Fix amdgcn -> amdgpu conversion for compiler-rt (#209765)
Summary:
We are apparently transitioning to using `amdgpu` everywhere, so these
need to be updated.
Commit: 4279d524cc78d0bac294bb29257c62665121d9f1
https://github.com/llvm/llvm-project/commit/4279d524cc78d0bac294bb29257c62665121d9f1
Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
A llvm/test/CodeGen/AMDGPU/vgpr-setreg-pred-block.mir
Log Message:
-----------
[AMDGPU][CodeGen] Place `S_NOP` after `S_SETREG_IMM32_B32` in predecessor MBB (#209620)
When placing a `S_SET_VGPR_MSB` at the beginning of a block, check
whether there exists a `S_SETREG_IMM32_B32(MODE)` in the predecessor
block that falls-through into it; if there is one a `S_NOP` has to be
inserted in between them.
Commit: ea9175f63571dda7efbdbeff9b6eed33879307ac
https://github.com/llvm/llvm-project/commit/ea9175f63571dda7efbdbeff9b6eed33879307ac
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/loadi8.ll
M llvm/test/Transforms/SLPVectorizer/X86/runtime-alias-checks.ll
Log Message:
-----------
Revert "[SLP] Support memory runtime alias checks"
This reverts commit 96a53b1c5356754b4708c0fee8517fd0d69cb1fd to fix
buildbots https://lab.llvm.org/buildbot/#/builders/223/builds/7209
reported in https://github.com/llvm/llvm-project/pull/209305?email_source=notifications&email_token=ABI45DXMMB4TIQHXXWA6NYD5E57EVA5CNFSNUABFM5UWIORPF5TWS5BNNB2WEL2JONZXKZKDN5WW2ZLOOQXTIOJYGA4TIMZVGU3KM4TFMFZW63VMON2GC5DFL5RWQYLOM5S2KZLWMVXHJLDGN5XXIZLSL5RWY2LDNM#issuecomment-4980943556
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209793
Commit: 6352d8437c41915ebdb03537660f3bb48a1bc02a
https://github.com/llvm/llvm-project/commit/6352d8437c41915ebdb03537660f3bb48a1bc02a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/xor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll
Log Message:
-----------
AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (49) (#209757)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 7d638b4dbcb10c224741cdd4634a768c7bc6d305
https://github.com/llvm/llvm-project/commit/7d638b4dbcb10c224741cdd4634a768c7bc6d305
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/InlineAsmCrash.ll
M llvm/test/CodeGen/AMDGPU/add_i128.ll
M llvm/test/CodeGen/AMDGPU/add_i64.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-initializer-unsupported.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-initializer.ll
M llvm/test/CodeGen/AMDGPU/alignbit-pat.ll
M llvm/test/CodeGen/AMDGPU/allow-check.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-function-calls-option.ll
M llvm/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll
M llvm/test/CodeGen/AMDGPU/barrier-elimination.ll
M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
M llvm/test/CodeGen/AMDGPU/branch-uniformity.ll
M llvm/test/CodeGen/AMDGPU/call-constant.ll
M llvm/test/CodeGen/AMDGPU/call-constexpr.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir
M llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll
M llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
M llvm/test/CodeGen/AMDGPU/coalescer-identical-values-undef.mir
M llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir
M llvm/test/CodeGen/AMDGPU/coalescer_remat.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf-broken.mir
M llvm/test/CodeGen/AMDGPU/collapse-endcf.mir
M llvm/test/CodeGen/AMDGPU/collapse-endcf2.mir
M llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll
M llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
M llvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir
M llvm/test/CodeGen/AMDGPU/commute-compares.ll
M llvm/test/CodeGen/AMDGPU/commute_modifiers.ll
M llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll
M llvm/test/CodeGen/AMDGPU/convergent-inlineasm.ll
M llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir
M llvm/test/CodeGen/AMDGPU/cttz-elts.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll
M llvm/test/CodeGen/AMDGPU/dce-disjoint-intervals.mir
M llvm/test/CodeGen/AMDGPU/debug-value2.ll
M llvm/test/CodeGen/AMDGPU/debug_frame.ll
M llvm/test/CodeGen/AMDGPU/default_amdhsa_code_object_version.ll
M llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-bfe-isel.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-bitreverse.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-ctpop.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-min-max.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-not-isel.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
M llvm/test/CodeGen/AMDGPU/enable-no-signed-zeros-fp-math.ll
M llvm/test/CodeGen/AMDGPU/endcf-loop-header.ll
M llvm/test/CodeGen/AMDGPU/endpgm-dce.mir
M llvm/test/CodeGen/AMDGPU/extload-align.ll
M llvm/test/CodeGen/AMDGPU/extract-load-i1.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector.ll
M llvm/test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll
M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fadd-fma-fmul-combine.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir
M llvm/test/CodeGen/AMDGPU/fix-vgpr-copies.mir
M llvm/test/CodeGen/AMDGPU/fold-cndmask.mir
M llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir
M llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir
M llvm/test/CodeGen/AMDGPU/fold-fmul-to-neg-abs.ll
M llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
M llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir
M llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir
M llvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
M llvm/test/CodeGen/AMDGPU/fold-implicit-operand.mir
M llvm/test/CodeGen/AMDGPU/fold-over-exec.mir
M llvm/test/CodeGen/AMDGPU/fold-readlane.mir
M llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address-codegen.ll
M llvm/test/CodeGen/AMDGPU/fp-to-int-to-fp.ll
M llvm/test/CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir
M llvm/test/CodeGen/AMDGPU/freeze-other-uses-issue-198094.ll
M llvm/test/CodeGen/AMDGPU/global-alias.ll
M llvm/test/CodeGen/AMDGPU/hoist-cond.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-deduced-arg-attr.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-1.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-3.ll
M llvm/test/CodeGen/AMDGPU/huge-number-operand-folds.mir
M llvm/test/CodeGen/AMDGPU/i1-copies-rpo.mir
M llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-phi-uniform-branch.ll
M llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir
M llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/invalid-inline-asm-constraint-crash.ll
M llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll
M llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
M llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
M llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll
M llvm/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (50) (#209776)
Fold the explicit -mcpu subtarget into the amdgpu subarch triple on
llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 ->
-mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu
following the default-subtarget pinning. Codegen output is unchanged.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 5699900ae02272a558761b6de3f18a790abe763f
https://github.com/llvm/llvm-project/commit/5699900ae02272a558761b6de3f18a790abe763f
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/test/AST/ByteCode/virtual-bases.cpp
Log Message:
-----------
[clang][bytecode] Fix virtual-bases.cpp on 32 bit hosts (#209766)
It currently fails on clang-armv8-quick with:
```console
# | error: diagnostics with 'error' severity seen but not expected:
# | File /home/tcwg-buildbot/worker/clang-armv8-quick/llvm/clang/test/AST/ByteCode/virtual-bases.cpp Line 441: static assertion failed due to requirement '((__builtin_constant_p((char *)&c.c) ? ((char *)&c.c) : ((char *)&c.c)) - (__builtin_constant_p((char *)&c) ? ((char *)&c) : ((char *)&c))) == 12'
# | File /home/tcwg-buildbot/worker/clang-armv8-quick/llvm/clang/test/AST/ByteCode/virtual-bases.cpp Line 442: static assertion failed due to requirement '((__builtin_constant_p((char *)&c.b) ? ((char *)&c.b) : ((char *)&c.b)) - (__builtin_constant_p((char *)&c) ? ((char *)&c) : ((char *)&c))) == 8'
# | File /home/tcwg-buildbot/worker/clang-armv8-quick/llvm/clang/test/AST/ByteCode/virtual-bases.cpp Line 443: static assertion failed due to requirement '((__builtin_constant_p((char *)&c.a) ? ((char *)&c.a) : ((char *)&c.a)) - (__builtin_constant_p((char *)&c) ? ((char *)&c) : ((char *)&c))) == 20'
# | File /home/tcwg-buildbot/worker/clang-armv8-quick/llvm/clang/test/AST/ByteCode/virtual-bases.cpp Line 444: static assertion failed due to requirement '((__builtin_constant_p((char *)&c.x) ? ((char *)&c.x) : ((char *)&c.x)) - (__builtin_constant_p((char *)&c) ? ((char *)&c) : ((char *)&c))) == 16'
# | error: diagnostics with 'note' severity seen but not expected:
# | File /home/tcwg-buildbot/worker/clang-armv8-quick/llvm/clang/test/AST/ByteCode/virtual-bases.cpp Line 441: expression evaluates to '8 == 12'
# | File /home/tcwg-buildbot/worker/clang-armv8-quick/llvm/clang/test/AST/ByteCode/virtual-bases.cpp Line 442: expression evaluates to '4 == 8'
# | File /home/tcwg-buildbot/worker/clang-armv8-quick/llvm/clang/test/AST/ByteCode/virtual-bases.cpp Line 443: expression evaluates to '16 == 20'
# | File /home/tcwg-buildbot/worker/clang-armv8-quick/llvm/clang/test/AST/ByteCode/virtual-bases.cpp Line 444: expression evaluates to '12 == 16'
# | 8 errors generated.
```
Commit: 0429183bd83dee21b7e074160e241129ca1cde25
https://github.com/llvm/llvm-project/commit/0429183bd83dee21b7e074160e241129ca1cde25
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/BUILD.gn
Log Message:
-----------
[gn build] Port 2375505c7c19 (#209797)
Commit: 21db8e9e2ad0ba161d5939de39119951c61e64ec
https://github.com/llvm/llvm-project/commit/21db8e9e2ad0ba161d5939de39119951c61e64ec
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/BUILD.gn
Log Message:
-----------
[gn build] Port 9a4deccf90ae (#209799)
Commit: bfc2d553401bfd69c57f848d35d5ec5952298cbb
https://github.com/llvm/llvm-project/commit/bfc2d553401bfd69c57f848d35d5ec5952298cbb
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/kernel_code_t_recurse.ll
M llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/knownbits-recursion.ll
M llvm/test/CodeGen/AMDGPU/lcssa-optnone.ll
M llvm/test/CodeGen/AMDGPU/lds-alignment.ll
M llvm/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll
M llvm/test/CodeGen/AMDGPU/lds-size.ll
M llvm/test/CodeGen/AMDGPU/liveness.mir
M llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdiv.fast.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.hsa.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.u24.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.legacy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getpc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.xfail.mir
M llvm/test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll
M llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir
M llvm/test/CodeGen/AMDGPU/machinelicm-copy-like-instrs.mir
M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
M llvm/test/CodeGen/AMDGPU/madak-inline-constant.mir
M llvm/test/CodeGen/AMDGPU/madmk.ll
M llvm/test/CodeGen/AMDGPU/mcp-use-before-def.mir
M llvm/test/CodeGen/AMDGPU/mem-builtins.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir
M llvm/test/CodeGen/AMDGPU/merge-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-m0.mir
M llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir
M llvm/test/CodeGen/AMDGPU/movrels-bug.mir
M llvm/test/CodeGen/AMDGPU/new-pm-machine-analysis.mir
M llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll
M llvm/test/CodeGen/AMDGPU/no-limit-coalesce.mir
M llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll
M llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll
M llvm/test/CodeGen/AMDGPU/nullptr.ll
M llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir
M llvm/test/CodeGen/AMDGPU/opencl-image-metadata.ll
M llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/opt_exec_copy_fold.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir
M llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll
M llvm/test/CodeGen/AMDGPU/peephole-opt-regseq-removal.mir
M llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir
M llvm/test/CodeGen/AMDGPU/preserve-user-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll
M llvm/test/CodeGen/AMDGPU/rcp_iflag.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll
M llvm/test/CodeGen/AMDGPU/reduce-saveexec.mir
M llvm/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll
M llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir
M llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir
M llvm/test/CodeGen/AMDGPU/regcoalescer-resolve-lane-conflict-by-subranges.mir
M llvm/test/CodeGen/AMDGPU/register-count-comments.ll
M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.mir
M llvm/test/CodeGen/AMDGPU/remat-dead-subreg.mir
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-dbg.mir
M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir
M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir
M llvm/test/CodeGen/AMDGPU/sched.barrier.inverted.mask.ll
M llvm/test/CodeGen/AMDGPU/schedule-global-loads.ll
M llvm/test/CodeGen/AMDGPU/schedule-physregdeps.mir
M llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir
M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
M llvm/test/CodeGen/AMDGPU/select-opt.ll
M llvm/test/CodeGen/AMDGPU/set-wave-priority.ll
M llvm/test/CodeGen/AMDGPU/setcc-select-hi32mask.ll
M llvm/test/CodeGen/AMDGPU/setcc-select.ll
M llvm/test/CodeGen/AMDGPU/setcc-sext.ll
M llvm/test/CodeGen/AMDGPU/setcc.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
M llvm/test/CodeGen/AMDGPU/sgpr-to-vreg1-copy.mir
M llvm/test/CodeGen/AMDGPU/sgprcopies.ll
M llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
M llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir
M llvm/test/CodeGen/AMDGPU/si-i1-copies.mir
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (51) (#209777)
Fold the explicit -mcpu subtarget into the amdgpu subarch triple on
llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 ->
-mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu
following the default-subtarget pinning. Codegen output is unchanged.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: ff58fb1cef69c6d9e2e8889f2e72b962858a5475
https://github.com/llvm/llvm-project/commit/ff58fb1cef69c6d9e2e8889f2e72b962858a5475
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-kill.ll
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir
M llvm/test/CodeGen/AMDGPU/si-lower-i1-copies.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-cycle-header.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-body.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-latch.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-multi-entry-cycle.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir
M llvm/test/CodeGen/AMDGPU/simplifydemandedbits-recursion.ll
M llvm/test/CodeGen/AMDGPU/skip-branch-taildup-ret.mir
M llvm/test/CodeGen/AMDGPU/skip-branch-trap.ll
M llvm/test/CodeGen/AMDGPU/spill-before-exec.mir
M llvm/test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll
M llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
M llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
M llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir
M llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll
M llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
M llvm/test/CodeGen/AMDGPU/splitkit-nolivesubranges.mir
M llvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/AMDGPU/stop-tail-duplicate-cfg-intrinsic.mir
M llvm/test/CodeGen/AMDGPU/subreg-intervals.mir
M llvm/test/CodeGen/AMDGPU/subreg_interference.mir
M llvm/test/CodeGen/AMDGPU/tail-dup-bundle.mir
M llvm/test/CodeGen/AMDGPU/trap.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-f64-to-f16.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-regsequence.mir
M llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
M llvm/test/CodeGen/AMDGPU/unsupported-calls.ll
M llvm/test/CodeGen/AMDGPU/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/AMDGPU/valu-i1.ll
M llvm/test/CodeGen/AMDGPU/vector-legalizer-divergence.ll
M llvm/test/CodeGen/AMDGPU/verify-sop.mir
M llvm/test/CodeGen/AMDGPU/vgpr_constant64_to_sgpr.mir
M llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
M llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
M llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-debug-non-first-terminators.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-no-redundant.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-trailing.mir
M llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll
M llvm/test/CodeGen/AMDGPU/wqm-debug-instr.mir
M llvm/test/CodeGen/AMDGPU/zext-i64-bit-operand.ll
M llvm/test/CodeGen/AMDGPU/zext-lid.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (52) (#209778)
Fold the explicit -mcpu subtarget into the amdgpu subarch triple on
llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 ->
-mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu
following the default-subtarget pinning. Codegen output is unchanged.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 4596278ca49b13280176c6ae25ab673772185d56
https://github.com/llvm/llvm-project/commit/4596278ca49b13280176c6ae25ab673772185d56
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/ScalableStaticAnalysis/Analyses/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/ScalableStaticAnalysis/BUILD.gn
Log Message:
-----------
[gn build] Port ef118b5b3a61 (#209800)
Commit: d0231d2195976b5b091b8e55f4d4fd2b55875ee5
https://github.com/llvm/llvm-project/commit/d0231d2195976b5b091b8e55f4d4fd2b55875ee5
Author: Luke Lau <luke at igalia.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i16-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i32-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i64-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i8-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/handle-iptr-with-data-layout-to-not-assert.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-half.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2-indices-0u.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-01u.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-0uu.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-012u.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-01uu.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-0uuu.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-gather-i32-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-gather-i64-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-load-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-store-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i32.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i64.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i32.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i64.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i32.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i64.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i8.ll
Log Message:
-----------
[LV] Fix LoopVectorize/X86/CostModel tests when regenerated with UTC. NFC (#209802)
Some of the cost model tests were passing, but their UTC arguments
were outdated and CHECK lines disappeared when regenerating them.
- Add additional --filter lines for VPlan cost model CHECK lines,
which were manually written previously
- Update the --filter argument for the updated INTERLEAVE-GROUP print
output
- Regenerate strided-load-*.ll tests with UTC
- Pass -vplan-print-metadata=false for tests that were using
hand-written regexes in CHECK lines
Commit: ee08b1c5553cd558458b9570646038b9422ca397
https://github.com/llvm/llvm-project/commit/ee08b1c5553cd558458b9570646038b9422ca397
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-add-nullptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ashr-narrow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fabs-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsub-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-itofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-lshr-narrow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-redundant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-neg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-amount-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-illegal-types.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-shlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic-shlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shifts.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-narrow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-shift.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.barrier.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbl-b32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-br.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fixed-function-abi-vgpr-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-readnone-intrinsic-callsite.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-zext-vec-index.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/knownbits-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-amdgcn-fdiv-fast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpyinline.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memmove.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memset.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memsetinline.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.implicit.ptr.buffer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.inline.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memmove.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.inline.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/merge-buffer-stores.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-reassoc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/selected-inst-flags.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector-pointer-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
Log Message:
-----------
AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (53) (#209779)
Fold the explicit -mcpu subtarget into the amdgpu subarch triple on
llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 ->
-mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu
following the default-subtarget pinning. Codegen output is unchanged.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 42c2980c7c632d7a45776d3e2c51627100f6e763
https://github.com/llvm/llvm-project/commit/42c2980c7c632d7a45776d3e2c51627100f6e763
Author: 陈子昂 <2802328816 at qq.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
A llvm/test/Transforms/LoopUnroll/full-unroll-scev-invalidation.ll
Log Message:
-----------
[LoopUnroll] Invalidate SCEV after full unrolling (#208874)
Full unrolling may leave stale ScalarEvolution loop and disposition
caches around the loop pass boundary. A later IndVars pass can then use
stale exit count information and incorrectly fold reachable exits.
Invalidate SCEV loop and disposition caches after successful full
unrolling before preserving `ScalarEvolutionAnalysis.`
Fixes #207744.
Commit: c57f88d5178861974c8bcd61657d87275c835aa5
https://github.com/llvm/llvm-project/commit/c57f88d5178861974c8bcd61657d87275c835aa5
Author: Chi-Chun, Chen <chichun.chen at hpe.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang/include/flang/Semantics/openmp-utils.h
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/check-omp-variant.cpp
M flang/lib/Semantics/openmp-utils.cpp
M flang/test/Semantics/OpenMP/metadirective-loop-applicability.f90
M flang/test/Semantics/OpenMP/metadirective-loop-nest.f90
M flang/unittests/Semantics/OpenMPUtils.cpp
Log Message:
-----------
[flang][OpenMP] Fix metadirective loop semantic checks (#208844)
This is a follow-up to https://github.com/llvm/llvm-project/pull/207088.
Post-merge review feedback:
* Rename mayVariantBeSelected to MayVariantBeSelected and move it to
the shared OpenMP semantic utilities so declare-variant checking can
reuse it.
* Explain why a WHEN selector is recorded only when its modifier list
contains exactly one element.
* Diagnose loop-associated variants that end a declaration-only
program unit, such as a module with no execution part.
Additional correctness fixes:
* Handle consecutive metadirectives and modules or submodules with
contained procedures without silently dropping an earlier
loop-associated variant.
* Prevent a loop-associated variant in an interface, BLOCK construct,
conditional branch, or nested body from being checked against an
unrelated loop outside that scope.
* Avoid false or missing loop diagnostics when match_any or match_none
combines target selectors with user or construct selectors.
Assisted with codex.
Commit: 36dd090234dff6a9059bf9288e4c61ec77a42d82
https://github.com/llvm/llvm-project/commit/36dd090234dff6a9059bf9288e4c61ec77a42d82
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/loadi8.ll
M llvm/test/Transforms/SLPVectorizer/X86/runtime-alias-checks.ll
Log Message:
-----------
[SLP] Support memory runtime alias checks
Vectorize straight-line code blocked by runtime-checkable may-alias
dependencies by versioning the block. Drop the deps, and if the tree is
profitable, emit base-object address-range overlap checks branching to a
vector fast path or an original-order scalar fallback.
Fixes #201534
Original Pull Request: https://github.com/llvm/llvm-project/pull/203631
Recommit after revert in a9ba4d3fd27a05b31adfeaab5dcd42d8e43c1931,
related to late commit before the release and small after-commit change
request
Recommit after revert in ea9175f63571dda7efbdbeff9b6eed33879307ac, fixed
testing with PROFCHECK=ON
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209820
Commit: 816a5eacc4407e091a76d0205a8221ade044f439
https://github.com/llvm/llvm-project/commit/816a5eacc4407e091a76d0205a8221ade044f439
Author: Vineet Kumar <173554+vntkmr at users.noreply.github.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang/include/flang/Evaluate/call.h
M flang/include/flang/Evaluate/fold.h
M flang/include/flang/Evaluate/shape.h
M flang/include/flang/Evaluate/traverse.h
M flang/include/flang/Evaluate/type.h
M flang/include/flang/Semantics/expression.h
M flang/lib/Evaluate/call.cpp
M flang/lib/Evaluate/characteristics.cpp
M flang/lib/Evaluate/fold-implementation.h
M flang/lib/Evaluate/fold.cpp
M flang/lib/Evaluate/formatting.cpp
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Evaluate/shape.cpp
M flang/lib/Evaluate/tools.cpp
M flang/lib/Evaluate/type.cpp
M flang/lib/Lower/ConvertCall.cpp
M flang/lib/Parser/program-parsers.cpp
M flang/lib/Semantics/check-call.cpp
M flang/lib/Semantics/expression.cpp
A flang/test/Evaluate/fold-conditional-arg.f90
M flang/test/Semantics/conditional-arg.f90
Log Message:
-----------
[flang] Add semantics support for Fortran 2023 conditional arguments (F2023 R1526-R1528) (#195345)
This PR
- Adds semantic analysis for F2023 conditional arguments (F2023
R1526-R1528), enforcing constraints F2023 C1538-C1545.
- Adds shape handling and folding for conditional args.
- Adds semantic tests.
(More details in commit messages)
This PR does not implement lowering to HLFIR; That will be a separate
PR.
AI use disclaimer: The changes in this PR were substantially
generated with the assistance of AI (claude opus 4.6 via Github
CoPilot). In accordance with the LLVM project’s AI use policy, I have
reviewed and tested the code to the best of my ability.
Commit: f10ede511119d7f31f2c6aaca3cbcb1ea00164ce
https://github.com/llvm/llvm-project/commit/f10ede511119d7f31f2c6aaca3cbcb1ea00164ce
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lldb/examples/python/templates/operating_system.py
M lldb/examples/python/templates/scripted_breakpoint.py
M lldb/examples/python/templates/scripted_frame_provider.py
M lldb/examples/python/templates/scripted_hook.py
M lldb/examples/python/templates/scripted_platform.py
M lldb/examples/python/templates/scripted_process.py
M lldb/examples/python/templates/scripted_thread_plan.py
Log Message:
-----------
[lldb/script] Add type hints to scripted extension base classes (#209680)
This patch adds type annotations to every method (parameters and return
types) and every `self.<name>` attribute of the scripted extension base
classes shipped under `lldb/examples/python/templates/`. Extension
authors reading the base classes -- or an IDE navigating them -- can now
see the `lldb.SB*` contract each method exposes without having to
cross-reference the docstring.
`scripting extension generate` also picks the annotations up: derived
class docstrings advertise each inherited attribute together with its
declared type, and the generated method signatures carry their parameter
and return annotations too.
The classes covered are `ScriptedProcess`, `ScriptedThread`,
`ScriptedFrame`, `PassthroughScriptedProcess`,
`PassthroughScriptedThread`, `ScriptedFrameProvider`,
`ScriptedBreakpointResolver`, `ScriptedThreadPlan`, `ScriptedHook`,
`ScriptedPlatform`, and `OperatingSystem`.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: 2c2e43675910603bab1b163655786e4850569d74
https://github.com/llvm/llvm-project/commit/2c2e43675910603bab1b163655786e4850569d74
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/Sema/SemaDecl.cpp
M clang/test/SemaTemplate/class-template-spec.cpp
Log Message:
-----------
Create a Template member to be the MemberSpec of a failed TemplVarDecl (#209604)
Patch #200092 changed to no longer check the previous var template when
setting whether the current one is a member specialization. However, if
the previous one was actually an error case (see the example here and in
the report), we ended up trying to do that anyway, which caused an
assertion.
This patch puts in a 'fake' declaration for the not-found declaration after we
emit the 'not found' error for the purposes of allowing our diagnostics to
continue evaluating these without causing problems.
Fixes: #209432
Commit: edea055ee85427ad700e74cfa074d6c5ed5e6d39
https://github.com/llvm/llvm-project/commit/edea055ee85427ad700e74cfa074d6c5ed5e6d39
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
M flang/test/Fir/CUDA/cuda-constructor-2.f90
M flang/test/Fir/CUDA/cuda-constructor.f90
A flang/test/Fir/CUDA/cuda-register-allocator-0.f90
A flang/test/Fir/CUDA/cuda-register-allocator-1.f90
Log Message:
-----------
[flang][cuda] Register allocator only when needed (#208355)
Register allocator only when needed to avoid bringing in symbol when not
strictly needed.
Commit: 67df1e0f664b85c08d4281e465d3502495bfa035
https://github.com/llvm/llvm-project/commit/67df1e0f664b85c08d4281e465d3502495bfa035
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel][mlir][acc] Fix f8f37a65d472e65561994fb7ae55f6b539c357d4 (#209809)
Add missing deps
Commit: bad82c1af5198267f44bba363e20b24dd23d2a24
https://github.com/llvm/llvm-project/commit/bad82c1af5198267f44bba363e20b24dd23d2a24
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
Log Message:
-----------
[bazel][lldb] Add layering deps (#209813)
Extra deps needed for #209749 and #209747
Commit: a57c590c159c934d3759703a3f773eb09d3ffb09
https://github.com/llvm/llvm-project/commit/a57c590c159c934d3759703a3f773eb09d3ffb09
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/test/Driver/openmp-invalid-target-id.c
Log Message:
-----------
[clang][OpenMP][test] Specify libomp flag (#209804)
The test added in #209740 assumes that `-fopenmp=libomp` is the default
value, and does not work when the build is configured w/ `libgomp` as
the default instead.
Commit: 2c57ae5efb0159521287c80255e3a604f3b0dcfe
https://github.com/llvm/llvm-project/commit/2c57ae5efb0159521287c80255e3a604f3b0dcfe
Author: Faijul Amin <md.faijul.amin at intel.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
A llvm/test/CodeGen/SPIRV/legalization/signed-narrow-int.ll
Log Message:
-----------
[SPIRV] Sign-extend operands of sign-sensitive ops on sub-pow2 widths (#203661)
## Problem
Without extensions, `SPIRVPreLegalizer` widens sub-pow2 scalars (`s4`,
`s24`, ...) to the next legal width by relabeling the LLT only — no
sign-extension is inserted. Sign-sensitive ops (signed `G_ICMP`,
`G_ASHR`, `G_SDIV`, `G_SREM`) then read the sign bit at the wrong
position. As a result `icmp slt i4 %x, 0` always returned `false` even
for negative `i4`.
## Fix
- `SPIRVLegalizerInfo.cpp`: declare `G_SEXT_INREG.lower()` so the
legalizer expands it to `(x << k) ashr k`.
- `SPIRVPreLegalizer.cpp`: before the widening loop, emit `G_SEXT_INREG`
on each value operand of a sign-sensitive MI whose original width is
sub-pow2.
## Test
`llvm/test/CodeGen/SPIRV/legalization/signed-narrow-int.ll` covers `icmp
slt`/`ashr`/`sdiv`/`srem` on `i4`, `icmp slt` on `i24`, and negative
cases (`icmp ult`, `lshr`) that must not emit sign-extension shifts
Commit: b61b45f30cb1d7e88a6877080978aa95b83b7f87
https://github.com/llvm/llvm-project/commit/b61b45f30cb1d7e88a6877080978aa95b83b7f87
Author: Alex Langford <alangford at apple.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lldb/source/Plugins/ObjectFile/ELF/ELFHeader.cpp
M lldb/source/Plugins/ObjectFile/ELF/ELFHeader.h
Log Message:
-----------
[lldb] Convert ELFSymbol dump methods to use StringRef (#209650)
I'm working on changing how Section stores its own name (currently a
ConstString). I broke this change out into its own small PR because of
the complexity of rewriting the format string in ELFSymbol::Dump.
Commit: e956df27dfaf556f54a96ed22e85f1e16c7a38e3
https://github.com/llvm/llvm-project/commit/e956df27dfaf556f54a96ed22e85f1e16c7a38e3
Author: Markos Horro <marcosh at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/ADT/BitVector.h
M llvm/include/llvm/ADT/SmallBitVector.h
M llvm/unittests/ADT/BitVectorTest.cpp
Log Message:
-----------
[LLVM][ADT] Adding range-based test_all and test_any methods for BitVector (#209790)
Commit: 0cf914adef4b0f1f5251354b91f5c709b95b1b1e
https://github.com/llvm/llvm-project/commit/0cf914adef4b0f1f5251354b91f5c709b95b1b1e
Author: Michael Jones <michaelrj at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M libcxx/cmake/caches/Generic-llvm-libc.cmake
M libcxx/test/configs/llvm-libc++-llvm-libc.cfg.in
M libcxx/test/libcxx/language.support/support.dynamic/assert.nothrow_new_not_overridden_fno_exceptions.pass.cpp
M libcxx/test/libcxx/language.support/support.dynamic/new_dont_return_nullptr.pass.cpp
M libcxx/test/libcxx/thread/thread.condition/PR30202_notify_from_pthread_created_thread.pass.cpp
M libcxx/test/libcxx/thread/thread.threads/thread.thread.class/thread.thread.member/native_handle.pass.cpp
M libcxx/test/std/depr/depr.c.headers/wchar_h.compile.pass.cpp
M libcxx/test/std/depr/depr.c.headers/wctype_h.compile.pass.cpp
M libcxx/test/std/input.output/syncstream/osyncstream/thread/several_threads.pass.cpp
M libcxx/test/std/numerics/complex.number/complex.member.ops/divide_equal_complex.pass.cpp
M libcxx/test/std/numerics/complex.number/complex.ops/complex_divide_complex.pass.cpp
M libcxx/test/std/numerics/complex.number/complex.ops/scalar_divide_complex.pass.cpp
M libcxx/test/std/numerics/rand/rand.dist/rand.dist.bern/rand.dist.bern.bin/eval.PR44847.pass.cpp
M libcxx/test/std/numerics/rand/rand.dist/rand.dist.bern/rand.dist.bern.bin/io.pass.cpp
M libcxx/test/std/strings/c.strings/cwchar.pass.cpp
M libcxx/test/std/strings/c.strings/cwctype.pass.cpp
M libcxx/test/std/strings/string.conversions/to_wstring.pass.cpp
M libcxx/test/std/thread/thread.condition/notify_all_at_thread_exit_lwg3343.pass.cpp
M libcxx/test/std/thread/thread.threads/thread.thread.this/sleep_for.signals.pass.cpp
M libcxx/test/std/time/time.hash/time.hash_enabled.pass.cpp
M libcxxabi/test/configs/llvm-libc++abi-llvm-libc.cfg.in
Log Message:
-----------
[libcxx][libc] update LLVM-libc test status (#201236)
This update removes some unnecessary carveouts, marks some newly
XFAILing tests, and unmarks some now passing tests.
With this change the status of tests is:
Total Discovered Tests: 11471
Unsupported : 2098 (18.29%)
Passed : 9260 (80.73%)
Expectedly Failed: 113 (0.99%)
Assisted-by: Automated tooling, human reviewed.
Commit: 547e9d0c9175f37c9ddd367bbe443a2fd7d6ab7a
https://github.com/llvm/llvm-project/commit/547e9d0c9175f37c9ddd367bbe443a2fd7d6ab7a
Author: Ulrich Weigand <ulrich.weigand at de.ibm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M openmp/runtime/src/kmp_barrier.cpp
Log Message:
-----------
[OpenMP] Fix endian bug in hierarchical barrier code (#117073)
The "oncore" flavor of the hierarchical barrier code uses a single
uint64 to hold both a barrier state *and* a set of flags for the current
node's "leaf kids" in the tree.
To make this work, the barrier state is placed in the least-significant
byte of the uint64, and the flags for leaf kids are placed in other
bytes of the uint64 starting from the most-significant byte to represent
the first child.
At least, this is how it works on little-endian systems. On big-endian
hosts, the current code unfortunately places the leaf kid flags starting
from the *least* significant byte of the uint64, where they will overlap
and clobber the barrier state byte, resulting in corrupted barrier
behavior.
To fix this, this PR changes the child flag offsets to always start with
the MSB, on both big- and little- endian hosts. This was complicated a
bit by the following issues:
- The byte offset was stored "off-by-one" for some reason. This makes it
impossible to represent the MSB on big- endian systems (i.e. byte 0,
which would have to be represented by -1 if offset by one, which does
not fit into the uint8 offset field).
Fixed by storing and using the "offset" field as the actual byte number,
not off-by-one.
- The "offset" field was never used for the master node, but it was
still computed. That computed value was also invalid as it pointed
outside the target uint64, but that didn't matter as it was unused. For
big-endian systems, however, the computation would have resulted in a
*negative* value, which again cannot be stored in the uint8 field.
Fixed by skipping the (unused) computation on the master node and
setting the "offset" field to a dummy value.
This is intended to be NFC on little-endian machines.
Commit: 0639fe182414f04d767175a195a8a26da5d48159
https://github.com/llvm/llvm-project/commit/0639fe182414f04d767175a195a8a26da5d48159
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineINSERT_SUBVECTOR - use peekThroughBitcastsAndExtracts helper to match target shuffles as well. NFC. (#209803)
We were always checking if the result of peekThroughBitcastsAndExtracts
was a target shuffle - so let the helper do it for us.
Makes it easier for future handling of faux shuffles as well.
Commit: d55259aa61b703ce63613a022c5cb14f6b588b46
https://github.com/llvm/llvm-project/commit/d55259aa61b703ce63613a022c5cb14f6b588b46
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/ADT/GenericCycleImpl.h
M llvm/include/llvm/ADT/GenericCycleInfo.h
M llvm/include/llvm/ADT/GenericUniformityImpl.h
M llvm/include/llvm/ADT/GenericUniformityInfo.h
M llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
M llvm/include/llvm/IR/GenericConvergenceVerifierImpl.h
M llvm/lib/Analysis/CFG.cpp
M llvm/lib/Analysis/UniformityAnalysis.cpp
M llvm/lib/CodeGen/MachineCycleAnalysis.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/Utils/FixIrreducible.cpp
Log Message:
-----------
[CycleInfo] Move representation-dependent queries to GenericCycleInfo. NFC
With the Euler tour representation (#208614), blocks live in
GenericCycleInfo::BlockLayout and GenericCycle keeps a `CI` back-pointer just
so the out-of-line contains(BlockT *) and blocks() can reach it.
Adopt the design suggested by @aengelke, move the
representation-dependent queries to GenericCycleInfo, taking the cycle
as an argument (contains, getBlocks, getExitBlocks, getExitingBlocks,
getCyclePreheader, getCyclePredecessor, verifyCycle, verifyCycleNest,
and per-cycle print), and delete GenericCycle::CI.
- GenericCycleInfo's move operations become defaulted, dropping the
CI re-pointing walk, and sizeof(GenericCycle) shrinks by a pointer.
- isCycleInvariant gains a MachineCycleInfo parameter, and
GenericUniformityInfo gains getCycleInfo() for callers that only hold the
uniformity result.
Aided by Claude Fable 5
Pull Request: https://github.com/llvm/llvm-project/pull/209665
Commit: a16f3a09415d28928b1e5133ad63ad3d2d97fa99
https://github.com/llvm/llvm-project/commit/a16f3a09415d28928b1e5133ad63ad3d2d97fa99
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
A libcxx/test/benchmarks/algorithms/modifying/replace_copy.bench.cpp
Log Message:
-----------
[libc++] Add benchmarks for std::replace_copy and std::replace_copy_if (#207070)
Assisted by Claude
Commit: 0a933be62ea9fb3c6835ffa37852ef9a0288bccf
https://github.com/llvm/llvm-project/commit/0a933be62ea9fb3c6835ffa37852ef9a0288bccf
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
A libcxx/test/benchmarks/algorithms/sorting/binary_search.bench.cpp
A libcxx/test/benchmarks/algorithms/sorting/equal_range.bench.cpp
M libcxx/test/benchmarks/algorithms/sorting/lower_upper_bound.bench.cpp
Log Message:
-----------
[libc++] Add benchmarks for std::binary_search and std::equal_range (#207268)
The found and not-found paths are measured as separate benchmarks. For
equal_range we additionally cover a unique match, a large equal range,
and an absent key.
As a drive-by, add a predicate variation to the existing lower_bound and
upper_bound benchmarks.
Commit: f4120c4a1d0daaac81983df10a809df883b25173
https://github.com/llvm/llvm-project/commit/f4120c4a1d0daaac81983df10a809df883b25173
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M libcxx/include/__algorithm/copy_n.h
M libcxx/include/__algorithm/for_each_n.h
M libcxx/include/__algorithm/generate_n.h
M libcxx/include/__algorithm/ranges_for_each_n.h
M libcxx/include/__bit_reference
A libcxx/test/libcxx/algorithms/alg.nonmodifying/alg.foreach/assert.for_each_n.pass.cpp
A libcxx/test/libcxx/algorithms/alg.nonmodifying/alg.foreach/assert.ranges.for_each_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/copy_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/ranges.copy_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/fill_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/ranges.fill_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.generate/generate_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.generate/ranges_generate_n.pass.cpp
Log Message:
-----------
[libc++] Treat negative counts in copy_n & friends as no-ops (#207086)
The standard specifies copy_n, fill_n and generate_n (both std and
ranges) to be no-ops when passed a negative count. This patch fixes
libc++ to abide by that requirement, with tests.
It's worth noting that std::for_each_n makes n > 0 a precondition
instead: we add the check and tests for it.
Fixes #193613
Commit: dccdacc2dc49c708a8fde04b04ae76b552aaf122
https://github.com/llvm/llvm-project/commit/dccdacc2dc49c708a8fde04b04ae76b552aaf122
Author: Victor Perez <victor.pc.upm at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
M mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/test/Dialect/Arith/canonicalize.mlir
Log Message:
-----------
[mlir][arith] Canonicalize `addf(negf(x), y)` to `subf(y, x)` (#209277)
`arith.addf` had no canonicalization patterns at all. This adds a
canonicalizer rewriting `addf(negf(x), y) -> subf(y, x)` (and the
commuted operand order).
The rewrite is valid under any rounding mode, which is propagated to the
`subf`: `negf` is an exact sign flip, IEEE addition is commutative, and
`y - x` is the correctly rounded `y + (-x)`, so `subf(y, x)` and
`addf(negf(x), y)` are bit-identical for every rounding mode. Fast-math
flags are propagated to the new `subf`.
----
Code partially generated with Claude Code.
Signed-off-by: Víctor Pérez Carrasco <victorperez at fb.com>
Co-authored-by: Víctor Pérez Carrasco <victorperez at fb.com>
Commit: 15cd911154b5712e37187c4507ee7b29c412b998
https://github.com/llvm/llvm-project/commit/15cd911154b5712e37187c4507ee7b29c412b998
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/BPF/sink-min-max.ll
Log Message:
-----------
[BPF] Use UTC for sink-min-max.ll
The assertions were providing a similar level of coverage. Autogenerate
them to make maintenance easier.
Reviewers: mtrofin, yonghong-song, eddyz87
Pull Request: https://github.com/llvm/llvm-project/pull/209681
Commit: c102184cbdcb8467ce1caf384ecd4e36d97fa37c
https://github.com/llvm/llvm-project/commit/c102184cbdcb8467ce1caf384ecd4e36d97fa37c
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lld/ELF/SyntheticSections.cpp
M lld/ELF/SyntheticSections.h
M lld/ELF/Writer.cpp
M lld/test/ELF/local-symbols-order.s
M lld/test/ELF/lto/parallel-internalize.ll
M lld/test/ELF/ppc64-local-entry.s
M lld/test/ELF/relocatable-comdat-multiple.s
M lld/test/ELF/relocatable-comdat2.s
M lld/test/ELF/relocatable-discard-locals.s
M lld/test/ELF/relocatable-gc.s
M lld/test/ELF/relocatable.s
M lld/test/ELF/strtab-nodedup.s
Log Message:
-----------
[ELF] Synthesize STT_FILE if necessary (#209087)
lld groups local symbols in .symtab by input file, appending a symbol
converted to STB_LOCAL (hidden visibility, version script `local:`, or
--exclude-libs) to its file's group. The nearest preceding STT_FILE then
claims the symbol, but the attribution can be wrong: the file may
contain multiple STT_FILE symbols (-r output), or lack an STT_FILE for
the symbol's unit.
```
FILE LOCAL DEFAULT ABS a.c
NOTYPE LOCAL DEFAULT 7 a_local
FILE LOCAL DEFAULT ABS b.c
NOTYPE LOCAL DEFAULT 7 b_local
NOTYPE LOCAL DEFAULT 7 a_localized
```
Follow GNU ld:
- If the output contains an STT_FILE symbol, place at the end of the
local part, after a synthetic STT_FILE with an empty name, every local
that cannot be attributed to a file: symbols converted to STB_LOCAL,
linker-synthesized symbols such as `_DYNAMIC`, and range-extension
thunks (parented to the internal file, which has no STT_FILE).
- For -r output, synthesize an STT_FILE named after the input file for
an input that outputs local symbols but no STT_FILE, so that its locals
are not attributed to a preceding file. We use the basename instead of
the full name for local determinism (#47367).
GNU ld synthesizes this per-input STT_FILE for executable and
shared-object output as well. Restrict it to -r for now to minimize test
updates.
Close #47367 and #191478
Commit: 521d3e375ecb81d8b7c2d501496be11bdbd8cec0
https://github.com/llvm/llvm-project/commit/521d3e375ecb81d8b7c2d501496be11bdbd8cec0
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp
M llvm/test/CodeGen/BPF/sink-min-max.ll
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
[BPF][ProfCheck] Fix sink-min-max.ll
In bpf-check-and-opt-ir, llvm.umax and llvm.umin are lowered into
explicit comparisons/i1 bitwise operations involving select. Make sure
to mark the selects as having an explicitly unknown profile given we
cannot infer what is likely/unlikely to avoid profcheck failures.
Reviewers: yonghong-song, mtrofin, eddyz87
Pull Request: https://github.com/llvm/llvm-project/pull/209682
Commit: 7cef6a72a1641cf3841b401782c4434635bf3d73
https://github.com/llvm/llvm-project/commit/7cef6a72a1641cf3841b401782c4434635bf3d73
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/ADT/GenericCycleImpl.h
M llvm/include/llvm/ADT/GenericCycleInfo.h
Log Message:
-----------
[CycleInfo] Number cycles and move the exit-block cache to GenericCycleInfo. NFC
Assign each cycle a preorder ID in layoutBlocks's Euler-tour walk and
move the caches into a lazily allocated table indexed by ID, shrinking
sizeof(GenericCycle) from 128 to 80. appendEntry/setSingleEntry no
longer invalidate: the exit-block set does not depend on entries. Delete
the unused GenericCycle::clear.
Aided by Claude Fable 5
Pull Request: https://github.com/llvm/llvm-project/pull/209666
Commit: 50d9b2768f4cf224ed7c3d15703aa2d5190f9b4a
https://github.com/llvm/llvm-project/commit/50d9b2768f4cf224ed7c3d15703aa2d5190f9b4a
Author: Matt <MattPD at users.noreply.github.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang/include/flang/Lower/OpenMP.h
M flang/include/flang/Lower/Support/ReductionProcessor.h
M flang/include/flang/Semantics/openmp-utils.h
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/Support/ReductionProcessor.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/mod-file.cpp
M flang/lib/Semantics/mod-file.h
M flang/lib/Semantics/openmp-utils.cpp
A flang/test/Lower/OpenMP/Todo/declare-reduction-allocatable-trivial.f90
R flang/test/Lower/OpenMP/Todo/declare-reduction-operator-multiple-types.f90
R flang/test/Lower/OpenMP/Todo/declare-reduction-operator-use-assoc.f90
R flang/test/Lower/OpenMP/Todo/multiple-types-declare_reduction.f90
M flang/test/Lower/OpenMP/declare-reduction-character-allocatable.f90
M flang/test/Lower/OpenMP/declare-reduction-initializer-component.f90
M flang/test/Lower/OpenMP/declare-reduction-initializer-defined-assign.f90
M flang/test/Lower/OpenMP/declare-reduction-initializer-rhs-call.f90
M flang/test/Lower/OpenMP/declare-reduction-intrinsic-op.f90
A flang/test/Lower/OpenMP/declare-reduction-intrinsic-same-name-different-scope.f90
M flang/test/Lower/OpenMP/declare-reduction-logical-init.f90
A flang/test/Lower/OpenMP/declare-reduction-merge-hermetic.f90
A flang/test/Lower/OpenMP/declare-reduction-merge-version-skew.f90
A flang/test/Lower/OpenMP/declare-reduction-name-type-token-collision.f90
A flang/test/Lower/OpenMP/declare-reduction-named-renamed.f90
A flang/test/Lower/OpenMP/declare-reduction-named-separate-rename.f90
A flang/test/Lower/OpenMP/declare-reduction-named-use-assoc.f90
M flang/test/Lower/OpenMP/declare-reduction-no-initializer-derived.f90
M flang/test/Lower/OpenMP/declare-reduction-no-initializer-intrinsic.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-collide.f90
M flang/test/Lower/OpenMP/declare-reduction-operator-derived.f90
M flang/test/Lower/OpenMP/declare-reduction-operator-host-assoc.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-merged.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-multiple-types.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-renamed.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-collide-unused.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-combiners.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-hermetic.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-intrinsic-all.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-intrinsic-collide.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-intrinsic.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-multitype-partial.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-reexport.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-remerge.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-rename-remerge.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-submodule.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-unused-unsupported.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-use-assoc.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-use-only-nonreduction.f90
M flang/test/Lower/OpenMP/declare-reduction-operator.f90
M flang/test/Lower/OpenMP/declare-reduction-same-name-different-scope.f90
A flang/test/Lower/OpenMP/declare-reduction-shadows-intrinsic-multiple-types.f90
A flang/test/Lower/OpenMP/declare-reduction-shadows-intrinsic-separate.f90
A flang/test/Lower/OpenMP/declare-reduction-shadows-intrinsic-use-assoc.f90
M flang/test/Lower/OpenMP/declare-reduction-shadows-intrinsic.f90
A flang/test/Lower/OpenMP/declare-reduction-special-separate-reexport.f90
M flang/test/Lower/OpenMP/declare-reduction-target-intrinsic.f90
A flang/test/Lower/OpenMP/multiple-types-declare_reduction.f90
M flang/test/Lower/OpenMP/omp-declare-reduction-combsub.f90
M flang/test/Lower/OpenMP/omp-declare-reduction-derivedtype.f90
M flang/test/Lower/OpenMP/omp-declare-reduction-initsub.f90
M flang/test/Lower/OpenMP/omp-declare-reduction.f90
A flang/test/Semantics/OpenMP/declare-reduction-ambiguous.f90
Log Message:
-----------
[flang][OpenMP] Lower cross-module user-defined declare reduction (#207493)
Lower a reduction clause naming a USE-associated, renamed, or merged-generic
user-defined reduction, which currently aborts lowering with a "not yet
implemented" TODO. Semantics already accepts these programs (since #200329).
This covers the defined-operator, intrinsic-operator, and named forms, each for
one or several types in a single declare reduction. One shape is still deferred.
A reduction on an allocatable or pointer operand of a trivial intrinsic element
type (integer, real, complex, or logical) is not lowered yet and reaches a clean
TODO, tracked by #186765. Character and derived-type allocatable reductions do
lower.
Fixes #207255.
Fixes #207489.
An imported reduction is materialized lazily. Its `omp.declare_reduction` op is
created on demand, only when a reduction clause has resolved the exact reduction
it references, through the same lowering path a local declare reduction uses.
There is no separate eager pass that walks accessible scopes to pre-create ops.
The module only-list property is therefore structural. A program using
`use m, only: <non-reduction>` never emits m's reduction, because nothing
references it. One path handles every import form: plain and renamed USE, nested
and merged generic operators, submodules, and intrinsic operators.
Resolve the use-site reduction to its source symbol through the shared semantic
resolver (`Fortran::semantics::omp::FindUserReductionSymbol`), extracted from
check-omp-structure.cpp into Semantics/openmp-utils so lowering and the semantic
checks share one resolution authority. Name the op from the resolved symbol's
ultimate name and owning scope via `getScopedUserReductionName`, on both the
clause and directive sides so the two cannot drift.
For a multi-type declare reduction, the same-file directive emits one op per
listed type and binds each variable to the op for its type. Lazy materialization
is stricter, emitting only the per-type op a clause requests, so an unsupported
sibling type does not block a supported one. The per-type lists advance in
lockstep: type, combiner, and initializer. The type suffix is unconditional,
including for a single-type reduction, so a multi-type per-type op cannot collide
with a single-type op sharing the same type-suffixed spelling.
Intrinsic-operator user reductions are named by their defining scope and ultimate
symbol, matching the defined-operator and named forms. Previously they used a
global name derived from the operator and element type, so two declare reductions
for the same operator and type in different scopes (two modules, or two
procedures in one file) could collide onto one op and silently bind the wrong
combiner. Builtin intrinsic reductions keep their global names.
For separate compilation the imported directive carries bound names but no typed
expressions, because mod-file reading runs only ResolveNames. The materializer
therefore runs expression analysis over the directive before lowering. Creating
the op from an imported module directive during lowering follows the imported
declare-mapper precedent.
An operator-less declare reduction (a special function such as max or min, or an
intrinsic operator such as `+` on an intrinsic type) has an internal mangled name
that is not valid Fortran, and no re-exported operator to recover through. When
such a reduction is re-exported through a facade, emitting it as a `use, only`
item produced a module file that failed to re-parse. The module-file writer
instead re-exports the defining module with a plain `use`, because a mangled name
cannot appear in an only-list. Entities the facade renames or makes private keep
their own use, rename, or private items, so the plain `use` does not widen their
visibility. The reduction then arrives as one shared use-association owned by the
defining module, binding the user's combiner rather than a facade-owned duplicate
that would fall back to the intrinsic. A private reduction is not re-exported.
When a reduction identifier resolves to more than one distinct user-defined
reduction for the list item's type, the clause is rejected as ambiguous rather
than selecting a combiner silently by USE order. Distinctness is by canonical
identity, the defining module and reduction name, so one reduction reached
through several USE, rename, or facade paths collapses to one candidate while
reductions from different modules stay separate. One case is not distinguished.
A same-named module loaded at two versions (a stale hermetic embed versus a
rebuilt copy) collapses to one candidate and is still resolved by USE order,
matching the prior behavior.
Assisted-by: Claude Opus 4.8, GPT-5.5.
Commit: 693ded3ecc9c18178c7fc7fc1186d624edb5e62f
https://github.com/llvm/llvm-project/commit/693ded3ecc9c18178c7fc7fc1186d624edb5e62f
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/runtimes/CMakeLists.txt
Log Message:
-----------
[LLVM] Fix not passing CMAKE_CROSSCOMPILING_EMULATOR for amdgpu (#209828)
Summary:
This only matches on amdgcn, just add amdgpu
Commit: 3a10c3aa3c2087ca4e6f0a18e182ced84a8a7fd0
https://github.com/llvm/llvm-project/commit/3a10c3aa3c2087ca4e6f0a18e182ced84a8a7fd0
Author: Rashmi Mudduluru <r_mudduluru at apple.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/include/clang/Frontend/SSAFOptions.h
M clang/include/clang/Options/Options.td
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/ScalableStaticAnalysis/Analyses/PointerFlow/PointerFlowExtractor.cpp
M clang/lib/ScalableStaticAnalysis/Analyses/SSAFAnalysesCommon.cpp
M clang/lib/ScalableStaticAnalysis/Analyses/SSAFAnalysesCommon.h
M clang/lib/ScalableStaticAnalysis/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp
A clang/test/Analysis/Scalable/PointerFlow/system-header-opt-out.cpp
M clang/test/Analysis/Scalable/help.cpp
M clang/unittests/ScalableStaticAnalysis/Analyses/PointerFlow/PointerFlowTest.cpp
Log Message:
-----------
[clang][SSAF] Optionally skip system-header contributors (#205446)
A new —ssaf-no-extract-from-system-headers switch that gates the
contributor finder so contributors located inside system headers are
dropped from the per-TU summary.
rdar://179151040
---------
Co-authored-by: Balázs Benics <benicsbalazs at gmail.com>
Commit: 5979f7c96f44d225219d3c637773455e51190ad2
https://github.com/llvm/llvm-project/commit/5979f7c96f44d225219d3c637773455e51190ad2
Author: Letu Ren <fantasquex at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/test/CIR/CodeGenBuiltins/builtins-elementwise.c
Log Message:
-----------
[CIR][NFC] Update stale elementwise handler (#207530)
A follow up of https://github.com/llvm/llvm-project/pull/204974
Clean up stale code of https://github.com/llvm/llvm-project/pull/169424
Add two missing CIR elementwise tests
Add three missing elementwise builtins as NYI
Assisted-by: Codex
Commit: b8ba3c2b72cb53268129bbecfeb4ba7ec5b8d831
https://github.com/llvm/llvm-project/commit/b8ba3c2b72cb53268129bbecfeb4ba7ec5b8d831
Author: Reinhard Stahn <rainij36 at proton.me>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M mlir/include/mlir/Conversion/Passes.h
M mlir/include/mlir/Conversion/Passes.td
A mlir/include/mlir/Conversion/SCFToAffine/SCFToAffine.h
M mlir/lib/Conversion/CMakeLists.txt
A mlir/lib/Conversion/SCFToAffine/CMakeLists.txt
A mlir/lib/Conversion/SCFToAffine/SCFToAffine.cpp
A mlir/test/Conversion/SCFToAffine/scf-to-affine.mlir
Log Message:
-----------
[mlir][SCFToAffine] Raise scf.for to affine.for (#200851)
Add a pass `-raise-scf-to-affine` that rewrites `scf.for` into
`affine.for` when the bounds and step are valid affine quantities. It
handles constant and dynamic steps, and integer-typed loops (by a
lossless cast of the bounds to `index`).
This is a first step; raising further scf ops to affine will follow.
Assisted-by: Claude Code (Anthropic)
Co-authored-by: Ming Yan <nexming7 at gmail.com>
Co-authored-by: Julian Farnsteiner <jcf96 at proton.me>
Commit: ea612545644d1e3f238ac4cd053758f569f9bf3b
https://github.com/llvm/llvm-project/commit/ea612545644d1e3f238ac4cd053758f569f9bf3b
Author: Karthika Devi C <kartc at qti.qualcomm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M polly/lib/CodeGen/BlockGenerators.cpp
M polly/lib/CodeGen/IslNodeBuilder.cpp
A polly/test/CodeGen/issue205732.ll
Log Message:
-----------
[Polly] Fix codegen assertions to account for DefinedBehaviorContext (#209188)
DeLICM may produce new read access relations whose domain is restricted
to the DefinedBehaviorContext (e.g., only valid when a parameter ensures
no UB). The validation in setNewAccessRelation already accounts for
this, but the debug assertions in createNewAccesses and
generateScalarLoads did not, causing false assertion failures during
code generation.
Intersect the checked domains with getBestKnownDefinedBehaviorContext()
to match the contract that DeLICM relies on.
Fixes #205732
Commit: 378629b2200b092fa33e6171e7c749c95ff92e9c
https://github.com/llvm/llvm-project/commit/378629b2200b092fa33e6171e7c749c95ff92e9c
Author: anoopkg6 <anoop.kumar6 at ibm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang/lib/Optimizer/CodeGen/TargetRewrite.cpp
Log Message:
-----------
[flang] Derive target-specific data layout from triple in TargetRewrite (#209649)
When target-rewrite runs without an explicit llvm.data_layout attribute,
it falls back to hardcoded generic default in MLIR (kDefaultDataLayout)
which specifies f128 ABI alignment as 16 bytes. This is incorrect for
targets where f128 ABI alignment differs from its size, such as SystemZ
which requires 8 bytes per the ELF ABI.
The target triple is available in the target-rewrite pass. Fix by
deriving the data layout from the target triple using
triple.computeDataLayout() before falling back to the generic default,
ensuring target-specific alignments are correctly reflected in
dlti.dl_spec.
@uweigand @dominik-steenken
---------
Co-authored-by: anoop.kumar6 at ibm.com <anoopk at b35lp63.lnxne.boe>
Commit: 09a947e3d02cbd8a7afd273bddbcf9fe489bfe9c
https://github.com/llvm/llvm-project/commit/09a947e3d02cbd8a7afd273bddbcf9fe489bfe9c
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbtest.py
M lldb/packages/Python/lldbsuite/test/lldbutil.py
M lldb/test/API/driver/longpath/TestLongPathDriver.py
M lldb/test/API/functionalities/longpath/TestLongPath.py
M lldb/test/API/tools/lldb-dap/longpath/TestDAP_launch_longPath.py
M lldb/test/Shell/helper/toolchain.py
Log Message:
-----------
[lldb][Windows] Use extended path prefix for rmtree (#209409)
The test suite previously only warned when a test build directory or
artifact path exceeded Windows' `MAX_PATH (260)` limit, and
`shutil.rmtree` could fail to clean up such directories. This replaces
the warnings with actual long-path support.
This is a recurring problem in Swiftlang.
Commit: c4c4f207590a1569b5c30ffe2f204f5d0d535a68
https://github.com/llvm/llvm-project/commit/c4c4f207590a1569b5c30ffe2f204f5d0d535a68
Author: Schrodinger ZHU Yifan <yfzhu at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M libc/src/__support/freelist.cpp
Log Message:
-----------
[libc][baremetal][NFC] cache away redundant freelist memory access during push and pop (#208282)
By explicitly caching Node *next = node->next; and Node *prev =
node->prev; at function entry:
#### Before (Original):
```llvm
13: ; preds = %6
%14 = load ptr, ptr %1, align 8 ; Load node->prev
%15 = getelementptr inbounds nuw i8, ptr %14, i64 8
store ptr %8, ptr %15, align 8 ; Store next to prev->next
%16 = load ptr, ptr %7, align 8 ; <--- REDUNDANT LOAD of node->next
store ptr %14, ptr %16, align 8 ; Store prev to next->prev
%17 = icmp eq ptr %3, %1
br i1 %17, label %18, label %20
18: ; preds = %13, %10
%19 = phi ptr [ null, %10 ], [ %16, %13 ]
store ptr %19, ptr %0, align 8
```
#### After (Manual GVN in remove ):
```llvm
13: ; preds = %6
%14 = load ptr, ptr %1, align 8 ; Load node->prev
%15 = getelementptr inbounds nuw i8, ptr %14, i64 8
store ptr %8, ptr %15, align 8 ; Store next to prev->next
store ptr %14, ptr %8, align 8 ; <--- REUSES CACHED %8 DIRECTLY
%16 = icmp eq ptr %3, %1
br i1 %16, label %17, label %19
17: ; preds = %13, %10
%18 = phi ptr [ null, %10 ], [ %8, %13 ] ; <--- REUSES CACHED %8 IN PHI NODE
store ptr %18, ptr %0, align 8
```
### 2. Compiler Optimization Remarks & LTO Impact
1. GVN Diagnostics:
• Before: freelist.cpp:41:11: remark: load of type ptr not eliminated
[-Rpass-missed=gvn]
• After: Clean (0 missed GVN remarks).
2. LTO (Link-Time Optimization) & Code Size:
Eliminates 1 memory read ( MOV64rm ) and 1 memory store ( MOV64mr ) at
every inlined call site in malloc / free.
Assisted-by: Gemini based automation tool (human-in-the-loop)
Commit: 27329918bf4c9430104449b9a5c0354f138417db
https://github.com/llvm/llvm-project/commit/27329918bf4c9430104449b9a5c0354f138417db
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
Log Message:
-----------
[AMDGPU] Limit unclaused VMEM w/a to specific targets (#209843)
Fixes: LCOMPILER-2448
Commit: be1b1a77732ce65d8de5f8316f0ce65e2be818ba
https://github.com/llvm/llvm-project/commit/be1b1a77732ce65d8de5f8316f0ce65e2be818ba
Author: Brandon Correa <bwancor at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/LineEditor/LineEditor.cpp
Log Message:
-----------
Turn signal handling on in LineEditor (#203616)
This PR was created to address
https://github.com/jank-lang/jank/issues/801.
Without signal handling, `CLRL+C` / `CTRL+Z` leaves the terminal in an
awkward state, breaking other command line tasks and forcing the user to
open a new/clean terminal window.
cc: @jeaye
### Edit
#### AI
Per the contribution policies and review practices, AI was used to
locate the root cause of the issue I was seeing. From there, I
personally wrote the code and manually tested the build to verify that
the change fixed the problem I was seeing.
#### Testing
Since there were no pre-existing unit tests for this module, no
additional unit tests were added for this PR. I validated the existing
build/tests locally and validated the change propagated through
manually.
Commit: 889b2d651a530952339e4992a2b5a891c7dd0af0
https://github.com/llvm/llvm-project/commit/889b2d651a530952339e4992a2b5a891c7dd0af0
Author: Dan Brown <61992655+danbrown-amd at users.noreply.github.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/AST/HLSL/HLSLControlFlowHint.hlsl
M clang/test/AST/HLSL/matrix-alias.hlsl
M clang/test/AST/HLSL/matrix-constructors.hlsl
M clang/test/AST/HLSL/matrix-elementexpr-tree-transform.hlsl
M clang/test/AST/HLSL/matrix-general-initializer.hlsl
M clang/test/AST/HLSL/matrix-member-access-scalar.hlsl
M clang/test/AST/HLSL/matrix-member-access-swizzle.hlsl
M clang/test/AST/HLSL/resources-in-structs-errors.hlsl
M clang/test/AST/HLSL/resources-in-structs.hlsl
M clang/test/AST/HLSL/vector-alias.hlsl
M clang/test/AST/HLSL/vector-constructors.hlsl
M clang/test/AST/HLSL/vk.spec-constant.usage.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/frem_modulo.hlsl
M clang/test/CodeGenHLSL/builtins/AllMemoryBarrier.hlsl
M clang/test/CodeGenHLSL/builtins/AllMemoryBarrierWithGroupSync.hlsl
M clang/test/CodeGenHLSL/builtins/DeviceMemoryBarrier.hlsl
M clang/test/CodeGenHLSL/builtins/DeviceMemoryBarrierWithGroupSync.hlsl
M clang/test/CodeGenHLSL/builtins/GroupMemoryBarrier.hlsl
M clang/test/CodeGenHLSL/builtins/GroupMemoryBarrierWithGroupSync.hlsl
M clang/test/CodeGenHLSL/builtins/InterlockedAdd.hlsl
M clang/test/CodeGenHLSL/builtins/InterlockedOr.hlsl
M clang/test/CodeGenHLSL/builtins/QuadReadAcrossDiagonal.hlsl
M clang/test/CodeGenHLSL/builtins/QuadReadAcrossX.hlsl
M clang/test/CodeGenHLSL/builtins/QuadReadAcrossY.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveAllEqual.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveAllTrue.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveAnyTrue.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveBallot.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveBitAnd.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveBitXor.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveCountBits.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveMax.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveMin.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveProduct.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveSum.hlsl
M clang/test/CodeGenHLSL/builtins/WavePrefixCountBits.hlsl
M clang/test/CodeGenHLSL/builtins/WavePrefixProduct.hlsl
M clang/test/CodeGenHLSL/builtins/WavePrefixSum.hlsl
M clang/test/CodeGenHLSL/builtins/WaveReadLaneAt.hlsl
M clang/test/CodeGenHLSL/builtins/acos-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/acos.hlsl
M clang/test/CodeGenHLSL/builtins/all.hlsl
M clang/test/CodeGenHLSL/builtins/any.hlsl
M clang/test/CodeGenHLSL/builtins/asdouble.hlsl
M clang/test/CodeGenHLSL/builtins/asin-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/asin.hlsl
M clang/test/CodeGenHLSL/builtins/atan-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/atan.hlsl
M clang/test/CodeGenHLSL/builtins/atan2-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/atan2-overloads_mat.hlsl
M clang/test/CodeGenHLSL/builtins/atan2.hlsl
M clang/test/CodeGenHLSL/builtins/atan2_mat.hlsl
M clang/test/CodeGenHLSL/builtins/clamp-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/clamp.hlsl
M clang/test/CodeGenHLSL/builtins/clip.hlsl
M clang/test/CodeGenHLSL/builtins/cosh-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/cosh.hlsl
M clang/test/CodeGenHLSL/builtins/cross.hlsl
M clang/test/CodeGenHLSL/builtins/ddx-coarse-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/ddx-coarse.hlsl
M clang/test/CodeGenHLSL/builtins/ddx-fine-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/ddx-fine.hlsl
M clang/test/CodeGenHLSL/builtins/ddx.hlsl
M clang/test/CodeGenHLSL/builtins/ddy-coarse-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/ddy-coarse.hlsl
M clang/test/CodeGenHLSL/builtins/ddy-fine-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/ddy-fine.hlsl
M clang/test/CodeGenHLSL/builtins/ddy.hlsl
M clang/test/CodeGenHLSL/builtins/degrees-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/degrees.hlsl
M clang/test/CodeGenHLSL/builtins/distance.hlsl
M clang/test/CodeGenHLSL/builtins/dot.hlsl
M clang/test/CodeGenHLSL/builtins/dot2add.hlsl
M clang/test/CodeGenHLSL/builtins/f16tof32-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/f16tof32.hlsl
M clang/test/CodeGenHLSL/builtins/f32tof16-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/f32tof16.hlsl
M clang/test/CodeGenHLSL/builtins/faceforward.hlsl
M clang/test/CodeGenHLSL/builtins/firstbithigh.hlsl
M clang/test/CodeGenHLSL/builtins/firstbitlow.hlsl
M clang/test/CodeGenHLSL/builtins/fma.hlsl
M clang/test/CodeGenHLSL/builtins/fmod.hlsl
M clang/test/CodeGenHLSL/builtins/frac-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/frac.hlsl
M clang/test/CodeGenHLSL/builtins/isinf-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/isinf.hlsl
M clang/test/CodeGenHLSL/builtins/isnan.hlsl
M clang/test/CodeGenHLSL/builtins/length.hlsl
M clang/test/CodeGenHLSL/builtins/lerp-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/lerp.hlsl
M clang/test/CodeGenHLSL/builtins/mad.hlsl
M clang/test/CodeGenHLSL/builtins/normalize-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/normalize.hlsl
M clang/test/CodeGenHLSL/builtins/radians-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/radians.hlsl
M clang/test/CodeGenHLSL/builtins/rcp.hlsl
M clang/test/CodeGenHLSL/builtins/reflect.hlsl
M clang/test/CodeGenHLSL/builtins/refract.hlsl
M clang/test/CodeGenHLSL/builtins/rsqrt-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/rsqrt.hlsl
M clang/test/CodeGenHLSL/builtins/sign.hlsl
M clang/test/CodeGenHLSL/builtins/sinh.hlsl
M clang/test/CodeGenHLSL/builtins/smoothstep.hlsl
M clang/test/CodeGenHLSL/builtins/step-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/step.hlsl
M clang/test/CodeGenHLSL/builtins/tan-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/tan.hlsl
M clang/test/CodeGenHLSL/builtins/tanh-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/tanh.hlsl
M clang/test/CodeGenHLSL/resources/StructuredBuffers-methods-ps.hlsl
M clang/test/CodeGenHLSL/resources/Textures-Mips.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_geps.hlsl
M clang/test/CodeGenHLSL/semantics/semantic.explicit-mix-builtin.vs.hlsl
M clang/test/Driver/dxc_hlsl-rootsig-ver.hlsl
M clang/test/ParserHLSL/access_specifiers.hlsl
M clang/test/ParserHLSL/hlsl_contained_type_attr.hlsl
M clang/test/ParserHLSL/hlsl_contained_type_attr_error.hlsl
M clang/test/ParserHLSL/hlsl_is_array_attr.hlsl
M clang/test/ParserHLSL/hlsl_is_array_attr_error.hlsl
M clang/test/ParserHLSL/hlsl_is_rov_attr.hlsl
M clang/test/ParserHLSL/hlsl_is_rov_attr_error.hlsl
M clang/test/ParserHLSL/hlsl_raw_buffer_attr.hlsl
M clang/test/ParserHLSL/hlsl_raw_buffer_attr_error.hlsl
M clang/test/ParserHLSL/hlsl_resource_class_attr.hlsl
M clang/test/ParserHLSL/hlsl_resource_class_attr_error.hlsl
M clang/test/ParserHLSL/hlsl_resource_dimension_attr.hlsl
M clang/test/ParserHLSL/hlsl_resource_dimension_attr_error.hlsl
M clang/test/ParserHLSL/semantic_parsing.hlsl
M clang/test/ParserHLSL/semantic_parsing_define.hlsl
M clang/test/SemaHLSL/Availability/attr-deprecated.hlsl
M clang/test/SemaHLSL/BuiltIns/binary-compat-overload-warnings.hlsl
M clang/test/SemaHLSL/BuiltIns/fma-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/matrix-constructors-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/ternary-compat-overload-warnings.hlsl
M clang/test/SemaHLSL/BuiltIns/unary-compat-overload-warnings.hlsl
M clang/test/SemaHLSL/BuiltIns/vec-scalar-compat-overload-warnings.hlsl
M clang/test/SemaHLSL/BuiltIns/vector-constructors-errors.hlsl
M clang/test/SemaHLSL/Language/InitIncompleteArrays.hlsl
M clang/test/SemaHLSL/Language/InitLists.hlsl
M clang/test/SemaHLSL/Language/NoVirtual.hlsl
M clang/test/SemaHLSL/Language/OutputParameters.hlsl
M clang/test/SemaHLSL/Language/TemplateOutArg.hlsl
M clang/test/SemaHLSL/Resources/ConstantBuffers.hlsl
M clang/test/SemaHLSL/Semantics/semantic.explicit-mix-builtin-vs.hlsl
M clang/test/SemaHLSL/Semantics/semantic.explicit-mix-location-2.hlsl
M clang/test/SemaHLSL/Semantics/semantic.explicit-mix-location.hlsl
M clang/test/SemaHLSL/Semantics/valid_entry_parameter.hlsl
M clang/test/SemaHLSL/Semantics/vertexid.vs.hlsl
M clang/test/SemaHLSL/Types/short-errors.hlsl
M clang/test/SemaHLSL/entry_shader.hlsl
M clang/test/SemaHLSL/num_threads.hlsl
M clang/test/SemaHLSL/prohibit_reference.hlsl
M clang/test/SemaHLSL/vk.spec-constant.error.hlsl
Log Message:
-----------
[HLSL] Adds diagnostics for missing/ambiguous shader entry function. (#184892)
Addresses #119260.
Commit: 2dac2abaff714c099880d1d41066d2609563242e
https://github.com/llvm/llvm-project/commit/2dac2abaff714c099880d1d41066d2609563242e
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel][mlir] Port b8ba3c2b72cb53268129bbecfeb4ba7ec5b8d831 (#209854)
Add SCFToAffine target + deps
Commit: 0256ff92c9e1033270a73ba83d0f34865ef63202
https://github.com/llvm/llvm-project/commit/0256ff92c9e1033270a73ba83d0f34865ef63202
Author: Kelvin Li <kli at ca.ibm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/test/lit.cfg.py
Log Message:
-----------
[clang][test][AIX] Set OBJECT_MODE=any for all clang test (#209531)
This patch sets OBJECT_MODE=any to have tools able to handle 32-bit or
64-bit objects.
Commit: b74c800578a06bba7b3bacc690cbe493759836a2
https://github.com/llvm/llvm-project/commit/b74c800578a06bba7b3bacc690cbe493759836a2
Author: Kyungtak Woo <kevinwkt at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
Log Message:
-----------
[compiler-rt][tsan] Fix -Wunused-template in tsan_interface_atomic.cpp (NFC) (#209621)
Commit: 4e1a6091623a4d3b28132b6b4940a264511f5d0e
https://github.com/llvm/llvm-project/commit/4e1a6091623a4d3b28132b6b4940a264511f5d0e
Author: Steven Wu <stevenwu at apple.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/Sema/ExternalSemaSource.h
M clang/include/clang/Sema/MultiplexExternalSemaSource.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Serialization/ASTReader.h
M clang/lib/Sema/MultiplexExternalSemaSource.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
A clang/test/PCH/unused-local-typedef-determinism.cpp
A clang/test/SemaCXX/warn-unused-local-typedef-deterministic-order.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ASTUtils.h
Log Message:
-----------
[Sema][Serialization] Emit unused local typedefs in a deterministic order (#209639)
Sema::UnusedLocalTypedefNameCandidates is populated while iterating a
Scope's
DeclsInScope, which is a SmallPtrSet whose iteration order depends on
pointer
values and is therefore not stable across runs. The candidates are
serialized
into the AST file -- both to assign declaration IDs and to write the
UNUSED_LOCAL_TYPEDEF_NAME_CANDIDATES record -- and are also used to emit
the
deferred -Wunused-local-typedef warnings, so neither the emitted PCH/AST
file
nor the diagnostics were reproducible. With deterministic compilation
caching
this surfaces as a "cache poisoned" error, because two builds of the
same PCH
produce different bytes.
Sort the candidates by source location at the point they are consumed,
via
Sema::getSortedUnusedLocalTypedefNameCandidates(), so that both the
diagnostics
and the serialized declarations are deterministic.
Commit: 26194d4623650fd3f9b58cda34b318197613e702
https://github.com/llvm/llvm-project/commit/26194d4623650fd3f9b58cda34b318197613e702
Author: Zachary Yedidia <zyedidia at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/docs/LFI.rst
M llvm/include/llvm/MC/MCLFIRewriter.h
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCLFIRewriter.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCLFIRewriter.h
M llvm/test/MC/AArch64/LFI/guard-elim.s
M llvm/test/MC/AArch64/LFI/mem-lr.s
A llvm/test/MC/AArch64/LFI/pac-errors.s
A llvm/test/MC/AArch64/LFI/pac.s
M llvm/test/MC/AArch64/LFI/return.s
Log Message:
-----------
[LFI][AArch64] Add PAC support for LFI (#207915)
This patch adds support for PAC instructions that sign `x30` by deferring
the LFI mask until the next control-flow instruction or label, allowing
an authentication instruction to run before the mask, which overwrites
the PAC signature bits in the top bits of the pointer. This relies on
FEAT_FPAC to provide a security benefit, which requires authentication
failure to cause a trap, rather than expecting the branch on an invalid
pointer to cause the trap.
Commit: 725f644a31627c08f6cec25a7eb2396ad690d08e
https://github.com/llvm/llvm-project/commit/725f644a31627c08f6cec25a7eb2396ad690d08e
Author: Björn Schäpers <bjoern at hazardy.de>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Improve requires clause parsing (#207542)
We did not consider dependent templates and thus ended the parsing after
template and forcing a line break there. The tests was formatted as:
template <typename T> struct S {
template <typename Foo>
requires T::template
Has<Foo> void func(Foo);
};
Commit: 105261293d6763055cecf7e37aced21de94eaefc
https://github.com/llvm/llvm-project/commit/105261293d6763055cecf7e37aced21de94eaefc
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/X86/fmaddsub-combine.ll
M llvm/test/CodeGen/X86/fmsubadd-combine.ll
Log Message:
-----------
[X86] fmaddsub-combine.ll + fmsubadd-combine.ll - cleanup 512-bit buildvector tests (#209850)
Followup to #207436 - the full buildvector and partial buildvector tests
are covered by PhaseOrdering/X86/fmaddsub.ll which outputs the (still
poor) vectorized shuffle patterns
Ensure the current middle-end IR is tested by the backend, even though
its still not optimal (and divergent between SSE and AVX targets) - I've
kept the buildvector backend patterns for now (and moved the buildvector
fmsubadd patterns to fmsubadd-combine.ll for consistency).
Next step will be to investigate why the middle-end IR result isn't
optimal.
Minor cleanup for #144489
Commit: f41f334bff98866aefa33f09ae67b61532afa4a5
https://github.com/llvm/llvm-project/commit/f41f334bff98866aefa33f09ae67b61532afa4a5
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/Analysis/CostModel/AMDGPU/sin.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-log.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-uniform-waterfall.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-uniform-intrinsic-combine.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-uniform-temporal-divergence.ll
M llvm/test/CodeGen/AMDGPU/atomic-optimizer-promote-i8.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimization_split_dt_update.ll
M llvm/test/CodeGen/AMDGPU/disable-preload-kernargs.ll
M llvm/test/CodeGen/AMDGPU/do-not-unify-divergent-exit-nodes-with-musttail.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.2dmsaa.ll
M llvm/test/CodeGen/AMDGPU/loop-vector-sink.ll
M llvm/test/CodeGen/AMDGPU/lower-intrinsics-barriers.ll
M llvm/test/CodeGen/AMDGPU/lower-intrinsics-cluster-barrier.ll
M llvm/test/CodeGen/AMDGPU/lower-intrinsics-split-barriers.ll
M llvm/test/CodeGen/AMDGPU/prevent-fmul-hoist-ir.ll
M llvm/test/CodeGen/AMDGPU/printf_builtin.ll
M llvm/test/CodeGen/AMDGPU/printf_nobuiltin.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-budget-exhausted.ll
M llvm/test/CodeGen/AMDGPU/vni8-live-reg-opt.ll
M llvm/test/Transforms/AggressiveInstCombine/AMDGPU/fold-consecutive-loads.ll
M llvm/test/Transforms/AggressiveInstCombine/AMDGPU/fold-loads-multiple-uses.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f32-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f32-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f64-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f64-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i32-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i32-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i64-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i64-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-mmra.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-private-gas.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2bf16-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2bf16-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2f16-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2f16-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomicrmw-flat-noalias-addrspace.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomicrmw-fp-vector.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomicrmw-integer-ops-0-to-add-0.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/phinode-address-infer.ll
M llvm/test/Transforms/InstCombine/AMDGPU/bitcast-fold-lane-ops.ll
M llvm/test/Transforms/InstCombine/AMDGPU/fmed3.ll
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.wave.shuffle.ll
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.wavefrontsize.ll
M llvm/test/Transforms/InstCombine/AMDGPU/mbcnt.ll
M llvm/test/Transforms/InstCombine/AMDGPU/rcp-contract-rsq.ll
M llvm/test/Transforms/InstCombine/AMDGPU/simplify-demanded-vector-elts-lane-intrinsics.ll
M llvm/test/Transforms/InstCombine/AMDGPU/trivially-uniform.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/load-i1-misaligned.ll
M llvm/test/Transforms/LoopVectorize/AMDGPU/buffer-fat-pointer.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/exp2-vectorize.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/external-shuffle.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/extract-ordering.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/inst-count-heuristic.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/notriviallyvectorizableintrinsicoperands.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f16.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/vectorize-i8.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/zext-duplicate-shift.ll
M llvm/test/Transforms/SandboxVectorizer/AMDGPU/basic.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/amdgpu-large-lds-offset.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/rebuild-trunc.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/reorder-gep-inbounds.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/reorder-gep.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/reunite-exts-source-types.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/reunite-exts.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn.ll
M llvm/test/Transforms/VectorCombine/AMDGPU/combine-scalar-selects.ll
M llvm/test/Transforms/VectorCombine/AMDGPU/extract-insert-i8.ll
M llvm/test/Transforms/VectorCombine/AMDGPU/shuffles-of-length-changing-shuffles.ll
Log Message:
-----------
AMDGPU: Migrate tests with regenerated checks to amdgpu subarch triple (54) (#209780)
Fold the explicit -mcpu subtarget into the amdgpu subarch triple on
autogenerated tests where the folded triple changes output relative to
the previous default subtarget (e.g. cost-model BASE lines, scheduling).
CHECK lines were regenerated with the update_*_test_checks.py scripts.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 27836a16cd229d25413e23d7d14ebe2678385121
https://github.com/llvm/llvm-project/commit/27836a16cd229d25413e23d7d14ebe2678385121
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
M llvm/test/CodeGen/AMDGPU/debug-value.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/max-sgprs.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll
M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/different-addrspace-addressing-mode-loops.ll
Log Message:
-----------
AMDGPU: Migrate uniform target-cpu attribute tests to subarch triple (55) (#209815)
Commit: 96a722a0ace661626d071166635728def97f6820
https://github.com/llvm/llvm-project/commit/96a722a0ace661626d071166635728def97f6820
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-flat-scratch-init-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-intrinsic-missing-nocallback.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-min-agpr-alloc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-nocallback-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-trap-leaf.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll
M llvm/test/CodeGen/AMDGPU/attributor-wwm.ll
M llvm/test/CodeGen/AMDGPU/issue120256-annotate-constexpr-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-constexpr-alias.ll
M llvm/test/CodeGen/AMDGPU/propagate-amdgpu-cluster-dims.ll
Log Message:
-----------
AMDGPU: Fold -mcpu into subarch triple for attributor tests (56) (#209816)
Commit: 90a2e5010fa88627cd21bd0311833c786be8a213
https://github.com/llvm/llvm-project/commit/90a2e5010fa88627cd21bd0311833c786be8a213
Author: Thurston Dang <thurston at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics-upgrade.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512vl-intrinsics.ll
Log Message:
-----------
[msan] Handle AVX512 mask.compress (#209654)
mask.compress selects elements from the first two operands according to
the mask; thus, we can propagate the shadow by applying the intrinsic to
the input shadows (with the mask unchanged i.e., trailingVerbatimArgs ==
1), using the forceIntegerIntrinsic option that was added in
https://github.com/llvm/llvm-project/pull/207053
Commit: d48f3ca0dc9027fd892336f7b4f046a6c5887c02
https://github.com/llvm/llvm-project/commit/d48f3ca0dc9027fd892336f7b4f046a6c5887c02
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel-system-sgprs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn-codegen.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-globalisel.ll
M llvm/test/CodeGen/AMDGPU/call-encoding.ll
M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global_smrd.ll
M llvm/test/CodeGen/AMDGPU/inline-calls.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-sgmask.ll
M llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll
M llvm/test/CodeGen/AMDGPU/madmk-madak-encoding-size.ll
M llvm/test/CodeGen/AMDGPU/mesa_regression.ll
M llvm/test/CodeGen/AMDGPU/not-scalarize-volatile-load.ll
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-def-after-use.mir
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permlane16_var-op-sel.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-shufflevector.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
M llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll
M llvm/test/CodeGen/AMDGPU/unpack-non-coissue-insts-post-ra-scheduler.mir
M llvm/test/CodeGen/AMDGPU/vgpr-large-tuple-alloc-error.ll
Log Message:
-----------
AMDGPU: Migrate more tests to using subarch triple commands (57) (#209817)
Mostly mechanical updates with some light cleanups manually
applied.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Commit: c40401dd8d28e88519433531c041b0b7e5ada8a9
https://github.com/llvm/llvm-project/commit/c40401dd8d28e88519433531c041b0b7e5ada8a9
Author: Amy Kwan <amy.kwan1 at ibm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Object/GOFFObjectFile.cpp
Log Message:
-----------
[Object][GOFF] Recognize RLD and LEN records (#207118)
This patch adds explicit cases for RT_RLD and RT_LEN records when
parsing GOFF objects. These record types are not handled yet, but
recognizing them allows us to diagnose them and avoids teating them as
unexpected records.
Commit: 9d09c774832bc99cde76ecb4847bb01680da533d
https://github.com/llvm/llvm-project/commit/9d09c774832bc99cde76ecb4847bb01680da533d
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Make VPBlockTy enum protected (NFC) (#209863)
VPBlockTy is an implementation detail, that is only needed in sub-types.
Make protected.
Commit: 0b18869a684febeb4144cd0213cef3163b8cb37e
https://github.com/llvm/llvm-project/commit/0b18869a684febeb4144cd0213cef3163b8cb37e
Author: Sirraide <aeternalmail at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/bindings/python/tests/cindex/test_diagnostics.py
M clang/include/clang/Basic/Diagnostic.td
M clang/include/clang/Basic/DiagnosticIDs.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Basic/DiagnosticIDs.cpp
M clang/lib/Parse/Parser.cpp
M clang/lib/Sema/SemaBase.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaStmt.cpp
M clang/lib/Sema/SemaType.cpp
Log Message:
-----------
[Clang] [Diagnostic] Extend DiagCompat() to C language modes (#209241)
This expands the compatibility warnings infrastructure added in #132348
to support C mode as well. Implementing this was actually fairly
straight-forward because we are only ever in C _or_ C++ mode, i.e.
during a single compilation we either emit only C compatibility warnings
or only C++ compatibility warnings. This means we can simply reuse the
existing code and just check for different LangOpts depending on whether
we're in C or C++ mode.
Concretely, this means that instead of e.g.
```
def ext_c2y_alignof_incomplete_array : Extension<
"'alignof' on an incomplete array type is a C2y extension">,
InGroup<C2y>;
def warn_c2y_compat_alignof_incomplete_array : Warning<
"'alignof' on an incomplete array type is incompatible with C standards "
"before C2y">, InGroup<CPre2yCompat>, DefaultIgnore;
```
you can now simply write
```
defm alignof_incomplete_array : C2yCompat<"'alignof' on an incomplete array type is">;
```
And when emitting the warning(s), code such as
```
Diag(OpLoc, getLangOpts().C2y
? diag::warn_c2y_compat_alignof_incomplete_array
: diag::ext_c2y_alignof_incomplete_array);
```
can now be replaced with
```
DiagCompat(OpLoc, diag_compat::alignof_incomplete_array);
```
I've also migrated the C compatibility warnings in
DiagnosticSemaKinds.td to use the new system to make sure that
everything is working properly.
Commit: 0f494fc6576600f79bbcdb5314fbed6c13da7395
https://github.com/llvm/llvm-project/commit/0f494fc6576600f79bbcdb5314fbed6c13da7395
Author: Vy Nguyen <1762963+oontvoo at users.noreply.github.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/CodeGen/CGExpr.cpp
M clang/test/CodeGen/amdgpu-builtin-is-invocable.c
M clang/test/CodeGen/amdgpu-builtin-processor-is.c
M clang/test/CodeGen/attr-nomerge.cpp
A clang/test/CodeGen/builtin-trap.c
M clang/test/CodeGen/pr53127.cpp
M clang/test/CodeGenCXX/microsoft-abi-byval-vararg.cpp
M clang/test/CodeGenCXX/microsoft-vector-deleting-dtors2.cpp
M clang/test/CodeGenCXX/trap-fnattr.cpp
M clang/test/CodeGenCXX/vararg-non-pod.cpp
M clang/test/DebugInfo/CXX/verbose-trap.cpp
M clang/test/Headers/gpuintrin.c
M clang/test/OpenMP/spirv_target_codegen_noexceptions.cpp
M compiler-rt/test/profile/gcov-__gcov_flush-terminate.c
Log Message:
-----------
[codegen]Ensure __builtin_trap() has an unreachable (#197789)
```
void test2() {
__builtin_trap();
}
```
Previously, this would generate this:
```
; Function Attrs: mustprogress noinline nounwind optnone uwtable
define dso_local void @test2()() #2 !dbg !14 {
call void @llvm.trap(), !dbg !15
ret void, !dbg !16
}
```
Now we'll have `unreachable` after the trap
```
; Function Attrs: noinline nounwind optnone uwtable
define dso_local void @test2() #0 {
call void @llvm.trap()
unreachable
}
```
Commit: 23ead65310da314ae04a1c30137f279beaac1a4f
https://github.com/llvm/llvm-project/commit/23ead65310da314ae04a1c30137f279beaac1a4f
Author: Patrik Dokoupil <61749375+pdokoupil at users.noreply.github.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_common_syscalls.inc
A compiler-rt/test/msan/Linux/syscalls_setgroups.cpp
Log Message:
-----------
[compiler-rt][sanitizer_common] Fix setgroups syscall pre-hook to check its input (#209207)
# About
`PRE_SYSCALL(setgroups)`/`setgroups16` called `POST_WRITE` on their
`grouplist` argument, but grouplist is a read-only input the kernel
never writes. Under MSan, `POST_WRITE` maps to `__msan_unpoison`, so
annotating a raw setgroups(2) via the documented
`__sanitizer_syscall_pre_setgroups` hook silently marked an
uninitialized group list as initialized -- before the syscall even ran,
and even on failure -- masking a real use-of-uninitialized-value bug.
Under TSan it recorded a write range where a read belongs.
Use PRE_READ, matching every other input-only argument in this file
(e.g. sched_setparam). Add an MSan regression test.
Commit: 09599503b1314a0394e57adbd6279d9a220bfdb8
https://github.com/llvm/llvm-project/commit/09599503b1314a0394e57adbd6279d9a220bfdb8
Author: Arda Serdar Pektezol <arda at pektezol.dev>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
A llvm/test/Transforms/LowerTypeTests/icall-branch-funnel-invalid-operand.ll
Log Message:
-----------
[LowerTypeTests] Avoid null dereference on invalid branch funnel operand (#204951)
On the linked issue, a null dereference happens when looping over`
ArrayRef<GlobalTypeMember *> Globals` at
`LowerTypeTestsModule::buildBitSetsFromDisjointSet()`. This stems from
the external globals in the IR which don't enter GlobalTypeMembers.
Following that, operator[] over the DenseMap returns null and it
propagates to the looped over GlobalTypeMember.
Prevent the null dereference via `.find()` and reporting fatal usage
error if it is not present. Add a negative regression test.
Additionally, the LangRef for the `@llvm.icall.branch.funnel` intrinsic
is missing (see #133635). It would also be nice to have a Verifier entry
for this intrinsic, and get rid of most report_fatal_error() in this
file since it's deprecated.
Fixes #191985
---------
Co-authored-by: Vitaly Buka <vitalybuka at google.com>
Commit: ce586b57f4a8e32d47df58dc1b11730f07ffc834
https://github.com/llvm/llvm-project/commit/ce586b57f4a8e32d47df58dc1b11730f07ffc834
Author: Thurston Dang <thurston at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512dq-intrinsics.ll
Log Message:
-----------
[msan] Handle AVX512 fpclass (floating-point classification) for packed double/float (#209652)
Each bit of the classifier constant specifies whether a particular
classifier is enabled. If Classifiers == 0 (no classifiers are enabled),
the output is trivially known to be zero, thus the output is fully
initialized.
Otherwise, each bit of the output is the bitwise OR of one or more
classifications; we approximate each bit of the output shadow based on
whether the corresponding input element is fully initialized (without
which the classification is potentially unknown). This is only
approximate, because some classifications do not rely on all the bits of
the input element.
This patch only handles packed double/single-precision floating-point.
Handling the scalar equivalents is more complicated because those
intrinsics encode a mask.
Commit: 835ae525713e27aa98c46469792cee980669c6ca
https://github.com/llvm/llvm-project/commit/835ae525713e27aa98c46469792cee980669c6ca
Author: Wenju He <wenju.he at intel.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M compiler-rt/lib/asan/asan_interceptors.cpp
Log Message:
-----------
[compiler-rt] Fix asan_interceptors.cpp build warning -Wunused-template (#209750)
mmap_interceptor/munmap_interceptor template functions are instantiated
in sanitizer_common_interceptors.inc only under `#if
SANITIZER_INTERCEPT_MMAP`. Fix `unused function template
'mmap_interceptor'` warning on Windows, which is error under -Werror.
Commit: 7021b428656d283626e9ab3c1a81795c1f6c7086
https://github.com/llvm/llvm-project/commit/7021b428656d283626e9ab3c1a81795c1f6c7086
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/induction-nowrap-from-scev-not-ir.ll
M llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-wrapping.ll
Log Message:
-----------
[ConstraintElim] Try to get induction step/start/flags from IR (NFC-ish) (#209284)
Handle the common integer inductions where the increment is plain add
PN, C by looking at IR instead of querying SCEV. There's effectively no
re-use between SCEV expression created in ConstraintElimination, and
handling simple cases in IR can avoid unnecessary, expensive SCEV
queries.
Should be NFC-ish. We miss trivial folding of the start value (see
regressed test), but that should not happen in end-to-end pipeline.
Improves compile-time for some workloads, ClamAV, mafft:
https://llvm-compile-time-tracker.com/compare.php?from=b8ba3c2b72cb53268129bbecfeb4ba7ec5b8d831&to=2bede223d3ec3ed6e2e9654b635258c50e4e90df&stat=instructions%3Au
I am working on follow-up changes that will handle more cases, where
avoiding unnecessary queries will be more important.
PR: https://github.com/llvm/llvm-project/pull/209284
Commit: 85204d0bce5b24fba24baa0b440b051b6d040f4c
https://github.com/llvm/llvm-project/commit/85204d0bce5b24fba24baa0b440b051b6d040f4c
Author: Paul Kirth <paulkirth at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M libcxx/test/libcxx/atomics/builtin_clear_padding.pass.cpp
Log Message:
-----------
[libcxx] Mark test unsupported in clang-24 (#209794)
After the version bump, we started seeing this test fail. For now mark
it unsupported in newer LLVM versions, until the underlying issue can be
addressed. More details can be found in #209787.
Commit: 5c0dfced1adc55429e32b1db08570abd3a219d85
https://github.com/llvm/llvm-project/commit/5c0dfced1adc55429e32b1db08570abd3a219d85
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/test/AST/ByteCode/builtin-object-size.cpp
Log Message:
-----------
[clang][bytecode] Fix tail padding with __builtin_object_size (#209771)
This fixes the new libcxx/atomics/builtin_clear_padding.pass.cpp
Commit: 50f2b9443d23eba757c3c0f42eef71e0f9721b15
https://github.com/llvm/llvm-project/commit/50f2b9443d23eba757c3c0f42eef71e0f9721b15
Author: David Green <david.green at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-bf16.ll
R llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc-bf16.ll
A llvm/test/CodeGen/AArch64/sve-fixed-length-fp-trunc-bf16.ll
Log Message:
-----------
[AArch64] Lower fixed width bf16 fpround (#209411)
Similar to #209194, this was previously hitting an error with an illegal
FP_ROUND_MERGE_PASSTHRU. This time we lower the fptrunc to a scalable
fptrunc and let it legalize naturally. On SVE systems a f64->bf16
fptrunc will fail to legalize, but lowers successfully with sve2 with
fcvtn. A store(fptrunc) -> truncstore combine was disabled too as it
fails with bf16.
Commit: ebd969054197c4767b0f47db0370ed26ac04c990
https://github.com/llvm/llvm-project/commit/ebd969054197c4767b0f47db0370ed26ac04c990
Author: Thurston Dang <thurston at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
Log Message:
-----------
[msan][NFCI] Add maybe_unused annotation for #209652 (#209878)
Fix compile error for non-assertion builds
(https://lab.llvm.org/buildbot/#/builders/228/builds/4987) after #209652
Commit: 03e3a6273adc16450c814a68444c1ca9e9768ce3
https://github.com/llvm/llvm-project/commit/03e3a6273adc16450c814a68444c1ca9e9768ce3
Author: Augusto Noronha <anoronha at apple.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lldb/source/Plugins/LanguageRuntime/CPlusPlus/CPPLanguageRuntime.cpp
Log Message:
-----------
[lldb] Skip the prologue before reading `this` when stepping into std::function (#209629)
Commit 40152b8 broke CPPLanguageRuntime::GetStepThroughTrampolinePlan by
changing operator() from a multi-line function to a single line
function.
This used to work by accident, because the fallback step-in plan first
advanced past the prologue and the trampoline detection was re-invoked
there with a valid `this`. Once operator() became a one-line inline
definition that intermediate step no longer happened.
Run past the prologue when stopped at the function entry and let the
step-through machinery re-invoke the plan, so the thread plan has a
valid `this` to read from.
Commit: 77e9b8cc155911b5a1378b20cd5e98784ab8a365
https://github.com/llvm/llvm-project/commit/77e9b8cc155911b5a1378b20cd5e98784ab8a365
Author: Vijay Kandiah <vkandiah at nvidia.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Lower/CUDA/cuda-implicit-managed-alloc.cuf
Log Message:
-----------
[flang][cuda] Skip implicit managed/unified attribution for COMMON objects (#209855)
Objects in Fortran `COMMON` blocks may not carry `ATTRIBUTES(MANAGED)`
or `ATTRIBUTES(UNIFIED)`. The implicit attribution added in
[#209292](https://github.com/llvm/llvm-project/pull/209292) did not
account for this, causing a spurious semantic error when a pointer in a
`COMMON` block was implicitly attributed. This change adds a
`!object->commonBlock()` guard to `SetImplicitCUDADataAttr` so that
COMMON members are left unattributed.
Commit: 2cffd1922d06ec79f3c602c4434280450f50f8ba
https://github.com/llvm/llvm-project/commit/2cffd1922d06ec79f3c602c4434280450f50f8ba
Author: zhijian lin <zhijian at ca.ibm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Log Message:
-----------
[NFC][PowerPC] Delete redundant ISD::TRUNCATE from setTargetDAGCombine (#200902)
there is
```
setTargetDAGCombine({ISD::TRUNCATE, ISD::VECTOR_SHUFFLE});
if (Subtarget.useCRBits()) {
setTargetDAGCombine({ISD::TRUNCATE, ISD::SETCC, ISD::SELECT_CC}); }
```
we do not need to set the (ISD::TRUNCATE again when
Subtarget.useCRBits()
Commit: cf293b069a6a1938bcef9271b04b6abc9e3292f8
https://github.com/llvm/llvm-project/commit/cf293b069a6a1938bcef9271b04b6abc9e3292f8
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M .github/new-prs-labeler.yml
A clang/docs/AMDGPUSupport.md
R clang/docs/AMDGPUSupport.rst
A clang/docs/APINotes.md
R clang/docs/APINotes.rst
A clang/docs/AllocToken.md
R clang/docs/AllocToken.rst
A clang/docs/BoundsSafety.md
R clang/docs/BoundsSafety.rst
A clang/docs/BoundsSafetyAdoptionGuide.md
R clang/docs/BoundsSafetyAdoptionGuide.rst
A clang/docs/BoundsSafetyImplPlans.md
R clang/docs/BoundsSafetyImplPlans.rst
A clang/docs/CIR/index.md
R clang/docs/CIR/index.rst
A clang/docs/CXXTypeAwareAllocators.md
R clang/docs/CXXTypeAwareAllocators.rst
A clang/docs/ClangPlugins.md
R clang/docs/ClangPlugins.rst
A clang/docs/CommandGuide/index.md
R clang/docs/CommandGuide/index.rst
A clang/docs/ControlFlowIntegrity.md
R clang/docs/ControlFlowIntegrity.rst
A clang/docs/DebuggingCoroutines.md
R clang/docs/DebuggingCoroutines.rst
A clang/docs/ExternalClangExamples.md
R clang/docs/ExternalClangExamples.rst
A clang/docs/FAQ.md
R clang/docs/FAQ.rst
A clang/docs/IntroductionToTheClangAST.md
R clang/docs/IntroductionToTheClangAST.rst
A clang/docs/LibClang.md
R clang/docs/LibClang.rst
A clang/docs/LibFormat.md
R clang/docs/LibFormat.rst
A clang/docs/LibTooling.md
R clang/docs/LibTooling.rst
A clang/docs/RISCVSupport.md
R clang/docs/RISCVSupport.rst
A clang/docs/Tooling.md
R clang/docs/Tooling.rst
Log Message:
-----------
[docs] Rename selected Clang docs to Markdown (#209281)
Tracking issue: https://github.com/llvm/llvm-project/issues/201242
Migration guide docs:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
RFC:
https://discourse.llvm.org/t/rfc-make-myst-markdown-the-llvm-docs-format-rip-rest/90840
This is the initial straight rename commit. It will probably break the
docs build, but it has to be a separate PR for blame preservation
purposes.
Commit: 1514df333358c221db20f841ecdbcc217409e89f
https://github.com/llvm/llvm-project/commit/1514df333358c221db20f841ecdbcc217409e89f
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/docs/AMDGPUSupport.md
M clang/docs/APINotes.md
M clang/docs/AllocToken.md
M clang/docs/BoundsSafety.md
M clang/docs/BoundsSafetyAdoptionGuide.md
M clang/docs/BoundsSafetyImplPlans.md
M clang/docs/CIR/index.md
M clang/docs/CXXTypeAwareAllocators.md
M clang/docs/ClangPlugins.md
M clang/docs/CommandGuide/index.md
M clang/docs/ControlFlowIntegrity.md
M clang/docs/DebuggingCoroutines.md
M clang/docs/ExternalClangExamples.md
M clang/docs/FAQ.md
M clang/docs/IntroductionToTheClangAST.md
M clang/docs/LibClang.md
M clang/docs/LibFormat.md
M clang/docs/LibTooling.md
M clang/docs/RISCVSupport.md
M clang/docs/Tooling.md
Log Message:
-----------
[docs] Rewrite selected Clang docs to Markdown (#209283)
Tracking issue: https://github.com/llvm/llvm-project/issues/201242
Migration guide docs:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
RFC:
https://discourse.llvm.org/t/rfc-make-myst-markdown-the-llvm-docs-format-rip-rest/90840
This was prepared with rst2myst plus LLM-assisted cleanup. I paged
through all the generated HTML looking for migration artifacts, and all
of the differences I could find appear to be formatting error
corrections.
I noticed that there is a large block of literal rst text in APINotes.md, but I will defer that for later cleanup.
Commit: b1cf1e5719c4673fc464083a8e93a585497a9f8b
https://github.com/llvm/llvm-project/commit/b1cf1e5719c4673fc464083a8e93a585497a9f8b
Author: Mircea Trofin <mtrofin at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/IR/FixedMetadataKinds.def
M llvm/lib/IR/Globals.cpp
M llvm/lib/Transforms/IPO/FunctionImport.cpp
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
M llvm/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp
M llvm/lib/Transforms/Utils/AssignGUID.cpp
M llvm/lib/Transforms/Utils/CloneModule.cpp
Log Message:
-----------
[NFC] rename `MD_unique_id` to `MD_guid` for consistency (#209880)
Commit: 195991885bce0b232b4f5aab16ff87d34473f464
https://github.com/llvm/llvm-project/commit/195991885bce0b232b4f5aab16ff87d34473f464
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/test/CIR/CodeGenBuiltins/builtin-call.cpp
M clang/test/CIR/CodeGenHLSL/matrix-element-expr-load.hlsl
Log Message:
-----------
[CIR] Fix a pair of CIR Build failures: (#209896)
HLSL added a bunch of diagnostics for entry functions that messed with
the matrix test, see here:
https://github.com/llvm/llvm-project/pull/184892/
The solution is to just mark the test as a library triple.
Builtin-trap stopped translating in classic codegen, so the call after
it is now missing (and there is an unreachable after it),w hich actually
better matches our behavior see:
https://github.com/llvm/llvm-project/pull/197789
This patch fixes both tests.
Commit: bfcea5d5f5c36097963c338b3609aee93242a573
https://github.com/llvm/llvm-project/commit/bfcea5d5f5c36097963c338b3609aee93242a573
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
Log Message:
-----------
[VPlan] Add VPlan print test for expanding SCEV with AddRec (NFC). (#209886)
Commit: 1ffd509c4b109fd894f67b2f1d8159d281e0f13a
https://github.com/llvm/llvm-project/commit/1ffd509c4b109fd894f67b2f1d8159d281e0f13a
Author: Nikhil Kalra <nikhil.kalra at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.cpp
M llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.h
Log Message:
-----------
[TableGen][GISel] Fix Matcher Creation for C++23 libc++ (#209783)
libc++ in C++23 mode evaluates make_unique eagerly, which requires
InstructionMatcher to be defined at the constexpr call to make_unique.
Currently, it's defined later in the file.
This patch moves the call to make_unique to the C++ file so that
InstructionMatcher is fully defined at time of instantiation.
Commit: c63bfe581cad89409e711a4c62fbf3de6cd42b40
https://github.com/llvm/llvm-project/commit/c63bfe581cad89409e711a4c62fbf3de6cd42b40
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang/include/flang/Support/Fortran-features.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Support/Fortran-features.cpp
M flang/test/Lower/CUDA/cuda-init.cuf
M flang/tools/bbc/bbc.cpp
Log Message:
-----------
[flang][cuda] Decouple CUFInit from CUDA language features (#209846)
In some cases, we do not want to emit the CUFInit function in the main.
Add a specific language feature for it so we can decouple it.
Commit: e5c19b0ebc54206348273fc2f7cf67cb195908ed
https://github.com/llvm/llvm-project/commit/e5c19b0ebc54206348273fc2f7cf67cb195908ed
Author: nitro <nitro123 at outlook.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M bolt/lib/Core/BinaryContext.cpp
A bolt/test/X86/jump-table-failed-reanalysis.s
Log Message:
-----------
[BOLT] Skip function instead of aborting on jump table analysis failure (#206742)
`analyzeJumpTable()` runs twice on a candidate jump table: once from
`analyzeMemoryAt` while the referencing function is being disassembled,
and
again from `populateJumpTables()` after disassembly. The second run is
stricter,
because the check that an entry points at an instruction
(`getInstructionAtOffset`) only fires once the target function reaches
the
`Disassembled` state. A table can therefore be accepted the first time
and
rejected the second -- for instance when an entry lands at an address
with no
instruction (a symbol whose declared size is larger than its
disassembled
extent). `populateJumpTables()` reached `llvm_unreachable("jump table
heuristic
failure")` and aborted in that case.
Handle it the way BOLT already handles indirect branches it can't
analyze: drop
the table and skip the owning function(s) via `addFragmentsToSkip()`.
The
`JumpTable` is deliberately left in the maps so it is still freed by
`~BinaryContext` (an earlier attempt at this, 52cd00ca, was reverted in
468d4f6d
because it erased the table without deallocating it).
New test `jump-table-failed-reanalysis.s` builds such a table; before
this change
BOLT aborts, after it the function is skipped and the rest of the binary
is
processed normally.
Commit: f7c4b05863cd9ffdcedf95c03480f1e6198c9bb7
https://github.com/llvm/llvm-project/commit/f7c4b05863cd9ffdcedf95c03480f1e6198c9bb7
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang-rt/lib/runtime/cudadevice.f90
Log Message:
-----------
[flang][cuda] Add PURE to time intrinsic so it can be used in DO CONCURRENT (#209901)
Commit: 1b5eb9b48dddd17b88f61f4718db357fbd2f8ed4
https://github.com/llvm/llvm-project/commit/1b5eb9b48dddd17b88f61f4718db357fbd2f8ed4
Author: Schrodinger ZHU Yifan <yfzhu at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M libc/config/baremetal/aarch64/entrypoints.txt
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/src/__support/freelist_heap.h
M libc/src/stdlib/CMakeLists.txt
M libc/src/stdlib/baremetal/CMakeLists.txt
A libc/src/stdlib/baremetal/malloc_usable_size.cpp
A libc/src/stdlib/malloc_usable_size.h
M libc/test/src/__support/freelist_heap_test.cpp
Log Message:
-----------
[libc][baremetal] expose `malloc_usable_size` from freelist heap (#208337)
Expose the `malloc_usable_size` API by reconstruct the `BlockRef` from a
pointer to the head of user payload. The operation is cheap as we only
do a query to the block header to obtain the metadata.
Assisted-by: Gemini based automation tools (human-in-the-loop)
Commit: 18d2b47a0d3b6bb5d55260e69bf51c47de8e0dc6
https://github.com/llvm/llvm-project/commit/18d2b47a0d3b6bb5d55260e69bf51c47de8e0dc6
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/MC/MCObjectFileInfo.h
Log Message:
-----------
[NFC] Remove unused MCObjectFileInfo methods (#209906)
Commit: ba2be3f8add2e63266686cb1bcd40c9fab07de7b
https://github.com/llvm/llvm-project/commit/ba2be3f8add2e63266686cb1bcd40c9fab07de7b
Author: Kewen Meng <Kewen.Meng at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M offload/test/lit.cfg
Log Message:
-----------
[Offload][AMDGPU] Make compiler-rt libs visible (#209849)
Fixed the failure in offload test after
https://github.com/llvm/llvm-project/pull/209765
Commit: b6059b6ce21886c3f8644355ae9017cf3ba04aad
https://github.com/llvm/llvm-project/commit/b6059b6ce21886c3f8644355ae9017cf3ba04aad
Author: Sam Elliott <aelliott at qti.qualcomm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
M llvm/lib/CodeGen/EarlyIfConversion.cpp
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/lib/CodeGen/TargetInstrInfo.cpp
M llvm/lib/CodeGen/TargetSchedule.cpp
M llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/X86/X86CmovConversion.cpp
A llvm/test/CodeGen/RISCV/sched-model-load-latency.ll
A llvm/test/CodeGen/RISCV/sched-model-mispredict-penalty.ll
Log Message:
-----------
[MCSched] Allow tuning LoadLatency/MispredictPenalty (#203139)
This means an existing scheduling model can be tweaked at runtime to
support an unknown processor rather than adding an entirely new model.
This is done with TargetSubtargetInfo so that specific targets can
override the relevant callbacks and the mechanism can eventually work
with LTO.
Commit: 670841415d3d5d1f85eb5859096880678967fd4e
https://github.com/llvm/llvm-project/commit/670841415d3d5d1f85eb5859096880678967fd4e
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_breakpointLocations.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_logpoints.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setBreakpoints.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setExceptionBreakpoints.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setFunctionBreakpoints.py
Log Message:
-----------
[lldb-dap] Migrate lldb-dap tests in `lldb-dap/breakpoint` (#208166)
migrate breakpointLocations, logpoints, setBreakpoints
exceptionBreakpoints and functionBreakpoints test
Commit: f9bda52e57a759d20224cd581f73f61ee3220e74
https://github.com/llvm/llvm-project/commit/f9bda52e57a759d20224cd581f73f61ee3220e74
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/test/CodeGen/X86/bmi.ll
M llvm/test/CodeGen/X86/bmi2.ll
Log Message:
-----------
[X86][APX] Add EVEX BMI opcodes to isDefConvertible (#209699)
To remove redundant test instructions.
Fixes: #207912
Assisted-by: Claude Sonnet 4.6
Commit: ff1a4d3c197c6210941caaa639edfa722fc8896c
https://github.com/llvm/llvm-project/commit/ff1a4d3c197c6210941caaa639edfa722fc8896c
Author: David Zbarsky <dzbarsky at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
A llvm/test/TableGen/CodeEmitterBaseEncodingPool.td
M llvm/test/TableGen/HwModeEncodeAPInt.td
M llvm/utils/TableGen/CodeEmitterGen.cpp
Log Message:
-----------
[TableGen] Pool duplicate code-emitter base encodings (#202619)
Pool duplicate multiword instruction base encodings across the default
encoding table and all hardware-mode encoding tables as unique `APInt`
rows, then emit a pointer-free fixed-width `uint64_t` row table and one
smallest-width opcode-to-row index table per mode. Use the pooled
representation only when the combined values and indices are smaller
than the original tables.
On a Release build, the AMDGPU base-encoding payload shrinks by 440,888
bytes, `llvm-mc` and `llc` each shrink by 445,632 bytes, and the LLVM
driver shrinks by 429,120 bytes.
All 421 TableGen tests passed.
Work towards #202616
AI tool disclosure: Co-authored with OpenAI Codex.
Commit: 2ac025b406e9b62ca3ae0af42a3d9d5dc649c234
https://github.com/llvm/llvm-project/commit/2ac025b406e9b62ca3ae0af42a3d9d5dc649c234
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/CodeGen/CodeGenFunction.cpp
Log Message:
-----------
Make Multiversion Function Resolvers set CurFn (#209918)
Commit #197789 manages to try to reference CurFn while generating a
trap, which some of the multiversion resolvers do. This patch makes sure
we set it to the resolver so we are inserting stuff into the right
places.
This somewhat shockingly causes no tests to fail, but it SHOULD stop the
UBSan failures.
Commit: f020acfd395d9094303e78c807bc168a46a783fa
https://github.com/llvm/llvm-project/commit/f020acfd395d9094303e78c807bc168a46a783fa
Author: Fei Peng <pengfei.02 at bytedance.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M compiler-rt/lib/tsan/rtl/tsan_platform.h
M compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp
Log Message:
-----------
[tsan] Add 47-bit VMA mapping for linux/aarch64 (#205949)
Add 47-bit VMA mapping to support TSan on the latest Android
emulator(16kb page size and 47 va bits).
Fixes https://github.com/llvm/llvm-project/issues/151931
Android kernel config:
https://android.googlesource.com/kernel/build/+/refs/heads/main-kernel-2026/kleaf/impl/defconfig/arm64_16k_defconfig#6
Commit: d4676e649ba86d7c389e1afe6d9ed4d8443e23ef
https://github.com/llvm/llvm-project/commit/d4676e649ba86d7c389e1afe6d9ed4d8443e23ef
Author: Henrik G. Olsson <hnrklssn at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/test/AST/ByteCode/builtin-object-size.cpp
Log Message:
-----------
[clang][bytecode] long double on arm64 darwin is 8 bytes (NFC) (#209930)
This test was failing on arm64 darwin targets. Generalise the #if so
that the win32 branch is also taken by arm64 darwin.
rdar://182340494
Commit: 047f12725a95425195f96b246300e782808322a3
https://github.com/llvm/llvm-project/commit/047f12725a95425195f96b246300e782808322a3
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M lldb/test/API/tools/lldb-dap/io/TestDAP_io.py
M lldb/test/API/tools/lldb-dap/launch/io/DAP_launch_io.py
M lldb/test/API/tools/lldb-dap/launch/io/TestDAP_launch_io_integratedTerminal.py
M lldb/test/API/tools/lldb-dap/launch/io/TestDAP_launch_io_internalConsole.py
M lldb/test/API/tools/lldb-dap/launch/io/main.cpp
Log Message:
-----------
[lldb-dap] Migrate DAP io tests. (#209538)
the launch_io* tests now allow testing args, input, and environment
together.
Previously, these test configurations were mutually exclusive. They are
now combined, removing the need to create a separate test for each input
source.
Migrated Tests:
- TestDAP_io.py
- TestDAP_launch_io_integratedTerminal.py
- TestDAP_launch_io_internalConsole.py
Commit: cc79c8cdc4e7f0a8a968e1d8c5b91b14ce1e183a
https://github.com/llvm/llvm-project/commit/cc79c8cdc4e7f0a8a968e1d8c5b91b14ce1e183a
Author: Jianjian Guan <jacquesguan at me.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVMIR.cpp
A clang/test/CIR/CodeGenBuiltins/RISCV/riscv-zihintntl.c
Log Message:
-----------
[CIR][RISCV] Support Zihintntl builtins (#205468)
Include __builtin_riscv_ntl_load and __builtin_riscv_ntl_store.
Commit: 071b86797f62e827bf18e83667b0d1875a5ee446
https://github.com/llvm/llvm-project/commit/071b86797f62e827bf18e83667b0d1875a5ee446
Author: yingopq <115543042+yingopq at users.noreply.github.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
A llvm/test/CodeGen/Mips/fake-use.ll
Log Message:
-----------
[Mips] Did not put fake_use into delay slot (#201537)
When compiling with -fextend-variable-liveness, the compiler generates FAKE_USE instructions that are not handled by the Mips assembly printer. This causes a fatal error: "Unsupported instruction : <MCInst 44 >" when using clang with -target mipsel-gnu-linux -Og.
The issue occurs because MipsDelaySlotFiller attempts to process FAKE_USE instructions (which are meta instructions) when searching for instructions to fill delay slots, eventually leading to the assembly printer trying to emit an unsupported instruction.
This patch fixes the crash by treating meta instructions (including FAKE_USE) the same way as debug instructions in the delay slot filler's searchRange function. Meta instructions should be skipped during delay slot filling.
Specifically, the fix:
1.Moves the terminateSearch check before debug/meta instruction checks to ensure proper search termination.
2.Adds isMetaInstruction() check alongside existing isDebugInstr() and isJumpTableDebugInfo() checks.
Fix #198835.
Commit: 1f9891c05cd1faa3c1d27af444180fe2cb5f7786
https://github.com/llvm/llvm-project/commit/1f9891c05cd1faa3c1d27af444180fe2cb5f7786
Author: Sam Elliott <aelliott at qti.qualcomm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/MC/MCSchedule.h
Log Message:
-----------
[MCSchedule][NFC] Use constexpr for static constants (#209934)
Hopefully fixes a compilation error seen in llvm/llvm-project#203139.
Commit: 31b3a0ab54e21a5d38fa83bdcce3e3aa07e2cb1e
https://github.com/llvm/llvm-project/commit/31b3a0ab54e21a5d38fa83bdcce3e3aa07e2cb1e
Author: Jianjian Guan <jacquesguan at me.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/test/Dialect/EmitC/invalid_ops.mlir
M mlir/test/Dialect/EmitC/ops.mlir
M mlir/test/Target/Cpp/common-cpp.mlir
Log Message:
-----------
[mlir][emitc] Add increment and decrement ops (#208648)
Commit: 503c44707051a2c1b804013e40c26714030dfc18
https://github.com/llvm/llvm-project/commit/503c44707051a2c1b804013e40c26714030dfc18
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/ADT/GenericCycleImpl.h
M llvm/include/llvm/ADT/GenericCycleInfo.h
M llvm/lib/Transforms/Utils/FixIrreducible.cpp
Log Message:
-----------
[CycleInfo] Drop GraphTraits and df_iterator. NFC (#209847)
depth_first uses SmallPtrSet visited-set, which is pure overhead on a
tree. Replace them with explicit child-stack walks and delete the unused
GraphTraits specializations to prevent misuse.
Commit: fc77e9da83e7b850edc336d1d6c4e4c50ff8ac43
https://github.com/llvm/llvm-project/commit/fc77e9da83e7b850edc336d1d6c4e4c50ff8ac43
Author: Haohai Wen <haohai.wen at intel.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/include/llvm/ObjectYAML/COFFYAML.h
M llvm/include/llvm/ObjectYAML/yaml2obj.h
M llvm/lib/ObjectYAML/COFFEmitter.cpp
M llvm/lib/ObjectYAML/yaml2obj.cpp
A llvm/test/tools/yaml2obj/COFF/output-limit.yaml
M llvm/tools/yaml2obj/yaml2obj.cpp
Log Message:
-----------
[yaml2obj] Apply output size limit to COFF (#209695)
Route the yaml2obj max-size setting through the COFF emitter and
buffer COFF output with ContiguousBlobAccumulator. This rejects
oversized YAML descriptions consistently with ELF.
Commit: bedbc79101106c143bfee9049ba74317dfa8b417
https://github.com/llvm/llvm-project/commit/bedbc79101106c143bfee9049ba74317dfa8b417
Author: Luke Lau <luke at igalia.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Inline EVL pattern into single match call in optimizeLatchExitInductionUser. NFC (#209953)
This was waiting on m_HeaderMask to be introduced at the time it was
added.
Commit: 48607d29847349a617d4416c7be820032881a5a0
https://github.com/llvm/llvm-project/commit/48607d29847349a617d4416c7be820032881a5a0
Author: sohail <sohailraj.satapathy at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/headers/stdfix.rst
M libc/include/stdfix.yaml
M libc/src/__support/fixed_point/CMakeLists.txt
M libc/src/__support/fixed_point/fx_bits.h
M libc/src/__support/fixed_point/fx_rep.h
M libc/src/stdfix/CMakeLists.txt
A libc/src/stdfix/divik.cpp
A libc/src/stdfix/divik.h
A libc/src/stdfix/divilk.cpp
A libc/src/stdfix/divilk.h
A libc/src/stdfix/divilr.cpp
A libc/src/stdfix/divilr.h
A libc/src/stdfix/divir.cpp
A libc/src/stdfix/divir.h
A libc/src/stdfix/diviuk.cpp
A libc/src/stdfix/diviuk.h
A libc/src/stdfix/diviulk.cpp
A libc/src/stdfix/diviulk.h
A libc/src/stdfix/diviulr.cpp
A libc/src/stdfix/diviulr.h
A libc/src/stdfix/diviur.cpp
A libc/src/stdfix/diviur.h
M libc/test/src/stdfix/CMakeLists.txt
A libc/test/src/stdfix/DiviFxTest.h
A libc/test/src/stdfix/divik_test.cpp
A libc/test/src/stdfix/divilk_test.cpp
A libc/test/src/stdfix/divilr_test.cpp
A libc/test/src/stdfix/divir_test.cpp
A libc/test/src/stdfix/diviuk_test.cpp
A libc/test/src/stdfix/diviulk_test.cpp
A libc/test/src/stdfix/diviulr_test.cpp
A libc/test/src/stdfix/diviur_test.cpp
Log Message:
-----------
[libc][stdfix] Implement divifx functions in LLVM libc (#206115)
Fixes #129124
Commit: 0216376fc192256a434d9eeb5c2782cdbdcdb1f6
https://github.com/llvm/llvm-project/commit/0216376fc192256a434d9eeb5c2782cdbdcdb1f6
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/cxx11.cpp
Log Message:
-----------
[clang][bytecode] Diagnose pointer subtractions of elements of different arrays (#209496)
Commit: 687fbfae778ac2953c35920fb042446ef967c239
https://github.com/llvm/llvm-project/commit/687fbfae778ac2953c35920fb042446ef967c239
Author: Alok Kumar Sharma <AlokKumar.Sharma at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/IPO/MergeFunctions.h
M llvm/lib/Transforms/IPO/MergeFunctions.cpp
A llvm/test/Transforms/MergeFunc/merge-functions-branch-weights.ll
A llvm/test/Transforms/MergeFunc/merge-functions-reordered-blocks-branch-weights.ll
A llvm/test/Transforms/MergeFunc/merge-functions-select-weights.ll
A llvm/test/Transforms/MergeFunc/merge-functions-value-profile.ll
M llvm/unittests/Transforms/IPO/MergeFunctionsTest.cpp
Log Message:
-----------
[MergeFunctions] Preserve instruction-level profile metadata during merging (#208009)
Merge branch weights and value profile metadata when equivalent
functions are folded. Branch weights are relative, so we scale them
to absolute counts via BlockFrequencyInfo before combining. Value
profile counts are already absolute, so we just sum them directly.
Commit: 75403b0b186f492b57bcb64f4a4b1c7716b11d98
https://github.com/llvm/llvm-project/commit/75403b0b186f492b57bcb64f4a4b1c7716b11d98
Author: Kazu Hirata <kazu at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/ADT/Eytzinger.h
M llvm/unittests/ADT/EytzingerTest.cpp
Log Message:
-----------
[ADT] Introduce EytzingerTable (#209343)
This patch introduces EytzingerTable, an owning container that stores
elements in a complete binary search tree formatted in Eytzinger
(breadth-first) order.
EytzingerTable::create is templated on the input container's value type,
allowing heterogeneous table construction such as building an
EytzingerTable<support::ulittle64_t> directly from a vector of native
uint64_t keys.
RFC:
https://discourse.llvm.org/t/rfc-faster-sample-profile-loading/90957/7
Assisted-by: Antigravity
Commit: 6705f3d3d2e6e9a151505375ab567ec82c54a637
https://github.com/llvm/llvm-project/commit/6705f3d3d2e6e9a151505375ab567ec82c54a637
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.h
Log Message:
-----------
[SLP][Modularisation][NFC] Extract commutativity and ordering helpers into SLPUtils 2/3 (#209080)
Please refer to RFC:
https://discourse.llvm.org/t/modularizing-slpvectorizer-cpp/90922
Move into SLPVectorizer/SLPUtils.{h,cpp} (namespace
llvm::slpvectorizer):
- UsesLimit (constant)
- isCommutative(Instruction *, Value *, bool)
- isCommutative(Instruction *) (overload)
- isCommutableOperand
- getNumberOfPotentiallyCommutativeOps
- getElementIndex
- inversePermutation
- reorderScalars
- shortBundleName (debug-only, #if !defined(NDEBUG))
- areAllOperandsNonInsts
- isUsedOutsideBlock
- doesNotNeedToBeScheduled
- doesNotNeedToSchedule
(Please note that the move is intended to be verbatim. I welcome
comments about latents issues/comment changes and any other simple
things but will take them in a separate patch.)
Assisted by Cursor.
Commit: 2b1a6e1857ccedb2f006721412177f4be45581b0
https://github.com/llvm/llvm-project/commit/2b1a6e1857ccedb2f006721412177f4be45581b0
Author: Pranav Kant <prka at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
Fix Bazel build for 48607d2 (#209960)
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=48607d29847349a617d4416c7be820032881a5a0
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: ed0ea836f6cc029b3c8ec9b2308f5e94038dac03
https://github.com/llvm/llvm-project/commit/ed0ea836f6cc029b3c8ec9b2308f5e94038dac03
Author: WMC <tnwilly at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp
M mlir/lib/Dialect/NVGPU/IR/NVGPUDialect.cpp
A mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm-mma-fp8.mlir
Log Message:
-----------
[NVGPU] Add FP8 (e4m3/e5m2) support to nvgpu.mma.sync (#207342)
This PR is stacked on #207307
## Description
Add FP8 E4M3/E5M2 support for `nvgpu.mma.sync`, building on the
NVVM-level
support in #207307. This adds NVGPU verification and lowering support,
registers
the supported `m16n8k16`/`m16n8k32` MMA variants, and adds coverage for
NVGPU
lowering and NVVM verification.
## Test
```sh
mlir-opt mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm-fp8.mlir \
-convert-nvgpu-to-nvvm -split-input-file
```
Co-authored with Claude Sonnet 5
---------
Signed-off-by: weimin023 <tnwilly at gmail.com>
Commit: 745b946cbbf30708044b4a2c4a7726d0c02ca0de
https://github.com/llvm/llvm-project/commit/745b946cbbf30708044b4a2c4a7726d0c02ca0de
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/cxx11.cpp
Log Message:
-----------
Revert "[clang][bytecode] Diagnose pointer subtractions of elements of different arrays" (#209969)
Reverts llvm/llvm-project#209496
Breaks the new virtual-bases.cpp test
Commit: 89a4b2f880a7b852cb9b4ff20a1e38a6b3a037a5
https://github.com/llvm/llvm-project/commit/89a4b2f880a7b852cb9b4ff20a1e38a6b3a037a5
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M libc/hdr/CMakeLists.txt
A libc/hdr/sys_select_macros.h
A libc/hdr/sys_wait_macros.h
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/fd_set.h
A libc/hdr/types/struct_rusage.h
A libc/hdr/types/struct_utsname.h
M libc/src/sys/select/linux/CMakeLists.txt
M libc/src/sys/select/linux/select.cpp
M libc/src/sys/select/select.h
M libc/src/sys/utsname/linux/CMakeLists.txt
M libc/src/sys/utsname/linux/uname.cpp
M libc/src/sys/utsname/uname.h
M libc/src/sys/wait/linux/CMakeLists.txt
M libc/src/sys/wait/wait4.h
M libc/src/sys/wait/wait4Impl.h
M libc/src/unistd/linux/CMakeLists.txt
M libc/src/unistd/linux/gethostname.cpp
Log Message:
-----------
[libc] Replace sys/select.h, sys/utsname.h and sys/wait.h includes with proxy headers (#209851)
I'm replacing system includes of <sys/select.h>, <sys/utsname.h>, and
<sys/wait.h> in non-test and non-proxy code with granular proxy headers.
- add proxy headers for sys/select.h and sys/wait.h macros as well as
fd_set, struct rusage, and struct utsname types
- switch select, uname, gethostname, and wait4 internal headers and
implementations to include the proxy headers instead of system headers
- update cmake dependencies for the affected entry points
Assisted by Gemini.
Commit: 5a530a22fae4aaa41da79779cd56db57f8de55f8
https://github.com/llvm/llvm-project/commit/5a530a22fae4aaa41da79779cd56db57f8de55f8
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M libc/include/llvm-libc-macros/netinet-in-macros.h
M libc/test/include/netinet_in_test.cpp
Log Message:
-----------
[libc] Reimplement IN6_IS_ADDR_* macros using statement expressions (#209772)
This patch fixes three issues with the previous implementation:
- the macro argument was being evaluated more than once
- casting to other types (uint32_t in particular) was an aliasing
violation
- it was casting to non-const pointers, resulting in compiler errors in
cases where the user passes a const ptr.
A statement expression fixes the first issue by using a temporary
variable. The second issue is fixed by using the appropriate members of
struct in6_addr. The last issue is fixed by dropping the cast
completely. This requires the user to pass a correctly types pointer (as
POSIX requires). Implementations keep it for compatibility with old code
passing void * and similar, but a quick survey shows that most modern
code passes the correct types. If this turns out to be an issue, we can
easily add the cast (to a const type) back.
Implementation notes:
- IN6_IS_ADDR_MULTICAST doesn't use the statement expression because the
argument is evaluated only once
- I use private helper macros (__IN6_IS_ADDR_UNSPECIFIED and
__IN6_IS_ADDR_LOOPBACK) so IN6_IS_ADDR_V4COMPAT does not nest statement
expressions
- I considered using private entrypoints (like we do with cpuset macros)
instead of statement expressions, but decided against it because these
macros are simpler and would thus result in a higher
boilerplate-to-useful-code ratio (particularly given our restriction on
calling other entrypoints)
Assisted by Gemini.
Commit: 762941070b1824ba5dc0a6b6a9e8c9dc4b5911e8
https://github.com/llvm/llvm-project/commit/762941070b1824ba5dc0a6b6a9e8c9dc4b5911e8
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M orc-rt/lib/executor/StandaloneMachOUnwindInfoRegistrar.cpp
M orc-rt/lib/executor/Unix/NativeDylibAPIs.inc
M orc-rt/lib/executor/Unix/NativeMemoryAPIs.inc
M orc-rt/lib/executor/sps-ci/MemoryAccessSPSCI.cpp
M orc-rt/test/unit/AllocActionTest.cpp
M orc-rt/test/unit/CompilerTest.cpp
M orc-rt/test/unit/ErrorCAPITest.cpp
M orc-rt/test/unit/ErrorExceptionInteropTest.cpp
M orc-rt/test/unit/ErrorTest.cpp
M orc-rt/test/unit/LockedAccessTest.cpp
M orc-rt/test/unit/QueueingRunnerTest.cpp
M orc-rt/test/unit/RTTITest.cpp
M orc-rt/test/unit/SPSWrapperFunctionTest.cpp
M orc-rt/test/unit/ThreadPoolRunnerTest.cpp
M orc-rt/test/unit/WrapperFunctionBufferTest.cpp
Log Message:
-----------
[orc-rt] Close with "// namespace" consistently. NFC. (#209979)
Commit: ac067a7e1366f1a9fca74b2cb69d6b005c6b732e
https://github.com/llvm/llvm-project/commit/ac067a7e1366f1a9fca74b2cb69d6b005c6b732e
Author: Harrison Hao <57025411+harrisonGPU at users.noreply.github.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-bf16.ll
Log Message:
-----------
[AMDGPU] Use v_pk_add_bf16 for scalar bf16 fadd on gfx1250/gfx13 (#209128)
Targets with packed bf16 instructions can do a scalar bf16 fadd with a
single `v_pk_add_bf16` operating on the low half, instead of promoting
to f32 and going through `v_fma_mix_f32_bf16 + v_cvt_pk_bf16_f32`.
Commit: 76ee189f61dfbe249159ed7e0e772b50b4eb7aeb
https://github.com/llvm/llvm-project/commit/76ee189f61dfbe249159ed7e0e772b50b4eb7aeb
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/IPO/MergeFunctions.h
M llvm/lib/Transforms/IPO/MergeFunctions.cpp
R llvm/test/Transforms/MergeFunc/merge-functions-branch-weights.ll
R llvm/test/Transforms/MergeFunc/merge-functions-reordered-blocks-branch-weights.ll
R llvm/test/Transforms/MergeFunc/merge-functions-select-weights.ll
R llvm/test/Transforms/MergeFunc/merge-functions-value-profile.ll
M llvm/unittests/Transforms/IPO/MergeFunctionsTest.cpp
Log Message:
-----------
Revert "[MergeFunctions] Preserve instruction-level profile metadata during merging" (#209987)
Reverts llvm/llvm-project#208009
Causes unit test failures.
Commit: 4ffab8581b9f35ed3934762aa9b9baf0fd84084f
https://github.com/llvm/llvm-project/commit/4ffab8581b9f35ed3934762aa9b9baf0fd84084f
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
Log Message:
-----------
[Mips] Fix test after #201537 (#209993)
Commit: ab1c8f643667ce85ec11dcfbdadac13e06291ce2
https://github.com/llvm/llvm-project/commit/ab1c8f643667ce85ec11dcfbdadac13e06291ce2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/docs/HIPSupport.md
Log Message:
-----------
clang/HIP: Update documentation for class name (#209992)
Commit: f5dfaa6dc5e85b6fbd4eb9f7eadef3ee010894d8
https://github.com/llvm/llvm-project/commit/f5dfaa6dc5e85b6fbd4eb9f7eadef3ee010894d8
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/test/Transforms/InstCombine/mul.ll
Log Message:
-----------
[InstCombine] Teach takeLog2 log2(X + 1) IIF X[0,1] -> X (#209741)
proof: https://alive2.llvm.org/ce/z/B7WjCg
Commit: 29cf2fb0116d6e13f81913440a41f577d11de664
https://github.com/llvm/llvm-project/commit/29cf2fb0116d6e13f81913440a41f577d11de664
Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/Rematerializer.h
M llvm/lib/CodeGen/Rematerializer.cpp
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/unittests/CodeGen/RematerializerTest.cpp
Log Message:
-----------
[CodeGen] Fine-grained LIS updates on remat and dead-def handling (#202673)
This replaces the rematerializer's manual bulk LIS update paradigm in
favor of an automated fine-grained one that
1. performs LIS updates as rematerializations happen and
2. handles the removal of dead-definitions properly (this replaces the
prior partial handling of live interval splitting).
The new approach should be less error-prone (clients do not have to
periodically update the LIS, which is now up-to-date at all times from
the client's perspective) and faster in general (live intervals aren't
fully re-created every time a def or use of a register changes).
Handling dead-definitions (through a `LiveRangeEditor`) adds some
complexity to the rematerializer since unrematerializable MIs can now
also be deleted. This is exposed to listeners through a new event.
Furthermore, rematerializable registers can now become "permanently
dead" if all their users were unrematerializable MIs that became dead as
a result of other rematerializations.
The combination of these two improvements makes handling live-interval
splitting unnecessary. Rematerializable registers have a single-def by
construction so cannot ever have multiple disconnected components. On
the other hand, if we remove dead definitions as they appear,
unrematerializable registers's live interval cannot become made up of
multiple disconnected components purely as a result of
rematerializations. It is the rematerializer's client responsibility to
ensure that the LIS is in a valid state before the rematerializer
analyses the function.
Commit: 4536b1c44ebb54780f04e1ec992547d70a2d9700
https://github.com/llvm/llvm-project/commit/4536b1c44ebb54780f04e1ec992547d70a2d9700
Author: Mateusz Chudyk <mateusz.chudyk at intel.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/Utils.h
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/combine-fdiv-inlineasm-operand.mir
M llvm/unittests/CodeGen/GlobalISel/GISelUtilsTest.cpp
Log Message:
-----------
[GlobalISel] Fix crash in isConstantOrConstantSplatVectorFP for non-register operands
isConstantOrConstantSplatVectorFP unconditionally accessed operand 0 as
a register, which causes a crash when the instruction is INLINEASM
(whose operand 0 is the asm string, not a register def).
This can happen when matchRepeatedFPDivisor walks the use-def chain of a
G_FDIV operand and reaches an INLINEASM instruction that defines the
dividend.
Commit: 09f8509bec1fec4636c8e592dcd55a80f39f2667
https://github.com/llvm/llvm-project/commit/09f8509bec1fec4636c8e592dcd55a80f39f2667
Author: ilia-cher <30845429+ilia-cher at users.noreply.github.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
M llvm/unittests/Target/AMDGPU/GCNRegPressureTest.cpp
Log Message:
-----------
[AMDGPU] Fix speculative register pressure queries (#208574)
There are two issues with the way we currently speculate register
pressure:
1. GCNDownwardRPTracker::advance(with UseInternalIterator=false), which
is called by the scheduler in schedNode, resets LastTrackedMI, so the
tracker (bumpDownwardPressure) doesn't know where the last scheduled
instruction is and falls back to the beginning of the basic block. As a
result, when we estimate RP impact for a given MI, we tend to find uses
that are often already scheduled and should be skipped.
2. When looking for the remaining uses between LastTrackedMI and the
candidate MI we should skip already scheduled instruction.
Commit: ca6fe413daa538440cf47d4734051e3be7293600
https://github.com/llvm/llvm-project/commit/ca6fe413daa538440cf47d4734051e3be7293600
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/docs/LangRef.md
Log Message:
-----------
[LangRef] State that the memory model is an axiomatic one (#208710)
Currently, one could read large parts of the memory model without learning for
sure whether it is meant as an operational model that describes how individual
operations change some notion of state or if it is an axiomatic model (like the
C++ memory model) that lists constraints that a candidate execution must
satisfy to be allowed.
While the description of what a read returns sounds somewhat operational,
aspects like the definition of fence instructions, the monotonic modification
order, and the total order of sequentially consistent operations place it in
the realm of axiomatic models.
This is an attempt to make the nature of the model more explicit (and maybe a
place to discuss the nature of the model), as suggested by RalfJung in the
reviews for #204329.
Commit: aa199a3bc9d4ecdf87026d4db8dbb52bffa40605
https://github.com/llvm/llvm-project/commit/aa199a3bc9d4ecdf87026d4db8dbb52bffa40605
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
Log Message:
-----------
AMDGPU: Fix creating temporary TTI in AMDGPUCodeGenPrepare (#209976)
This should always be queried from the pass manager
Co-authored-by: Claude (Claude Opus 4.8) <noreply at anthropic.com>
Commit: 2bc2229f40028c66f6fe5956659570b55133035c
https://github.com/llvm/llvm-project/commit/2bc2229f40028c66f6fe5956659570b55133035c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/test/DebugInfo/AMDGPU/bitcast-store-combine-debugloc.ll
M llvm/test/DebugInfo/AMDGPU/cfi.ll
M llvm/test/DebugInfo/AMDGPU/code-pointer-size.ll
M llvm/test/DebugInfo/AMDGPU/dbg-value-sched-crash.ll
M llvm/test/DebugInfo/AMDGPU/debug-loc-copy.ll
M llvm/test/DebugInfo/AMDGPU/dwarfdump-relocs.ll
M llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-cfi-directives.s
M llvm/test/DebugInfo/AMDGPU/pointer-address-space.ll
M llvm/test/DebugInfo/AMDGPU/print-reg-name.s
M llvm/test/DebugInfo/AMDGPU/variable-locations.ll
M llvm/test/DebugInfo/AMDGPU/wqm-wwm-debug-loc.ll
Log Message:
-----------
AMDGPU: Migrate DebugInfo tests to new subarch triples (58) (#209818)
Mostly mechanical by script
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Commit: 0f6a60fd6a2f54e5af99bb5c7c85e794b2ff3841
https://github.com/llvm/llvm-project/commit/0f6a60fd6a2f54e5af99bb5c7c85e794b2ff3841
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/test/CodeGen/MIR/AMDGPU/cfi-pseudos.mir
M llvm/test/CodeGen/MIR/AMDGPU/custom-pseudo-source-values.ll
M llvm/test/CodeGen/MIR/AMDGPU/dead-flag-on-use-operand-parse-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/instr-mmra-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/instr-mmra.mir
M llvm/test/CodeGen/MIR/AMDGPU/killed-flag-on-def-parse-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-min-num-agprs.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-metadata.mir
M llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir
M llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-expect-id.mir
M llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-parse.mir
M llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-undefine-matadata.mir
M llvm/test/CodeGen/MIR/AMDGPU/parse-cfi-unsigned-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-invalid-register-class-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-invalid-register-name-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-mfi.ll
M llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-stack-type-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/ptradd-flags.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_wait_alu-errors.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_wait_alu.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_wait_loadcnt_dscnt-errors.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_wait_loadcnt_dscnt.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_waitcnt-errors.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_waitcnt.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_waitcnt_soft.mir
M llvm/test/CodeGen/MIR/AMDGPU/subreg-def-is-not-ssa.mir
M llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir
M llvm/test/CodeGen/MIR/AMDGPU/virtreg-uses-unallocatable-class.mir
M llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-bad-phys.mir
M llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-bad-split.mir
M llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-self-split.mir
M llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash.mir
Log Message:
-----------
AMDGPU: Migrate MIR parser tests to new subarch triples (59) (#209819)
Mechanical migration by script.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Commit: 041149970208fd709524e3b19c6aff4b41b58813
https://github.com/llvm/llvm-project/commit/041149970208fd709524e3b19c6aff4b41b58813
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/test/tools/llvm-split/AMDGPU/address-taken-externalize-with-call.ll
M llvm/test/tools/llvm-split/AMDGPU/address-taken-externalize.ll
M llvm/test/tools/llvm-split/AMDGPU/declarations.ll
M llvm/test/tools/llvm-split/AMDGPU/indirect-call-inline-asm-debug.ll
M llvm/test/tools/llvm-split/AMDGPU/indirect-call-inline-asm.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-cost-ranking.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependencies.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-duplication.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-external.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-indirect-callee-md.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-indirect.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-overridable.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-global-variables-noexternal.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-global-variables.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-load-balancing.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-no-dependencies.ll
M llvm/test/tools/llvm-split/AMDGPU/large-kernels-merging-weak_odr.ll
M llvm/test/tools/llvm-split/AMDGPU/large-kernels-merging.ll
M llvm/test/tools/llvm-split/AMDGPU/non-kernels-dependencies.ll
M llvm/test/tools/llvm-split/AMDGPU/non-kernels-dependency-indirect.ll
M llvm/test/tools/llvm-split/AMDGPU/preserve-globals.ll
M llvm/test/tools/llvm-split/AMDGPU/recursive-search-2.ll
M llvm/test/tools/llvm-split/AMDGPU/recursive-search-8.ll
Log Message:
-----------
AMDGPU: Use amdgpu triples in llvm-split tests (60) (#209866)
Update by regex
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Commit: dab4c918c2453cc5650563571c35c6949bf5c611
https://github.com/llvm/llvm-project/commit/dab4c918c2453cc5650563571c35c6949bf5c611
Author: roman1741941 <rdivacky at vlakno.cz>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.h
M llvm/utils/TableGen/RegisterBankEmitter.cpp
Log Message:
-----------
[TableGen] Optimize register bank and info emission. (#208297)
Don't go via a BitVector just to a read a single value out of it.
Commit: 88acd428fd72f44312408c3fb6165992fb3b043a
https://github.com/llvm/llvm-project/commit/88acd428fd72f44312408c3fb6165992fb3b043a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/test/Analysis/KernelInfo/enable-kernel-info/amdgpu.test
M llvm/test/Analysis/KernelInfo/flat-addrspace/amdgpu.test
M llvm/test/Analysis/KernelInfo/launch-bounds/amdgpu.ll
M llvm/test/Analysis/KernelInfo/openmp/README.md
M llvm/test/Analysis/KernelInfo/openmp/amdgpu.ll
Log Message:
-----------
AMDGPU: Migrate KernelInfo tests to new subarch triples (61) (#209867)
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Commit: 36d2fb92bcac253e2e1bb20b7ea7b22033027691
https://github.com/llvm/llvm-project/commit/36d2fb92bcac253e2e1bb20b7ea7b22033027691
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.format.i8.xfail.ll
Log Message:
-----------
[AMDGPU] Reject sub-dword format buffer loads and stores (#209703)
An i8 `buffer.{load,store}.format` has no corresponding hardware
instruction so diagnose it in SelectionDAG and fail legalization in
GlobalISel instead of emitting invalid format opcodes
Commit: 65d3601c44632bd0b5b90d559953cbd47442c0e2
https://github.com/llvm/llvm-project/commit/65d3601c44632bd0b5b90d559953cbd47442c0e2
Author: Jesse Huang <jesse.huang at sifive.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td
A llvm/test/CodeGen/RISCV/short-forward-branch-opt-zibi.ll
Log Message:
-----------
[RISC-V] Make Short Forward Branches capable of matching Zibi instructions (#208637)
Add new SFB patterns to make `PseudoCCMOVGPR` capable of matching `beqi`
and `bnei`, so that it can be folded into `PseudoCC*` of `SFBALU_rr`
variants
Commit: 8a77787a526e31f48dd4d6f4cd9d68b982d8b772
https://github.com/llvm/llvm-project/commit/8a77787a526e31f48dd4d6f4cd9d68b982d8b772
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/test/CodeGen/X86/bitcnt-load-with-cmov.ll
R llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt-i64.ll
R llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt.ll
R llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt-i64.ll
R llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt.ll
Log Message:
-----------
Revert "[X86] Remove redundant `cmp` before `adc` after `lzcnt` or `tzcnt`" (#210006)
Reverts #208392 - while we investigate a miscompile due to CF/ZF mismatch
Commit: bf397be011e2cecce6ca0c1d0342eef217a06059
https://github.com/llvm/llvm-project/commit/bf397be011e2cecce6ca0c1d0342eef217a06059
Author: Harrison Hao <57025411+harrisonGPU at users.noreply.github.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/docs/LangRef.md
M llvm/include/llvm/IR/Instructions.h
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/test/Assembler/atomic.ll
A llvm/test/Assembler/invalid-load-store-atomic-elementwise.ll
A llvm/test/Bitcode/atomic-load-store-elementwise.ll
M llvm/test/Bitcode/compatibility.ll
M llvm/unittests/IR/VerifierTest.cpp
Log Message:
-----------
[IR] Add elementwise modifier to atomic loads (#204556)
Add an `elementwise` modifier to atomic loads to represent
per-element atomic semantics for fixed-vector loads.
Without the modifier, a vector atomic load remains a whole-value
atomic operation. With `elementwise`, the load behaves as if it were
expanded into one scalar atomic load per fixed-vector element, without
providing atomicity for the vector value as a whole.
Discussion:
https://discourse.llvm.org/t/rfc-add-elementwise-modifier-to-atomic-loads-and-stores/91100
Commit: 9c6a9f5fa37ffc21d4561301772bc600bd344d4c
https://github.com/llvm/llvm-project/commit/9c6a9f5fa37ffc21d4561301772bc600bd344d4c
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
Log Message:
-----------
[CodeGen][ARM64EC] Copy first four arguments to FP registers in vararg exit thunks (#209581)
ARM64EC vararg functions receive all types of the first four arguments
in x0-x3. Because x86_64 expects floating-point arguments in FP
registers, always copy x0-x3 to d0-d3 in the exit thunks, matching
MSVC's behavior.
Commit: c012610ab9924f465baea5e62397056ea9594567
https://github.com/llvm/llvm-project/commit/c012610ab9924f465baea5e62397056ea9594567
Author: Ben Dunbobbin <Ben.Dunbobbin at sony.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M cross-project-tests/CMakeLists.txt
A cross-project-tests/dtlto/remote-options.test
Log Message:
-----------
[DTLTO] Add remote compiler option forwarding coverage (#208589)
Add a cross-project DTLTO test that checks the existing LTO
configuration state serialized into the remote Clang command line. The
test uses the validate.py distributor to inspect the generated DTLTO
JSON.
Cover all the existing forwarded options.
Add paired negative checks for optional flags so the test also verifies
they are not emitted when the corresponding configuration state is not
set.
Commit: d94df008e71552fe5e07fa789bfa7f097cfdb0d9
https://github.com/llvm/llvm-project/commit/d94df008e71552fe5e07fa789bfa7f097cfdb0d9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/test/tools/llvm-reduce/mir/drop-ir-references.mir
M llvm/test/tools/llvm-reduce/mir/generic-vreg.mir
M llvm/test/tools/llvm-reduce/mir/infer-triple.mir
M llvm/test/tools/llvm-reduce/mir/input-file-does-not-exist.mir
M llvm/test/tools/llvm-reduce/mir/instr-reduce-dead-def.mir
M llvm/test/tools/llvm-reduce/mir/multiple-functions.mir
M llvm/test/tools/llvm-reduce/mir/preserve-block-info.mir
M llvm/test/tools/llvm-reduce/mir/preserve-frame-info.mir
M llvm/test/tools/llvm-reduce/mir/preserve-func-info.mir
M llvm/test/tools/llvm-reduce/mir/preserve-machine-function-info-amdgpu.mir
M llvm/test/tools/llvm-reduce/mir/preserve-max-call-frame-size.mir
M llvm/test/tools/llvm-reduce/mir/preserve-mem-operands.mir
M llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir
M llvm/test/tools/llvm-reduce/mir/reduce-instruction-flags.mir
M llvm/test/tools/llvm-reduce/mir/reduce-instruction-unreachable-block.mir
M llvm/test/tools/llvm-reduce/mir/reduce-register-defs.mir
M llvm/test/tools/llvm-reduce/mir/reduce-register-hints.mir
M llvm/test/tools/llvm-reduce/mir/reduce-register-masks.mir
M llvm/test/tools/llvm-reduce/mir/reduce-register-uses-generic.mir
M llvm/test/tools/llvm-reduce/mir/reduce-register-uses.mir
M llvm/test/tools/llvm-reduce/mir/remove-frame-destroy.mir
M llvm/test/tools/llvm-reduce/mir/subreg-def0.mir
M llvm/test/tools/llvm-reduce/mir/subreg-def1.mir
M llvm/test/tools/llvm-reduce/mir/tracks-reg-liveness.mir
M llvm/test/tools/llvm-reduce/mir/undef-virt-reg.mir
Log Message:
-----------
AMDGPU: Convert llvm-reduce tests to new subarch triples (62) (#209868)
Pick arbitrary real subarch
Commit: fb2feebb64a6975f993791d86f00b085d6cd3bca
https://github.com/llvm/llvm-project/commit/fb2feebb64a6975f993791d86f00b085d6cd3bca
Author: Luke Lau <luke at igalia.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction-cost.ll
Log Message:
-----------
[RISCV][VPlan] Cost vp.merges that are likely to be folded away as free (#209387)
A vp.merge is lowered to a PseudoVMERGE_VVM on RISC-V, and
RISCVVectorPeehole usually folds away PseudoVMERGE_VVMs when its true
operand is a binary op.
This accounts for this in the cost model and plumbs it through the loop
vectorizer. The following reduction loop was previously considered
unprofitable to vectorize, but after this change is now vectorized, and
folds away all its vp.merges:
void three_gathers(const long *a, const long *c, const long *d,
const long *b, long n, long *out) {
long s1 = 0, s2 = 0, s3 = 0;
for (long i = 0; i < n; i++) {
long j = b[i];
s1 += a[j];
s2 += c[j];
s3 += d[j];
}
out[0] = s1;
out[1] = s2;
out[2] = s3;
}
Some vp.merges have only phis for their operands which can't be folded
away, coming from FindLastIV reductions. So this extends and reuses the
VectorInstrContext hint to limit the discount when one of the operands
is a binary op.
Also see the commit message in 9e77f59005917e32f09136fa43018f471267f5bd
which mentions the vp.merge cost should be updated.
Commit: c1ba7d0aaad6baa898c6735f71a99791839a1847
https://github.com/llvm/llvm-project/commit/c1ba7d0aaad6baa898c6735f71a99791839a1847
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/cxx11.cpp
M clang/test/AST/ByteCode/virtual-bases.cpp
Log Message:
-----------
Reapply "[clang][bytecode] Diagnose pointer subtractions of elements … (#209998)
…of different arrays" (#209969)
This reverts commit 745b946cbbf30708044b4a2c4a7726d0c02ca0de.
Use only one `fold()` for the virtual base offset assertions.
The pointer subtraction _is_ invalid, but the current interpreter
doesn't diagnose it since the `LValueDesignator`s are invalid.
Commit: 2b8125c686614ffc5c5f8cde007cd6ddcf6649d8
https://github.com/llvm/llvm-project/commit/2b8125c686614ffc5c5f8cde007cd6ddcf6649d8
Author: Wenju He <wenju.he at intel.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/Basic/OpenCLExtensions.def
A clang/test/Misc/amdgcn.unsupported_core_3.1.cl
M clang/test/SemaOpenCL/extension-version.cl
Log Message:
-----------
[Clang][OpenCL] Promote a few extensions to OpenCL 3.1 core (#204330)
Following 6 OpenCL extensions are promoted to core features in 3.1:
https://github.com/KhronosGroup/OpenCL-Docs/commit/9fff1a87a975
- cl_khr_extended_bit_ops
- cl_khr_integer_dot_product
- cl_khr_subgroup_extended_types
- cl_khr_subgroup_rotate
- cl_khr_subgroup_shuffle
- cl_khr_subgroup_shuffle_relative
A target claiming OpenCL C 3.1 conformance without supporting one of
these features is now diagnosed.
Updated release notes for the change.
Assisted-by: Claude
Commit: adc0f685fe94e66e68698ac87a8595e878477a61
https://github.com/llvm/llvm-project/commit/adc0f685fe94e66e68698ac87a8595e878477a61
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-llvm-debuginfo-analyzer.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
M llvm/test/CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll
M llvm/test/CodeGen/AMDGPU/debug-independence-revertScheduling.ll
M llvm/test/CodeGen/AMDGPU/debug-independence-scheduleRegion.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll
M llvm/test/CodeGen/AMDGPU/implicitarg-attributes.ll
M llvm/test/CodeGen/AMDGPU/issue176578.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-check-metadata.ll
M llvm/test/CodeGen/AMDGPU/pr155452.ll
M llvm/test/CodeGen/AMDGPU/rename-disconnected-bug.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-phi.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.gfx950.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
M llvm/test/CodeGen/AMDGPU/vgpr-count-compute.ll
M llvm/test/CodeGen/AMDGPU/vgpr-count-graphics-chain.ll
M llvm/test/CodeGen/AMDGPU/vgpr-count-graphics.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
Log Message:
-----------
AMDGPU: Convert tests to use subarch from triples in the file (#209869)
This set was using target triple in the source rather than command
line arguments.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Commit: 9277129afc6be0e4cf919bce1e0d2c56521af654
https://github.com/llvm/llvm-project/commit/9277129afc6be0e4cf919bce1e0d2c56521af654
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/convergent.mir
M llvm/test/CodeGen/AMDGPU/generic-targets-require-v6.ll
M llvm/test/CodeGen/AMDGPU/hsa-generic-target-features.ll
Log Message:
-----------
AMDGPU: Use subarch in tests using generic arches (#209870)
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Commit: 65180a50117244b4758e03175bed2dc34fc74f91
https://github.com/llvm/llvm-project/commit/65180a50117244b4758e03175bed2dc34fc74f91
Author: Mel Chen <mel.chen at sifive.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
Log Message:
-----------
[VPlan] Relax address constraints during stride analysis (#209168)
VPlanTransforms::convertToStridedAccesses() only handled loads whose
address was a VPWidenGEPRecipe, missing pointer-induction loops where
the address is computed differently. Analyze the address VPValue
directly so these cases are also converted to strided loads.
Fixed #207171
Commit: 9b5ad6ee5dc5139f2a156350da64a84df8145fc6
https://github.com/llvm/llvm-project/commit/9b5ad6ee5dc5139f2a156350da64a84df8145fc6
Author: 311Volt <41923095+311Volt at users.noreply.github.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M offload/liboffload/API/Program.td
M offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa.h
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/plugins-nextgen/cuda/dynamic_cuda/cuda.h
M offload/plugins-nextgen/cuda/src/rtl.cpp
M offload/plugins-nextgen/level_zero/include/L0Trace.h
M offload/plugins-nextgen/level_zero/src/L0Program.cpp
M offload/unittests/OffloadAPI/common/Environment.cpp
M offload/unittests/OffloadAPI/common/Environment.hpp
M offload/unittests/OffloadAPI/program/olCreateProgram.cpp
Log Message:
-----------
[offload] add translation of plugin-specific error codes to Offload API ECs (#207208)
liboffload plugins would not always exhaustively map the underlying
API's error values to ol_errc_t, resulting in unintended behavior - e.g.
olCreateProgram, given an invalid binary, would return OL_ERRC_UNKNOWN
instead of OL_ERRC_INVALID_BINARY.
This patch largely eliminates the most glaring cases of this by
assigning an ol_errc_t value to every error code of the underlying API
in every plugin. The proper granularity for this mapping is per-API
call, but that is a large rework that belongs in a separate patch.
Assisted-by: Claude
Commit: 83582cfcdb4973a337195c1f59d6a3468d135434
https://github.com/llvm/llvm-project/commit/83582cfcdb4973a337195c1f59d6a3468d135434
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/test/CodeGen/c11atomics.c
Log Message:
-----------
[clang][CodeGen] Do not use atomicrmw in compound assignments with FP conversions (#209114)
Per C11 6.5.16.2p1, when the left operand of operator `+=` has atomic
type, the right shall have arithmetic type. Do not try the `atomicrmw`
fast-path when FP conversion, arithmetic and truncation are required, as
a single atomic operation may not correctly capture the combined
semantics.
Fixes: https://github.com/llvm/llvm-project/issues/208997.
Commit: 59d7709ee9352df286bfb9b7a3b97c38deae5495
https://github.com/llvm/llvm-project/commit/59d7709ee9352df286bfb9b7a3b97c38deae5495
Author: Shikhar Jain <shikharj at qti.qualcomm.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M polly/lib/Transform/DeLICM.cpp
A polly/test/DeLICM/outofquota-greedycollapse.ll
Log Message:
-----------
Bound ISL operations during DeLICM scalar collapsing (#203073)
The IslMaxOperationsGuard in DeLICM previously covered only the zone
analysis performed in computeZone(). The subsequent greedyCollapse() ->
collapseScalarsToStore() path calls computeScalarReachingOverwrite(),
which performs an unbounded ISL lexmin().
Share a single[already present], dormant IslMaxOperationsGuard across
both regions and arm it narrowly around each operation intensive
computation via IslQuotaScope, so the same operations budget covers both
computeZone() and the scalar collapsing. When the quota is exceeded
during scalar collapsing, bail out cleanly: increment DeLICMOutOfQuota
and emit an "OutOfQuota" analysis remark.
Fixes: https://github.com/llvm/llvm-project/issues/202045
Commit: ad792fafbe64b3889ffac6e06bdd2a91ab8591bb
https://github.com/llvm/llvm-project/commit/ad792fafbe64b3889ffac6e06bdd2a91ab8591bb
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.cpp
Log Message:
-----------
[SLP][NFC] Address follow-up cleanups in SLPUtils (#210016)
Follow-up to #206881, addressing deferred review comments:
- Assert VL is non-empty in allSameType before consume_front.
- Use llvm::all_of instead of std::all_of in allSameOpcode.
- Rewrite isVectorLikeInstWithConstOps as a dyn_cast + opcode switch.
---------
Co-authored-by: Antonio Frighetto <me at antoniofrighetto.com>
Commit: 20a86a2fb7a793a59d7535ceb4d0f67c07b2f10e
https://github.com/llvm/llvm-project/commit/20a86a2fb7a793a59d7535ceb4d0f67c07b2f10e
Author: 311Volt <41923095+311Volt at users.noreply.github.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M offload/unittests/OffloadAPI/program/olCreateProgram.cpp
Log Message:
-----------
[offload] fix failure of olCreateProgramTest.TruncatedBinary (#210024)
https://github.com/llvm/llvm-project/pull/207208 caused a CI failure on
openmp-offload-amdgpu-clang-flang in the
olCreateProgramTest.TruncatedBinary test.
This PR removes this test case, as it's unclear whether guarding against
such cases is worth it.
Commit: 83eac376c5dfc4e730955f37a48f24850e0b5a52
https://github.com/llvm/llvm-project/commit/83eac376c5dfc4e730955f37a48f24850e0b5a52
Author: Kareem Ergawy <kergawy at nvidia.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M flang/include/flang/Lower/PFTBuilder.h
M flang/lib/Lower/PFTBuilder.cpp
A flang/test/Lower/pre-fir-tree-multiway-branch.f90
M flang/test/Lower/pre-fir-tree02.f90
Log Message:
-----------
[flang][PFT] record every target of multiway branches (#210012)
The Evaluation node stored branch targets in a single `Evaluation *`
(`controlSuccessor`). `markBranchTarget` therefore silently dropped
every target after the first when lowering a computed `GO TO` or
arithmetic `IF`, so any analysis that consulted `controlSuccessor` to
enumerate branch targets saw only the first label.
Add `extraControlSuccessors` alongside
`controlSuccessor`. `markBranchTarget` still fills `controlSuccessor`
with the first target, but appends each subsequent distinct target to
`extraControlSuccessors`. Extend the PFT dumper to print the extra
targets after the first ("-> N, M, K"), so PFT dumps expose every branch
target.
Co-Authored-By: Claude Sonnet 4.6 <noreply at anthropic.com>
Co-authored-by: Claude Sonnet 4.6 <noreply at anthropic.com>
Commit: 5a98e96135e223890cbf0640584e30c0db695ecf
https://github.com/llvm/llvm-project/commit/5a98e96135e223890cbf0640584e30c0db695ecf
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M flang/test/Driver/fakeflang.F
M flang/tools/CMakeLists.txt
M flang/tools/fakeflang/CMakeLists.txt
R flang/tools/fakeflang/ensure_flang_exists.cmake
M flang/tools/fakeflang/fakeflang.cpp
M flang/tools/flang-driver/CMakeLists.txt
M llvm/cmake/modules/LLVMExternalProjectUtils.cmake
Log Message:
-----------
[Flang][CMake] Use fakeflang as dispatcher (#209482)
With #203481 where `runtimes-configure` does not depend on `flang`
anymore, the following race could happen in incremental builds: While
ninja/make builds some of the libFortran*.so libraries in a
BUILD_SHARED_LIBS=ON build, CMake tries to execute flang which tries to
load the .so libraries while they are linked. This race condition can
only happen in incremental builds because before the real bin/flang is
built completely the first time, it points to fakeflang which would be
working. Only in an incremental build, would the real bin/flang already
been built created before, pointing to the currently re-built flang.
I did not think this would be possible because CMake only needs to probe
flang once and thereafter (in the incremental build) remembers the probe
result in `CMakeFiles/<version>/CMakeFortranCompiler.cmake`. CMake does
not support changing the compiler once configured and errors-out if you
try to change `CMAKE_Fortran_COMPILER`. I do not know why/when CMake is
re-probing the compiler in some incremental builds, but has been
reported to do so in #205360.
This patch avoids any replacement of build artifacts and instead decides
in fakeflang when to call real flang or to emulate the Flang
preprocessor. The decision is made based of on the FLANG_BOOTSTRAP_PROBE
environment variable that is set only in the configure step. The feature
that allows this is unfortunately only available starting in CMake 4.2.
All suppported CMake versions before CMake 4.2 use the filename
`CMakeFortranCompilerId.F`, so make the decision based on that when
using earlier versions of CMake.
Tested with CMake 3.20, 3.28, 3.31, 4.1, and 4.2.
Fixes #205360
Commit: 57ceb12780157d68f7c14d5ed8f18bc87dc768fd
https://github.com/llvm/llvm-project/commit/57ceb12780157d68f7c14d5ed8f18bc87dc768fd
Author: Wenju He <wenju.he at intel.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/include/llvm/DebugInfo/PDB/Native/LinePrinter.h
Log Message:
-----------
[DebugInfo][NFC] Fix PDB/Native/LinePrinter.h build warning -Wmicrosoft-unqualified-friend (#209715)
Fix build warning on Windows, which is error under -Werror: unqualified
friend declaration referring to type outside of the nearest enclosing
namespace is a Microsoft extension; add a nested name specifier
[-Wmicrosoft-unqualified-friend]
Commit: 5e4f44041d32234ea8227cbb2473173bd5edfc1c
https://github.com/llvm/llvm-project/commit/5e4f44041d32234ea8227cbb2473173bd5edfc1c
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/test/CodeGen/amdgpu-builtin-is-invocable.c
M clang/test/CodeGen/amdgpu-builtin-processor-is.c
M clang/test/CodeGenCXX/dynamic-cast-address-space.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/test/MC/AMDGPU/gfx13_asm_vds.s
Log Message:
-----------
[AMDGPU] Clean up GFX13 feature list (#208416)
GFX13 features were previously mostly inherited from GFX12/GFX1250.
- define an explicit gfx13 target parser feature list, including
gfx13-insts and cvt-pknorm-vop3-insts.
- remove transpose load F4/F6 support from gfx13 (previously copied from
gfx12)
Commit: 3faf46d218d3cb888c818b3e99d7e05b06ca68fa
https://github.com/llvm/llvm-project/commit/3faf46d218d3cb888c818b3e99d7e05b06ca68fa
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt/InProcessControllerAccess.h
M orc-rt/include/orc-rt/Session.h
M orc-rt/lib/executor/InProcessControllerAccess.cpp
M orc-rt/test/unit/SessionTest.cpp
Log Message:
-----------
[orc-rt] Session::OnCallControllerReturnFn, comments. NFC. (#210035)
Rename Session::OnCallHandlerCompleteFn to
Session::OnControllerCallReturnFn and add a comment to clarify its
purpose: This callback is used to handle retured values from calls to
the controller.
Commit: 8866215f30953c7df146276ac10753de941b1fcb
https://github.com/llvm/llvm-project/commit/8866215f30953c7df146276ac10753de941b1fcb
Author: mkovacevic99 <mkovacevic at baylibre.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/include/llvm-c/Orc.h
Log Message:
-----------
[Orc] Update the comment so it doesn't mention TargetTriple argument that no longer exists (#210023)
Completes the fix for the
https://github.com/llvm/llvm-project/issues/80097
Commit: 3d87de86a24d1bff2821e4eb2f2d28e58605a394
https://github.com/llvm/llvm-project/commit/3d87de86a24d1bff2821e4eb2f2d28e58605a394
Author: Philip742 <philip.wilkinson at arm.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
Log Message:
-----------
[mlir][tosa] Add support for MXFP in CONCAT (#209719)
Adds support to profile compliance for MXFP variants of CONCAT
Signed-off-by: Philip Wilkinson <philip.wilkinson at arm.com>
Commit: 18fc5a8adbe5dba7dc281bacdb149e95dc7dc1be
https://github.com/llvm/llvm-project/commit/18fc5a8adbe5dba7dc281bacdb149e95dc7dc1be
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/test/TableGen/MacroFusion.td
M llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp
Log Message:
-----------
[TableGen][RISCV] Generate pre/post-RA statistics for macro fusions (#209394)
Teach `MacroFusionPredicatorEmitter` to emit `Statistic` counters
recording how often each macro fusion is matched, and wire them
up for RISC-V.
This is based on the idea in #186499, generalized so counters are
generated automatically for any target using the emitter.
Because both the pre-RA and post-RA schedulers run MacroFusion,
a single counter would conflate the two. Counters are split into
pre-RA/post-RA variants, distinguished by the `NoVRegs` property,
addressing the double-counting concern from #186499:
```cpp
STATISTIC(NumTuneLDADDFusionPreRA, "Times TuneLDADDFusion Triggered (pre-ra)");
STATISTIC(NumTuneLDADDFusionPostRA, "Times TuneLDADDFusion Triggered (post-ra)");
...
if (SecondMI.getMF()->getProperties().hasNoVRegs())
++NumTuneLDADDFusionPostRA;
else
++NumTuneLDADDFusionPreRA;
```
Besides, RISC-V counters use the `riscv-macro-fusion` debug type.
Co-authored-by: Sam Elliott <aelliott at qti.qualcomm.com>
Assisted-by: TRAE CLI (DeepSeek V4 Pro)
Commit: db7356dde8312a86e79ec0d7b7f844878a1a743c
https://github.com/llvm/llvm-project/commit/db7356dde8312a86e79ec0d7b7f844878a1a743c
Author: Petr Hosek <phosek at google.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M libcxx/src/include/overridable_function.h
M libcxx/src/new.cpp
M libcxxabi/src/stdlib_new_delete.cpp
Log Message:
-----------
[libc++] Partially revert #208330 (#209928)
We found out that the new mechanism for detecting overriden functions
does not support Arm Pointer Authentication (PAuth). Addressing this
limitation is going to require changes to Clang. In the meantime, we
switched back to the old mechanism when PAuth is enabled.
Commit: 3bf897eaac63ea4e6b8c4f77d84f833f63167e3d
https://github.com/llvm/llvm-project/commit/3bf897eaac63ea4e6b8c4f77d84f833f63167e3d
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/loop-invariant-gather-inst-count.ll
Log Message:
-----------
[SLP][NFC]Add a test with the non-profitable instcount check across the loops, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/210045
Commit: ee5cff53cf4f0c23254bda94c7249e4ea008d457
https://github.com/llvm/llvm-project/commit/ee5cff53cf4f0c23254bda94c7249e4ea008d457
Author: Kseniya Tikhomirova <kseniya.tikhomirova at intel.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M libsycl/unittests/mock/helpers.cpp
Log Message:
-----------
[libsycl] Fix mock error in unittest helper (#209726)
Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
Commit: 66e8cc5ec83d7ec5e506c53b11c1d22887c0c418
https://github.com/llvm/llvm-project/commit/66e8cc5ec83d7ec5e506c53b11c1d22887c0c418
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/or-non-negative.ll
M llvm/test/Transforms/PhaseOrdering/constraint-eliminiation-interactions.ll
Log Message:
-----------
[ConstraintElim] Handle (X | Y) >s -1 as X >s -1 && Y >s -1. (#209743)
InstCombine canonicalizes X >=s 0 && Y >=s 0 as (X | Y) >=s 0. Teach
ConstraintElimination to recover the signed-positive information by
looking through compares of binary ORs.
Alive2 Proof: https://alive2.llvm.org/ce/z/sqNF8M
Compile-time impact is neutral
https://llvm-compile-time-tracker.com/compare.php?from=88acd428fd72f44312408c3fb6165992fb3b043a&to=a2aa4cacb953b32d6319939b9aee3226a7294334&stat=instructions%3Au
PR: https://github.com/llvm/llvm-project/pull/209743
Commit: 6388cfc492e82702dfc1aa965adab7e85c7ad3d8
https://github.com/llvm/llvm-project/commit/6388cfc492e82702dfc1aa965adab7e85c7ad3d8
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/reduction.ll
Log Message:
-----------
[AMDGPU] Add missing FMF flags in tests (NFC) (#210055)
The flags should be on the select, not the fcmp for nsz to have
any effect.
Commit: 424fec2368d615dff78b4167e78e9bbb06fc4214
https://github.com/llvm/llvm-project/commit/424fec2368d615dff78b4167e78e9bbb06fc4214
Author: Jessica Clarke <jrtc27 at jrtc27.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/test/Analysis/AliasSet/memset.ll
Log Message:
-----------
[NFC][test][AliasSet] Canonicalise memset.ll's overload suffices (#210059)
The second overload suffix here corresponds to the type of the length,
the third argument, which is an i64 not an i32. Canonicalise this to
avoid confusion from inconsistency.
Whilst here, fix the whitespace used to align the arguments in the
intrinsic declarations, a remnant of losing the two characters in "i8"
when migrating to opaque pointers.
Fixes: 9f0916129024 ("[AST] Add test coverage of memsets")
Fixes: ac924305793c ("[AliasSet] Convert tests to opaque pointers
(NFC)")
Commit: 006d13e206401545c011028d85749071acdc5326
https://github.com/llvm/llvm-project/commit/006d13e206401545c011028d85749071acdc5326
Author: Alex Duran <alejandro.duran at intel.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M offload/plugins-nextgen/level_zero/include/L0Kernel.h
M offload/plugins-nextgen/level_zero/include/L0Options.h
M offload/plugins-nextgen/level_zero/src/L0Options.cpp
M offload/plugins-nextgen/level_zero/src/L0Queue.cpp
Log Message:
-----------
[OFFLOAD][L0][NFC] Cleanup dead code (#210060)
As we have done several refactorings lately, some dead code/data was
left behind inadvertedly. This is just cleaning it up.
Commit: 6ba12f1878384fa0d5be092b511f67e7e808772b
https://github.com/llvm/llvm-project/commit/6ba12f1878384fa0d5be092b511f67e7e808772b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/test/Transforms/VectorCombine/X86/fold-signbit-reduction-cmp.ll
Log Message:
-----------
[X86] fold-signbit-reduction-cmp.ll - test for each x86-64 cpu level (#210051)
Commit: 26c200d88e720fa88e8692ace13a493696ac591f
https://github.com/llvm/llvm-project/commit/26c200d88e720fa88e8692ace13a493696ac591f
Author: Ayokunle Amodu <ayokunle321 at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx1250.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-vi-f16.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
Log Message:
-----------
[CIR][AMDGPU] Add support for AMDGCN sin builtins (#197784)
Adds codegen for the following AMDGCN sin builtins:
- __builtin_amdgcn_sinf (float)
- __builtin_amdgcn_sinh (half)
- __builtin_amdgcn_sin_bf16 (bfloat16)
These are lowered to the corresponding `llvm.amdgcn.sin` intrinsic.
Commit: 8739d89c4c2475eefc4638882311515fc67f9f9b
https://github.com/llvm/llvm-project/commit/8739d89c4c2475eefc4638882311515fc67f9f9b
Author: Yuan Suo <suoyuan666 at s5n.xyz>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h
M clang/lib/Analysis/LifetimeSafety/Checker.cpp
M clang/lib/Sema/SemaLifetimeSafety.h
M clang/test/Sema/LifetimeSafety/invalidations.cpp
M clang/test/Sema/LifetimeSafety/safety.cpp
Log Message:
-----------
[LifetimeSafety] Introduce buildOriginFlowChain to use-after-invalidation (#208891)
After completing the implementation of `buildOriginFlowChain`, we should
integrate it into the remaining diagnostics. I started with
`use-after-invalidation` because there is already an overload of
`buildOriginFlowChain` for `UseFact`.
While testing, I noticed the following diagnostics:
```txt
test.cpp:9:23: note: result of call to 'begin<std::vector<int>>' aliases the storage of parameter 'v'
9 | auto it = std::find(std::begin(v), std::end(v), 3); // expected-warning {{parameter 'v' is later invalidated}} \
| ^~~~~~~~~~~~~
test.cpp:9:13: note: result of call to 'find<__gnu_cxx::__normal_iterator<int *, std::vector<int>>, int>' aliases the storage of parameter 'v'
9 | auto it = std::find(std::begin(v), std::end(v), 3); // expected-warning {{parameter 'v' is later invalidated}} \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
```
I think these diagnostics could be made clearer, but I'd prefer to
address that in a separate PR.
---------
Signed-off-by: Yuan Suo <suoyuan666 at s5n.xyz>
Commit: 19595357e32b36383a025fddaaf8c38f90658b7b
https://github.com/llvm/llvm-project/commit/19595357e32b36383a025fddaaf8c38f90658b7b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vpdpwssd.ll
Log Message:
-----------
[X86] combineAdd - remove unnecessary add(a,concat(vpmaddwd(x,y),vpmaddwd(z,w))) -> vpdpwssd(a,concat(x,z),concat(y,w)) fold (#209838)
We already handle vpmaddwd concatenation in combineConcatVectorOps - but
512-bit vpmaddwd is only available on BWI targets, which was missing
from the tests
Technically if there's a target that has AVX512VNNI but not BWI, then
this fold would be useful, but there's no such target and there's a
limit to "what if" optimisations we really need.
A small attempt at cleaning out some not very useful code from
X86ISelLowering.cpp - I'm intending to do a lot more of this for 24.x / #143088
Commit: e3d3b3b0cf3672480d6f781a9726cec1e7983d14
https://github.com/llvm/llvm-project/commit/e3d3b3b0cf3672480d6f781a9726cec1e7983d14
Author: DylanFleming-arm <85629460+DylanFleming-arm at users.noreply.github.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M libc/CMakeLists.txt
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/src/__support/CPP/CMakeLists.txt
M libc/src/__support/CPP/simd.h
M libc/src/__support/mathvec/CMakeLists.txt
A libc/src/__support/mathvec/acosf.h
A libc/src/__support/mathvec/acoshf.h
A libc/src/__support/mathvec/acospif.h
A libc/src/__support/mathvec/asinf.h
A libc/src/__support/mathvec/asinhf.h
A libc/src/__support/mathvec/asinpif.h
A libc/src/__support/mathvec/atanf.h
A libc/src/__support/mathvec/atanhf.h
A libc/src/__support/mathvec/cbrtf.h
M libc/src/__support/mathvec/common_constants.h
A libc/src/__support/mathvec/cosf.h
A libc/src/__support/mathvec/coshf.h
A libc/src/__support/mathvec/cospif.h
A libc/src/__support/mathvec/erff.h
A libc/src/__support/mathvec/exp10f.h
A libc/src/__support/mathvec/exp10m1f.h
A libc/src/__support/mathvec/exp2f.h
A libc/src/__support/mathvec/exp2m1f.h
M libc/src/__support/mathvec/expf.h
M libc/src/__support/mathvec/expf_utils.h
A libc/src/__support/mathvec/expm1f.h
A libc/src/__support/mathvec/log10f.h
A libc/src/__support/mathvec/log1pf.h
A libc/src/__support/mathvec/log2f.h
A libc/src/__support/mathvec/logf.h
A libc/src/__support/mathvec/rsqrtf.h
A libc/src/__support/mathvec/sinf.h
A libc/src/__support/mathvec/sinhf.h
A libc/src/__support/mathvec/sinpif.h
A libc/src/__support/mathvec/sqrtf.h
A libc/src/__support/mathvec/tanf.h
A libc/src/__support/mathvec/tanhf.h
A libc/src/__support/mathvec/tanpif.h
M libc/src/mathvec/CMakeLists.txt
A libc/src/mathvec/abi_prefix.h
A libc/src/mathvec/acosf.h
A libc/src/mathvec/acoshf.h
A libc/src/mathvec/acospif.h
A libc/src/mathvec/asinf.h
A libc/src/mathvec/asinhf.h
A libc/src/mathvec/asinpif.h
A libc/src/mathvec/atanf.h
A libc/src/mathvec/atanhf.h
A libc/src/mathvec/cbrtf.h
A libc/src/mathvec/cosf.h
A libc/src/mathvec/coshf.h
A libc/src/mathvec/cospif.h
A libc/src/mathvec/erff.h
A libc/src/mathvec/exp10f.h
A libc/src/mathvec/exp10m1f.h
A libc/src/mathvec/exp2f.h
A libc/src/mathvec/exp2m1f.h
M libc/src/mathvec/expf.h
A libc/src/mathvec/expm1f.h
M libc/src/mathvec/generic/CMakeLists.txt
A libc/src/mathvec/generic/acosf.cpp
A libc/src/mathvec/generic/acoshf.cpp
A libc/src/mathvec/generic/acospif.cpp
A libc/src/mathvec/generic/asinf.cpp
A libc/src/mathvec/generic/asinhf.cpp
A libc/src/mathvec/generic/asinpif.cpp
A libc/src/mathvec/generic/atanf.cpp
A libc/src/mathvec/generic/atanhf.cpp
A libc/src/mathvec/generic/cbrtf.cpp
A libc/src/mathvec/generic/cosf.cpp
A libc/src/mathvec/generic/coshf.cpp
A libc/src/mathvec/generic/cospif.cpp
A libc/src/mathvec/generic/erff.cpp
A libc/src/mathvec/generic/exp10f.cpp
A libc/src/mathvec/generic/exp10m1f.cpp
A libc/src/mathvec/generic/exp2f.cpp
A libc/src/mathvec/generic/exp2m1f.cpp
M libc/src/mathvec/generic/expf.cpp
A libc/src/mathvec/generic/expm1f.cpp
A libc/src/mathvec/generic/log10f.cpp
A libc/src/mathvec/generic/log1pf.cpp
A libc/src/mathvec/generic/log2f.cpp
A libc/src/mathvec/generic/logf.cpp
A libc/src/mathvec/generic/rsqrtf.cpp
A libc/src/mathvec/generic/sinf.cpp
A libc/src/mathvec/generic/sinhf.cpp
A libc/src/mathvec/generic/sinpif.cpp
A libc/src/mathvec/generic/sqrtf.cpp
A libc/src/mathvec/generic/tanf.cpp
A libc/src/mathvec/generic/tanhf.cpp
A libc/src/mathvec/generic/tanpif.cpp
A libc/src/mathvec/log10f.h
A libc/src/mathvec/log1pf.h
A libc/src/mathvec/log2f.h
A libc/src/mathvec/logf.h
A libc/src/mathvec/rsqrtf.h
A libc/src/mathvec/sinf.h
A libc/src/mathvec/sinhf.h
A libc/src/mathvec/sinpif.h
A libc/src/mathvec/sqrtf.h
A libc/src/mathvec/tanf.h
A libc/src/mathvec/tanhf.h
A libc/src/mathvec/tanpif.h
M libc/test/src/mathvec/CMakeLists.txt
A libc/test/src/mathvec/UnitTestWrappers.h
A libc/test/src/mathvec/acosf_test.cpp
A libc/test/src/mathvec/acoshf_test.cpp
A libc/test/src/mathvec/acospif_test.cpp
A libc/test/src/mathvec/asinf_test.cpp
A libc/test/src/mathvec/asinhf_test.cpp
A libc/test/src/mathvec/asinpif_test.cpp
A libc/test/src/mathvec/atanf_test.cpp
A libc/test/src/mathvec/atanhf_test.cpp
A libc/test/src/mathvec/cbrtf_test.cpp
A libc/test/src/mathvec/cosf_test.cpp
A libc/test/src/mathvec/coshf_test.cpp
A libc/test/src/mathvec/cospif_test.cpp
A libc/test/src/mathvec/erff_test.cpp
M libc/test/src/mathvec/exhaustive/CMakeLists.txt
A libc/test/src/mathvec/exhaustive/acosf_test.cpp
A libc/test/src/mathvec/exhaustive/acoshf_test.cpp
A libc/test/src/mathvec/exhaustive/acospif_test.cpp
A libc/test/src/mathvec/exhaustive/asinf_test.cpp
A libc/test/src/mathvec/exhaustive/asinhf_test.cpp
A libc/test/src/mathvec/exhaustive/asinpif_test.cpp
A libc/test/src/mathvec/exhaustive/atanf_test.cpp
A libc/test/src/mathvec/exhaustive/atanhf_test.cpp
A libc/test/src/mathvec/exhaustive/cbrtf_test.cpp
A libc/test/src/mathvec/exhaustive/cosf_test.cpp
A libc/test/src/mathvec/exhaustive/coshf_test.cpp
A libc/test/src/mathvec/exhaustive/cospif_test.cpp
A libc/test/src/mathvec/exhaustive/erff_test.cpp
M libc/test/src/mathvec/exhaustive/exhaustive_test.h
A libc/test/src/mathvec/exhaustive/exp10f_test.cpp
A libc/test/src/mathvec/exhaustive/exp10m1f_test.cpp
A libc/test/src/mathvec/exhaustive/exp2f_test.cpp
A libc/test/src/mathvec/exhaustive/exp2m1f_test.cpp
M libc/test/src/mathvec/exhaustive/expf_test.cpp
A libc/test/src/mathvec/exhaustive/expm1f_test.cpp
A libc/test/src/mathvec/exhaustive/log10f_test.cpp
A libc/test/src/mathvec/exhaustive/log1pf_test.cpp
A libc/test/src/mathvec/exhaustive/log2f_test.cpp
A libc/test/src/mathvec/exhaustive/logf_test.cpp
A libc/test/src/mathvec/exhaustive/rsqrtf_test.cpp
A libc/test/src/mathvec/exhaustive/sinf_test.cpp
A libc/test/src/mathvec/exhaustive/sinhf_test.cpp
A libc/test/src/mathvec/exhaustive/sinpif_test.cpp
A libc/test/src/mathvec/exhaustive/sqrtf_test.cpp
A libc/test/src/mathvec/exhaustive/tanf_test.cpp
A libc/test/src/mathvec/exhaustive/tanhf_test.cpp
A libc/test/src/mathvec/exhaustive/tanpif_test.cpp
A libc/test/src/mathvec/exp10f_test.cpp
A libc/test/src/mathvec/exp10m1f_test.cpp
A libc/test/src/mathvec/exp2f_test.cpp
A libc/test/src/mathvec/exp2m1f_test.cpp
M libc/test/src/mathvec/expf_test.cpp
A libc/test/src/mathvec/expm1f_test.cpp
A libc/test/src/mathvec/log10f_test.cpp
A libc/test/src/mathvec/log1pf_test.cpp
A libc/test/src/mathvec/log2f_test.cpp
A libc/test/src/mathvec/logf_test.cpp
A libc/test/src/mathvec/rsqrtf_test.cpp
A libc/test/src/mathvec/sinf_test.cpp
A libc/test/src/mathvec/sinhf_test.cpp
A libc/test/src/mathvec/sinpif_test.cpp
A libc/test/src/mathvec/sqrtf_test.cpp
A libc/test/src/mathvec/tanf_test.cpp
A libc/test/src/mathvec/tanhf_test.cpp
A libc/test/src/mathvec/tanpif_test.cpp
Log Message:
-----------
[libc][mathvec] Add loop over scalar for unary FP32 (#199273)
Adds all FP32 unary functions currently supported in scalar LLVM LIBM to
LIBMVEC as loop over scalars.
Includes some cleanup of existing mathvec testing infrastructure
Commit: 1cb7e838cd47ecad4050948c0c907ecb1f466ac3
https://github.com/llvm/llvm-project/commit/1cb7e838cd47ecad4050948c0c907ecb1f466ac3
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Log Message:
-----------
[AMDGPU] Simplify some isVALU calls. NFC. (#210057)
Commit: 122efb26893f7e214d0223615c3a4abcc0ac7796
https://github.com/llvm/llvm-project/commit/122efb26893f7e214d0223615c3a4abcc0ac7796
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M libcxx/include/__algorithm/is_heap_until.h
M libcxx/test/std/algorithms/alg.sorting/alg.heap.operations/is.heap/ranges_is_heap_until.pass.cpp
Log Message:
-----------
[libc++] Optimize std::is_heap_until (#209141)
Fixes #208299
Commit: 6e7ff09291652cc784a095707029852e249902f9
https://github.com/llvm/llvm-project/commit/6e7ff09291652cc784a095707029852e249902f9
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Log Message:
-----------
[AMDGPU] Improve debug printing of regunits in SIInsertWaitcnts (#210066)
Use the standard printRegUnit helper.
Commit: c7a5b9c0ddd1a5e89a3e8b5a79a916f03e0689b7
https://github.com/llvm/llvm-project/commit/c7a5b9c0ddd1a5e89a3e8b5a79a916f03e0689b7
Author: Sean Clarke <sclarke at tenstorrent.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/include/llvm/Analysis/HashRecognize.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Analysis/HashRecognize.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
M llvm/test/Analysis/HashRecognize/cyclic-redundancy-check.ll
A llvm/test/Transforms/LoopIdiom/AArch64/cyclic-redundancy-check.ll
A llvm/test/Transforms/LoopIdiom/RISCV/cyclic-redundancy-check.ll
A llvm/test/Transforms/LoopIdiom/X86/cyclic-redundancy-check.ll
M llvm/test/Transforms/LoopIdiom/cyclic-redundancy-check.ll
Log Message:
-----------
[LoopIdiomRecognize] Enable clmul optimization for CRC loops (#203405)
The current `optimizeCRCLoop` function always optimizes CRC loops to use
a 256-entry Sarwate lookup table to process a byte at a time (except on
Hexagon and with optsize). However, some targets are able to process
larger chunks of CRC data with carry-less/polynomial multiplication
instructions. Implement this approach in IR for such targets using the
`llvm.clmul` intrinsic. (Only with optsize for the moment, though.)
Like the current CRC loop optimization, this does not apply to the
Hexagon target, despite it having a `pmpyw` instruction.
Assisted-by: Claude Opus 4.8
Commit: 73aa9102362f07e2f8fc537b3d2f72062d4a1e68
https://github.com/llvm/llvm-project/commit/73aa9102362f07e2f8fc537b3d2f72062d4a1e68
Author: Kseniya Tikhomirova <kseniya.tikhomirova at intel.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M libsycl/docs/index.rst
M libsycl/include/sycl/__impl/detail/kernel_arg_helpers.hpp
A libsycl/include/sycl/__impl/detail/linearization.hpp
M libsycl/include/sycl/__impl/detail/unified_range_view.hpp
A libsycl/include/sycl/__impl/group.hpp
A libsycl/include/sycl/__impl/memory_enums.hpp
A libsycl/include/sycl/__impl/nd_item.hpp
A libsycl/include/sycl/__impl/nd_range.hpp
M libsycl/include/sycl/__impl/queue.hpp
A libsycl/include/sycl/__impl/sub_group.hpp
M libsycl/include/sycl/__spirv/spirv_vars.hpp
M libsycl/include/sycl/sycl.hpp
M libsycl/src/detail/queue_impl.cpp
A libsycl/test/basic/group.cpp
A libsycl/test/basic/group_local_id.cpp
A libsycl/test/basic/linear_sub_group.cpp
A libsycl/test/basic/nd_range.cpp
M libsycl/test/basic/queue_parallel_for_generic.cpp
A libsycl/test/basic/sub_group_by_value_semantics.cpp
A libsycl/test/basic/sub_group_common.cpp
M libsycl/unittests/queue/sycl_kernel_launch.cpp
Log Message:
-----------
[libsycl] Implement nd_range kernel submissions (#206505)
This PR adds core SYCL 2020 nd_range kernel submissions (including
nd_item, group, and sub_group).
Assisted with GH Copilot.
---------
Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
Commit: 0852ac5649a0ac6959af6fbc2e4cf6cf4bad7238
https://github.com/llvm/llvm-project/commit/0852ac5649a0ac6959af6fbc2e4cf6cf4bad7238
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCSchedule.td
M llvm/lib/Target/PowerPC/PPCSchedule440.td
M llvm/lib/Target/PowerPC/PPCScheduleA2.td
M llvm/lib/Target/PowerPC/PPCScheduleE500.td
M llvm/lib/Target/PowerPC/PPCScheduleE500mc.td
M llvm/lib/Target/PowerPC/PPCScheduleE5500.td
M llvm/lib/Target/PowerPC/PPCScheduleG3.td
Log Message:
-----------
[PowerPC] Remove itinerary IIC_LdStDCBA (#207227)
The itinerary IIC_LdStDCBA is defined and used in scheduling models, but
no instruction is assigned to it. However, since the instruction is
basically retired (not part of the portable Power ISA), and all
scheduling models model it similar to IIC_LdStDCBF, the itinerary can be
removed.
Commit: 96cab305c0402e051d16e748911bd469b4ad57fe
https://github.com/llvm/llvm-project/commit/96cab305c0402e051d16e748911bd469b4ad57fe
Author: Robert Imschweiler <robert.imschweiler at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/IR/VerifierAMDGPU.cpp
M llvm/test/Assembler/callbr.ll
Log Message:
-----------
[AMDGPU] Improve amdgcn_kill verification (#208220)
Commit: 8c22bbde747ce8c577318c3fb6cafaae6f1b8aec
https://github.com/llvm/llvm-project/commit/8c22bbde747ce8c577318c3fb6cafaae6f1b8aec
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV][P-ext] Replace lowerBuildVectorAsRV32PNarrowingShift with shuffle lowering. (#209088)
Add an implementation of isExtractSubvectorCheap for extracting
v2i16/v4i8 from a v4i16/v8i8 vector on RV32. This allows the
build_vector+extract_elt pattern to be turned into
shuffle_vector+extract_subvectors.
Assisted-by: Claude
Commit: 00674044ab7111ce25ac9a613fefeace7dff1125
https://github.com/llvm/llvm-project/commit/00674044ab7111ce25ac9a613fefeace7dff1125
Author: Benjamin Jurk <106487517+bnjmnjrk at users.noreply.github.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/include/llvm/IR/PatternMatch.h
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/unittests/IR/PatternMatch.cpp
Log Message:
-----------
[PatternMatch] Add m_SpecificType(Type*) matcher (#208427)
Fixes #208401.
Commit: d333df5aeb31ecf867e1a7908a7814485f4aa7f0
https://github.com/llvm/llvm-project/commit/d333df5aeb31ecf867e1a7908a7814485f4aa7f0
Author: aokblast <aokblast at FreeBSD.org>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M lldb/source/Target/Target.cpp
Log Message:
-----------
[LLDB] Print stderr in HandleStop (#208875)
There are some testcases silently fail in stopping hook without
returning anything on FreeBSD. We dump the error from the handler to
make it easier to debug.
Commit: 7fc7d8d5d2c10db1cff7f53175ad4cb158f0890d
https://github.com/llvm/llvm-project/commit/7fc7d8d5d2c10db1cff7f53175ad4cb158f0890d
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes e3d3b3b (#210068)
This fixes e3d3b3b0cf3672480d6f781a9726cec1e7983d14.
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=e3d3b3b0cf3672480d6f781a9726cec1e7983d14
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 638d6736400891b03f211487ccb643a49f14f743
https://github.com/llvm/llvm-project/commit/638d6736400891b03f211487ccb643a49f14f743
Author: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/lib/Sema/SemaLifetimeSafety.h
A clang/test/Sema/LifetimeSafety/annotation-suggestions-fixits.c
Log Message:
-----------
[LifetimeSafety] Add better lifetimebound fix-it spelling for C (#209967)
Use `__attribute__((lifetimebound))` as the default lifetimebound fix-it
spelling in pre-C23 C.
C++ and C23 continue to use `[[clang::lifetimebound]]` as the default
spelling.
When no explicit lifetimebound macro is configured, pre-C23 C only looks
for `__attribute__((lifetimebound))`, C++ and C23 keep looking for
`[[clang::lifetimebound]]` macros first, then
`__attribute__((lifetimebound))`.
Follow up of https://github.com/llvm/llvm-project/pull/204045
Commit: 9ec7974432975674b0128ea85a54cb3e5b0ffa75
https://github.com/llvm/llvm-project/commit/9ec7974432975674b0128ea85a54cb3e5b0ffa75
Author: LU-JOHN <John.Lu at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/CMakeLists.txt
Log Message:
-----------
[AMDGPU] Update libc/runtime target to use amdgpu (#210032)
Update libc/runtime targets to use "amdgpu" instead of "amdgcn". This
change is necessary to do libc testing with a
check-libc-amdgpu-amd-amdhsa target. The previous
check-libc-amdgcn-amd-amdhsa target already stopped working after
https://github.com/llvm/llvm-project/pull/209247.
Signed-off-by: John Lu <John.Lu at amd.com>
Commit: dfa1360735f5a834ce96c8c63594e2cdc3bfe0ea
https://github.com/llvm/llvm-project/commit/dfa1360735f5a834ce96c8c63594e2cdc3bfe0ea
Author: Ayokunle Amodu <ayokunle321 at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx1250.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-vi-f16.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
Log Message:
-----------
[CIR][AMDGPU] Add support for AMDGCN cos builtins (#197806)
Adds codegen for the following AMDGCN cos builtins:
- __builtin_amdgcn_cosf (float)
- __builtin_amdgcn_cosh (half)
- __builtin_amdgcn_cos_bf16 (bfloat16)
These are lowered to the corresponding `llvm.amdgcn.cos` intrinsic.
Commit: 8f0a479f46c98e1a098319786d0848e4b9e0a98d
https://github.com/llvm/llvm-project/commit/8f0a479f46c98e1a098319786d0848e4b9e0a98d
Author: jandrovins <46629861+jandrovins at users.noreply.github.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Transforms/IPO/Instrumentor.cpp
A llvm/test/Instrumentation/Instrumentor/load_store_gpu_ind.json
A llvm/test/Instrumentation/Instrumentor/load_store_gpu_ind.ll
Log Message:
-----------
[Instrumentor] Fix indirect arguments on gpu targets (#209835)
When an argument is passed indirectly,
`IRTCallDescription::createLLVMCall` spills it into a temporary alloca
and passes that alloca address to the runtime call. The alloca is
created in the target's alloca address space. On GPUs it is not address
space 0, which is what the runtime expects for indirect parameters. The
alloca pointer was passed as the argument, so its type didn't match the
call's declared parameter type, causing a "bad signature" assertion in
`CallInst::init` when instrumenting GPU code that requires indirection.
The solution is therefore to cast this pointer to address space 0 before
passing it the the instrumentor call.
Commit: 689fa1d6d74a465130ad0b1705813e14d1cd5b1a
https://github.com/llvm/llvm-project/commit/689fa1d6d74a465130ad0b1705813e14d1cd5b1a
Author: Hardik Kumar <hardikxk at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/include/clang/AST/CommentLexer.h
Log Message:
-----------
Fix Unintialised char *CommentLexer resulting in potential UB. (#210067)
The patch intialised the pointer to a .
Previously the pointer would have some garbage value which might have
resulted in UB.
closes #210034
Commit: f57bdc62619417a2ee9076ac05db9d115c3ba464
https://github.com/llvm/llvm-project/commit/f57bdc62619417a2ee9076ac05db9d115c3ba464
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
A llvm/test/Transforms/ConstraintElimination/and-negative.ll
M llvm/test/Transforms/PhaseOrdering/constraint-eliminiation-interactions.ll
Log Message:
-----------
[ConstraintElim] Handle (X & Y) <s 0 as X <s 0 && Y <s 0. (#210033)
InstCombine canonicalizes X <s 0 && Y <s 0 as (X & Y) <s 0. Teach
ConstraintElimination to recover the signed-negative information by
looking through compares of binary ANDs.
Alive2 Proof: https://alive2.llvm.org/ce/z/R6DWqD
Depends on https://github.com/llvm/llvm-project/pull/209743
PR: https://github.com/llvm/llvm-project/pull/210033
Commit: c9ec54a8a781166546c1001a8bfb2448fbacda44
https://github.com/llvm/llvm-project/commit/c9ec54a8a781166546c1001a8bfb2448fbacda44
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
Log Message:
-----------
[RISCV] Add DUMMY_REG_PAIR_WITH_X0->GPR copy to copyPhysReg. (#209964)
The register coalescer can convert (extract_subreg x0_pair, sub_gpr_odd)
to a read of DUMMY_REG_PAIR_WITH_X0. This patch treats it the same as a
copy from X0.
I don't know if this is a good long term fix, but I think it's ok for
now. I will continue to look for other options.
Commit: a5b70908d9cacd0aa1c918c920e8a6118b4340ce
https://github.com/llvm/llvm-project/commit/a5b70908d9cacd0aa1c918c920e8a6118b4340ce
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.td
M clang/test/CodeGen/amdgpu-builtin-is-invocable.c
M clang/test/CodeGen/amdgpu-builtin-processor-is.c
M clang/test/CodeGenCXX/dynamic-cast-address-space.cpp
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MIMGInstructions.td
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.compr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.compr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sudot4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sudot8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
M llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
M llvm/test/CodeGen/AMDGPU/unsupported-av-load.ll
M llvm/test/CodeGen/AMDGPU/unsupported-av-store.ll
Log Message:
-----------
[AMDGPU] Guard more intrinsics with target features (#203956)
Commit: 53dae32b8a3e973a1677bd2745b9128741d69f59
https://github.com/llvm/llvm-project/commit/53dae32b8a3e973a1677bd2745b9128741d69f59
Author: Kseniya Tikhomirova <kseniya.tikhomirova at intel.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M libsycl/include/sycl/__impl/queue.hpp
Log Message:
-----------
[libsycl] fix nd_range template resolution (#210081)
Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
Commit: d76f5249eaca89f73ff8e55783153a8376938abf
https://github.com/llvm/llvm-project/commit/d76f5249eaca89f73ff8e55783153a8376938abf
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M lldb/tools/lldb-server/lldb-gdbserver.cpp
Log Message:
-----------
[lldb][Windows] Don't let the inferior inherit the --pipe handle (#207024)
`lldb-server` writes its listening socket id to the `--pipe` handle and
then closes it. The parent process that spawned it reads the pipe until
EOF purely as a synchronization point (`"the server is now listening"`).
On Windows the inferior is launched with `bInheritHandles=TRUE` (it
needs the ConPTY handles), so it also inherited the pipe's write end.
That kept the write end open after `lldb-server` closed its own handle,
so the parent never saw EOF: it blocked until its read timeout and the
client's connection handshake timed out first.
This patch clears `HANDLE_FLAG_INHERIT` on the `--pipe` handle so the
inferior cannot keep the write end open, while leaving it valid for
lldb-server's own use.
rdar://180736036
Commit: 694c561cf73e81943395e18b2d96621baf68efe5
https://github.com/llvm/llvm-project/commit/694c561cf73e81943395e18b2d96621baf68efe5
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/include/llvm/ADT/GenericCycleImpl.h
M llvm/include/llvm/ADT/GenericCycleInfo.h
M llvm/lib/Transforms/Utils/FixIrreducible.cpp
Log Message:
-----------
[CycleInfo] Store cycles in a flat preorder array. NFC (#209981)
Store cycles by value in one array in cycle-forest preorder, each cycle
immediately followed by its descendants, instead of heap-allocating each
cycle and holding its children in a std::vector<std::unique_ptr<>>.
Child and top-level iteration become pointer arithmetic that skips a
subtree via a new NumDescendants count, and sizeof(GenericCycle) drops
from 72 to 48. GenericCycleInfoCompute builds the forest with temporary
nodes, then flatten() moves it into the array.
GenericCycle still exposes raw pointers into this array. The eventual
goal is to replace them with an opaque handle, so all access goes
through GenericCycleInfo and the storage stays an implementation detail.
Aided by Fable 5
Commit: 16c6374250a465204e067b518577a2b4fd655f93
https://github.com/llvm/llvm-project/commit/16c6374250a465204e067b518577a2b4fd655f93
Author: Tom Stellard <tstellar at redhat.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M .github/workflows/llvm-abi-tests.yml
Log Message:
-----------
workflows/llvm-abi-tests: Fix typo (#209917)
Introduced by 9bd8bbb2b76c55ca83ddb6e0aa8a3a79b65706d4.
Commit: be1728c99d806654d4ce4e7ad17aa89885e8053c
https://github.com/llvm/llvm-project/commit/be1728c99d806654d4ce4e7ad17aa89885e8053c
Author: Rithik Sharma <rithiksh02 at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
A clang/include/clang/CIR/Dialect/IR/CIRStdOps.td
M clang/include/clang/CIR/Dialect/Passes.h
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/Transforms/IdiomRecognizer.cpp
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
M clang/lib/CIR/Lowering/CIRPasses.cpp
A clang/test/CIR/CodeGen/func-identity-attr.c
A clang/test/CIR/CodeGen/func-identity-attr.cpp
A clang/test/CIR/IR/func-identity-attr.cir
A clang/test/CIR/Transforms/idiom-recognizer-guards-void-result.cpp
A clang/test/CIR/Transforms/idiom-recognizer-guards.cpp
A clang/test/CIR/Transforms/idiom-recognizer-inline-namespace.cpp
A clang/test/CIR/Transforms/idiom-recognizer.cir
M clang/test/CIR/Transforms/idiom-recognizer.cpp
M clang/tools/cir-opt/cir-opt.cpp
Log Message:
-----------
[CIR] Add support for the IdiomRecognizer pass (#208854)
This patch adds the `IdiomRecognizer` pass, which raises calls to known
standard library functions into dedicated operations that later passes
can optimize. The implementation follows the ClangIR incubator, and
upstream had only the pass skeleton and the frontend wiring.
The pass recognizes the standard find algorithm and raises it to the new
operation `cir.std.find`. A call is raised when its callee carries the
matching identity tag, the argument count and the types line up, the
callee is not variadic, and the call is not `musttail`. LoweringPrepare
lowers the operation back to the original call with its attributes, so
behavior never changes when no transform fires.
The tag is the new `func_identity` form under the `func_info` union on
`cir.func`. It holds one entry from an enum naming the entities the
recognizer knows, so the tag itself carries no names. `CIRGen` attaches
it by the plain name, the std membership with inline namespaces looked
through, and whether the function is free, so members, static members,
operators, and functions outside std never match, while the recognizer
checks the shape of each call.
The pass reads facts from the operations alone, so the AST requirement
and its wiring are gone, the pass is registered with `cir-opt`, and a
test drives it over parsed CIR assembly.
Commit: 3736a7bed1baae7c4b461062f89ddd76f799480d
https://github.com/llvm/llvm-project/commit/3736a7bed1baae7c4b461062f89ddd76f799480d
Author: Ilia Kuklin <ikuklin at accesssoftek.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M lldb/docs/dil-expr-lang.ebnf
M lldb/source/ValueObject/DILEval.cpp
M lldb/test/API/commands/frame/var-dil/expr/Literals/TestFrameVarDILLiterals.py
M lldb/test/API/commands/frame/var-dil/expr/Literals/main.cpp
A lldb/test/API/commands/frame/var-dil/expr/NullptrVar/Makefile
A lldb/test/API/commands/frame/var-dil/expr/NullptrVar/TestFrameVarDILNullptrVar.py
A lldb/test/API/commands/frame/var-dil/expr/NullptrVar/main.c
Log Message:
-----------
[lldb] Add `nullptr` literal to DIL (#208831)
DIL will first attempt resolving `nullptr` as a variable, and if there
is none, `nullptr` will be resolved as a null pointer.
Commit: ab5e01593562aa25bd104118ff42192d4a6ea80f
https://github.com/llvm/llvm-project/commit/ab5e01593562aa25bd104118ff42192d4a6ea80f
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/include/llvm/ADT/GenericCycleImpl.h
M llvm/include/llvm/ADT/GenericCycleInfo.h
M llvm/include/llvm/ADT/GenericUniformityImpl.h
M llvm/include/llvm/IR/GenericConvergenceVerifierImpl.h
M llvm/lib/CodeGen/MachineCycleAnalysis.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/Utils/FixIrreducible.cpp
Log Message:
-----------
[CycleInfo] Move cycle accessors to GenericCycleInfo. NFC (#209990)
Move member functions off GenericCycle onto GenericCycleInfo.
GenericCycle now holds only data and the child-iterator type, and all
cycle queries go through GenericCycleInfo. This prepares replacing the
GenericCycle pointer with an opaque handle.
Aided by Claude Opus 4.8
Commit: 0d37efa88b64ee83230599c13587b06ec43e06c0
https://github.com/llvm/llvm-project/commit/0d37efa88b64ee83230599c13587b06ec43e06c0
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
Log Message:
-----------
SPIRV: Fix constructing temporary TTI in SPIRVPrepareFunctions (#209977)
Passes should obtain TargetTransformInfo from the analysis manager
and never construct one. It may contain pipeline configuration state
(e.g., TargetLibraryInfo).
Co-authored-by: Claude (Claude Opus 4.8) <noreply at anthropic.com>
Commit: 4a578be311736c684214e87aa07800cd76dd2471
https://github.com/llvm/llvm-project/commit/4a578be311736c684214e87aa07800cd76dd2471
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
Log Message:
-----------
PPC: Avoid constructing TargetTransformInfo in isHardwareLoopProfitable (#209972)
PPCTTIImpl::isHardwareLoopProfitable constructed a throwaway
TargetTransformInfo only to call CodeMetrics::analyzeBasicBlock. TTI
may contain pipeline configuration state, and should only be queried
from the PassManager. It was also particularly ugly to construct one
here given that we're inside a TTIImpl.
Most of what analyzeBasicBlock computes was not used here. Directly
sum the instruction code size costs, which was the only used component
of the analysis.
Co-authored-by: Claude (Claude Opus 4.8) <noreply at anthropic.com>
Commit: 2fc864be4c7b254d61a0d2c397660951ac108cb7
https://github.com/llvm/llvm-project/commit/2fc864be4c7b254d61a0d2c397660951ac108cb7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M llvm/unittests/FuzzMutate/StrategiesTest.cpp
M llvm/unittests/Target/AMDGPU/AMDGPUMCExprTest.cpp
M llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
M llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.h
M llvm/unittests/Target/AMDGPU/CSETest.cpp
M llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp
M llvm/unittests/Target/AMDGPU/ExecMayBeModifiedBeforeAnyUse.cpp
M llvm/unittests/Target/AMDGPU/PALMetadata.cpp
M llvm/unittests/Target/AMDGPU/UniformityAnalysisTest.cpp
M llvm/unittests/Transforms/Utils/CodeExtractorTest.cpp
Log Message:
-----------
AMDGPU: Use subarch triples in more unit tests (#210011)
Avoid looking up the target by the cpu name with the legacy
amdgcn name.
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: 49744c0cc07c85f201267d75ec064eab743270d4
https://github.com/llvm/llvm-project/commit/49744c0cc07c85f201267d75ec064eab743270d4
Author: Ron Green [NVIDIA] <rogreen at nvidia.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M flang/lib/Parser/openacc-parsers.cpp
M flang/test/Parser/acc-unparse.f90
Log Message:
-----------
[flang][OpenACC] Allow blanks around ':' in a gang-arg (#210089)
The parsers for the STATIC, DIM, and NUM forms of an OpenACC gang-arg
used the token strings "STATIC: ", "DIM: ", and "NUM: ", none of which
permit a blank between the keyword and the ':' separator. A space in a
TokenStringMatch pattern is the only place a blank is accepted in the
source (outside the leading/trailing skip), so a directive such as
!$acc loop gang(static : 1)
was rejected with "expected end of OpenACC directive", even though
free-form Fortran allows optional blanks around the separator.
Move the blank in each token string to before the ':' ("STATIC :", etc.)
so zero or more blanks are accepted on either side of the separator. The
_tok form keeps the blank optional, so the no-space spelling still
parses without a warning.
Add parser/unparse coverage for the spaced spellings of the static, dim,
and num gang arguments.
Commit: 4180e2bb885271956e80344354b046a9b4cf3031
https://github.com/llvm/llvm-project/commit/4180e2bb885271956e80344354b046a9b4cf3031
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/include/llvm/ADT/GenericUniformityImpl.h
Log Message:
-----------
[UniformityAnalysis] Make divergent-exit cycle print order deterministic (#210107)
Once the set spills to the heap its iteration order follows allocation
addresses, so the printed order is nondeterministic.
Fix https://reviews.llvm.org/D130746 ("RFC: Uniformity Analysis for
Irreducible Control Flow")
Commit: 74dee943ac272caa4cd80a2a23c7f866dd96b4ec
https://github.com/llvm/llvm-project/commit/74dee943ac272caa4cd80a2a23c7f866dd96b4ec
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
A llvm/test/tools/llvm-reduce/remove-funcs-inline-history.ll
M llvm/tools/llvm-reduce/deltas/ReduceFunctions.cpp
Log Message:
-----------
[llvm-reduce] Fix !inline_history verifier issues (#199373)
We'd RAUW a function which would cause !inline_history metadata nodes to
be `ptr null` which doesn't pass the verifier.
Instead we can keep around metadata usages of the function with
replaceNonMetadataUsesWith().
Commit: 8da6ab53c7533b9bc1e8eb5a2c8eaf195c45c0b3
https://github.com/llvm/llvm-project/commit/8da6ab53c7533b9bc1e8eb5a2c8eaf195c45c0b3
Author: UebelAndre <github at uebelandre.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M utils/bazel/.bazelrc
M utils/bazel/llvm-project-overlay/clang-tools-extra/include-cleaner/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/lit_test.bzl
A utils/bazel/llvm-project-overlay/llvm/utils/lit/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/utils/lit/tests/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/tblgen.bzl
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
[bazel] Updated lit_test to work from external workspaces (#204489)
This change should not change the behavior of tests but instead ensure
that no matter where a test is run (either as an external repo or as an
overlay from `./utils/bazel`) that the rendered source paths are correct
for that context.
Commit: 202cb24d246a871e7ae0b5ebf900582d76e7a334
https://github.com/llvm/llvm-project/commit/202cb24d246a871e7ae0b5ebf900582d76e7a334
Author: Qiongsi Wu <qiongsiwu at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticSerializationKinds.td
M clang/lib/Serialization/ASTReader.cpp
M clang/unittests/Serialization/ModuleCacheTest.cpp
Log Message:
-----------
[clang][Modules] Adding Specific Diagnostics when a Finalized PCM is Out-of-date due to Input File Changes (#209857)
We have good diagnostics coverage when a pcm cannot be dropped in
`ASTReader::readASTCore`, because we call `canRecoverFromOutOfDate` to
check if the pcm is finalized or not. This check is missing for input
file changes.
This PR fixes the diagnostics, so we do not fall to the generic error
`err_module_rebuild_finalized`, which is hard to reason and act on.
Commit: a730dda7d520cff562e77efbe02b5bba470a2b36
https://github.com/llvm/llvm-project/commit/a730dda7d520cff562e77efbe02b5bba470a2b36
Author: Qiongsi Wu <qiongsiwu at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/include/clang/Basic/AtomicLineLogger.h
M clang/include/clang/DependencyScanning/DependencyScanningService.h
M clang/include/clang/DependencyScanning/DependencyScanningWorker.h
M clang/include/clang/DependencyScanning/InProcessModuleCache.h
M clang/include/clang/Serialization/InMemoryModuleCache.h
M clang/include/clang/Serialization/ModuleCache.h
M clang/lib/DependencyScanning/DependencyScannerImpl.cpp
M clang/lib/DependencyScanning/DependencyScanningWorker.cpp
M clang/lib/DependencyScanning/InProcessModuleCache.cpp
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Serialization/InMemoryModuleCache.cpp
M clang/lib/Serialization/ModuleCache.cpp
M clang/lib/Tooling/DependencyScanningTool.cpp
A clang/test/ClangScanDeps/logging-drop-pcm.c
A clang/test/ClangScanDeps/logging-simple-by-name.c
A clang/test/ClangScanDeps/logging-simple.c
A clang/test/ClangScanDeps/logging-two-threads.c
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
M clang/tools/clang-scan-deps/Opts.td
M clang/unittests/Basic/AtomicLineLoggerTest.cpp
M clang/unittests/DependencyScanning/InProcessModuleCacheTest.cpp
M clang/unittests/Serialization/InMemoryModuleCacheTest.cpp
Log Message:
-----------
[clang][DependencyScanning] Logging Dependency Scanning Events (#195896)
This PR sets up an `AtomicLineLogger` (added by
https://github.com/llvm/llvm-project/pull/205395) to log the sequence of
dependency scanning events. The logging is triggered by a new `LogPath`
option in `DependencyScanningServiceOptions`. This PR adds an option
`-log-path=` to `clang-scan-deps` to trigger the log.
We are logging 16 events during dependency scanning.
| Event | Logged In | When |
|-------|-----------|------|
| `starting scanning command: <args>` | `DependencyScanningWorker.cpp` |
Start of each TU scan |
| `finished scanning command: <args>` | `DependencyScanningWorker.cpp` |
End of each TU scan |
| `init_compiler_instance_with_context: <args>` |
`DependencyScanningTool.cpp` | CompilerInstanceWithContext created for
by-name scanning |
| `start scan_by_name: <module name>` | `DependencyScanningTool.cpp` |
Start of a by-name module query |
| `finish scan_by_name: <module name>` | `DependencyScanningTool.cpp` |
End of a by-name module query |
| `module_compile_thread: parent=<TID> pcm_compile: <pcm path>` |
`CompilerInstance::compileModule` | A new thread is created to compile a
pcm |
| `timestamp_read: <pcm path>` |
`InProcessModuleCache::getModuleTimestamp` | Validation timestamp read |
| `timestamp_write: <pcm path>` |
`InProcessModuleCache::updateModuleTimestamp` | Validation timestamp
update |
| `pcm_write: <pcm path>` | `InProcessModuleCache::write` | PCM write to
disk attempted |
| `pcm_read_disk: <pcm path>` | `InProcessModuleCache::read` | PCM read
from disk attempted |
| `pcm_read_cached: <pcm path>` | `InMemoryModuleCache::lookupPCM` | PCM
looked up in in-memory cache |
| `pcm_add: <pcm path>` | `InMemoryModuleCache::addPCM` | PCM added to
cache (not validated) |
| `pcm_add_built: <pcm path>` | `InMemoryModuleCache::addBuiltPCM` | PCM
added to cache (final) |
| `pcm_finalized: <pcm path>` | `InMemoryModuleCache::finalizePCM` | PCM
marked as validated/final |
| `pcm_dropped: <pcm path>` | `InMemoryModuleCache::tryToDropPCM` | PCM
dropped (validation failed) |
| `pcm_not_dropped: <pcm path>` | `InMemoryModuleCache::tryToDropPCM` |
PCM not dropped (validation failed, but already final) |
In addition to checking the logger's functionality,
`clang/test/ClangScanDeps/logging-simple.c` checks against the change
committed by https://github.com/llvm/llvm-project/pull/177062. Without
https://github.com/llvm/llvm-project/pull/177062,
`clang/test/ClangScanDeps/logging-simple.c` fails.
This implementation adds a single instance of `AtomicLineLogger` to the
`DependencyScanningService`. Most of the plumbing goes into the
`ModuleCache` and its derived classes.
Assisted-by: claude-opus-4.6
rdar://39907408
Commit: 908b5931ce3d9630ae3b897bd4c523945038fdcd
https://github.com/llvm/llvm-project/commit/908b5931ce3d9630ae3b897bd4c523945038fdcd
Author: Nikita Terentev <svet58585 at mail.ru>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/test/CodeGen/PowerPC/builtins-ppc-fma.c
M clang/test/CodeGen/PowerPC/builtins-ppc-fpconstrained.c
Log Message:
-----------
[NFC][Clang][PowerPC] Fix suspicious unsequenced volatile accesses in codegen tests (#199338)
When trying to add new Sema check in PR
https://github.com/llvm/llvm-project/pull/180955 some tests failed.
The following pattern is observed in these tests:
```
volatile x;
x = __builtinXXX(x, x, x);
```
For C and C++ standards order of evaluate funcall argument is
unsequence(or indeterminate sequence) and unsequence access for same
volatile variable is UB(because read volatile qualified variable is
side-effects).
As far as I undestand, unsequenced accesses is unwanted and new warning
is correct.
This PR try to fix it for tests:
```
\clang\test\CodeGen\PowerPC\builtins-ppc-fma.c
\clang\test\CodeGen\PowerPC\builtins-ppc-fpconstrained.c
```
Topics on discourse:
https://discourse.llvm.org/t/suspicious-use-volatile-qualified-variable-in-clang-codegen-tests/90837
Closed similar issue for SystemZ :
https://github.com/llvm/llvm-project/issues/186584
Commit: dd2e6e03c75918dce69e9d1f46e7b356ef31c60d
https://github.com/llvm/llvm-project/commit/dd2e6e03c75918dce69e9d1f46e7b356ef31c60d
Author: Alexander Richardson <mail at alexrichardson.me>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
Log Message:
-----------
[RISCV][RVY] Fix DwarfRegAlias for X10_Y to X15_Y (#210104)
The initial commit had typos here missing the leading 1.
This was not noticed since we don't have any tests yet that
emit .cfi_offset etc.
Fixes 5eb3969c7a0b192d74bf4730f854d4cfc25a6c77
Commit: 409f15dbb1d3853fb563e6ac902a1067411c8b9f
https://github.com/llvm/llvm-project/commit/409f15dbb1d3853fb563e6ac902a1067411c8b9f
Author: Alex Langford <alangford at apple.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M lldb/include/lldb/Core/Section.h
M lldb/source/API/SBSection.cpp
M lldb/source/Commands/CommandObjectMemory.cpp
M lldb/source/Plugins/ObjectFile/ELF/ELFHeader.cpp
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Target/SectionLoadList.cpp
M lldb/source/Target/Target.cpp
M lldb/tools/lldb-test/lldb-test.cpp
Log Message:
-----------
[lldb] Section::GetName should return a StringRef (#209926)
Section currently owns a ConstString to hold onto its name. I plan on
changing this in the future, but first I want to remove ConstString from
its API. This commit starts with `GetName`.
Commit: 03c539c79af2d917be5f5120fb49e714d0f23101
https://github.com/llvm/llvm-project/commit/03c539c79af2d917be5f5120fb49e714d0f23101
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
Log Message:
-----------
[RISCV] Use MCRegister. NFC (#210110)
Commit: 5d99b0a9a79dd72ae45b88a7815edaf600808698
https://github.com/llvm/llvm-project/commit/5d99b0a9a79dd72ae45b88a7815edaf600808698
Author: Mauri de Souza Meneguzzo <mauri870 at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M compiler-rt/lib/tsan/rtl/tsan_interface.h
M compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
Log Message:
-----------
[tsan][go]: add a128 store, load, compare_exchange (#196833)
This commit adds a128 load, store and compare_exchange to the Go
sanitizer functions. This is needed for a new Go atomic type that
operate on 16-byte values.
The SANITIZER_GO macro was gating a128 and is now lifted. Based on the
__TSAN_HAS_INT128 macro definition, the only architecture excluded by it
that intersects with [Go race support
](https://go.dev/doc/articles/race_detector#Requirements) is s390x.
For https://github.com/golang/go/issues/61236
Commit: fb908ede5170c8eadb4ff86b491ca48a23f23c17
https://github.com/llvm/llvm-project/commit/fb908ede5170c8eadb4ff86b491ca48a23f23c17
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaTemplate.cpp
M clang/test/CXX/temp/temp.param/p10-2a.cpp
Log Message:
-----------
Add fallback type for Constrained placeholders other than plain auto. (#209893)
We were diagnosing this and leave the type in place, but that broke
invariants when
looking it up later. This patch just sets a fallback type to just the
'auto' (or a supported
type at least) instead, so that we gracefully continue.
Fixes: #208658
Commit: 55fc45605710c642cf49a732f7d96a95c120db9f
https://github.com/llvm/llvm-project/commit/55fc45605710c642cf49a732f7d96a95c120db9f
Author: Farid Zakaria <farid.m.zakaria at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
Log Message:
-----------
[NFC] Refactor when selecting x86-64 EH encoding to be less prone to error (#210109)
Use a case-scoped local (EHCM) rather than mutating the object file's
code model, so only the EH encoding selection is affected.
Commit: f6ed48325939e40940fccce886e5414d26b7114e
https://github.com/llvm/llvm-project/commit/f6ed48325939e40940fccce886e5414d26b7114e
Author: hulxv <hulxxv at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M libc/src/__support/math/CMakeLists.txt
M libc/src/__support/math/acos.h
M libc/src/__support/math/acosbf16.h
M libc/src/__support/math/acosf.h
M libc/src/__support/math/acospif.h
M libc/src/__support/math/asin.h
M libc/src/__support/math/asin_utils.h
M libc/src/__support/math/asinbf16.h
M libc/src/__support/math/asinf.h
M libc/src/__support/math/asinpi.h
M libc/src/__support/math/asinpif.h
M libc/src/__support/math/atan2f.h
M libc/src/__support/math/atan2f16.h
M libc/src/__support/math/atan_utils.h
M libc/src/__support/math/atanf.h
R libc/src/__support/math/inv_trigf_utils.h
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[libc][math] reduce duplicated inv trig helpers (#191364)
Instead of duplicate inv trig helpers for float and double. we can unify
them when that is possible and drop inv_trigf_utils after moving helpers
to asin_utils and atan_utils. That makes everything clean.
Commit: dce66b626c98c2c85b77b6b77cef24adc4f01460
https://github.com/llvm/llvm-project/commit/dce66b626c98c2c85b77b6b77cef24adc4f01460
Author: Damian Rouson <rouson at lbl.gov>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M flang/docs/FortranStandardsSupport.md
Log Message:
-----------
[Flang] [Docs] Update DO CONCURRENT status (#209299)
Update the documentation of
1. `reduce` locality support
2. `do concurrent` support (link to implementation details).
---------
Co-authored-by: Dan Bonachea <dobonachea at lbl.gov>
Co-authored-by: Tarun Prabhu <tarunprabhu at gmail.com>
Commit: 37cf7d04a3a7ec460aabed51a9a383d60bc63572
https://github.com/llvm/llvm-project/commit/37cf7d04a3a7ec460aabed51a9a383d60bc63572
Author: Zhen Wang <zhenw at nvidia.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M flang/lib/Lower/ConvertCall.cpp
A flang/test/Lower/CUDA/cuda-managed-func-result.cuf
Log Message:
-----------
[flang][cuda] Fix invalid host free of managed allocatable function results (#209945)
An allocatable function result with a CUDA data attribute is allocated
with the CUDA allocator, but the caller freed the temporary with a host
`free` (via `hlfir.destroy` → `fir.freemem`), corrupting the heap.
Release it through the CUDA-aware deallocation (`cuf.deallocate`)
instead.
Commit: 5f371b2add3e2784e6e9921b42842e2a6622e24e
https://github.com/llvm/llvm-project/commit/5f371b2add3e2784e6e9921b42842e2a6622e24e
Author: Anshil Gandhi <95053726+gandhi56 at users.noreply.github.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-flat-scratch-svs.mir
Log Message:
-----------
[AMDGPU] Fold constant offset into SV form addressing in SVS frame index fallback (#208629)
Depends on #208624 (which depends on #208612).
In the SVS fallback path of `SIRegisterInfo::eliminateFrameIndex` for
flat scratch, the scratch address was materialized by moving the full
frame offset into the scavenged vaddr VGPR and forcing the
instruction's immediate offset to `0`, which also silently dropped
any pre-existing immediate offset on the instruction.
This splits the full constant offset with `TII->splitFlatOffset`, folding
as much as possible into the SV form instruction's immediate offset
field and materializing only the remainder (plus the frame register,
if any) into the vaddr VGPR.
Test: adds `scratch_{store,load}_svs_split_offset` to
`eliminate-frame-index-flat-scratch-svs.mir` (non-zero instruction
offset, now preserved and folded) and regenerates the existing checks.
Made with [Cursor](https://cursor.com)
Resolves https://github.com/llvm/llvm-project/issues/178968
Commit: d4f4524291d734c4b3ddb55d205c6fffeefbea6a
https://github.com/llvm/llvm-project/commit/d4f4524291d734c4b3ddb55d205c6fffeefbea6a
Author: Ayokunle Amodu <ayokunle321 at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx1250.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
Log Message:
-----------
[CIR][AMDGPU] Add support for AMDGCN exp2 builtins (#198025)
Adds codegen support for the following AMDGCN exp2 builtins:
- __builtin_amdgcn_exp2f (float)
- __builtin_amdgcn_exp2_bf16 (bfloat16)
These are lowered to the corresponding `llvm.amdgcn.exp2` intrinsic.
Commit: 4c50e41095b36cfa2e362a4f1990c4df59533836
https://github.com/llvm/llvm-project/commit/4c50e41095b36cfa2e362a4f1990c4df59533836
Author: DylanFleming-arm <85629460+DylanFleming-arm at users.noreply.github.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M libc/src/mathvec/abi_prefix.h
Log Message:
-----------
[libc][mathvec] Fix missing ABI-prefix from causing errors (#210127)
abi_prefix.h throws errors for unsupported ABI targets. This patch
modifies that behaviour to instead fall back onto a default
naming scheme instead, as to not break non-vfabi supporting targets.
Commit: 6563d2500c82deb27c7dab9bc17334de777f8cbc
https://github.com/llvm/llvm-project/commit/6563d2500c82deb27c7dab9bc17334de777f8cbc
Author: David CARLIER <devnexen at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_internal.h
M compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_libcdep.cpp
M compiler-rt/lib/sanitizer_common/tests/sanitizer_symbolizer_test.cpp
Log Message:
-----------
[sanitizer_common] fix shadowed ret hiding symbolizer read failures. (#209971)
The inner `bool ret` from ReadFromFile shadowed the outer one that is
returned, so a dead/closed symbolizer (0-byte read or read error) was
reported as success: SendCommand never restarted the crashed process,
and the addr2line path aborted on a CHECK over an empty buffer.
Regression from acfeb1a6c244. Add a regression test that feeds an EOF fd
through ReadFromSymbolizer and expects failure.
Commit: e1fa984ae0a87cf6de3b656496ced466b35995c0
https://github.com/llvm/llvm-project/commit/e1fa984ae0a87cf6de3b656496ced466b35995c0
Author: Mariusz Borsa <wrotki at msn.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
A compiler-rt/test/asan/TestCases/Darwin/atos-canary-symbolize.cpp
Log Message:
-----------
[Sanitizers][Darwin] Add atos-canary test (#209338)
We've observed tests using atos symbolizer ocasionally failing for
several test runs on x86_64 machines, then stabilizing again. We were
unable to reproduce
this with local builds, so it's unclear what the root cause is.
To help investigate similar failures in the future, we're adding a test
exercising atos itself. Should atos start to fail again, this test
should fail too, and provide way more info helping debugging than other
tests do
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
---------
Co-authored-by: Mariusz Borsa <m_borsa at apple.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Commit: 5fc5c2e4cde7ca12cbbd3868a8c24e0bbfcf570a
https://github.com/llvm/llvm-project/commit/5fc5c2e4cde7ca12cbbd3868a8c24e0bbfcf570a
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGExprCXX.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/CodeGenModule.h
M clang/test/CodeGenCXX/microsoft-vector-deleting-dtors.cpp
M clang/test/CodeGenCXX/microsoft-vector-deleting-dtors2.cpp
A clang/test/CodeGenCXX/msvc-global-delete-forwarding-at-delete-site.cpp
M clang/test/CodeGenCXX/msvc-global-delete-scalar-array-split.cpp
M clang/test/CodeGenCXX/msvc-global-delete-scope-no-dtor.cpp
M clang/test/CodeGenCXX/msvc-no-global-delete-forwarding.cpp
Log Message:
-----------
[clang][win] Fix __global_delete wrappers for Arm64EC and cross-TU ::delete (#209585)
PR #188372 made Clang's MSVC-ABI deleting-destructor path route global
deletes
through compiler-generated __global_delete / __global_array_delete
wrappers
instead of referencing ::operator delete directly. This lets a deleting
destructor be emitted in environments (e.g. kernel mode) where no global
::operator delete exists: each wrapper defaults to a trapping
__empty_global_delete fallback, and a real forwarding body that calls
::operator delete is materialized only when the program actually uses
::delete.
This change refines how those wrappers and their fallbacks are emitted,
fixing
two problems that made the #188372 mechanism fail in practice.
New behavior:
- The trapping fallback is now emitted as a weak GlobalAlias to
__empty_global_delete rather than via an /alternatename directive. This
lowers
to a COFF weak-external-with-default -- exactly what MSVC emits -- so a
real
__global_delete defined in any TU overrides the fallback in every other
TU at
link time.
- A ::delete expression now registers the wrapper for its resolved
global
operator delete directly (in EmitCXXDeleteExpr), so the strong
forwarding body
is emitted in that TU regardless of where the class's deleting
destructor is
defined. This matches MSVC, which emits the forwarder at every ::delete
site.
Bugs fixed:
1. Arm64EC (miscompile -> LNK2019). /alternatename only names the plain
symbol,
not the backend-generated "$$h" hybrid EC symbol referenced by the exit
thunk, so Arm64EC images left __global_delete$exit_thunk unresolved. The
weak
GlobalAlias correctly produces the "$$h" symbol, exit thunk, and plain
alias
(verified on both x64 and Arm64EC).
2. Cross-TU ::delete (runtime crash). Previously the forwarding body was
only
emitted in a TU that *both* emitted a matching vector deleting
destructor and
contained a ::delete. A TU that only performed `::delete p` -- with the
class
defined elsewhere -- emitted no forwarder, so nothing overrode the
weak-alias
trap and the program executed a trapping __empty_global_delete at
runtime
(STATUS_ILLEGAL_INSTRUCTION). Registering the wrapper at the ::delete
site
fixes this.
To share wrapper-creation logic between the deleting-destructor path and
the
delete-expression path, getOrCreateMSVCGlobalDeleteWrapper is promoted
from a
static helper in CGClass.cpp to a CodeGenModule method.
Verified end-to-end: a weak alias in one TU and a strong forwarder in
another
resolve to the forwarder under both lld-link and MSVC link.exe, and the
previously-crashing delete-only TU now runs cleanly.
Commit: db43e54c966ce9146a05bc0e8cb1550f65f89e35
https://github.com/llvm/llvm-project/commit/db43e54c966ce9146a05bc0e8cb1550f65f89e35
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/reproducer-remarks.ll
M llvm/test/Transforms/ConstraintElimination/trunc.ll
Log Message:
-----------
[ConstraintElim] Add trunc nuw support to condition checks (#209844)
Adding support for trunc nuw %x to i1 by using the m_ICmpLike pattern in
conditions the same way as icmp ne %x, 0
proof: https://alive2.llvm.org/ce/z/ZyDWZ2
Commit: da6f3e6cc2565e4c6cf720931845c8eee132ce86
https://github.com/llvm/llvm-project/commit/da6f3e6cc2565e4c6cf720931845c8eee132ce86
Author: Ikhlas Ajbar <iajbar at quicinc.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp
A llvm/test/CodeGen/Hexagon/rdfopt-liveins-hang.mir
Log Message:
-----------
[Hexagon] Fix HexagonRDFOpt hang during live-in recomputation (#209986)
After HexagonRDFOpt, the compiler recomputed live-in registers for every
block in one batch. On large inputs (e.g. kernel builds) this was slow,
and on some functions each pass changed the live-in values of other
blocks, triggering more passes until the compiler hung (PR #207422).
Fix: process blocks one at a time in post-order (successors before
predecessors) and stop as soon as nothing changes. Add a pass limit as a
safety net to keep compile time bounded in all cases.
Commit: c0b8c59b65afd268f286f56ef71f6433ac47dfd1
https://github.com/llvm/llvm-project/commit/c0b8c59b65afd268f286f56ef71f6433ac47dfd1
Author: David CARLIER <devnexen at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M compiler-rt/lib/memprof/memprof_allocator.cpp
A compiler-rt/test/memprof/TestCases/memprof_histogram_tail_clear.cpp
A compiler-rt/test/memprof/TestCases/memprof_nonhistogram_tail_clear.cpp
Log Message:
-----------
[compiler-rt][memprof] clear histogram tail granule on allocation. (#208911)
ClearShadow rounded the size down, leaving the partial tail counter
(ceil(size/8)-th) uncleared, so a recycled chunk leaked a stale count
into the last histogram bucket. Round up instead.
Commit: e59415baa96d15415a230d1c438c722dca71516e
https://github.com/llvm/llvm-project/commit/e59415baa96d15415a230d1c438c722dca71516e
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/X86/mul-shl-nsw-intmin.ll
Log Message:
-----------
[SLP][NFC]Add tests with incorrect nsw propagation in shl/mul, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/210145
Commit: 909ba8d3508cf7177da65a4d1399f7bc5a3a4b98
https://github.com/llvm/llvm-project/commit/909ba8d3508cf7177da65a4d1399f7bc5a3a4b98
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/test/CodeGen/AMDGPU/bf16-math.ll
Log Message:
-----------
[AMDGPU] Select upper 16-bits for inline constants in packed BF16 (#209861)
>From gfx1250 software programming guide, v_pk_*_bf16 instructions using
inline constants must use OPSEL to select the upper 16-bits.
Fixes: LCOMPILER-2445
Commit: 8116ab2889d74f25b8c5c0f0dbd7f6bb3aabfc8c
https://github.com/llvm/llvm-project/commit/8116ab2889d74f25b8c5c0f0dbd7f6bb3aabfc8c
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/test/Transforms/InstCombine/sincos.ll
Log Message:
-----------
[InstCombine] Use getInsertionPointAfterDef to get sin/cos InsertPt. (#210130)
The current logic added in
https://github.com/llvm/llvm-project/pull/194616
picks an incorrect insert point for the argument is an invoke.
Use getInsertionPointAfterDef and bail out if there is no such insert
point.
Fixes crashes in the added tests.
Fixes https://github.com/llvm/llvm-project/issues/210111
Commit: 85cc99660cf051157f0ce50e3a976312b1f829bd
https://github.com/llvm/llvm-project/commit/85cc99660cf051157f0ce50e3a976312b1f829bd
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/mul-shl-nsw-intmin.ll
Log Message:
-----------
[SLP]Drop nsw when shl by BW-1 is converted to mul
shl nsw X, BW-1 is valid at X = -1, but mul X, INT_MIN is not nsw-safe
there. Drop nsw on the vector mul when a shl lane with shift amount
BW-1 is unified into mul during opcode interchange.
Fixes #210093
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/210152
Commit: e78a880505ca0c9ed102fc48100b4cdb280f4e34
https://github.com/llvm/llvm-project/commit/e78a880505ca0c9ed102fc48100b4cdb280f4e34
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
Log Message:
-----------
[RISCV][P-ext] Make undef vectors Legal. (#210106)
Add a few additional isel patterns to avoid false dependencies. We may
want to enable the BreakFalseDep pass in the future.
Commit: 152fdb8ae8725dab7e529c5cedec1d5151506307
https://github.com/llvm/llvm-project/commit/152fdb8ae8725dab7e529c5cedec1d5151506307
Author: Scott Manley <rscottmanley at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M mlir/lib/Dialect/OpenACC/Transforms/ACCCGToGPU.cpp
Log Message:
-----------
[OpenACC] emit NYI for multi-rank or non-memref type array reduction (#210143)
This should be an NYI and not an assertion
Commit: 1387002dc6bee9b9f4b430afebc4141a0f603bb1
https://github.com/llvm/llvm-project/commit/1387002dc6bee9b9f4b430afebc4141a0f603bb1
Author: Muhammad Bassiouni <60100307+bassiounix at users.noreply.github.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/lib/Parse/ParseExprCXX.cpp
M clang/lib/Parse/ParseStmt.cpp
Log Message:
-----------
[Clang][NFC] Update diagnostic handling for C2y compatibility in parser (#209920)
Follow-up on #198244 after #209241
Commit: a11e3727f82f1395e7554f348c76a9af5f05b0b5
https://github.com/llvm/llvm-project/commit/a11e3727f82f1395e7554f348c76a9af5f05b0b5
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV][P-ext] Remove redundant shuffle lowering for packed widening high-half convert. (#210128)
The more general lowerVECTOR_SHUFFLEAsPZip can handle this case.
Commit: d9d1d919de92b1086b583168b4edccfa19bc854d
https://github.com/llvm/llvm-project/commit/d9d1d919de92b1086b583168b4edccfa19bc854d
Author: Alex Duran <alejandro.duran at intel.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M offload/plugins-nextgen/level_zero/src/L0Plugin.cpp
Log Message:
-----------
[OFFLOAD][L0] Don't return error on initImpl if library/drivers are missing (#210083)
When a Level Zero driver is not present in the environment the current
behavior makes olInit fail if the level_zero plugin is requested. This
changes the behavior to match other plugins where it doesn't fail but
return 0 supported devices.
Commit: 44e3f3cb248de5c1a071182367ee719baf3683df
https://github.com/llvm/llvm-project/commit/44e3f3cb248de5c1a071182367ee719baf3683df
Author: Akshay K <iit.akshay at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/test/CIR/CodeGen/ternary-throw.cpp
Log Message:
-----------
[CIR] Fix use-after-free when emitting ternary with a throw-expression arm (#208850)
Fixes #208848.
When a conditional operator arm is a noreturn expression, such as
`throw`, `VisitAbstractConditionalOperator` saved an insertion point in
the empty dead-code block created after the expression. The intent was
to insert a `cir.yield` later, once the types of both arms were known.
However, `LexicalScope::cleanup()` removes that empty block when the
arm’s scope exits, leaving the deferred insertion point with a dangling
block pointer.
Avoid saving the insertion point for noreturn arms. These regions
already terminate with `cir.unreachable` and do not require a
`cir.yield`. The CIR verifier accepts ternary regions that terminate
with `cir.unreachable`.
Extended `ternary-throw.cpp` with scalar-rvalue cases covering `throw`
in either arm and in both arms. The existing tests only covered glvalue
conditionals, which take the LValue emission path and never reach this
code.
Commit: b74a97cae97a7732df5bcdef3d09f08a2e586468
https://github.com/llvm/llvm-project/commit/b74a97cae97a7732df5bcdef3d09f08a2e586468
Author: firmiana <firmiana402 at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M lldb/source/Expression/DWARFExpression.cpp
M lldb/unittests/Expression/DWARFExpressionTest.cpp
Log Message:
-----------
[lldb] Produce generic results for DWARF relational operations (#210122)
DWARF relational operations produce a generic result, whose width is the
target address size. LLDB currently assigns the C++ `bool` comparison
result directly to `Scalar`; because `Scalar` has no `bool` constructor,
this creates a 32-bit integer even on 64-bit targets.
The stricter binary operand checks added in #201288 exposed this in
x86-64 `_sigtramp` CFI. A later `DW_OP_plus` combines a 64-bit generic
address with the 32-bit relational result, so evaluation fails and
signal-frame unwinding stops. The generic-operand relaxation in #209641
does not cover this case because the relational result is narrower than
the address size.
Convert the results of `DW_OP_eq`, `DW_OP_ge`, `DW_OP_gt`, `DW_OP_le`,
`DW_OP_lt`, and `DW_OP_ne` through the existing `to_generic` helper.
## Testing
Add a unit test that evaluates each relational opcode with an 8-byte
address size and then consumes its result with `DW_OP_plus`.
Commit: 5b46dcf59375181dee1fbd6e1d1cdb3f0c8f5289
https://github.com/llvm/llvm-project/commit/5b46dcf59375181dee1fbd6e1d1cdb3f0c8f5289
Author: Ilya Leoshkevich <iii at linux.ibm.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/include/llvm/DWP/DWP.h
M llvm/lib/DWP/DWP.cpp
A llvm/test/tools/llvm-dwp/SystemZ/big_endian_info_v5.s
M llvm/test/tools/llvm-dwp/X86/compress.test
Log Message:
-----------
[llvm-dwp] Fix endianness issues (#203424)
llvm-dwp fails on SystemZ, which is big-endian, as follows:
$ cat min.c
int main() {}
$ clang -g -O0 -gsplit-dwarf min.c -o min
$ llvm-dwp -e min -o min.dwp
error: compile unit exceeds .debug_info section range: 905969668 >= 58
This is because it hardcodes IsLittleEndian=true in multiple places. Fix
by forwarding endianness of the current object file.
Add a SystemZ-specific test.
Add proper big-endian support to X86/compress.test and add an
explanation regarding what the hardcoded blobs are and how they are
generated.
Commit: c9a9737dee777f5fe19131911e8ca3c8ca3c7031
https://github.com/llvm/llvm-project/commit/c9a9737dee777f5fe19131911e8ca3c8ca3c7031
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
A lld/docs/DTLTO.md
R lld/docs/DTLTO.rst
A lld/docs/ELF/large_sections.md
R lld/docs/ELF/large_sections.rst
A lld/docs/ELF/linker_script.md
R lld/docs/ELF/linker_script.rst
A lld/docs/ELF/start-stop-gc.md
R lld/docs/ELF/start-stop-gc.rst
A lld/docs/ELF/warn_backrefs.md
R lld/docs/ELF/warn_backrefs.rst
A lld/docs/MachO/index.md
R lld/docs/MachO/index.rst
A lld/docs/MachO/ld64-vs-lld.md
R lld/docs/MachO/ld64-vs-lld.rst
A lld/docs/NewLLD.md
R lld/docs/NewLLD.rst
A lld/docs/ReleaseNotes.md
R lld/docs/ReleaseNotes.rst
A lld/docs/WebAssembly.md
R lld/docs/WebAssembly.rst
A lld/docs/error_handling_script.md
R lld/docs/error_handling_script.rst
A lld/docs/index.md
R lld/docs/index.rst
A lld/docs/missingkeyfunction.md
R lld/docs/missingkeyfunction.rst
A lld/docs/windows_support.md
R lld/docs/windows_support.rst
Log Message:
-----------
[docs] Rename LLD docs to Markdown (#209894)
Tracking issue: https://github.com/llvm/llvm-project/issues/201242
Migration guide docs:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
RFC:
https://discourse.llvm.org/t/rfc-make-myst-markdown-the-llvm-docs-format-rip-rest/90840
This is the initial straight rename commit. It will probably break the
docs build, but it has to be a separate PR for blame preservation
purposes.
Commit: f8107f628360eb0c7c4a04af98e768ffa637c1b3
https://github.com/llvm/llvm-project/commit/f8107f628360eb0c7c4a04af98e768ffa637c1b3
Author: Tim Corringham <timothy.corringham at amd.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/test/AST/HLSL/Textures-AST.hlsl
M clang/test/CodeGenHLSL/resources/Textures-GetDimensions.hlsl
M clang/test/CodeGenHLSL/resources/Textures-Load.hlsl
M clang/test/SemaHLSL/Resources/RWTexture2D-mips-errors.hlsl
M clang/test/SemaHLSL/Resources/RWTexture2D-unsupported-methods-errors.hlsl
M clang/test/SemaHLSL/Resources/Textures-GetDimensions.hlsl
M clang/test/SemaHLSL/Resources/Textures-Load-errors.hlsl
Log Message:
-----------
[HLSL] Implement RWTexture2DArray (#208725)
Add front-end support for RWTexture2DArray, and update related tests to
include coverage of this resource.
Fixes #194947
---------
Co-authored-by: Tim Corringham <tcorring at amd.com>
Commit: ab35099249433e55ba586285c2087d0bd7f65e9c
https://github.com/llvm/llvm-project/commit/ab35099249433e55ba586285c2087d0bd7f65e9c
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M lld/docs/DTLTO.md
M lld/docs/ELF/large_sections.md
M lld/docs/ELF/linker_script.md
M lld/docs/ELF/start-stop-gc.md
M lld/docs/ELF/warn_backrefs.md
M lld/docs/MachO/index.md
M lld/docs/MachO/ld64-vs-lld.md
M lld/docs/NewLLD.md
M lld/docs/ReleaseNotes.md
M lld/docs/WebAssembly.md
M lld/docs/conf.py
M lld/docs/error_handling_script.md
M lld/docs/index.md
M lld/docs/missingkeyfunction.md
M lld/docs/windows_support.md
Log Message:
-----------
[docs] Rewrite LLD docs to Markdown (#209897)
Tracking issue: #201242
This is a stacked PR based on #209894 , which will be a standalone
commit that renames *.rst -> *.md before this PR lands for history
preservation purposes. See the [migration guide] for more information.
[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
This was prepared with rst2myst plus LLM-assisted cleanup. I paged
through all the generated HTML looking for migration artifacts, and all
of the differences I could find appear to be formatting error
corrections. Please spot check my work and approve if it looks good.
Commit: d49307497bbf9f49e6a603c605319dc39113c51c
https://github.com/llvm/llvm-project/commit/d49307497bbf9f49e6a603c605319dc39113c51c
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
M flang/test/Fir/CUDA/cuda-constructor-2.f90
Log Message:
-----------
[flang][cuda] Register allocator when cuf.allocate or cuf.deallocate are present (#210147)
Commit: fe616e4d87cfbce9317537aa95e6068ac103a373
https://github.com/llvm/llvm-project/commit/fe616e4d87cfbce9317537aa95e6068ac103a373
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M libc/config/linux/aarch64/headers.txt
M libc/config/linux/arm/headers.txt
M libc/config/linux/i386/headers.txt
M libc/config/linux/riscv/headers.txt
M libc/config/linux/x86_64/headers.txt
M libc/include/CMakeLists.txt
A libc/include/alloca.yaml
M libc/include/llvm-libc-macros/CMakeLists.txt
A libc/include/llvm-libc-macros/alloca-macros.h
M libc/test/include/CMakeLists.txt
A libc/test/include/alloca_test.cpp
Log Message:
-----------
[libc] Implement alloca.h header (#210150)
Implemented the alloca.h header for LLVM libc.
* libc/include/llvm-libc-macros/alloca-macros.h: Defined alloca macro
using __builtin_alloca.
* libc/include/alloca.yaml: Added header specification.
* libc/include/CMakeLists.txt,
libc/include/llvm-libc-macros/CMakeLists.txt: Registered the new header
and macro targets.
* libc/config/linux/*/headers.txt: Enabled the header for Linux targets
(x86_64, aarch64, arm, i386, riscv).
* libc/test/include/alloca_test.cpp, libc/test/include/CMakeLists.txt:
Added and registered functional unit tests.
Tested by running the new unit and hermetic tests.
Assisted-by: Automated tooling, human reviewed.
Commit: c96a176dd15690ed8181c6764b26d0303008a40f
https://github.com/llvm/llvm-project/commit/c96a176dd15690ed8181c6764b26d0303008a40f
Author: Mauri de Souza Meneguzzo <mauri870 at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M compiler-rt/lib/tsan/rtl/tsan_interface.h
Log Message:
-----------
[tsan] Enable __TSAN_HAS_INT128 on s390x and mips64 (#197319)
The s390x exclusion was added in
https://github.com/llvm/llvm-project/commit/b17673816d7f65e07015489993b22049e36b04db
(https://reviews.llvm.org/D105629)
citing lack of hardware 128-bit atomics. s390x does have the CDSG
instruction,
but `alignof(__int128) == 8` on the s390x psABI while CDSG requires
16-byte
alignment, so Clang does not define
`__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16` for
this target. The mips64 exclusion has been present since
`__TSAN_HAS_INT128` was
introduced in
https://github.com/llvm/llvm-project/commit/06bbca9ec4bbc5a103c94c4973797ea4ddf944b5
(https://reviews.llvm.org/D18543) with no documented
rationale. Clang similarly does not define
`__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16`
for mips64.
Both exclusions are unnecessary. When
`__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16` is
not defined, all a128 operations use the SpinMutex-based emulation path,
which
serializes 128-bit accesses under a global lock without requiring any
hardware
CAS16 support.
Verified with Clang (targets: s390x-linux-gnu, mips64-linux-gnuabi64,
mips64el-linux-gnuabi64): all three produce the full set of 12
`__tsan_atomic128_*` symbols with zero `__sync_*_16 / __atomic_*_16`
libcall references.
Runtime testing has not been performed as I lack access to these
architectures.
Relates https://github.com/llvm/llvm-project/pull/196833
For https://github.com/golang/go/issues/61236
Commit: 58db4cea87114268cca4c2957232de7db9327ceb
https://github.com/llvm/llvm-project/commit/58db4cea87114268cca4c2957232de7db9327ceb
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/masked-blended-loads.ll
Log Message:
-----------
[SLP][NFC]Add a test with GEPs under the same select condition, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/210173
Commit: 7cfe30df768f109dbaead1ed5f7538c10ba65d2e
https://github.com/llvm/llvm-project/commit/7cfe30df768f109dbaead1ed5f7538c10ba65d2e
Author: Kevin Bravo <kbravjr at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/docs/ReleaseNotes.md
M llvm/docs/TableGen/ProgRef.rst
M llvm/lib/TableGen/Record.cpp
M llvm/test/TableGen/true-false.td
Log Message:
-----------
[TableGen] Short-circuit !cond operator (#208942)
Fixes #163213
TableGen `!cond` operator currently resolves all subsequent conditions
and values even if it already found a condition that resolves to `true`.
This change short-circuits on the first `true` resolution found
iterating from left to right. It folds a new `CondOpInit` with only the
conditions and values that have already been resolved, including the
current condition and value.
Commit: f6f08fa7e5d56aa07f9ebc51500f2c9fd6df8e1b
https://github.com/llvm/llvm-project/commit/f6f08fa7e5d56aa07f9ebc51500f2c9fd6df8e1b
Author: Matsu <47756807+khaki3 at users.noreply.github.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Lower/CUDA/cuda-implicit-managed-alloc.cuf
Log Message:
-----------
[flang][cuda] Use managed allocation for saved locals (#210133)
Example:
```fortran
subroutine work
real, allocatable, save :: q(:)
allocate(q(10))
end
```
`SAVE` gives the local allocatable descriptor static storage. Implicitly
attributing it as Unified causes allocation to look it up as a
registered CUDA global, but no device symbol is registered for the
descriptor.
Fix: use Managed attribution for saved subprogram-local allocatables and
pointers, avoiding the invalid CUDA symbol lookup.
Commit: aaa4ebd2ad174920ddce67c4641292a44788e879
https://github.com/llvm/llvm-project/commit/aaa4ebd2ad174920ddce67c4641292a44788e879
Author: John Paul Jepko <john.jepko at ericsson.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/AST/ComputeDependence.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
M clang/test/Analysis/bstring.c
M clang/test/Analysis/malloc.c
M clang/test/Analysis/pr22954.c
M clang/test/Sema/builtin-memcpy.c
M clang/test/Sema/builtin-object-size.c
M clang/test/Sema/warn-fortify-source.c
A clang/test/Sema/warn-stringop-overread-fortify.c
A clang/test/Sema/warn-stringop-overread.c
M clang/test/SemaCXX/warn-memset-bad-sizeof.cpp
M compiler-rt/test/asan/TestCases/Windows/issue64990.cpp
Log Message:
-----------
[Clang][Sema] Reland -Wstringop-overread with computeDependence fix (#208012)
Reland #183004 and follow-up #205201 (reverted in #207840) which adds `-Wstringop-overread` to warn when memory functions `memcpy`, `memmove`, `memcmp`, and other related builtins read more bytes than the source buffer size.
The revert was due to a crash when a memory function is called on `&x` where `x` is a static constexpr local inside a template. The original PR exposed a bug in `computeDependence(UnaryOperator*)` where only the value-dependence bit is set for this case, when the instantiation-dependence bit should also be set. This is the root cause behind the crash.
Fix `computeDependence` to properly set both value and instantiation-dependence bits, and add a regression for this crash via `warn-stringop-overread.c`.
Commit: 68f703f3e58a52c41b39dfc654a675560b6c5614
https://github.com/llvm/llvm-project/commit/68f703f3e58a52c41b39dfc654a675560b6c5614
Author: Daniel Kiss <daniel.kiss at arm.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/docs/UsersManual.md
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/ARM.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/CodeGen/AArch64/branch-protection-attr.c
M clang/test/CodeGen/AArch64/sign-return-address.c
M clang/test/Driver/aarch64-security-options.c
M clang/test/Preprocessor/aarch64-target-features.c
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/TargetParser/ARMTargetParserCommon.h
M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
M llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
M llvm/lib/TargetParser/ARMTargetParserCommon.cpp
M llvm/test/CodeGen/AArch64/sign-return-address.ll
A llvm/test/CodeGen/AArch64/windows-pac-invalid-a-key.ll
M llvm/test/CodeGen/AArch64/wineh-bti.ll
Log Message:
-----------
[AArch64][COFF] Branch-protection=standard/pac-ret means "b-key" on Windows (#203989)
On AArch64 Windows the `B-key` is the only supported key for userspace,
let's make "standard" and "pac-ret" options generate "b-key".
Fixes: #203852
Commit: 95ff1fa00ed4c35b3589fa92b591e02444fcc5d5
https://github.com/llvm/llvm-project/commit/95ff1fa00ed4c35b3589fa92b591e02444fcc5d5
Author: Anshil Gandhi <95053726+gandhi56 at users.noreply.github.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/test/CodeGen/AMDGPU/add-max.ll
M llvm/test/CodeGen/AMDGPU/uaddsat.ll
Log Message:
-----------
[AMDGPU] Lower uniform uaddsat.i32 to SALU insts (#210168)
Map uaddsat.i32(i32 %a, i32 %b) to the following:
```
s_not_b32 s4, s17 ; s17 = %b
s_min_u32 s4, s16, s4 ; s16 = %a
s_add_u32 s4, s4, s17
```
Co-authored-by: Shilei Tian <i at tianshilei.me>
Commit: 0acbbccdbd5b5a218b459acc9abc6b3dc7f338a6
https://github.com/llvm/llvm-project/commit/0acbbccdbd5b5a218b459acc9abc6b3dc7f338a6
Author: Brad Smith <brad at comstyle.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/test/Driver/aarch64-features.c
M clang/test/Driver/aarch64-fmv.c
M clang/test/Driver/linux-ld.c
Log Message:
-----------
[Android] Drop workarounds for older Android API levels pre 23 (#161893)
Drop workarounds for Android API levels pre 23.
The minimum Android API currently supported by the LTS NDK is 23.
Commit: 7812fef524a0aef0b34599c2eb81b66843fbcdd8
https://github.com/llvm/llvm-project/commit/7812fef524a0aef0b34599c2eb81b66843fbcdd8
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
A llvm/test/CodeGen/RISCV/rvp-widening-convert-isel.ll
Log Message:
-----------
[RISCV][P-ext] Add RISCVISD::PWZIP for RV32. (#210134)
This node takes 2 32-bit vector inputs and produces a 64-bit vector
result. By extracting the subvector during lowering, we expose more
opportunities for optimizations.
Commit: 5978ac06a2cc75025703008c373fc7c94246f7a3
https://github.com/llvm/llvm-project/commit/5978ac06a2cc75025703008c373fc7c94246f7a3
Author: Eric Christopher <echristo at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
Log Message:
-----------
[NFC] Inline DwarfExpression frame register check (#210186)
Inline DwarfExpression frame register check as it's the only call.
Tested via make check.
Assisted by AI.
Commit: bd0395ebfe9830b1e3dc9580021fb5a3ab343a51
https://github.com/llvm/llvm-project/commit/bd0395ebfe9830b1e3dc9580021fb5a3ab343a51
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/headers/time.rst
M libc/include/sys/time.yaml
M libc/include/time.yaml
M libc/src/sys/time/CMakeLists.txt
A libc/src/sys/time/gettimeofday.h
M libc/src/sys/time/linux/CMakeLists.txt
A libc/src/sys/time/linux/gettimeofday.cpp
M libc/src/time/CMakeLists.txt
R libc/src/time/gettimeofday.h
M libc/src/time/linux/CMakeLists.txt
R libc/src/time/linux/gettimeofday.cpp
M libc/test/src/sys/time/CMakeLists.txt
A libc/test/src/sys/time/gettimeofday_test.cpp
M libc/test/src/time/CMakeLists.txt
R libc/test/src/time/gettimeofday_test.cpp
Log Message:
-----------
[libc] Move gettimeofday to sys/time.h header. (#210185)
`gettimeofday` is supposed to be declared in the `<sys/time.h>` header,
not the `<time.h>` where we've had it previously. Move the declaration
to the correct header, and move the files with implementation and unit
tests accordingly.
Note that `gettimeofday` is removed removed from POSIX-2024, but let's
keep it available for now, since there's fair amount of existing code
that still uses it.
Commit: 5ed5468f3810cd3c424eec5e9288884f67594068
https://github.com/llvm/llvm-project/commit/5ed5468f3810cd3c424eec5e9288884f67594068
Author: Eric Christopher <echristo at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
Log Message:
-----------
[NFC][LSR] Remove duplicate debug expression update (#210188)
Remove duplicate debug expression update we assigned
the same DIExpression twice so let's just remove the redundant call.
Tested via make check.
Assisted by AI.
Commit: 205a66201235c03b892e075ae548d6ea12f024a3
https://github.com/llvm/llvm-project/commit/205a66201235c03b892e075ae548d6ea12f024a3
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M clang/lib/Driver/ToolChains/MinGW.cpp
M clang/test/Driver/mingw-sysroot.cpp
Log Message:
-----------
[clang][mingw] Try both native and ARM64EC triples when looking for a sysroot on the ARM64EC target (#210017)
Similarly to MSVC, a MinGW toolchain may provide support for both ARM64
and ARM64EC in a single sysroot. Structuring the toolchain this way has
the additional advantage of seamlessly supporting linking ARM64X images.
Support this configuration in findClangRelativeSysroot.
Commit: 092ac9c0c776fc5a3eddf779643d004230260300
https://github.com/llvm/llvm-project/commit/092ac9c0c776fc5a3eddf779643d004230260300
Author: David Mentler <mentlerd at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M lldb/docs/resources/test.md
A lldb/packages/Python/lldbsuite/support/xcode.py
M lldb/packages/Python/lldbsuite/test/dotest.py
M lldb/packages/Python/lldbsuite/test/dotest_args.py
Log Message:
-----------
[lldb][test] Allow dotest.py to call for Xcode to attach (#209628)
This speeds up the debugging of API tests a little on macOS.
(AppleScript written by Claude based on Xcode.sdef)
Commit: eb819b90735b819c1afd98ab3aa14183fa57157e
https://github.com/llvm/llvm-project/commit/eb819b90735b819c1afd98ab3aa14183fa57157e
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/sub-nsw-icmp-eq-zero-reorder.ll
Log Message:
-----------
[SLP][NFC]Add a test with incorrect nsw in reordered sub feeding equal cmp, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/210204
Commit: e5c143f96b37f2215a0b07d46df7600d06a372f4
https://github.com/llvm/llvm-project/commit/e5c143f96b37f2215a0b07d46df7600d06a372f4
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/sub-nsw-icmp-eq-zero-reorder.ll
Log Message:
-----------
[SLP]Drop nsw when reordering a sub feeding icmp eq/ne 0
A sub used only by icmp eq/ne 0 is treated as commutative, so SLP may
swap its operands, and nsw does not survive a - b -> b - a (a - b can
be INT_MIN while b - a overflows).
Fixes #210177
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/210205
Commit: 396d2555ddac2d6a4885ec3ad2c73fcee00f5bd3
https://github.com/llvm/llvm-project/commit/396d2555ddac2d6a4885ec3ad2c73fcee00f5bd3
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp
M llvm/test/MC/Disassembler/WebAssembly/wasm.txt
Log Message:
-----------
[WebAssembly] Don't assert on a non-zero call_indirect table index (#210120)
WebAssemblyInstPrinter::printInst asserted that a non-symbol table
operand of call_indirect is the immediate 0, on the assumption that only
MVP single-table compilation units reach the printer. That is true for
code generated by the compiler, but the printer is shared by the
disassembler.
The disassembler must produce output for any byte sequence it is pointed
at and shouldn't abort on the operand values it decodes. A non-zero
immediate table index is both a valid encoding, from a multi-table
module, and a routine result of best-effort disassembly of a range that
is not all code, which is how I hit this in LLDB.
Print the table operand when it is a symbol or a non-zero immediate, and
omit it only for the implicit table 0. This makes the output lossless
and unambiguous, matching how a table symbol is already printed. MVP and
table-symbol output are unchanged, so there is no effect on the
compiler's assembly.
Commit: 71a7c24dec4fe7ab5eda28650cf8d9138b9ca994
https://github.com/llvm/llvm-project/commit/71a7c24dec4fe7ab5eda28650cf8d9138b9ca994
Author: Ikhlas Ajbar <iajbar at quicinc.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
A llvm/test/MC/Hexagon/relax-align.s
Log Message:
-----------
[Hexagon] Add MC lit test for dropped fixups after packet relaxation (#210157)
Test that a branch fixup is preserved when MC relaxes a packet
containing a conditional compare-and-jump due to a following .p2align
directive. Regression test for issue #163851.
Commit: 5337314b4bea4be5e86396eb21e59f4d123af175
https://github.com/llvm/llvm-project/commit/5337314b4bea4be5e86396eb21e59f4d123af175
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[WebAssembly] Port WebAssemblySetP2AlignOperandsPass
Standard NewPM pass porting.
Reviewers: dschuff, sbc100, aheejin
Pull Request: https://github.com/llvm/llvm-project/pull/209871
Commit: 0fc03f0454b5a5d6d35338a6f4d1092960d63e17
https://github.com/llvm/llvm-project/commit/0fc03f0454b5a5d6d35338a6f4d1092960d63e17
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
A bolt/docs/BOLTAArch64OptimizationStatus.md
R bolt/docs/BOLTAArch64OptimizationStatus.rst
A bolt/docs/GettingStarted.md
R bolt/docs/GettingStarted.rst
A bolt/docs/index.md
R bolt/docs/index.rst
Log Message:
-----------
[bolt][docs] Rename BOLT docs to Markdown (#210198)
Tracking issue: #201242
See the [migration guide] for more information.
[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
This is the initial straight rename commit. It will probably break the
docs build, but it has to be a separate PR for blame preservation
purposes.
Commit: 2494e80d1cd91911713ec8451a961e07b9da8b9c
https://github.com/llvm/llvm-project/commit/2494e80d1cd91911713ec8451a961e07b9da8b9c
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyFixBrTableDefaults.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[WebAssembly] Port WebAssemblyFixBrTableDefaultsPass
Standard NewPM pass porting.
Reviewers: dschuff, sbc100, aheejin
Pull Request: https://github.com/llvm/llvm-project/pull/209882
Commit: d0dd060443b657f3d96bd1b2dcd32974cccfa6fc
https://github.com/llvm/llvm-project/commit/d0dd060443b657f3d96bd1b2dcd32974cccfa6fc
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.compr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.compr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
M llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
Log Message:
-----------
[NFC] Use new target triple for some tests (#210202)
They were mistakenly reverted back to the old ones.
Commit: 565ef24d6c1b31e2fbf736b2b115d49d49b86af7
https://github.com/llvm/llvm-project/commit/565ef24d6c1b31e2fbf736b2b115d49d49b86af7
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyCleanCodeAfterTrap.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[WebAssembly] Port WebAssemblyCleanCodeAfterTrapPass
Standard NewPM pass porting.
Reviewers: sbc100, dschuff, aheejin
Pull Request: https://github.com/llvm/llvm-project/pull/209892
Commit: 03ab16cb415ff8dc2cb06332a628b79a718c74d8
https://github.com/llvm/llvm-project/commit/03ab16cb415ff8dc2cb06332a628b79a718c74d8
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M bolt/docs/BOLTAArch64OptimizationStatus.md
M bolt/docs/GettingStarted.md
M bolt/docs/index.md
Log Message:
-----------
[docs] Finish MyST migration for BOLT docs (#210199)
Tracking issue: #201242
See the [migration guide] for more information.
[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
This is a stacked PR based on #210198, which will be a standalone commit
that
renames *.rst -> *.md before this PR lands for history preservation
purposes.
This was prepared with rst2myst plus LLM-assisted cleanup. I paged
through all the generated HTML looking for migration artifacts, and all
of the differences I could find appear to be formatting error
corrections. Please spot check my work and approve if it looks good. You
can use the HTML links below to confirm it renders properly.
-----
Before/after validation links:
| Source file | Before HTML | After HTML |
| --- | --- | --- |
| `bolt/docs/BOLTAArch64OptimizationStatus.md` |
[before](https://llvmdocs.staging.reidkleckner.dev/bolt/docs-old/BOLTAArch64OptimizationStatus.html)
|
[after](https://llvmdocs.staging.reidkleckner.dev/bolt/docs/BOLTAArch64OptimizationStatus.html)
|
| `bolt/docs/GettingStarted.md` |
[before](https://llvmdocs.staging.reidkleckner.dev/bolt/docs-old/GettingStarted.html)
|
[after](https://llvmdocs.staging.reidkleckner.dev/bolt/docs/GettingStarted.html)
|
| `bolt/docs/index.md` |
[before](https://llvmdocs.staging.reidkleckner.dev/bolt/docs-old/index.html)
|
[after](https://llvmdocs.staging.reidkleckner.dev/bolt/docs/index.html)
|
Commit: 611d015f0030e0d4f1b3bd2270205f6f6b6e20eb
https://github.com/llvm/llvm-project/commit/611d015f0030e0d4f1b3bd2270205f6f6b6e20eb
Author: Peter Collingbourne <pcc at google.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/utils/gn/README.rst
M llvm/utils/gn/build/BUILD.gn
M llvm/utils/gn/build/BUILDCONFIG.gn
M llvm/utils/gn/build/buildflags.gni
M llvm/utils/gn/build/symlink_or_copy.gni
M llvm/utils/gn/build/toolchain/BUILD.gn
M llvm/utils/gn/secondary/BUILD.gn
M llvm/utils/gn/secondary/bolt/tools/driver/BUILD.gn
M llvm/utils/gn/secondary/clang-tools-extra/clang-doc/tool/BUILD.gn
M llvm/utils/gn/secondary/clang-tools-extra/clangd/xpc/framework/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
M llvm/utils/gn/secondary/clang/tools/driver/BUILD.gn
M llvm/utils/gn/secondary/lld/tools/lld/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-ar/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-cxxfilt/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-debuginfod-find/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-debuginfod/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-dwp/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-libtool-darwin/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-lipo/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-ml/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-nm/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-objcopy/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-objdump/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-rc/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-readobj/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-readtapi/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-size/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-strings/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-symbolizer/BUILD.gn
Log Message:
-----------
gn build: Support building debug binaries from a release build directory.
This change makes it so that all binaries in `bin` have a corresponding
debug binary target `$TARGET.dbg` that will build a debug binary in
`bin.dbg/$TARGET`. This is implemented using a separate toolchain for
the debug builds. This has the following advantages over a separate
debug build directory:
1. Can use release mode tblgen to generate code for the debug build
binaries, which speeds up the build because it can run tblgen faster as
well as being able to reuse the tblgen binary from the release build.
2. Can reuse runtimes built in the release mode clang's resource
directory, avoiding the need to build them again with a slow debug
build of clang.
Assisted-by: gemini
Reviewers: aeubanks, nico
Reviewed By: aeubanks
Pull Request: https://github.com/llvm/llvm-project/pull/197843
Commit: a45ae4cf77776bdae8ab79c3b5b4d4ef7cbd7d99
https://github.com/llvm/llvm-project/commit/a45ae4cf77776bdae8ab79c3b5b4d4ef7cbd7d99
Author: lntue <lntue at google.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M libc/src/__support/FPUtil/Hypot.h
M libc/src/__support/math/hypot.h
M libc/test/src/math/smoke/hypot_test.cpp
Log Message:
-----------
[libc][math] Fix double-rounding errors with denormal inputs for hypot function. (#208247)
The issue was reported by Paul Zimmermann.
Solution: for denormal inputs, we use 1.0 + x trick after proper scaling
to mimick rounding at denormal scale.
Commit: eafc387c1da0620642f469fde70455c554ba3470
https://github.com/llvm/llvm-project/commit/eafc387c1da0620642f469fde70455c554ba3470
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M orc-rt/include/CMakeLists.txt
A orc-rt/include/orc-rt/CCallback.h
A orc-rt/test/unit/CCallbackTest.cpp
M orc-rt/test/unit/CMakeLists.txt
Log Message:
-----------
[orc-rt] Add asCCallback utility -- C callbacks for methods. (#210048)
Adds orc_rt::asCCallback<&Class::method>, which produces a C-ABI
function pointer that forwards to the given member function. The first
parameter of the generated trampoline is an opaque context pointer (
void * for non-const methods, const void * for const methods) that is
cast back to the class type and used as the receiver:
struct Counter {
void inc(int N) { Count += N; }
int Count = 0;
};
Counter C;
void (*CB)(void *, int) = asCCallback<&Counter::inc>;
CB(asCCallbackContext<&Counter::inc>(C), 2); // C.Count == 2
asCCallbackContext produces the matching context pointer via
static_cast, so any base-class offset is applied and const-ness is
preserved; pairing it with asCCallback by the same method keeps things
correct under inheritance and const-qualification. (A raw cast of &C
would give the trampoline the wrong `this` when method's class is a base
at a non-zero offset.)
Specializations cover the const x noexcept combinations. The trampoline
is always noexcept -- a C caller cannot unwind a C++ exception, so an
escaping one terminates -- and return/argument types are restricted to
C-compatible (non-reference, trivially copyable) types via
static_assert.
Commit: 5658411aed0f610380323918ce4b02016f2df6f2
https://github.com/llvm/llvm-project/commit/5658411aed0f610380323918ce4b02016f2df6f2
Author: Kaitlin Peng <kaitlinpeng at microsoft.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/lib/CodeGen/Targets/SPIR.cpp
M clang/test/CodeGenHLSL/resources/RWBuffer-imageformat.hlsl
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/test/CodeGen/SPIRV/hlsl-resources/SignedBufferLoadStore.ll
M llvm/test/CodeGen/SPIRV/hlsl-resources/UnsignedBufferLoadStore.ll
Log Message:
-----------
[SPIRV] Pack 64-bit vec2 typed buffers into 4x32-bit images (#208626)
Commit: 6b9929001d0b46d087e871934e50e4783147fa7d
https://github.com/llvm/llvm-project/commit/6b9929001d0b46d087e871934e50e4783147fa7d
Author: Amir Ayupov <aaupov at fb.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M bolt/docs/profiles.md
M bolt/include/bolt/Profile/DataReader.h
M bolt/lib/Profile/DataReader.cpp
A bolt/test/X86/profile-symbols-mode.s
Log Message:
-----------
[BOLT] Add fdata symbols mode (#209932)
Add a new fdata profile mode accepting symbol names as-is.
It addresses the UX gap surfaced by #208313 that all methods of selecting
functions to process (symbolized profile types, `-funcs*` options) expect
disambiguated local symbols.
Introduce fdata mode activated by a `symbols` header line, where each subsequent
line is a (mangled) symbol name. The names are matched against restored function
names (with disambiguation suffix stripped), and every matching function gets an
execution count of 1.
This can be used to drive selective instrumentation (`--instrument-hot-only`) or
basic linker-script style optimizations.
Symbols are stored as branch entry data so matching reuses the existing default
branch profile path.
Test Plan:
Update docs/profiles.md and add profile-symbols-mode.s
Commit: 398f2117379f42764e433d19ea0d0cd65009a4aa
https://github.com/llvm/llvm-project/commit/398f2117379f42764e433d19ea0d0cd65009a4aa
Author: Aviral Goel <aviralg at users.noreply.github.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M clang/include/clang/ScalableStaticAnalysis/Core/EntityLinker/StaticLibrary.h
M clang/include/clang/ScalableStaticAnalysis/Core/EntityLinker/TUSummaryEncoding.h
A clang/test/Analysis/Scalable/ssaf-linker/Outputs/lib-explicit-triple.json
A clang/test/Analysis/Scalable/ssaf-linker/Outputs/lib-namespace-override.json
A clang/test/Analysis/Scalable/ssaf-linker/Outputs/libempty.json
A clang/test/Analysis/Scalable/ssaf-linker/Outputs/libtwo.json
M clang/test/Analysis/Scalable/ssaf-linker/help.test
A clang/test/Analysis/Scalable/ssaf-linker/static-library-create.test
A clang/test/Analysis/Scalable/ssaf-linker/static-library-help.test
A clang/test/Analysis/Scalable/ssaf-linker/static-library-time.test
A clang/test/Analysis/Scalable/ssaf-linker/static-library-verbose.test
M clang/tools/clang-ssaf-linker/CMakeLists.txt
M clang/tools/clang-ssaf-linker/SSAFLinker.cpp
A clang/tools/clang-ssaf-linker/StaticLibraryCreateCLI.cpp
A clang/tools/clang-ssaf-linker/StaticLibraryCreateCLI.h
Log Message:
-----------
[clang][ssaf] Add static-library create subcommand (#208799)
This change adds `clang-ssaf-linker static-library create` for bundling
TU summaries into a StaticLibrary archive. The linker has been
refactored to dispatch on `cl::SubCommand`; invocations without a
subcommand still run the existing linker pipeline unchanged for backward
compatibility.
rdar://181930526
Commit: 9f839a4396916283cc28e45d18d7f4742ad5094a
https://github.com/llvm/llvm-project/commit/9f839a4396916283cc28e45d18d7f4742ad5094a
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Fix non-determinism in pointers comparison, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/210216
Commit: a07b91d8243b8a8051dbbe5739eacc7942269c61
https://github.com/llvm/llvm-project/commit/a07b91d8243b8a8051dbbe5739eacc7942269c61
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M lldb/bindings/python/CMakeLists.txt
M lldb/bindings/python/python-wrapper.swig
M lldb/docs/CMakeLists.txt
A lldb/examples/python/templates/scripted_stackframe_recognizer.py
A lldb/include/lldb/Interpreter/Interfaces/ScriptedStackFrameRecognizerInterface.h
M lldb/include/lldb/Interpreter/ScriptInterpreter.h
M lldb/include/lldb/Target/StackFrameRecognizer.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/include/lldb/lldb-forward.h
M lldb/source/Interpreter/ScriptInterpreter.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/CMakeLists.txt
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPythonInterface.cpp
A lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedStackFrameRecognizerPythonInterface.cpp
A lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedStackFrameRecognizerPythonInterface.h
M lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
M lldb/source/Target/StackFrameRecognizer.cpp
M lldb/test/API/commands/frame/recognizer/TestFrameRecognizer.py
M lldb/test/API/commands/frame/recognizer/recognizer.py
M lldb/unittests/ScriptInterpreter/Python/PythonTestSuite.cpp
Log Message:
-----------
[lldb/script] Migrate frame recognizers onto ScriptedPythonInterface (#209805)
Give `frame recognizer add -l` a formal
ScriptedStackFrameRecognizerInterface, matching the architecture already
used by ScriptedProcess, ScriptedBreakpoint, etc.: a C++ interface
header, a Python-backed implementation built on
ScriptedPythonInterface's CreatePluginObject/Dispatch machinery,
PluginManager registration, and a generatable Python ABC template
(scripted_stackframe_recognizer.py).
get_recognized_arguments' documented contract returns a plain list of
lldb.SBValue (not an lldb.SBValueList), so it bypasses the generic
Dispatch<ValueObjectListSP>() extractor and calls the SWIG bridge
directly, matching the legacy behavior exactly.
ScriptedStackFrameRecognizer now holds a single interface object created
once in its constructor and reused across every RecognizeFrame() call,
same lifecycle as before.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: 3e1948e9a528d1bc82f2a671a00c02fa8717f26f
https://github.com/llvm/llvm-project/commit/3e1948e9a528d1bc82f2a671a00c02fa8717f26f
Author: Eric Christopher <echristo at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/unittests/IR/MetadataTest.cpp
Log Message:
-----------
Add expression validation tests for DW_OP_swap (#210184)
Add DIExpression validation tests for DW_OP_swap that we noticed were
missing. The tests are based on the existing expression tests for
DW_OP_stack_value.
Tested via make check.
Assisted by AI.
Commit: b9869c8c920a7dfa983e215bc30729b13d8b353b
https://github.com/llvm/llvm-project/commit/b9869c8c920a7dfa983e215bc30729b13d8b353b
Author: Shanzhi Chen <chenshanzhi at huawei.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-64-128bit-loads.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-64-128bit-stores.ll
Log Message:
-----------
[AArch64][SVE] Support lowering masked loads/stores of <4 x bf16> and <8 x bf16> (#208744)
Add support for lowering masked loads/stores of <4 x bf16> and <8 x
bf16> when target features contain "+sve" and "+bf16".
Fixes: #201149
Commit: 464b46a73b7592c95222cf2e64b34ffe6f2cf251
https://github.com/llvm/llvm-project/commit/464b46a73b7592c95222cf2e64b34ffe6f2cf251
Author: Benjamin Luke <benjamin.luke at sony.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/Basic/ABIVersions.def
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/CodeGen/CGFunctionInfo.h
M clang/include/clang/CodeGen/CodeGenABITypes.h
M clang/lib/CodeGen/ABIInfo.h
M clang/lib/CodeGen/CGCUDARuntime.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGDeclCXX.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprCXX.cpp
M clang/lib/CodeGen/CGExprComplex.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGObjCRuntime.cpp
M clang/lib/CodeGen/CGVTables.cpp
M clang/lib/CodeGen/CodeGenABITypes.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/CodeGenTypes.h
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/lib/CodeGen/MicrosoftCXXABI.cpp
M clang/lib/CodeGen/Targets/X86.cpp
M clang/test/CodeGen/sysv_abi.c
A clang/test/CodeGen/target-avx-function-abi.c
A clang/test/CodeGenCXX/target-avx-method-abi.cpp
M clang/unittests/CodeGen/CodeGenExternalTest.cpp
M clang/unittests/CodeGen/TestCompiler.h
Log Message:
-----------
[clang][CodeGen][X86_64] Honor per-function AVX ABI in C/C++ call paths, maintain old psABI for PlayStation. (#193298)
Fixes https://github.com/llvm/llvm-project/issues/64706
Wire per function x86 AVX ABI level into CodeGen arrangement methods so
__attribute(__target("avx"))) / __attribute(__target("avx512f"))) on
methods, ctors, and free-functions affects ABI lowering consistently.
Specifically:
- Added X86AVXABILevel member to CGFunctionInfo.
- Populated X86AVXABILevel member in CGFunctionInfo objects via
arrangement methods declared in CodeGenTypes.h.
- Respect CGFunctionInfo AVX Level in X86_64ABIInfo::computeInfo.
- Add/extend regression tests for:
- free-function target-attribute AVX ABI lowering
- C++ method/ctor target-attribute AVX ABI lowering
- PS4/PS5 legacy ABI behavior (no per-function AVX ABI change)
---------
Co-authored-by: Aaron Ballman <aaron at aaronballman.com>
Commit: 7fec267c9a44c76604e1135ee0ef694c4eaae784
https://github.com/llvm/llvm-project/commit/7fec267c9a44c76604e1135ee0ef694c4eaae784
Author: sohail <sohailraj.satapathy at gmail.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M libc/test/src/stdfix/DiviFxTest.h
Log Message:
-----------
[libc][stdfix] Guard DiviFxTest shift edge cases against narrow IntType (#209970)
Fixes riscv32 buildbot failure from #206115.
Commit: 9d2181c78f4e248069e39ec0e5b899dfbfcf3d6a
https://github.com/llvm/llvm-project/commit/9d2181c78f4e248069e39ec0e5b899dfbfcf3d6a
Author: Eric Christopher <echristo at gmail.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
Log Message:
-----------
[NFC] Reuse DwarfExpression fragment (#210181)
Reuse DwarfExpression fragment information since nothing changes it
between the outside of the loop and the inside of the loop.
Tested via make check.
Assisted by AI.
Commit: 1a3347f608394b12c5a18cb5b3457af4e85449a1
https://github.com/llvm/llvm-project/commit/1a3347f608394b12c5a18cb5b3457af4e85449a1
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
[bazel][clang][ssaf] Fix 398f2117379f42764e433d19ea0d0cd65009a4aa (#210222)
Commit: 27d7b61322f1528cc582a62d1b74683d24cc987b
https://github.com/llvm/llvm-project/commit/27d7b61322f1528cc582a62d1b74683d24cc987b
Author: Harrison Hao <57025411+harrisonGPU at users.noreply.github.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/GVN.cpp
Log Message:
-----------
[GVN][NFC] Use LoadInst::getProperties() when creating PRE load (#208605)
Use load's properties via getProperties() instead of individually
forwarding isVolatile(), getAlign(), getOrdering() and getSyncScopeID().
Reference: https://github.com/llvm/llvm-project/pull/206470
Commit: 4a75259134c72d8be7fa3ea36c9dc7bfc02640ac
https://github.com/llvm/llvm-project/commit/4a75259134c72d8be7fa3ea36c9dc7bfc02640ac
Author: hev <wangrui at loongson.cn>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
A llvm/test/CodeGen/LoongArch/lasx/issue207316.ll
M llvm/test/CodeGen/LoongArch/lasx/xvexth.ll
M llvm/test/CodeGen/LoongArch/lsx/vexth.ll
Log Message:
-----------
[LoongArch] Fix invalid VEXTH combines for unsupported type extensions (#209725)
`performEXTENDCombine` could form `VEXTH`/`VEXTH_U` nodes for
unsupported type combinations, such as extending `v8i8` to `v8i32` or
`v2i64` to `v2i128`. These illegal nodes would later reach instruction
selection and trigger backend failures:
* `Cannot select: LoongArchISD::VEXTH`
* `Don't know how to legalize this operation`
Prevent these combines from firing by verifying that the destination
type is legal and has exactly twice the total bit width of the source
before forming a `VEXTH`/`VEXTH_U` node.
Apply the same checks to `performSHLCombine` for consistency.
Fixes
https://github.com/llvm/llvm-project/pull/207316#issuecomment-4978234865
Fixes
https://github.com/llvm/llvm-project/pull/207316#issuecomment-4979233899
Commit: 8aaa15e82688177db7c0c3fa06103d10f6799598
https://github.com/llvm/llvm-project/commit/8aaa15e82688177db7c0c3fa06103d10f6799598
Author: Haohai Wen <haohai.wen at intel.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/include/llvm/ObjectYAML/BBAddrMapYAML.h
M llvm/lib/ObjectYAML/BBAddrMapYAML.cpp
M llvm/lib/ObjectYAML/ELFEmitter.cpp
Log Message:
-----------
[ObjectYAML][NFC] Hoist BBAddrMap yaml2obj encoder into a shared helper (#205991)
Preparatory NFC refactor to let the upcoming COFF emitter reuse the
BBAddrMap YAML encoder.
Commit: ddd21a5500bc65354211c0088520d0b331e862d7
https://github.com/llvm/llvm-project/commit/ddd21a5500bc65354211c0088520d0b331e862d7
Author: Vijay Kandiah <vkandiah at nvidia.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M flang/include/flang/Lower/CUDA.h
M flang/lib/Lower/Allocatable.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Lower/CUDA/cuda-gpu-unified.cuf
R flang/test/Lower/CUDA/cuda-implicit-managed-alloc.cuf
Log Message:
-----------
[flang][cuda] Managed backing for -gpu=unified allocatables/pointers (#210149)
Under `-gpu=unified`, allocatables and pointers with no explicit CUDA data
attribute must be reachable from the device. Back them with CUDA managed
memory by selecting the unified allocator index at the ALLOCATE site (in
lowering), instead of stamping an implicit `Unified`/`Managed` CUDA data attribute
on the symbol in the frontend — the approach introduced in PR #209292.
This is necessary because attributing the symbol in the frontend routed every
plain allocatable/pointer through the CUDA Fortran managed descriptor
pipeline (constructor registration, `cuf.allocate`/`cuf.free`), which added
per-`ALLOCATE` overhead, forced special-casing for objects that may not legally carry a
CUDA attribute (COMMON members, derived-type components, module globals), and
changed symbol semantics used well beyond allocation. Choosing the allocator
index at the `ALLOCATE` site keeps the object a plain host allocatable/pointer while
the storage still comes from the managed allocator.
Commit: 963e226d9a6b923b10c8e328438838bd42e03d18
https://github.com/llvm/llvm-project/commit/963e226d9a6b923b10c8e328438838bd42e03d18
Author: Tom Stellard <tstellar at redhat.com>
Date: 2026-07-16 (Thu, 16 Jul 2026)
Changed paths:
M .github/workflows/release-binaries.yml
M .github/workflows/validate-release-version/action.yml
Log Message:
-----------
workflows: Fixes for release-binaries and upload-release-artifact (#209246)
There were some bugs in upload-release-artifact workflow and
release-binaries was not including this action in its checkout.
Commit: fe64fbbafc19e46ef461fac3ec0b4144a1ffc847
https://github.com/llvm/llvm-project/commit/fe64fbbafc19e46ef461fac3ec0b4144a1ffc847
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.h
Log Message:
-----------
[SLP][modularisation][NFC] Extract mask, shuffle and AA helpers into SLUtils 3/3 (#209973)
Move the mask/shuffle construction and alias-analysis free helpers out
of SLPVectorizer.cpp into SLPVectorizer/SLPUtils.{h,cpp} (namespace
llvm::slpvectorizer).
Moved:
transformScalarShuffleIndiciesToVector
getShufflevectorNumGroups
calculateShufflevectorMask
UseMask (enum)
buildUseMask
isUndefVector
doesInTreeUserNeedToExtract
getLocation
isSimple
addMask
fixupOrderingIndices
getAltInstrMask
replicateMask
RFC: https://discourse.llvm.org/t/modularizing-slpvectorizer-cpp/90922
Commit: 3c6b4870425e7b62a966ff04f51f78920adbedb8
https://github.com/llvm/llvm-project/commit/3c6b4870425e7b62a966ff04f51f78920adbedb8
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt/Session.h
M orc-rt/include/orc-rt/TaskGroup.h
M orc-rt/test/unit/SessionTest.cpp
M orc-rt/test/unit/TaskGroupTest.cpp
Log Message:
-----------
[orc-rt] Add TaskGroup::TokenSource; drop raw group accessor (#210240)
Session::managedCodeTaskGroup() returned the raw
std::shared_ptr<TaskGroup> for the managed-code group, exposing the
group's full interface -- including close() and addOnComplete() -- to
callers, even though those operations are reserved for the Session.
Add TaskGroup::TokenSource, a strong handle whose sole role is to serve
as an argument to the TaskGroup::Token constructor. Session now exposes
managedCodeTokenSource() in its place, so clients can acquire tokens (to
keep managed code alive across shutdown) without gaining the ability to
close the group or register completion callbacks.
Commit: f2ef5670cf70371153caeb0ebbeae2323a61f8e0
https://github.com/llvm/llvm-project/commit/f2ef5670cf70371153caeb0ebbeae2323a61f8e0
Author: Carl Ritson <carl.ritson at amd.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_dpp_lds_expected_active_lanes.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir
M llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
Log Message:
-----------
[AMDGPU] Refactor GFX11 VALU Mask Hazard Waitcnt Merging (#169213)
Move GFX11 SGPR VALU mask hazard waitcnt merging to the a forward scan
within the AMDGPUWaitSGPRHazard pass.
This simplifies the hazard recognizer code and allows merging of waitcnt
instructions in cases where SGPRs unaffected by pending writes are used.
In turn this greatly decreasing numbers of waits inserted in sequences
of V_CMP instructions writing SGPRs improving VALU pipeline performance.
Commit: 78ed03f555ea75d2337f618930c062f4d881a08b
https://github.com/llvm/llvm-project/commit/78ed03f555ea75d2337f618930c062f4d881a08b
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
A flang/test/Lower/global-initialization-parens.f90
Log Message:
-----------
[flang] Add lowering tests for parenthesized initial values (#209664)
Add a LIT test that baselines the current lowering of parenthesized
initial values in fir.global initializer regions. Today a parenthesized
scalar or derived constant survives constant folding as a Parentheses
node and is lowered to a fir.no_reassoc operation inside the global init
region, while parentheses around characters, array named-constants, and
structure-constructor components are stripped before lowering.
This test pins that behavior so that an upcoming change to the
initializer-lowering path shows its behavior delta explicitly and has a
regression guard.
Assisted-by: AI
Commit: 15ae01dd24261bd70947aab884098e5dcd4096dd
https://github.com/llvm/llvm-project/commit/15ae01dd24261bd70947aab884098e5dcd4096dd
Author: David Zbarsky <dzbarsky at gmail.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M clang-tools-extra/clangd/CMakeLists.txt
A clang-tools-extra/clangd/LSPBinder.cpp
M clang-tools-extra/clangd/LSPBinder.h
M llvm/include/llvm/Support/LSP/Transport.h
M llvm/lib/Support/LSP/Transport.cpp
M llvm/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn
M utils/bazel/llvm-project-overlay/clang-tools-extra/clangd/BUILD.bazel
Log Message:
-----------
[clangd][Support] Outline LSP payload decode errors (#203121)
Move failed payload handling from `clangd::LSPBinder::parse<T>` and
`llvm::lsp::MessageHandler::parse<T>` into their non-inline
`handleParseError` functions, while keeping successful payload
conversion specialized in each `parse<T>` instantiation.
For a Darwin arm64 build, stripped clangd decreased by 32,848 bytes and
`__TEXT,__text` decreased by 25,180 bytes.
`ClangdTests --gtest_filter=LSPBinderTest.*` passes, and
`llvm/lib/Support/LSP/Transport.cpp` passes a standalone syntax compile.
Work towards #202616
AI tool disclosure: Co-authored with OpenAI Codex.
Co-authored-by: OpenAI Codex <noreply at openai.com>
Commit: c488b2c2407bf29bb20f67bb8f3cf39c637d231e
https://github.com/llvm/llvm-project/commit/c488b2c2407bf29bb20f67bb8f3cf39c637d231e
Author: Sameer Sahasrabuddhe <sameer.sahasrabuddhe at amd.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/docs/AMDGPUDMAOperations.md
Log Message:
-----------
[Docs][AMDGPU] Consistent use of "wave-uniform", "per-lane" and "immediate" (#209974)
When documenting DMA operations, use consistent qualifiers
(wave-uniform, per-lane, immediate) instead of referring to SGPRs and
VGPRs.
Assisted-By: Claude Opus 4.6
Commit: a376783e2ed3a44f63991c97513711faad09525b
https://github.com/llvm/llvm-project/commit/a376783e2ed3a44f63991c97513711faad09525b
Author: maflcko <6399679+maflcko at users.noreply.github.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M compiler-rt/lib/ubsan/ubsan_diag.cpp
M compiler-rt/test/ubsan/TestCases/Integer/suppressions-nested-calls.c
Log Message:
-----------
[compiler-rt][ubsan] Fix suppressions for inlined functions (#206735)
Align suppression PC handling with getCallerLocation(), so function
suppressions identify the inlined function that caused a report.
Intentionally match only the innermost inline frame.
Extend suppressions-nested-calls.c coverage to -O1.
Fixes https://github.com/llvm/llvm-project/issues/209501
---------
Co-authored-by: MarcoFalke <*~=`'#}+{/-|&$^_ at 721217.xyz>
Commit: 30bc042395a6cf0aa1e5de4fcc625d5b8c611767
https://github.com/llvm/llvm-project/commit/30bc042395a6cf0aa1e5de4fcc625d5b8c611767
Author: maflcko <6399679+maflcko at users.noreply.github.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M compiler-rt/test/lit.common.cfg.py
Log Message:
-----------
[compiler-rt][test] Use configured Python for lit page-size probe (#209175)
Use the same Python executable configured for the test suite, rather
than relying on python3 being on PATH.
Co-authored-by: MarcoFalke <*~=`'#}+{/-|&$^_ at 721217.xyz>
Commit: c5837b469c6d6f35eb0822cd9ebd7c2aa7e2ab75
https://github.com/llvm/llvm-project/commit/c5837b469c6d6f35eb0822cd9ebd7c2aa7e2ab75
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M libc/test/src/sys/socket/linux/CMakeLists.txt
M libc/test/src/sys/socket/linux/bind_test.cpp
M libc/test/src/sys/socket/linux/connect_accept_test.cpp
M libc/test/src/sys/socket/linux/listen_test.cpp
M libc/test/src/sys/socket/linux/socket_test_support.h
M libc/test/src/sys/socket/linux/sockname_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/socket/BUILD.bazel
Log Message:
-----------
[libc][bazel] Add remaining sys/socket functions and tests (#209798)
This patch adds the following sys/socket functions and syscall wrapper
libraries to BUILD.bazel:
- accept
- accept4
- bind
- connect
- getpeername
- getsockname
- listen
- sockatmark
I'm also enabling the unit tests for these functions. Running AF_UNIX
socket tests under Bazel ran into a problem where the absolute path to
the test sandbox directory exceeds the 108-byte limit of
sockaddr_un::sun_path. To work around that, I added a TestDirectoryScope
helper that temporarily chdirs into the test directory so the tests can
use short relative filenames, and restores the original working
directory on exit.
Assisted by Gemini.
Commit: 9445ad3f91d4331eead867f8b3c9c8a3818edac0
https://github.com/llvm/llvm-project/commit/9445ad3f91d4331eead867f8b3c9c8a3818edac0
Author: Rana Pratap Reddy <RanaPratapReddy.Nimmakayala at amd.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
A clang/test/CIR/CodeGenHIP/amdgcn-buffer-rsrc-type.hip
Log Message:
-----------
[CIR][AMDGPU] Adds `__amdgpu_buffer_rsrc_t` in the buffer-resource address space (#204782)
CIR previously lowering every AMDGPU opaque pointer to
`!cir.ptr<!void>`. Now `__amdgpu_buffer_rsrc_t` lower to
`!cir.ptr<!void, target_address_space(8)>` similar to (`ptr
addrspace(8)` in LLVM IR) matching CodeGen.
This change requires for upcoming raw buffer load/store/atomic builtins.
Those builtins `__builtin_amdgcn_raw_buffer_load/store_b*,
__builtin_amdgcn_raw_ptr_buffer_atomic_*` take a
`__amdgpu_buffer_rsrc_t` as operand, and the corresponding LLVM
intrinsics expect a `ptr addrspace(8)` resource argument.
Commit: 513ac13e7e5037af4b39c8c582dd7927f4c807fc
https://github.com/llvm/llvm-project/commit/513ac13e7e5037af4b39c8c582dd7927f4c807fc
Author: SiHuaN <liyongtai at iscas.ac.cn>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M clang/lib/Headers/riscv_packed_simd.h
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
Log Message:
-----------
[Clang][RISCV] Add P extension reinterpret cast intrinsics (#210241)
Implement the "Reinterpret casts" section of the RISC-V P extension intrinsic
spec in `riscv_packed_simd.h`.
The 82 `__riscv_preinterpret_<from>_<to>` intrinsics provide
bit-pattern-preserving conversions between packed types and equal-width
scalars, and between equal-width packed types. They generate no instructions;
each is a `__builtin_bit_cast`.
Commit: 61fa8d3db491c4a864242f22ce31b730fb78ecb5
https://github.com/llvm/llvm-project/commit/61fa8d3db491c4a864242f22ce31b730fb78ecb5
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/LibcallLoweringInfo.h
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/lib/CodeGen/DwarfEHPrepare.cpp
M llvm/lib/CodeGen/ExpandIRInsts.cpp
M llvm/lib/CodeGen/LibcallLoweringInfo.cpp
M llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
M llvm/lib/CodeGen/SafeStack.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/StackProtector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
Log Message:
-----------
CodeGen: Rename LibcallLoweringModuleAnalysisResult to ModuleLibcallLoweringInfo (#210176)
Commit: 6f2bd9fd1a5e7c61893abf2f1e9246610e6a32f8
https://github.com/llvm/llvm-project/commit/6f2bd9fd1a5e7c61893abf2f1e9246610e6a32f8
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Optimizer/Transforms/CUDA/CUFDeviceFuncTransform.cpp
A flang/test/Fir/CUDA/cuda-device-func-transform-aio.mlir
Log Message:
-----------
[flang][cuda] Add option to flag descriptor I/O as error (#210170)
Descriptor I/O is too expensive in some compilation mode (nordc). Add
ability to emit an error if they are found in device code.
Commit: 02f55a9e5e4775bc17cc23f9d1e7f5ee23cf63cd
https://github.com/llvm/llvm-project/commit/02f55a9e5e4775bc17cc23f9d1e7f5ee23cf63cd
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M libc/config/linux/aarch64/headers.txt
M libc/config/linux/riscv/headers.txt
M libc/config/linux/x86_64/headers.txt
Log Message:
-----------
[libc] add net/if.h to the list of installed headers (#210021)
on aarch64, riscv and x86_64.
Commit: c571b0bd7330a4b737ad7dec31e7f2b52edd3953
https://github.com/llvm/llvm-project/commit/c571b0bd7330a4b737ad7dec31e7f2b52edd3953
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M libc/include/llvm-libc-types/struct_sockaddr_storage.h
M libc/test/src/sys/socket/linux/sockaddr_storage_test.cpp
Log Message:
-----------
[libc] Fix size of struct sockaddr_storage (#210037)
My cleverness with the union backfired as it introduced an
(architecture-specific) padding between before it. Drop the union to
avoid that.
This probably wouldn't break much as the structure exists just to
allocate space (and this made it larger), but we should fix it
nonetheless.
Commit: c4903855b64ee801d1b9caeb970921a63475c98b
https://github.com/llvm/llvm-project/commit/c4903855b64ee801d1b9caeb970921a63475c98b
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M flang-rt/CMakeLists.txt
M flang/test/Driver/fakeflang.F
M flang/tools/fakeflang/fakeflang.cpp
M runtimes/cmake/config-Fortran.cmake
Log Message:
-----------
[fakeflang] Also detect CMakeTestGNU.c (#210175)
Two fixes when using CMake < 3.28 after #209482:
* In addition to `flang`, also recognize `fakeflang` to determine
whether any workaround for CMake not completely supporting Flang is
needed. `fakeflang` is used as a shim in #209482.
* For CMake < 3.24, CMake does not reognize Flang at all and tries other
methods to detect to the compiler, including the file `CMakeTestGNU.c`.
Make `fakeflang` recognize it as a probe attempt.
This should fix the
[openmp-offload-amdgpu-clang-flang](https://lab.llvm.org/buildbot/#/builders/67)
buildbot. The buildbot is currently upgrade to a newer CMake version,
and the minimum required version of CMake will become 3.31 soon.
Commit: 250f791e7002afb308e4a59dc5ef3e1f2e1c10af
https://github.com/llvm/llvm-project/commit/250f791e7002afb308e4a59dc5ef3e1f2e1c10af
Author: Raphael Isemann <rise at apple.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M lldb/source/Plugins/SymbolLocator/DebugSymbols/SymbolLocatorDebugSymbols.cpp
Log Message:
-----------
[lldb] Fix tsan error in SymbolLocatorDebugSymbols (#209698)
g_dlsym_DBGCopyFullDSYMURLForUUID and g_dlsym_DBGCopyDSYMPropertyLists
are two globals that are lazily initialized when first used. TSan
complains that this lazy init code is not thread-safe as there is no
synchronization mechanism. In practice, the only race that can happen
here is that we initialize the same values concurrently, which should be
'safe' on any platform.
This patch moves the initialization code into a static local that
returns a const object. This makes this code thread-safe by construction
and fixes the TSan error.
It also fixes that we keep calling dlopen if the initialization fails.
That is, the `g_dlsym_DBGCopyFullDSYMURLForUUID == nullptr` will always
be true on systems where the framework doesn't exist, so this code will
try loading it on every function call and fail.
Commit: 89f5334990c5aa853fcbaa361aefe5b999e63dc5
https://github.com/llvm/llvm-project/commit/89f5334990c5aa853fcbaa361aefe5b999e63dc5
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M libc/docs/CMakeLists.txt
R libc/docs/headers/time.rst
A libc/utils/docgen/time.yaml
Log Message:
-----------
[libc][docs] Dynamically generate time.h documentation (#210197)
Removed the static time.rst file.
Added time to docgen_list in libc/docs/CMakeLists.txt. Created
libc/utils/docgen/time.yaml to define the functions.
Assisted-by: Automated tooling, human reviewed.
Commit: d68dc184b1cec0a01876b3f635bce6c25a64edf6
https://github.com/llvm/llvm-project/commit/d68dc184b1cec0a01876b3f635bce6c25a64edf6
Author: Kareem Ergawy <kergawy at nvidia.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M flang/lib/Lower/PFTBuilder.cpp
A flang/test/Lower/pre-fir-tree-assigned-goto.f90
Log Message:
-----------
[flang][PFT] record every target of an assigned GO TO (#210065)
Assigned GO TO (`go to v [, (l1, l2, ...)]`) is the third multiway
branch in the language, alongside the computed GO TO and arithmetic IF
that were addressed in PR #210012. Its PFTBuilder handler previously
did:
[&](const parser::AssignedGotoStmt &) {
eval.isUnstructured = true;
markSuccessorAsNewBlock(eval);
},
i.e. it recorded no branch targets at all -- neither `controlSuccessor`
nor `extraControlSuccessors` was populated.
Handle the assigned GO TO the same way PR #210012 handles the computed
GO TO and arithmetic IF: iterate every possible target and call
`markBranchTarget(eval, label)` for each, so that `controlSuccessor`
receives the first and `extraControlSuccessors` receives the rest.
Co-authored-by: Claude Sonnet 4.6 <noreply at anthropic.com>
Commit: d134db0b2b989a2b15f91f24acca43497dfe0919
https://github.com/llvm/llvm-project/commit/d134db0b2b989a2b15f91f24acca43497dfe0919
Author: Sean Clarke <sclarke at tenstorrent.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/Analysis/HashRecognize.cpp
M llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
M llvm/test/Analysis/HashRecognize/cyclic-redundancy-check.ll
M llvm/test/Transforms/LoopIdiom/cyclic-redundancy-check.ll
Log Message:
-----------
[HashRecognize] Remove byte-multiple trip count requirement (#210086)
The newly added carryless-multiply CRC loop optimization (#203405) does
not require a byte-multiple trip count unlike the Sarwate method which
was previously implemented. Loosen this requirement in HashRecognize and
reapply it in `optimizeCRCLoop`.
Commit: cc98c1eb84c690c65fba77b72c269a869978c898
https://github.com/llvm/llvm-project/commit/cc98c1eb84c690c65fba77b72c269a869978c898
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/include/llvm/ADT/GenericConvergenceVerifier.h
M llvm/include/llvm/ADT/GenericCycleImpl.h
M llvm/include/llvm/ADT/GenericCycleInfo.h
M llvm/include/llvm/ADT/GenericUniformityImpl.h
M llvm/include/llvm/ADT/GenericUniformityInfo.h
M llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
M llvm/include/llvm/IR/CycleInfo.h
M llvm/include/llvm/IR/GenericConvergenceVerifierImpl.h
M llvm/lib/Analysis/CFG.cpp
M llvm/lib/Analysis/UniformityAnalysis.cpp
M llvm/lib/CodeGen/MachineCycleAnalysis.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/IR/CycleInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
M llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
M llvm/lib/Transforms/Utils/FixIrreducible.cpp
Log Message:
-----------
[CycleInfo] Represent cycles by an opaque handle. NFC (#210117)
Consumers refer to a cycle by a GenericCycle pointer into
GenericCycleInfo's storage. Introduce GenericCycleRef, a value handle
wrapping the cycle's preorder index, and route every GenericCycleInfo
query and mutation through it. GenericCycle becomes an internal
implementation detail, so its storage representation can change without
touching callers.
Aided by Claude Opus 4.8, reviewed by Fable 5
Suggested by
https://github.com/llvm/llvm-project/pull/208614#pullrequestreview-4683378136
Commit: 90e31c46d005ae0a7f5968c38a9310bee499923c
https://github.com/llvm/llvm-project/commit/90e31c46d005ae0a7f5968c38a9310bee499923c
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/LTO/LTO.cpp
A llvm/test/ThinLTO/X86/Inputs/cache-defined-globals-order.ll
A llvm/test/ThinLTO/X86/cache-defined-globals-order.ll
Log Message:
-----------
[LTO] Sort DefinedGlobals in LTO cache key (#210025)
Sort the DefindeGlobals by GUID when computing the LTO cache key, to
avoid making the cache key dependent on the insertion order. This fixes
large compile-time regressions in rust incremental builds.
Alternatively one could make collectDefinedGVSummariesPerModule() work
on the sortedRange(), but as that is also used in other places, it
probably makes sense to sort locally.
The issue was introduced in 760bb06cb3cd98832f1e4e7a4eaebd98b66d2bdd.
Commit: b69dd3366863acff56b0b2efdc4c4938097bb43e
https://github.com/llvm/llvm-project/commit/b69dd3366863acff56b0b2efdc4c4938097bb43e
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M mlir/test/Integration/Dialect/Vector/CPU/compress.mlir
M mlir/test/Integration/Dialect/Vector/CPU/expand.mlir
M mlir/test/Integration/Dialect/Vector/CPU/gather.mlir
M mlir/test/Integration/Dialect/Vector/CPU/maskedload.mlir
M mlir/test/Integration/Dialect/Vector/CPU/maskedstore.mlir
M mlir/test/Integration/Dialect/Vector/CPU/scatter.mlir
Log Message:
-----------
[mlir][vector][nfc] Update integration tests (#210090)
Add comments, unify naming, remove redundant printing hooks.
Commit: 8b269587981fdc3b487cda5559ef75eeb475e613
https://github.com/llvm/llvm-project/commit/8b269587981fdc3b487cda5559ef75eeb475e613
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/test/Transforms/VectorCombine/X86/fold-signbit-reduction-cmp.ll
Log Message:
-----------
[VectorCombine][X86] Add test coverage for #209714 (#210063)
Commit: 981c0f9037fc2e1e5c70ba2cfe61128557b5eeff
https://github.com/llvm/llvm-project/commit/981c0f9037fc2e1e5c70ba2cfe61128557b5eeff
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M lldb/test/API/functionalities/thread/finish-from-empty-func/TestEmptyFuncThreadStepOut.py
M lldb/test/API/functionalities/thread/finish-from-empty-func/main.c
Log Message:
-----------
[lldb][test] Handle potential compiler differences in TestEmptyFuncThreadStepOut.py (#210050)
Fixes #195958
It was reported that this test sometimes failed in CI because lldb would
step out to line 6 instead of line 7.
Jim Ingham expained on the issue that both could be valid locations
(https://github.com/llvm/llvm-project/issues/195958#issuecomment-4384269846).
There's no garauntee that "step out" would go to the source line after
the call you step out of. All it does is go to the first location
outside of the call. If the compiler so chose, that could be on the same
line as the call.
I was not able to reproduce this failure mode, but I think it was
happening in CI before, and is possible. So I've made the test accept
line 6 or 7. Anything further than that we've gone too far and the test
will fail.
Commit: 9ee8b18b6c0758e57cedfa57e99ba85dfd247d35
https://github.com/llvm/llvm-project/commit/9ee8b18b6c0758e57cedfa57e99ba85dfd247d35
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M mlir/test/Integration/Dialect/Vector/CPU/gather.mlir
Log Message:
-----------
[mlir][vector] Fix e2e test post #210090 (#210270)
Failing bots:
* https://lab.llvm.org/buildbot/#/builders/177/builds/37626
* https://lab.llvm.org/buildbot/#/builders/116/builds/30570
Commit: 4894d4e87c332af24809b20573d880a4073b738b
https://github.com/llvm/llvm-project/commit/4894d4e87c332af24809b20573d880a4073b738b
Author: Ian Anderson <iana at apple.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M clang/include/clang/Options/Options.td
M clang/test/Driver/darwin-target-variant-sdk-version.c
Log Message:
-----------
[clang][driver] Add a -target-variant alias for -darwin-target-variant (#208388)
Swift Build uses the `-target-variant` argument which is an alias for
-darwin-target-variant that's only present in the Xcode version of
clang. Upstream it for general support and parity with swiftc.
Co-authored-by: Alex Lorenz <arphaman at gmail.com>
Commit: 12c4c0bf0269218c6ffdddae1c895f892a3e4e75
https://github.com/llvm/llvm-project/commit/12c4c0bf0269218c6ffdddae1c895f892a3e4e75
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHWEvents.def
M llvm/lib/Target/AMDGPU/AMDGPUHWEvents.h
M llvm/lib/Target/AMDGPU/AMDGPUWaitcntUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUWaitcntUtils.h
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/test/CodeGen/AMDGPU/expert_scheduling_gfx12.mir
Log Message:
-----------
[AMDGPU] Handle expert scheduling VA_VDST WAR hazards (#201619)
Handle WAR hazards where a VALU reading a VGPR is followed by a VMEM
writing the same VGPR. It is possible, though not very common, that the
VMEM will complete first. To guard against this the compiler must insert
a wait on VA_VDST.
Commit: 2580624091e36b85c162439513eef8e752217a1d
https://github.com/llvm/llvm-project/commit/2580624091e36b85c162439513eef8e752217a1d
Author: cqwrteur <oyzawqgcfc at gmail.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M libcxx/src/support/runtime/exception_pointer_msvc.ipp
Log Message:
-----------
[libcxx] avoid include Uppercase windows headers (#208903)
We should use unknwn.h and windows.h instead of Unknwn.h and Windows.h
because Linux and other non‑Windows systems treat filenames as
case‑sensitive. Windows does not, so mixed‑case includes work there but
break elsewhere. Both mingw‑w64‑crt and windows‑msvc‑sysroot provide all
Windows headers in fully lowercase, so using the lowercase forms ensures
consistent cross‑platform builds.
Fixes #208901
Commit: a3bcc010c7b7d5fa43ab7928a88312841c4322dd
https://github.com/llvm/llvm-project/commit/a3bcc010c7b7d5fa43ab7928a88312841c4322dd
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M lld/COFF/Driver.cpp
M lld/COFF/InputFiles.cpp
M lld/COFF/InputFiles.h
A lld/test/COFF/link-dll-arm64x.s
Log Message:
-----------
[LLD] [COFF] Fix linking directly against an ARM64X DLL without import library (#210080)
In mingw mode, when linking against a DLL, the user can either provide a
regular import library, or provide the actual DLL. When importing ARM64X
image, add both native and EC views to the symbol table on EC targets.
Also getMachine() on such images returns ARM64X, treat it as ARM64
instead.
Commit: f520e7083a12f0642eff8fc19fc4c90ccccc7da5
https://github.com/llvm/llvm-project/commit/f520e7083a12f0642eff8fc19fc4c90ccccc7da5
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRV.h
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
Log Message:
-----------
[SPIR-V][NewPM] Fix SPIRVEmitIntrinsics registration with the new pass manager (#209966)
Commit: 0e1b0935ff6f326ba1b9c2d23ba9fa7b41e6941d
https://github.com/llvm/llvm-project/commit/0e1b0935ff6f326ba1b9c2d23ba9fa7b41e6941d
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/test/CodeGen/SPIRV/sitofp-with-bool.ll
M llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll
Log Message:
-----------
[SPIR-V] Preserve signed i1 semantics in sitofp (#209232)
selectIToF hardcoded IsSigned=false when materializing the bool-to-int
conversion, so sitofp i1 true was miscompiled as 1.0 instead of -1.0
Commit: 5fcab35be3b450256e3b02a735900071c0b74a54
https://github.com/llvm/llvm-project/commit/5fcab35be3b450256e3b02a735900071c0b74a54
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
A llvm/test/MC/AMDGPU/amdhsa-kernel-prologue.s
M llvm/test/MC/AMDGPU/hsa-gfx1250-v4.s
M llvm/test/MC/AMDGPU/hsa-gfx1251-v4.s
Log Message:
-----------
[AMDGPU] Add assembler check for GFX1250 unclaused vmem workaround (#209517)
Warn if an entrypoint does not start with the standard workaround
sequence.
Commit: 6cafa889cd398ca70992e0df518b2414a2607327
https://github.com/llvm/llvm-project/commit/6cafa889cd398ca70992e0df518b2414a2607327
Author: Nerixyz <nerixdev at outlook.de>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M lldb/source/Plugins/SymbolFile/NativePDB/UdtRecordCompleter.cpp
M lldb/test/Shell/SymbolFile/NativePDB/Inputs/globals-fundamental.lldbinit
M lldb/test/Shell/SymbolFile/NativePDB/globals-fundamental.cpp
A lldb/test/Shell/SymbolFile/NativePDB/static-class-constants.cpp
Log Message:
-----------
[lldb][NativePDB] Use active bits for constant width (#196104)
Static constants with bit widths less than 16 (e.g. char/unsigned char)
in classes were not available. These constants are still encoded with 16
bits
([here](https://github.com/llvm/llvm-project/blob/dd145eb8997878143f648a7601741f6409330963/llvm/lib/DebugInfo/CodeView/CodeViewRecordIO.cpp#L341-L343))
even though they only need less bits. When we tried to create an
initializer for them, we'd check if the bit width (=16) was small enough
to fit into the target (<16). This would fail.
This was a problem in the following code:
```cpp
struct Foo {
// width(unsigned char) = 8, but 255 was encoded and read as 16 bit
static constexpr unsigned char u8_max = 255;
};
```
This PR fixes the issue by using `APSInt::getActiveBits` for unsigned
types and `APSInt::getSignificantBits` for signed types. They get the
number of bits required to encode the value. For example a constant 64
would need 7 bits in unsigned and 8 bits in signed types.
Commit: e8f9589942ecd93d94de2af2e875964693e55129
https://github.com/llvm/llvm-project/commit/e8f9589942ecd93d94de2af2e875964693e55129
Author: Ilia Kuklin <ikuklin at accesssoftek.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M clang/include/clang/Options/Options.td
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/dxc_debug.hlsl
M llvm/lib/MC/MCDXContainerWriter.cpp
M llvm/lib/Target/DirectX/DXILWriter/DXILWriterPass.cpp
M llvm/test/CodeGen/DirectX/ContainerData/ContainerFlags.ll
Log Message:
-----------
[Driver][DirectX] Add `/Qstrip_debug` flag (#204832)
Add the flag that removes ILDB part from the main DXContainer.
Commit: d444e3ebb8ae69cdb628be3b3b0c632f13df9a08
https://github.com/llvm/llvm-project/commit/d444e3ebb8ae69cdb628be3b3b0c632f13df9a08
Author: Chibuoyim (Wilson) Ogbonna <ogbonnachibuoyim12 at gmail.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/AST/ExprCXX.cpp
M clang/test/SemaCXX/using-decl-templates.cpp
Log Message:
-----------
[Clang][Sema] Fix crash in UnresolvedMemberExpr check (#209792)
This closes https://github.com/llvm/llvm-project/issues/209427
The test currently crashes because while iterating over the candidate
members of an unresolved member expression, `decl` is a `UsingShadowDecl`
with underlying decl as `UnresolvedUsingValueDecl`.
The current `isa<UnresolvedUsingValueDecl>(decl)` guard only checks the
outer `UsingShadowDecl` and misses the unresolved-using decl hidden
inside it, so `getAsFunction()` returns nullptr and
`cast<CXXMethodDecl>(nullptr)` asserts.
This patch checks the `UnresolvedUsingValueDecl` inside by calling
`getUnderlyingDecl()` before the guard.
This used to happen before a2794f9f363361f87a3538b90b78ff13381d5ce1.
Commit: 06effa5b965f68a24dcea8550efc86225b186f54
https://github.com/llvm/llvm-project/commit/06effa5b965f68a24dcea8550efc86225b186f54
Author: mayanksolanki393 <mayanksolanki393 at gmail.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/IR/Verifier.cpp
M llvm/test/Verifier/matrix-intrinsics.ll
Log Message:
-----------
[LLVM][Verifier] Remove constant-only matrix stride check (#207665)
Remove the verifier check requiring constant column-major matrix
load/store strides to be greater than or equal to the row count.
The stride operand is not an immarg, so the verifier must not enforce
constraints that only apply when the argument happens to be constant.
Commit: afa73e4ff6db57b0416eb44127105b8092bd01f8
https://github.com/llvm/llvm-project/commit/afa73e4ff6db57b0416eb44127105b8092bd01f8
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/eq.ll
M llvm/test/Transforms/ConstraintElimination/ne.ll
Log Message:
-----------
[ConstraintElimination] Handle equality predicates with signed system (#205331)
Equality predicate solving has been supported for quite a while, eq/ne
facts were extended to the signed constraint system more recently
(7fb97bee9269f0d4239908ac8def70be696991c6). When solving
eq/ne conditions, query the signed system as well on inconclusive
answers from the unsigned one.
Fixes: https://github.com/llvm/llvm-project/issues/205282.
Fixes: https://github.com/llvm/llvm-project/issues/63505.
Commit: 2b2df2677619cb0377d27d8b766b8fc265749345
https://github.com/llvm/llvm-project/commit/2b2df2677619cb0377d27d8b766b8fc265749345
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M lld/COFF/Driver.cpp
M lld/COFF/InputFiles.cpp
M lld/COFF/InputFiles.h
R lld/test/COFF/link-dll-arm64x.s
Log Message:
-----------
Revert "[LLD] [COFF] Fix linking directly against an ARM64X DLL without import library (#210080)" (#210299)
This reverts commit a3bcc010c7b7d5fa43ab7928a88312841c4322dd, which
breaks in asan build.
Commit: 2a006dff821342c1726fd3137f804186851a26bb
https://github.com/llvm/llvm-project/commit/2a006dff821342c1726fd3137f804186851a26bb
Author: Joel Walker <theagingboy05 at gmail.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/knownbits-vashr.mir
Log Message:
-----------
[AArch64][GlobalISel] Add sign bits for G_VASHR (#210269)
Ports the `AArch64ISD::VASHR` case from
`ComputeNumSignBitsForTargetNode` to the GlobalISel hook: an arithmetic
right shift by K adds K copies of the sign bit, so the result has
`min(SignBits(Src) + K, ScalarSizeInBits)` sign bits. `G_VASHR`'s shift
amount is always an immediate in `[1, ElementBits]`.
Follow-up to #198314, which added the `G_FCM*` cases.
Assisted by Claude (Anthropic).
Commit: a4cad33430cf5d2d03eb91ce5e41ed1b9ef7cc4d
https://github.com/llvm/llvm-project/commit/a4cad33430cf5d2d03eb91ce5e41ed1b9ef7cc4d
Author: Joel Walker <theagingboy05 at gmail.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/Support/KnownBits.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
M llvm/test/Transforms/InstCombine/known-bits.ll
Log Message:
-----------
[KnownBits] Use X < Y identity and umin(MaxX, MaxY - 1) bound in urem (#210262)
Tightens `KnownBits::urem` with the two facts `ConstantRange::urem`
already uses:
- `L % R == L` when `MaxL < MinR`: return the LHS bits unchanged. This
can propagate known one bits, which the current leading-zeros-only
reasoning never produces.
- `L % R <= umin(MaxL, MaxR - 1)`, since a zero divisor is UB: keep that
bound's leading zeros. This is one bit stronger than the per-operand
leading-zero count when `MaxR` is a power of two, and together with
`remGetLowBits` it subsumes the power-of-two-constant special case,
which is removed.
Soundness is covered by the existing exhaustive unit test (widths 1 and
4; additionally brute-forced at width 5). Across all 6480 valid width-4
KnownBits pairs, non-optimal results drop from 3332 to 2090. The
residual is number-theoretic (e.g. the exact value of `10 % 3`), out of
reach of leading-bit/range reasoning, so `CheckOptimality` stays off for
urem, as for udiv (#209360).
Assisted by Claude (Anthropic).
Commit: 671c0a275a1f304f22855fabb299090233fdbd54
https://github.com/llvm/llvm-project/commit/671c0a275a1f304f22855fabb299090233fdbd54
Author: tyan0 <takashi.yano at nifty.ne.jp>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M clang/lib/Driver/ToolChain.cpp
A clang/test/Driver/Inputs/resource_dir/lib/cygwin/libclang_rt.builtins-x86_64.a
A clang/test/Driver/Inputs/resource_dir_with_per_target_subdir/lib/x86_64-pc-windows-cygnus/libclang_rt.builtins.a
A clang/test/Driver/cygwin-print-file-name.c
Log Message:
-----------
[Clang][Driver] Fix compiler-rt library directory for cygwin (#208925)
If compiler-rt is built with `LLVM_ENABLE_PER_TARGET_RUNTIME_DIR=OFF`,
its search directory is incorrect.
Specifically, `ToolChain::getOSLibName()` returns `windows` instead of
`cygwin` in a Cygwin environment, due to falling back to getOS(). This
results in a link error against compiler-rt.
This patch makes `getOSLibName()` return `cygwin`, ensuring that
compiler-rt is linked correctly.
---------
Signed-off-by: Takashi Yano <takashi.yano at nifty.ne.jp>
Commit: 8377d59dfade3f1a4bf5779ddd90359bd4ddc249
https://github.com/llvm/llvm-project/commit/8377d59dfade3f1a4bf5779ddd90359bd4ddc249
Author: Kseniya Tikhomirova <kseniya.tikhomirova at intel.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M libsycl/src/event.cpp
M libsycl/unittests/event/event.cpp
Log Message:
-----------
[libsycl] add explicit instantiations for event::get_profiling_info (#210118)
Assisted by GH Copilot.
Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
Commit: 4d37b5bf3099d099302cce447168b3ece4efef5e
https://github.com/llvm/llvm-project/commit/4d37b5bf3099d099302cce447168b3ece4efef5e
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
M llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
Log Message:
-----------
[LV] Add additional SCEV expansion tests with AddRecs. (NFC) (#210159)
Add additional test coverage for SCEV expansion of AddRecs, including
cases where extends are needed, different start and steps, as well as
cases where the outer header is not the plan's entry block.
Commit: a9e5bb572703780e3eea4a2759104a141ea73466
https://github.com/llvm/llvm-project/commit/a9e5bb572703780e3eea4a2759104a141ea73466
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/tools/clang-ssaf-linker/BUILD.gn
Log Message:
-----------
[gn build] Port 398f2117379f (#210308)
Commit: 9a2d9c7fef47c0af321150f75d8f21db06cccb43
https://github.com/llvm/llvm-project/commit/9a2d9c7fef47c0af321150f75d8f21db06cccb43
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/test/Analysis/ScalarEvolution/exit-count-non-strict.ll
M llvm/test/Analysis/ScalarEvolution/incorrect-exit-count.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/memset-pattern.ll
M llvm/test/CodeGen/ARM/select-imm.ll
A llvm/test/Transforms/IndVarSimplify/iv-widen-addrec-flag-inferred-late.ll
Log Message:
-----------
[SCEV] Try to fold ZExt/SExt of AddRec before existing lookup. (#208805)
Move AddRec fold for ZExt & SExt before existing SCEV lookup. This can
improve results, when we constructed SCEV for a ZExt/SExt during earlier
analysis and flags on the operand AddRec have not been
refined/strengthend yet.
This improves results in some cases and fixes a regression here:
https://github.com/dtcxzyw/llvm-opt-benchmark-nightly/pull/654#discussion_r3554885279.
On a large C/C++ corpus with 32k bitcode files, ~2% more IVs get
widened, removing a large number of ZExt instructions.
Compile-time impact in the noise
https://llvm-compile-time-tracker.com/compare.php?from=167d65906cc3c636221158abe8289ab4a03dfc7d&to=381abca0d5ead4443d86287d754f47c21396a9be&stat=instructions:u
Commit: 62a932ac3e2702a5493934c6362f9e058a204557
https://github.com/llvm/llvm-project/commit/62a932ac3e2702a5493934c6362f9e058a204557
Author: Abhina Sree <Abhina.Sreeskantharajan at ibm.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
A clang/test/CodeGen/SystemZ/systemz-module.flags.c
M llvm/include/llvm/IR/Module.h
M llvm/lib/IR/Module.cpp
Log Message:
-----------
[SystemZ][z/OS] Fix zos_translation_time module flag (#210058)
The zos_translation_time flag needs to be 64-bit to handle the year 2038
problem.
Commit: 23b0281d75a4320a4e6e3d837edf94911d98d252
https://github.com/llvm/llvm-project/commit/23b0281d75a4320a4e6e3d837edf94911d98d252
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
A llvm/test/CodeGen/X86/tailcall-i686-pic.ll
Log Message:
-----------
[X86] Fix assertion failure for tail call on i686+pic (#210302)
The pattern for TCRETURNmi has a IsNotPIC predicate, but the
checkTCRetEnoughRegs() predicate that's part of the X86tcret_enough_regs
PatFrag is evaluated first, so we can't assert that PIC is disabled
here. We should just return false in that case.
Fixes https://github.com/llvm/llvm-project/issues/210300.
Commit: 38104cf836c3903647c917a5b251e938f4eadbb9
https://github.com/llvm/llvm-project/commit/38104cf836c3903647c917a5b251e938f4eadbb9
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64.h
A llvm/lib/Target/AArch64/AArch64PTrueCoalescing.cpp
M llvm/lib/Target/AArch64/AArch64PassRegistry.def
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/CMakeLists.txt
M llvm/test/CodeGen/AArch64/O3-pipeline.ll
A llvm/test/CodeGen/AArch64/sve-ptrue-coalesce.mir
Log Message:
-----------
[LLVM][SVE] Add MachineInst pass to coalesce PTRUE instructions. (#204820)
SVE predicate registers contain a bit for each byte of a data register.
When operating on bigger element types the overlaping predicate bits are
grouped together but typically only the least-significant-bit is read as
part of the operation. This means the value of the other bits does not
affect the operation, making it possible to use the result of PTRUE for
a larger element typed operation, assuming the predicate patterns are
equivalent. For example:
ADD_S (PTRUE_H 31), Z0, Z1 == ADD_S (PTRUE_S 31), Z0, Z1
AArch64PTrueCoalescingPass uses this fact to reduce the number of PTRUE
instructions in a function, with the general trend towards needing a
single PTRUE based on the smallest element type in use.
NOTE: The pass will be enabled by default using a dedicated PR to make
it easier to revert if something goes wrong.
Commit: de4f929700f8d87041e0b050ec6028f0ac5276ad
https://github.com/llvm/llvm-project/commit/de4f929700f8d87041e0b050ec6028f0ac5276ad
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86.cpp
M lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_x86.h
Log Message:
-----------
[lldb][x86] Remove GCC 6 workaround (#210317)
Added by 3bea7306e8669f94bacafae68748a9139cfc0b98.
We now require GCC >= 7.4 so it can be removed.
I tested a standalone reproducer with GCC 7.3 and
clang 5. Neither have the problem.
https://godbolt.org/z/3zKrT9c8s
Standalone reproducer:
```
struct Base {
Base(int) {}
};
struct Derived : virtual Base {
#ifdef WORKAROUND
Derived(int a): Base(a) {}
#endif
virtual void g() = 0;
};
struct Final : Derived {
Final(int n) : Base(n)
#ifdef WORKAROUND
, Derived(n)
#endif
{}
void g() override {}
};
```
Commit: b9f5bcbcfbe6aa4943c808afd3bb82243ecb3193
https://github.com/llvm/llvm-project/commit/b9f5bcbcfbe6aa4943c808afd3bb82243ecb3193
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/Basic/ABIVersions.def
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/CodeGen/CGFunctionInfo.h
M clang/include/clang/CodeGen/CodeGenABITypes.h
M clang/lib/CodeGen/ABIInfo.h
M clang/lib/CodeGen/CGCUDARuntime.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGDeclCXX.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprCXX.cpp
M clang/lib/CodeGen/CGExprComplex.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGObjCRuntime.cpp
M clang/lib/CodeGen/CGVTables.cpp
M clang/lib/CodeGen/CodeGenABITypes.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/CodeGenTypes.h
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/lib/CodeGen/MicrosoftCXXABI.cpp
M clang/lib/CodeGen/Targets/X86.cpp
M clang/test/CodeGen/sysv_abi.c
R clang/test/CodeGen/target-avx-function-abi.c
R clang/test/CodeGenCXX/target-avx-method-abi.cpp
M clang/unittests/CodeGen/CodeGenExternalTest.cpp
M clang/unittests/CodeGen/TestCompiler.h
Log Message:
-----------
Revert "[clang][CodeGen][X86_64] Honor per-function AVX ABI in C/C++ call paths, maintain old psABI for PlayStation." (#210303)
Reverts llvm/llvm-project#193298
Causes a major compile-time regression.
Commit: 75ec1a4e80a9377f8f1e2ff063b094e016787926
https://github.com/llvm/llvm-project/commit/75ec1a4e80a9377f8f1e2ff063b094e016787926
Author: Manuel Carrasco <Manuel.Carrasco at amd.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
A llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable-default-address-space.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable-init-expr.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable-multi-gve.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable-no-backing-var.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable-no-type.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable-path-null.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable-skip-static-member.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable-skip-type-not-in-regs.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable-static-member.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable.ll
Log Message:
-----------
[SPIRV] Emit NonSemantic DebugGlobalVariable (#207230)
Add emitDebugGlobalVariable to the NSDI handler, translating each
DIGlobalVariable to a
[DebugGlobalVariable](https://github.khronos.org/SPIRV-Registry/nonsemantic/NonSemantic.Shader.DebugInfo.html#DebugGlobalVariable)
ext inst.
Commit: 4f76a4c5a3f8711fe13b05c0f93ac78349396292
https://github.com/llvm/llvm-project/commit/4f76a4c5a3f8711fe13b05c0f93ac78349396292
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
Log Message:
-----------
[NFC] RelNotes Formatting fix I screwed up in 209893 (#210325)
Commit: 40ae05d4773f5c1b2a84ea7dc908d92671b8daa9
https://github.com/llvm/llvm-project/commit/40ae05d4773f5c1b2a84ea7dc908d92671b8daa9
Author: adams381 <adams at nvidia.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/unittests/CIR/CMakeLists.txt
A clang/unittests/CIR/IntTypeABIAlignTest.cpp
Log Message:
-----------
[CIR] Return power-of-two ABI alignment for non-fundamental int widths (#210187)
`cir::IntType::getABIAlignment` returns `width / 8` for non-`_BitInt`
integers. For a non-fundamental width such as `i24` it returns 3, which
is
not a power of two, so a consumer that builds an `llvm::Align` from it
would
hit the power-of-two assertion unless it rounds the value up itself.
This rounds the alignment up to a power of two inside `getABIAlignment`,
matching how LLVM's default DataLayout aligns these (an `i24` aligns
like
`i32`). The fundamental widths are unchanged (`i8` -> 1, `i16` -> 2,
`i32` -> 4, `i64` -> 8), `__int128` stays at 16, and a sub-byte width
like
`i1` now reports 1 instead of 0. A unit test pins these cases.
Commit: 1f2772f8e26beb909c2a559f1fb08697e3e06909
https://github.com/llvm/llvm-project/commit/1f2772f8e26beb909c2a559f1fb08697e3e06909
Author: Iliyan Georgiev <Iliyan.Georgiev at arm.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
Log Message:
-----------
[mlir][tosa] Add support for MXFP conv2d (#210054)
- Adds profile compliance support for MXFP conv2d
- Relax conv2d accumulator constraits. They are checked as part of
validation pass
and this would allow experimentation with different types.
Signed-off-by: Iliyan Georgiev <iliyan.georgiev at arm.com>
Commit: 6f64e7cf0ad7699a5f1e6b2418d4c2cdcdb26470
https://github.com/llvm/llvm-project/commit/6f64e7cf0ad7699a5f1e6b2418d4c2cdcdb26470
Author: Shreyansh Lodha <lodhashreyansh1603 at gmail.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M clang/lib/Parse/ParseCXXInlineMethods.cpp
M clang/lib/Parse/Parser.cpp
M clang/test/AST/ast-dump-decl.cpp
A clang/test/AST/ast-dump-deleted-defaulted-range.cpp
M clang/test/AST/ast-dump-funcs.cpp
M clang/test/AST/ast-dump-record-definition-data-json.cpp
M clang/test/Analysis/inlining/Inputs/expected-plists/path-notes.cpp.plist
M clang/test/CoverageMapping/default-method.cpp
M clang/unittests/AST/SourceLocationTest.cpp
M clang/unittests/Tooling/RecursiveASTVisitorTests/CXXMethodDecl.cpp
Log Message:
-----------
[Clang][AST] Add source range for deleted and defaulted functions (#205408)
Earlier wrong ranges for default and deleted functions were reported.
Post this fix all ranges for functions are reported.
Fix: Extended the declarator's source range to include the delete /
default tokens by calling
D.SetRangeEnd(PP.getLocForEndOfToken(KilLoc).getLocWithOffset(-1)) after
consuming each keyword in ParseFunctionDefinition. Previously, the range
ended at the function name, onitting the delete/default specifier
entirely.
Regression tested and no regressions found.
Assisted-by: Claude Code (Anthropic) — used in developing this patch.
Closes #64805
Commit: 7c1b00b38d7fb9eecfd345c51f9e9509e6b039ad
https://github.com/llvm/llvm-project/commit/7c1b00b38d7fb9eecfd345c51f9e9509e6b039ad
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
Log Message:
-----------
[AMDGPU] Fix type of SIlds / AMDGPUISD::LDS node (#210340)
iPTR means i64 here, but this node operates on 32-bit LDS addresses.
Commit: 499b69cf07e03a23a420ee773261fcfcfc1c3df9
https://github.com/llvm/llvm-project/commit/499b69cf07e03a23a420ee773261fcfcfc1c3df9
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/DWARFLinker/Parallel/DWARFLinkerCompileUnit.cpp
M llvm/lib/DWARFLinker/Parallel/DWARFLinkerUnit.h
Log Message:
-----------
[DWARFLinker] Fix data race on the per-unit file-name cache (#208967)
CompileUnit::getDirAndFilenameFromLineTable reads and mutates the unit's
FileNames DenseMap without synchronization. During the parallel
type-name assignment phase a unit's cache is touched both by its own
worker and, through cross-unit type-name references
(addReferencedODRDies calling addDieNameFromDeclFileAndDeclLine) by
other units' workers.
The concurrent find/insert/grow corrupts the map and trips the
assertion:
```
Assertion failed: (TheBucket), function findBucketForInsertion, DenseMap.h
```
Guard the cache with a mutex. Store each entry in a heap-allocated pair
so the StringRefs handed back to callers stay valid across a concurrent
rehash. Otherwise a short (small-string-optimized) file name would move
when another insertion grows the map, dangling a StringRef already
returned.
Commit: 2a00d50e6012e1ee31904d394c088be907b6aa8b
https://github.com/llvm/llvm-project/commit/2a00d50e6012e1ee31904d394c088be907b6aa8b
Author: Delaram Talaashrafi <dtalaashrafi at nvidia.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M flang/lib/Semantics/check-acc-structure.cpp
M flang/lib/Semantics/check-acc-structure.h
M flang/test/Semantics/OpenACC/acc-loop-routine-call.f90
Log Message:
-----------
[Flang][OpenACC] Check routine level for function references in loops (#209529)
Extend the loop/routine-level compatibility check to `FunctionReference`
calls. Resolve `!$acc routine` information from procedure pointers and
interface symbols, not only `SubprogramDetails`.
Commit: f1b5b061832610e78d5be7313f0ab3e5e55d790f
https://github.com/llvm/llvm-project/commit/f1b5b061832610e78d5be7313f0ab3e5e55d790f
Author: David Young <davidayoung at meta.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/docs/CommandGuide/lit.rst
M llvm/utils/lit/lit/LitConfig.py
M llvm/utils/lit/lit/TestingConfig.py
M llvm/utils/lit/lit/cl_arguments.py
M llvm/utils/lit/lit/main.py
A llvm/utils/lit/tests/Inputs/pass-env/lit.cfg
A llvm/utils/lit/tests/Inputs/pass-env/test.txt
A llvm/utils/lit/tests/pass-env.py
Log Message:
-----------
Modify lit config to allow specify extra env vars to pass through to lit invocation (#208239)
lit's pass-through environment allow-list is hard-coded in
TestingConfig.py. There are cases where a particular test environment
needs an extra variable passed through (e.g. credentials or tooling
paths required to fetch dependencies during a test), but today the only
way to add one is to fork this list downstream.
This adds a --pass-env NAME option (repeatable, and also honored via
LIT_OPTS) that copies the named variable from lit's environment into the
test environment, in addition to the built-in allow-list. Since the
caller chooses exactly which variables to forward, passing through a
wrong or sensitive variable is user error rather than a default. The
default is empty, so existing behavior — only the hard-coded list is
passed through — is unchanged.
test creation help via Claude
Commit: d7aacfc940c3f1553973f1ebf7d11a6513fda1ed
https://github.com/llvm/llvm-project/commit/d7aacfc940c3f1553973f1ebf7d11a6513fda1ed
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M lldb/include/lldb/Host/common/DomainSocket.h
M lldb/source/Host/common/DomainSocket.cpp
M lldb/unittests/Host/SocketTest.cpp
M lldb/unittests/Process/gdb-remote/GDBRemoteCommunicationServerLLGSTest.cpp
M lldb/unittests/Utility/UriParserTest.cpp
Log Message:
-----------
[lldb] Support Windows paths in AF_UNIX domain-socket URIs (#206985)
On Windows an `AF_UNIX` socket path is a native filesystem path. Placed
directly in a unix-connect:// URI it isn't a valid `host:port`
authority, so `URI::Parse` confuses the drive letter colon as a port
separator and connection setup fails.
This patch converts the path in the [RFC
8089](https://datatracker.ietf.org/doc/html/rfc8089) file-URI form
instead which parses as an ordinary URI with an empty host. DomainSocket
converts between the native path and this URI form at its boundaries.
Both are no-ops on POSIX: behavior is unchanged, and `URI::Parse` and
the GDB-remote consumers are left untouched.
rdar://180736036
Commit: 0b1652db8a18b336f39855fcf9b5137fa0b4b3c9
https://github.com/llvm/llvm-project/commit/0b1652db8a18b336f39855fcf9b5137fa0b4b3c9
Author: Kane Wang <wangqiang1 at kylinos.cn>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
A llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-xchg.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-xchg-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-xchg-rv64.mir
Log Message:
-----------
[RISCV][GlobalISel] Legalize G_ATOMICRMW_XCHG (#209983)
This commit makes `xchg` consistent with `add/and/or/xor` across all
type/extension combinations. Updates `legalizer-info-validation.mir` for
the newly defined rules and adds `atomicrmw-xchg.ll` and
`legalize-atomicrmw-xchg-rv{32,64}.mir` tests.
Commit: d05f7b28b6f7de6e9ca89e1b9e3aca8c8380e322
https://github.com/llvm/llvm-project/commit/d05f7b28b6f7de6e9ca89e1b9e3aca8c8380e322
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn
Log Message:
-----------
[gn build] Port 38104cf836c3 (#210356)
Commit: 45f76eac198fdee52d61c57e667f48a7f5e9581f
https://github.com/llvm/llvm-project/commit/45f76eac198fdee52d61c57e667f48a7f5e9581f
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/unittests/CIR/BUILD.gn
Log Message:
-----------
[gn build] Port 40ae05d4773f (#210357)
Commit: 30f270edb42c5d37e4c4a413ebfc7a6513565b30
https://github.com/llvm/llvm-project/commit/30f270edb42c5d37e4c4a413ebfc7a6513565b30
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M lld/COFF/Driver.cpp
M lld/COFF/InputFiles.cpp
M lld/COFF/InputFiles.h
A lld/test/COFF/link-dll-arm64x.s
Log Message:
-----------
[LLD] [COFF] Fix linking directly against an ARM64X DLL without import library (#210311)
In mingw mode, when linking against a DLL, the user can either provide a
regular import library, or provide the actual DLL. When linking against
an ARM64X image, add both native and EC views to the symbol table on EC
targets. Also getMachine() on such images returns ARM64X, treat it as
ARM64 instead.
Commit: 4671287932028a32caa4bce6aea35f9de3f1daa8
https://github.com/llvm/llvm-project/commit/4671287932028a32caa4bce6aea35f9de3f1daa8
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
Log Message:
-----------
[lldb][Windows] Reuse preloaded exe module on launch (#210010)
# Brief
Recreating the module everytime causes the path to be canonicalized.
This does not work well with subst drives, because the newly created
module will not have the correct drive path, causing breakpoints to be
unresolved.
# Description
`ProcessWindows::OnDebuggerConnected` derives the executable module from
`GetModuleFileNameExW` on every connect. This returns the process
image's *real* path, so when the target is created via a subst'd or
mapped drive (e.g. `S:\...\a.out`, where `S:` is subst for `C:\S`) it
comes back as `C:\S\...\a.out`. `GetOrCreateModule` then fails to match
the module LLDB had already preloaded and creates a duplicate instead.
The duplicate leaves the original module's breakpoint location orphaned
unresolved while the new module's location is resolved, so a source line
breakpoint reports two locations with only one resolved. Generic tests
that assert exactly one resolved location fail with `"2 != 1"` and
`"Expecting 1 locations, got 2"`.
# Fix
This patch fixes this by first attempting to reuse the existing module
if it exists. In practice, LLDB only looks for the executable during
attach.
This is a problem in Swiftlang where we run our tests with a subst
drive. The impacted tests are:
-
`lang/c/{array_types,function_types,set_values,enum_types,anonymous,forward,local_variables}`
- `lang/cpp/{class_types,inlines}`
- `commands/{apropos/with-process,command/nested_alias,memory/write}`
- `functionalities/{memory/find,dead-strip,memory/holes}`
- `commands/expression/entry-bp`
Commit: e57b9c0761706905e42da3cfa485cebc3629d72a
https://github.com/llvm/llvm-project/commit/e57b9c0761706905e42da3cfa485cebc3629d72a
Author: Prajwal Nadig <pnadig at apple.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M clang/include/clang/ExtractAPI/ExtractAPIVisitor.h
A clang/test/ExtractAPI/availability_typedef_anonymous_record.c
Log Message:
-----------
[ExtractAPI] Include availability attributes for anonymous typedefs (#209187)
When an anonymous type is defined and has availability attributes, the
attributes are attached to the typedef rather than the type being
defined. This patch updates the anonymous type handling logic to merge
the availability from the typedef in order to correctly include it in
the symbol graph.
rdar://125497949
Commit: 06340b81573a6824c0ddd54fcba5ae8ffacacd6f
https://github.com/llvm/llvm-project/commit/06340b81573a6824c0ddd54fcba5ae8ffacacd6f
Author: Prajwal Nadig <pnadig at apple.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M clang/include/clang/ExtractAPI/DeclarationFragments.h
M clang/lib/ExtractAPI/DeclarationFragments.cpp
A clang/test/ExtractAPI/objc_nullability.m
Log Message:
-----------
[ExtractAPI] Include nullability attributes (#209221)
Nullability attributes (nullable, nonnull, null_unspecified,
null_resettable) add valuable context about the type, and would be
useful when viewing declarations. This patch updates ExtractAPI to
include these attributes in the symbol graph.
rdar://139097216
Commit: 709b7d1bd4a71e484702d610f81b5cf84303386f
https://github.com/llvm/llvm-project/commit/709b7d1bd4a71e484702d610f81b5cf84303386f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] Pull out isFoldableAsShuffle lamdba as helper function. NFC. (#210354)
For future reuse.
Commit: de5cef3127047836fceb416f8083942783834489
https://github.com/llvm/llvm-project/commit/de5cef3127047836fceb416f8083942783834489
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.h
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
M mlir/test/Dialect/Vector/vector-reduce-to-contract.mlir
Log Message:
-----------
[mlir][vector] Extend `combineContractAndBroadcast` to accept `vector.shape_cast` (#208752)
`combineContractAndBroadcast` is a pattern that matches
`vector.contract` operations whose inputs are defined by
`vector.broadcast`, e.g.:
```mlir
%0 = vector.broadcast %lhs : vector<8x4xi32> to vector<1x8x4xi32>
%1 = vector.broadcast %rhs : vector<8x4xi32> to vector<1x8x4xi32>
%result = vector.contract {
indexing_maps = [#map0, #map1, #map2],
iterator_types = ["reduction", "parallel", "parallel", "reduction"],
kind = #vector.kind<add>
} %0, %1, %acc : vector<1x8x4xi32>, vector<1x8x4xi32> into vector<8x8xi32>
```
The pattern folds away the reduction over a unit dimension introduced by
the defining operations, producing a simplified `vector.contract`:
```mlir
vector.contract {
indexing_maps = [#[[$MAP0]], #[[$MAP1]], #[[$MAP2]]]
iterator_types = ["parallel", "parallel", "reduction"]
} %0, %1, %acc : vector<8x4xi32>, vector<8x4xi32> into vector<8x8xi32>
```
This change extends the pattern to also accept broadcast-like
`vector.shape_cast` operations:
```mlir
%0 = vector.shape_cast %lhs : vector<8x4xi32> to vector<1x8x4xi32>
%1 = vector.shape_cast %rhs : vector<8x4xi32> to vector<1x8x4xi32>
%result = vector.contract {
indexing_maps = [#map0, #map1, #map2],
iterator_types = ["reduction", "parallel", "parallel", "reduction"],
kind = #vector.kind<add>
} %0, %1, %acc : vector<1x8x4xi32>, vector<1x8x4xi32> into vector<8x8xi32>
```
Note that `mlir::vector::isBroadcastableTo` was only moved to make it
available to the newly introduced `ShapeCastOp` helper,
`ShapeCastOp::isBroadcastLike()`.
Commit: bcb459015e12fb03e4ae3d56393883b2974f96fb
https://github.com/llvm/llvm-project/commit/bcb459015e12fb03e4ae3d56393883b2974f96fb
Author: Zachary Henkel <zachary.henkel at gmail.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M compiler-rt/test/sanitizer_common/android_commands/android_common.py
M lldb/examples/python/delta.py
M lldb/examples/python/gdbremote.py
Log Message:
-----------
Replace Python's deprecated tempfile.mktemp() with secure temp APIs (#210123)
Python's tempfile.mktemp() is deprecated and insecure: it returns a path
without creating the file, leaving a TOCTOU/symlink window before the
file is opened. Replace every use, choosing the temp API by lifetime:
- compiler-rt android_common.py adb(): tempfile.TemporaryFile
(anonymous, auto-deleted), read back via seek(0); drops manual
close()/unlink().
- compiler-rt android_common.py pull_from_device():
tempfile.TemporaryDirectory so "adb pull" writes into a private,
auto-cleaned directory.
- lldb examples delta.py / gdbremote.py start_gdb_log():
tempfile.NamedTemporaryFile(delete=False); the log must outlive the call
for a later stop_gdb_log, so it is intentionally not auto-deleted.
Reported by internal static analysis and contributed upstream for the
benefit of the wider community.
Assisted-by: GitHub Copilot CLI (Claude Opus 4.8)
I do not have commit access and will need someone to submit on my
behalf.
Commit: 5f7060ce4559c1079e850c96b106f1a43955b828
https://github.com/llvm/llvm-project/commit/5f7060ce4559c1079e850c96b106f1a43955b828
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/Frontend/FrontendActions.h
M clang/include/clang/Frontend/FrontendOptions.h
M clang/include/clang/Options/Options.td
M clang/include/clang/Sema/Sema.h
R clang/include/clang/Sema/TemplateInstCallback.h
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Frontend/FrontendActions.cpp
M clang/lib/Frontend/InterfaceStubFunctionsConsumer.cpp
M clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp
M clang/lib/Parse/ParseAST.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaType.cpp
R clang/test/Templight/templight-deduced-func.cpp
R clang/test/Templight/templight-default-arg-inst.cpp
R clang/test/Templight/templight-default-func-arg.cpp
R clang/test/Templight/templight-default-template-arg.cpp
R clang/test/Templight/templight-empty-entries-fix.cpp
R clang/test/Templight/templight-exception-spec-func.cpp
R clang/test/Templight/templight-explicit-template-arg.cpp
R clang/test/Templight/templight-memoization.cpp
R clang/test/Templight/templight-nested-memoization.cpp
R clang/test/Templight/templight-nested-template-instantiation.cpp
R clang/test/Templight/templight-one-instantiation.cpp
R clang/test/Templight/templight-prior-template-arg.cpp
Log Message:
-----------
[clang] remove templight support (#210166)
Removed as unmaintained, per discussion in
https://discourse.llvm.org/t/rfc-removing-templight-support/90777
Commit: 60846c8b0c1c47c03c25fe28ecaea00e698a3450
https://github.com/llvm/llvm-project/commit/60846c8b0c1c47c03c25fe28ecaea00e698a3450
Author: Hongyu Chen <xxs_chy at outlook.com>
Date: 2026-07-18 (Sat, 18 Jul 2026)
Changed paths:
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
Log Message:
-----------
[RISCV][P-ext][NFC] Add cross-project tests for packed zip/unzip intrinsics (#209575)
Commit: a55b011dabf8e5761d9955f98aa1138a10bd1a8a
https://github.com/llvm/llvm-project/commit/a55b011dabf8e5761d9955f98aa1138a10bd1a8a
Author: Abhina Sree <Abhina.Sreeskantharajan at ibm.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M clang/test/CodeGen/SystemZ/systemz-module.flags.c
Log Message:
-----------
[SystemZ/[z/OS] Guard source-epoch related testcase to 64-bit clang targets (#210341)
This patch guards the following testcase for 64-bit clang targets Clang :: CodeGen/SystemZ/systemz-module.flags.c
Commit: d63bd842939f22fad4e29660d66b99a9bf94e4b4
https://github.com/llvm/llvm-project/commit/d63bd842939f22fad4e29660d66b99a9bf94e4b4
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
A flang/test/Fir/create-box-codegen.fir
M flang/test/Fir/fir-ops.fir
M flang/test/Fir/invalid.fir
Log Message:
-----------
[flang] Added fir.create_box operation. (#210220)
This patch adds `fir.create_box` operation that allows
creating `!fir.box<>` values with arbitrary byte strides.
It can be used to recreate boxes describing non-contiguous
arrays from descriptor components (base_addr/lbs/extents/strides)
across offload regions.
This is just initial definition and code generation code.
The folders and passes producing this operation will be added
later.
Commit: fd55bbd6022ccb8d854f580b56c39177e80c256e
https://github.com/llvm/llvm-project/commit/fd55bbd6022ccb8d854f580b56c39177e80c256e
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M compiler-rt/test/profile/Linux/counter_promo_for.c
M compiler-rt/test/profile/Linux/counter_promo_while.c
Log Message:
-----------
[compiler-rt] Fix tests after #205331 (#210370)
New optimizations changed some compiler-rt tests. Update the test
expectations based on this.
Fixes #210355.
Commit: 0b666f74f94fffc2bc3380365704bcb61f2767d2
https://github.com/llvm/llvm-project/commit/0b666f74f94fffc2bc3380365704bcb61f2767d2
Author: David Young <davidayoung at meta.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/plugin_config.bzl
Log Message:
-----------
Add missing BigArchive container plugin to lldb's bazel build (#210304)
Another missing plugin and its libraries in the LLDB bazel build. Based
this one on source/Plugins/ObjectContainer/Big-Archive/CMakeLists.txt
and its dependecies ( {}.cpp & {}.h)
waiting on CI to confirm bazel is correct as cannot build locally.
Can confirm this library will convert to BUCK internally at Meta and
build with buck2 where we do have in the default plugin list.
bazel rule assisted with: claude
Commit: 53c048b3732610c8d2d65c1d41603de26eb6ac4e
https://github.com/llvm/llvm-project/commit/53c048b3732610c8d2d65c1d41603de26eb6ac4e
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M libcxx/utils/ci/images/libcxx_release_runners.txt
Log Message:
-----------
[libc++] Update release runners to the image that was used on main at the branch point (#210378)
This will allow retaining a stable image for CI throughout the whole
LLVM 23 release.
Commit: a67eac3e141e1044dd98524a010e719b42f51f5e
https://github.com/llvm/llvm-project/commit/a67eac3e141e1044dd98524a010e719b42f51f5e
Author: Anshil Gandhi <95053726+gandhi56 at users.noreply.github.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SOPInstructions.td
Log Message:
-----------
[NFC][AMDGPU] Cleanup in SOPInstructions.td (#210367)
- Eliminate code which was accidentally merged during a merge-conflict
(https://github.com/llvm/llvm-project/pull/203155/changes#r3560059941)
- Remove comments as they are specific to usubsat.
Commit: db1f902cd6a95c9b80136dfcbe8beb7a58290641
https://github.com/llvm/llvm-project/commit/db1f902cd6a95c9b80136dfcbe8beb7a58290641
Author: Mishal Shah <mishal_shah at apple.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M .ci/compute_projects.py
M .ci/compute_projects_test.py
M .github/workflows/premerge.yaml
Log Message:
-----------
Add macOS premerge check workflow (#207435)
Added a premerge check workflow for macOS self-hosted runners to build
and test projects.
Commit: f04bf4791ae6d56b822f9bca6eb82ce4adccb989
https://github.com/llvm/llvm-project/commit/f04bf4791ae6d56b822f9bca6eb82ce4adccb989
Author: Mikhail R. Gadelha <mikhail at igalia.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M libc/src/__support/File/linux/CMakeLists.txt
M libc/src/__support/File/linux/dir.cpp
M libc/src/__support/File/linux/file.cpp
M libc/src/__support/OSUtil/linux/CMakeLists.txt
M libc/src/__support/OSUtil/linux/auxv.h
M libc/src/__support/threads/linux/CMakeLists.txt
M libc/src/__support/threads/linux/thread.cpp
M libc/src/sched/linux/CMakeLists.txt
M libc/src/sched/linux/sched_getaffinity.cpp
M libc/src/spawn/linux/CMakeLists.txt
M libc/src/spawn/linux/posix_spawn.cpp
M libc/src/stdio/linux/CMakeLists.txt
M libc/src/stdio/linux/remove.cpp
M libc/src/sys/ipc/linux/CMakeLists.txt
M libc/src/sys/ipc/linux/ftok.cpp
R libc/src/sys/ipc/linux/kernel_statx.h
M libc/src/sys/mman/linux/CMakeLists.txt
M libc/src/sys/mman/linux/shm_unlink.cpp
M libc/src/sys/time/linux/CMakeLists.txt
M libc/src/sys/time/linux/utimes.cpp
M libc/startup/linux/x86_64/CMakeLists.txt
M libc/startup/linux/x86_64/tls.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[libc][NFC] Port raw syscall users to existing syscall_wrappers (#208039)
Several call sites still invoked syscall_impl directly (or carried
their own SYS_* fallback ladders) for syscalls that already have a
wrapper in src/__support/OSUtil/linux/syscall_wrappers.
This PR removes these syscalls in favor of the syscall_wrappers.
Commit: 246c752ef1b6098a7aa222f02ca09db76e17cabe
https://github.com/llvm/llvm-project/commit/246c752ef1b6098a7aa222f02ca09db76e17cabe
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/test/src/sys/socket/BUILD.bazel
Log Message:
-----------
[bazel][libc] Add layering deps (#210380)
Not sure why CI didn't catch it, but
c5837b469c6d6f35eb0822cd9ebd7c2aa7e2ab75 adds some targets that are
broken when layering checks are enabled.
Commit: c42ce32264f94a8800f4250d7b716cca55f77df6
https://github.com/llvm/llvm-project/commit/c42ce32264f94a8800f4250d7b716cca55f77df6
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
A compiler-rt/docs/ASanABI.md
R compiler-rt/docs/ASanABI.rst
A compiler-rt/docs/BuildingCompilerRT.md
R compiler-rt/docs/BuildingCompilerRT.rst
A compiler-rt/docs/TestingGuide.md
R compiler-rt/docs/TestingGuide.rst
M flang/docs/CMakeLists.txt
A flang/docs/CommandGuide/index.md
R flang/docs/CommandGuide/index.rst
A libsycl/docs/CodingGuidelines.md
R libsycl/docs/CodingGuidelines.rst
A libsycl/docs/index.md
R libsycl/docs/index.rst
M libsycl/test/README.md
A libunwind/docs/BuildingLibunwind.md
R libunwind/docs/BuildingLibunwind.rst
M libunwind/docs/conf.py
A libunwind/docs/index.md
R libunwind/docs/index.rst
M lldb/source/Plugins/TraceExporter/common/TraceHTR.h
A lldb/source/Plugins/TraceExporter/docs/htr.md
R lldb/source/Plugins/TraceExporter/docs/htr.rst
A llvm-libgcc/docs/LLVMLibgcc.md
R llvm-libgcc/docs/LLVMLibgcc.rst
M llvm-libgcc/generate_version_script.py
M offload/docs/conf.py
A offload/docs/index.md
R offload/docs/index.rst
Log Message:
-----------
[docs] Rename misc rst docs to md (#210208)
Tracking issue: #201242
See the [migration guide] for more information.
[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
This is the initial straight rename commit.
Many of these miscellaneous .rst files are not actually part of a real
docs build, since docs/conf.py does not exist for many of them.
Commit: 9b096bb7abf7b57182ae8556451aa34dacd535ec
https://github.com/llvm/llvm-project/commit/9b096bb7abf7b57182ae8556451aa34dacd535ec
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M lldb/bindings/interfaces.swig
M lldb/include/lldb/API/LLDB.h
M lldb/include/lldb/API/SBDefines.h
A lldb/include/lldb/API/SBProtocolServer.h
M lldb/source/API/CMakeLists.txt
A lldb/source/API/SBProtocolServer.cpp
M lldb/unittests/API/CMakeLists.txt
A lldb/unittests/API/SBProtocolServerTest.cpp
Log Message:
-----------
[lldb] Add SBProtocolServer to start protocol servers programmatically (#209923)
Starting a protocol server (such as MCP, and in the future potentially
DAP) is only possible from the command line today, via `protocol-server
start`. Add an SB API so an embedder can start one in its own process
and learn where to connect.
SBProtocolServer wraps ProtocolServer::GetOrCreate/Start/Stop and
exposes the listening connection URI. This lets a tool host the engine's
protocol server in-process and talk to it as a normal client, reusing
the server's tools rather than reimplementing them.
Assisted-by: Claude
Commit: 2b6e9d261433f5ec8c49502f91d63dd7d07346c3
https://github.com/llvm/llvm-project/commit/2b6e9d261433f5ec8c49502f91d63dd7d07346c3
Author: Artem Belevich <tra at google.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/test/CodeGen/NVPTX/atomicrmw-allow-ftz-atomics.ll
M llvm/test/CodeGen/NVPTX/atomicrmw-sm60.ll
M llvm/test/CodeGen/NVPTX/atomicrmw-sm70.ll
M llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll
M llvm/test/CodeGen/NVPTX/atomicrmw.py
M llvm/test/CodeGen/NVPTX/atomics.ll
Log Message:
-----------
[NVPTX] Set default value of nvptx-allow-ftz-atomics to true (#206154)
This is a follow-up to https://github.com/llvm/llvm-project/pull/200732.
Setting the default value of nvptx-allow-ftz-atomics to true preserves
the status quo. It allows the NVPTX backend to emit native
floating-point atomic add instructions by default, rather than falling
back to the CAS loop required for strict FTZ compliance.
Correct FTZ handling forces a lot of existing code to emit CAS loops.
This introduces thread divergence, breaking code that relies on atomic
operations being non-divergent (for example, warp-wide atomic additions
followed by a load of the reduced value without explicit
synchronization).
While FTZ-correct atomic behavior is desirable as a long-term default,
introducing thread divergence into a common operation that previously
"happened to work" without synchronization is highly disruptive.
Defaulting to true makes the FTZ-correct behavior opt-in for now,
allowing users time to audit and adapt their code.
Test cases are updated to verify both enabled and disabled states of the
option, alongside the new default behavior.
Commit: 50c8f07e3eebf1ff5a1d9378d77aef5df9583293
https://github.com/llvm/llvm-project/commit/50c8f07e3eebf1ff5a1d9378d77aef5df9583293
Author: Endre Fülöp <endre.fulop at sigmatechnology.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp
A clang/test/Analysis/std-c-library-functions-non-integral-ssize_t.cpp
Log Message:
-----------
[clang][analyzer] Fix assertion failure in StdLibraryFunctionsChecker with non-integral ssize_t (#209655)
In StdLibraryFunctionsCheckers' `RangeConstraint::checkSpecificValidity`
asserted that the constrained argument type is integral. When user code
typedefs `ssize_t` to a non-integral type (e.g. `float`) even though
this violates POSIX.1-2017, which requires `ssize_t` to be a signed
integer type, the signature still matches (same canonical type) and the
assertion fires during constraint validation. Remove it and let
`validateByConstraints` gracefully reject the summary by returning
false.
Fixes #209436
Commit: 40c4fea67f49b841bd064624219efceab91b65e0
https://github.com/llvm/llvm-project/commit/40c4fea67f49b841bd064624219efceab91b65e0
Author: Krisitan Erik Olsen <kristian.erik at outlook.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Utils/SSAUpdater.cpp
A llvm/test/Transforms/SROA/sroa-self-referential-load.ll
Log Message:
-----------
[SROA] Fix assertion failure when promoting self-referential load/store (#208826)
When LoadAndStorePromoter::run processes a block where a store's value
operand is defined by the load being promoted (a self-referential cycle
in unreachable code), it sets StoredValue to the load instruction. When
it then calls replaceAllUsesWith, the doRAUW assertion fires because the
replacement value contains the value being replaced.
The single-block promotion paths in promoteSingleBlockAlloca already
guard against this with a check for ReplVal == LI, replacing with poison
instead. This patch adds the same guard to the in-block load path in
LoadAndStorePromoter::run, which was missing it. Substituting poison is
correct here since this situation only arises in unreachable code.
The regression was introduced in #135609, which added the
propagateStoredValuesToLoads path in SROA that routes through
LoadAndStorePromoter::run. LoadStoreRewriter handles aggregates and is
unrelated to this path.
Fixes #204799
Commit: 714d124d0aaf3effa3e83d01783fe0ed2cd3eea9
https://github.com/llvm/llvm-project/commit/714d124d0aaf3effa3e83d01783fe0ed2cd3eea9
Author: Hongyu Chen <xxs_chy at outlook.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
Log Message:
-----------
Revert "[RISCV][P-ext][NFC] Add cross-project tests for packed zip/unzip intrinsics" (#210401)
Reverts llvm/llvm-project#209575
Commit: 93b1240309309d5c2f8f94527ff7c7bd5df359af
https://github.com/llvm/llvm-project/commit/93b1240309309d5c2f8f94527ff7c7bd5df359af
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M compiler-rt/docs/ASanABI.md
M compiler-rt/docs/BuildingCompilerRT.md
M compiler-rt/docs/TestingGuide.md
M flang/docs/CommandGuide/index.md
M libsycl/docs/CodingGuidelines.md
M libsycl/docs/index.md
M libunwind/docs/BuildingLibunwind.md
M libunwind/docs/index.md
M lldb/source/Plugins/TraceExporter/docs/htr.md
M llvm-libgcc/docs/LLVMLibgcc.md
M offload/docs/conf.py
M offload/docs/index.md
Log Message:
-----------
[docs] Finish misc MyST migration (#210209)
Tracking issue: #201242
See the [migration guide] for more information.
[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
This is a stacked PR based on #210208, which is the standalone rename
commit for this miscellaneous Markdown migration batch.
This was prepared with rst2myst plus LLM-assisted cleanup. LLDB man
pages are intentionally left as reStructuredText because LLDB man-page
building should not take on Markdown parser dependencies.
Unfortunately, many of these miscellaneous docs do not have working
standalone doc build targets, so I was not able to render HTML for all
of them. I think the scope is small enough that this is reviewable by
hand.
Commit: 91bb8f4ee8452d3e2bda7544556fa66dba462414
https://github.com/llvm/llvm-project/commit/91bb8f4ee8452d3e2bda7544556fa66dba462414
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/test/Transforms/LoopVectorize/VPlan/RISCV/expand-scev.ll
M llvm/test/Transforms/LoopVectorize/VPlan/dissolve-replicate-regions.ll
Log Message:
-----------
[VPlan] Introduce vputils::doesGeneratePerAllLanes (#199047)
Introduce a query for recipes that produce scalar values for all VF
lanes, returning true for non-single-scalar replicates, non-first-lane
SIVSteps, and a couple of VPInstructions.
Commit: 93bce300db95e4fbb82b1a6ef69fe125c71b77f3
https://github.com/llvm/llvm-project/commit/93bce300db95e4fbb82b1a6ef69fe125c71b77f3
Author: Ayokunle Amodu <ayokunle321 at gmail.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx1250.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
Log Message:
-----------
[CIR][AMDGPU] Add support for AMDGCN log builtins (#198032)
Adds codegen support for the following AMDGCN log builtins:
- __builtin_amdgcn_logf (float)
- __builtin_amdgcn_log_bf16 (bfloat16)
These are lowered to the corresponding `llvm.amdgcn.log` intrinsic.
Commit: 3e55f3c56e8706fa12792b5a4de05f636bf798d0
https://github.com/llvm/llvm-project/commit/3e55f3c56e8706fa12792b5a4de05f636bf798d0
Author: Jackson Stogel <jtstogel at gmail.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M libc/test/UnitTest/HermeticTestUtils.cpp
M libc/test/src/stdlib/CMakeLists.txt
M libc/test/src/stdlib/realpath_test.cpp
Log Message:
-----------
[libc][realpath][test] Create test files/directories (#209369)
Follow-up PRs will add path validation etc to `realpath`, which will
require paths to exist in the filesystem.
This PR bumps the memory limit in `HermeticTestUtils.cpp`. The realpath
unit tests allocate quite a few strings, and since memory in hermetic
tests is never freed, the unit test quickly reaches the limit.
Commit: 4070621c866fb4156f7c7d15039d12a4295f46c2
https://github.com/llvm/llvm-project/commit/4070621c866fb4156f7c7d15039d12a4295f46c2
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.cpp
M flang/lib/Optimizer/OpenACC/Support/RegisterOpenACCExtensions.cpp
A flang/test/Transforms/OpenACC/acc-implicit-declare-type-descriptor-create-box.fir
Log Message:
-----------
[flang][OpenACC] Discover type descriptors referenced by fir.create_box (#210393)
Register the IndirectGlobalAccess interface for fir.create_box so
acc-implicit-declare finds the derived-type type-descriptor global a
create_box of a record array needs on the device, as it already does
for fir.embox and fir.rebox.
Assisted-by: Cursor
Commit: 14bb933c87a193471d54336c4c883466ee99c89f
https://github.com/llvm/llvm-project/commit/14bb933c87a193471d54336c4c883466ee99c89f
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2026-07-17 (Fri, 17 Jul 2026)
Changed paths:
M .ci/compute_projects.py
M .ci/compute_projects_test.py
M .github/new-prs-labeler.yml
M .github/workflows/llvm-abi-tests.yml
M .github/workflows/premerge.yaml
M .github/workflows/release-binaries.yml
M .github/workflows/validate-release-version/action.yml
A bolt/docs/BOLTAArch64OptimizationStatus.md
R bolt/docs/BOLTAArch64OptimizationStatus.rst
A bolt/docs/GettingStarted.md
R bolt/docs/GettingStarted.rst
A bolt/docs/index.md
R bolt/docs/index.rst
M bolt/docs/profiles.md
M bolt/include/bolt/Profile/DataReader.h
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Profile/DataReader.cpp
A bolt/test/X86/jump-table-failed-reanalysis.s
A bolt/test/X86/profile-symbols-mode.s
M clang-tools-extra/clangd/CMakeLists.txt
A clang-tools-extra/clangd/LSPBinder.cpp
M clang-tools-extra/clangd/LSPBinder.h
M clang-tools-extra/clangd/SemanticHighlighting.cpp
M clang-tools-extra/clangd/unittests/PrerequisiteModulesTest.cpp
M clang/bindings/python/tests/cindex/test_diagnostics.py
A clang/docs/AMDGPUSupport.md
R clang/docs/AMDGPUSupport.rst
A clang/docs/APINotes.md
R clang/docs/APINotes.rst
A clang/docs/AllocToken.md
R clang/docs/AllocToken.rst
A clang/docs/BoundsSafety.md
R clang/docs/BoundsSafety.rst
A clang/docs/BoundsSafetyAdoptionGuide.md
R clang/docs/BoundsSafetyAdoptionGuide.rst
A clang/docs/BoundsSafetyImplPlans.md
R clang/docs/BoundsSafetyImplPlans.rst
A clang/docs/CIR/index.md
R clang/docs/CIR/index.rst
A clang/docs/CXXTypeAwareAllocators.md
R clang/docs/CXXTypeAwareAllocators.rst
A clang/docs/ClangPlugins.md
R clang/docs/ClangPlugins.rst
A clang/docs/CommandGuide/index.md
R clang/docs/CommandGuide/index.rst
A clang/docs/ControlFlowIntegrity.md
R clang/docs/ControlFlowIntegrity.rst
A clang/docs/DebuggingCoroutines.md
R clang/docs/DebuggingCoroutines.rst
A clang/docs/ExternalClangExamples.md
R clang/docs/ExternalClangExamples.rst
A clang/docs/FAQ.md
R clang/docs/FAQ.rst
M clang/docs/HIPSupport.md
A clang/docs/IntroductionToTheClangAST.md
R clang/docs/IntroductionToTheClangAST.rst
A clang/docs/LibClang.md
R clang/docs/LibClang.rst
A clang/docs/LibFormat.md
R clang/docs/LibFormat.rst
A clang/docs/LibTooling.md
R clang/docs/LibTooling.rst
A clang/docs/RISCVSupport.md
R clang/docs/RISCVSupport.rst
M clang/docs/ReleaseNotes.md
A clang/docs/Tooling.md
R clang/docs/Tooling.rst
M clang/docs/UsersManual.md
M clang/include/clang/AST/CommentLexer.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h
M clang/include/clang/Basic/AtomicLineLogger.h
M clang/include/clang/Basic/BuiltinsAMDGPU.td
M clang/include/clang/Basic/Diagnostic.td
M clang/include/clang/Basic/DiagnosticIDs.h
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/DiagnosticSerializationKinds.td
M clang/include/clang/Basic/OpenCLExtensions.def
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
A clang/include/clang/CIR/Dialect/IR/CIRStdOps.td
M clang/include/clang/CIR/Dialect/Passes.h
M clang/include/clang/DependencyScanning/DependencyScanningService.h
M clang/include/clang/DependencyScanning/DependencyScanningWorker.h
M clang/include/clang/DependencyScanning/InProcessModuleCache.h
M clang/include/clang/ExtractAPI/DeclarationFragments.h
M clang/include/clang/ExtractAPI/ExtractAPIVisitor.h
M clang/include/clang/Frontend/FrontendActions.h
M clang/include/clang/Frontend/FrontendOptions.h
M clang/include/clang/Frontend/SSAFOptions.h
M clang/include/clang/Options/Options.td
M clang/include/clang/ScalableStaticAnalysis/Core/EntityLinker/StaticLibrary.h
M clang/include/clang/ScalableStaticAnalysis/Core/EntityLinker/TUSummaryEncoding.h
M clang/include/clang/Sema/ExternalSemaSource.h
M clang/include/clang/Sema/MultiplexExternalSemaSource.h
M clang/include/clang/Sema/Sema.h
R clang/include/clang/Sema/TemplateInstCallback.h
M clang/include/clang/Serialization/ASTReader.h
M clang/include/clang/Serialization/InMemoryModuleCache.h
M clang/include/clang/Serialization/ModuleCache.h
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/ComputeDependence.cpp
M clang/lib/AST/ExprCXX.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Analysis/LifetimeSafety/Checker.cpp
M clang/lib/Basic/DiagnosticIDs.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/ARM.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Dialect/Transforms/IdiomRecognizer.cpp
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
M clang/lib/CIR/Lowering/CIRPasses.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVMIR.cpp
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprCXX.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/CodeGenModule.h
M clang/lib/CodeGen/Targets/SPIR.cpp
M clang/lib/DependencyScanning/DependencyScannerImpl.cpp
M clang/lib/DependencyScanning/DependencyScanningWorker.cpp
M clang/lib/DependencyScanning/InProcessModuleCache.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/lib/Driver/ToolChains/MinGW.cpp
M clang/lib/ExtractAPI/DeclarationFragments.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Frontend/FrontendActions.cpp
M clang/lib/Frontend/InterfaceStubFunctionsConsumer.cpp
M clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp
M clang/lib/Headers/riscv_packed_simd.h
M clang/lib/Parse/ParseAST.cpp
M clang/lib/Parse/ParseCXXInlineMethods.cpp
M clang/lib/Parse/ParseExprCXX.cpp
M clang/lib/Parse/ParseStmt.cpp
M clang/lib/Parse/Parser.cpp
M clang/lib/ScalableStaticAnalysis/Analyses/PointerFlow/PointerFlowExtractor.cpp
M clang/lib/ScalableStaticAnalysis/Analyses/SSAFAnalysesCommon.cpp
M clang/lib/ScalableStaticAnalysis/Analyses/SSAFAnalysesCommon.h
M clang/lib/ScalableStaticAnalysis/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/MultiplexExternalSemaSource.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaBase.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaLifetimeSafety.h
M clang/lib/Sema/SemaStmt.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/InMemoryModuleCache.cpp
M clang/lib/Serialization/ModuleCache.cpp
M clang/lib/StaticAnalyzer/Checkers/MPI-Checker/MPIFunctionClassifier.cpp
M clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp
M clang/lib/Tooling/DependencyScanningTool.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
M clang/test/AST/ByteCode/builtin-object-size.cpp
M clang/test/AST/ByteCode/cxx11.cpp
M clang/test/AST/ByteCode/virtual-bases.cpp
M clang/test/AST/HLSL/HLSLControlFlowHint.hlsl
R clang/test/AST/HLSL/Texture2D-AST.hlsl
R clang/test/AST/HLSL/Texture2D-scalar-AST.hlsl
R clang/test/AST/HLSL/Texture2D-shorthand-AST.hlsl
R clang/test/AST/HLSL/Texture2D-vector-AST.hlsl
R clang/test/AST/HLSL/Texture2DArray-scalar-AST.hlsl
R clang/test/AST/HLSL/Texture2DArray-shorthand-AST.hlsl
R clang/test/AST/HLSL/Texture2DArray-vector-AST.hlsl
A clang/test/AST/HLSL/Textures-AST.hlsl
A clang/test/AST/HLSL/Textures-scalar-AST.hlsl
A clang/test/AST/HLSL/Textures-shorthand-AST.hlsl
A clang/test/AST/HLSL/Textures-vector-AST.hlsl
M clang/test/AST/HLSL/matrix-alias.hlsl
M clang/test/AST/HLSL/matrix-constructors.hlsl
M clang/test/AST/HLSL/matrix-elementexpr-tree-transform.hlsl
M clang/test/AST/HLSL/matrix-general-initializer.hlsl
M clang/test/AST/HLSL/matrix-member-access-scalar.hlsl
M clang/test/AST/HLSL/matrix-member-access-swizzle.hlsl
M clang/test/AST/HLSL/resources-in-structs-errors.hlsl
M clang/test/AST/HLSL/resources-in-structs.hlsl
M clang/test/AST/HLSL/vector-alias.hlsl
M clang/test/AST/HLSL/vector-constructors.hlsl
M clang/test/AST/HLSL/vk.spec-constant.usage.hlsl
M clang/test/AST/ast-dump-decl.cpp
A clang/test/AST/ast-dump-deleted-defaulted-range.cpp
M clang/test/AST/ast-dump-funcs.cpp
M clang/test/AST/ast-dump-record-definition-data-json.cpp
M clang/test/Analysis/MPIMock.h
A clang/test/Analysis/Scalable/PointerFlow/system-header-opt-out.cpp
M clang/test/Analysis/Scalable/help.cpp
A clang/test/Analysis/Scalable/ssaf-linker/Outputs/lib-explicit-triple.json
A clang/test/Analysis/Scalable/ssaf-linker/Outputs/lib-namespace-override.json
A clang/test/Analysis/Scalable/ssaf-linker/Outputs/libempty.json
A clang/test/Analysis/Scalable/ssaf-linker/Outputs/libtwo.json
M clang/test/Analysis/Scalable/ssaf-linker/help.test
A clang/test/Analysis/Scalable/ssaf-linker/static-library-create.test
A clang/test/Analysis/Scalable/ssaf-linker/static-library-help.test
A clang/test/Analysis/Scalable/ssaf-linker/static-library-time.test
A clang/test/Analysis/Scalable/ssaf-linker/static-library-verbose.test
M clang/test/Analysis/bstring.c
M clang/test/Analysis/inlining/Inputs/expected-plists/path-notes.cpp.plist
M clang/test/Analysis/malloc.c
M clang/test/Analysis/mpichecker.cpp
M clang/test/Analysis/pr22954.c
A clang/test/Analysis/std-c-library-functions-non-integral-ssize_t.cpp
A clang/test/CIR/CodeGen/func-identity-attr.c
A clang/test/CIR/CodeGen/func-identity-attr.cpp
M clang/test/CIR/CodeGen/ternary-throw.cpp
A clang/test/CIR/CodeGenBuiltins/RISCV/riscv-zihintntl.c
M clang/test/CIR/CodeGenBuiltins/builtin-call.cpp
M clang/test/CIR/CodeGenBuiltins/builtins-elementwise.c
A clang/test/CIR/CodeGenHIP/amdgcn-buffer-rsrc-type.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx1250.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-vi-f16.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
M clang/test/CIR/CodeGenHLSL/matrix-element-expr-load.hlsl
A clang/test/CIR/IR/func-identity-attr.cir
A clang/test/CIR/Transforms/idiom-recognizer-guards-void-result.cpp
A clang/test/CIR/Transforms/idiom-recognizer-guards.cpp
A clang/test/CIR/Transforms/idiom-recognizer-inline-namespace.cpp
A clang/test/CIR/Transforms/idiom-recognizer.cir
M clang/test/CIR/Transforms/idiom-recognizer.cpp
M clang/test/CXX/temp/temp.param/p10-2a.cpp
A clang/test/ClangScanDeps/logging-drop-pcm.c
A clang/test/ClangScanDeps/logging-simple-by-name.c
A clang/test/ClangScanDeps/logging-simple.c
A clang/test/ClangScanDeps/logging-two-threads.c
M clang/test/CodeGen/AArch64/branch-protection-attr.c
M clang/test/CodeGen/AArch64/sign-return-address.c
M clang/test/CodeGen/PowerPC/builtins-ppc-fma.c
M clang/test/CodeGen/PowerPC/builtins-ppc-fpconstrained.c
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
A clang/test/CodeGen/SystemZ/systemz-module.flags.c
M clang/test/CodeGen/amdgpu-builtin-is-invocable.c
M clang/test/CodeGen/amdgpu-builtin-processor-is.c
M clang/test/CodeGen/attr-nomerge.cpp
A clang/test/CodeGen/builtin-trap.c
M clang/test/CodeGen/c11atomics.c
M clang/test/CodeGen/pr53127.cpp
M clang/test/CodeGenCXX/dynamic-cast-address-space.cpp
M clang/test/CodeGenCXX/microsoft-abi-byval-vararg.cpp
M clang/test/CodeGenCXX/microsoft-vector-deleting-dtors.cpp
M clang/test/CodeGenCXX/microsoft-vector-deleting-dtors2.cpp
A clang/test/CodeGenCXX/msvc-global-delete-forwarding-at-delete-site.cpp
M clang/test/CodeGenCXX/msvc-global-delete-scalar-array-split.cpp
M clang/test/CodeGenCXX/msvc-global-delete-scope-no-dtor.cpp
M clang/test/CodeGenCXX/msvc-no-global-delete-forwarding.cpp
M clang/test/CodeGenCXX/trap-fnattr.cpp
M clang/test/CodeGenCXX/vararg-non-pod.cpp
M clang/test/CodeGenHLSL/BasicFeatures/frem_modulo.hlsl
M clang/test/CodeGenHLSL/builtins/AllMemoryBarrier.hlsl
M clang/test/CodeGenHLSL/builtins/AllMemoryBarrierWithGroupSync.hlsl
M clang/test/CodeGenHLSL/builtins/DeviceMemoryBarrier.hlsl
M clang/test/CodeGenHLSL/builtins/DeviceMemoryBarrierWithGroupSync.hlsl
M clang/test/CodeGenHLSL/builtins/GroupMemoryBarrier.hlsl
M clang/test/CodeGenHLSL/builtins/GroupMemoryBarrierWithGroupSync.hlsl
M clang/test/CodeGenHLSL/builtins/InterlockedAdd.hlsl
M clang/test/CodeGenHLSL/builtins/InterlockedOr.hlsl
M clang/test/CodeGenHLSL/builtins/QuadReadAcrossDiagonal.hlsl
M clang/test/CodeGenHLSL/builtins/QuadReadAcrossX.hlsl
M clang/test/CodeGenHLSL/builtins/QuadReadAcrossY.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveAllEqual.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveAllTrue.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveAnyTrue.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveBallot.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveBitAnd.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveBitXor.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveCountBits.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveMax.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveMin.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveProduct.hlsl
M clang/test/CodeGenHLSL/builtins/WaveActiveSum.hlsl
M clang/test/CodeGenHLSL/builtins/WavePrefixCountBits.hlsl
M clang/test/CodeGenHLSL/builtins/WavePrefixProduct.hlsl
M clang/test/CodeGenHLSL/builtins/WavePrefixSum.hlsl
M clang/test/CodeGenHLSL/builtins/WaveReadLaneAt.hlsl
M clang/test/CodeGenHLSL/builtins/acos-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/acos.hlsl
M clang/test/CodeGenHLSL/builtins/all.hlsl
M clang/test/CodeGenHLSL/builtins/any.hlsl
M clang/test/CodeGenHLSL/builtins/asdouble.hlsl
M clang/test/CodeGenHLSL/builtins/asin-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/asin.hlsl
M clang/test/CodeGenHLSL/builtins/atan-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/atan.hlsl
M clang/test/CodeGenHLSL/builtins/atan2-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/atan2-overloads_mat.hlsl
M clang/test/CodeGenHLSL/builtins/atan2.hlsl
M clang/test/CodeGenHLSL/builtins/atan2_mat.hlsl
M clang/test/CodeGenHLSL/builtins/clamp-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/clamp.hlsl
M clang/test/CodeGenHLSL/builtins/clip.hlsl
M clang/test/CodeGenHLSL/builtins/cosh-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/cosh.hlsl
M clang/test/CodeGenHLSL/builtins/cross.hlsl
M clang/test/CodeGenHLSL/builtins/ddx-coarse-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/ddx-coarse.hlsl
M clang/test/CodeGenHLSL/builtins/ddx-fine-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/ddx-fine.hlsl
M clang/test/CodeGenHLSL/builtins/ddx.hlsl
M clang/test/CodeGenHLSL/builtins/ddy-coarse-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/ddy-coarse.hlsl
M clang/test/CodeGenHLSL/builtins/ddy-fine-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/ddy-fine.hlsl
M clang/test/CodeGenHLSL/builtins/ddy.hlsl
M clang/test/CodeGenHLSL/builtins/degrees-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/degrees.hlsl
M clang/test/CodeGenHLSL/builtins/distance.hlsl
M clang/test/CodeGenHLSL/builtins/dot.hlsl
M clang/test/CodeGenHLSL/builtins/dot2add.hlsl
M clang/test/CodeGenHLSL/builtins/f16tof32-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/f16tof32.hlsl
M clang/test/CodeGenHLSL/builtins/f32tof16-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/f32tof16.hlsl
M clang/test/CodeGenHLSL/builtins/faceforward.hlsl
M clang/test/CodeGenHLSL/builtins/firstbithigh.hlsl
M clang/test/CodeGenHLSL/builtins/firstbitlow.hlsl
M clang/test/CodeGenHLSL/builtins/fma.hlsl
M clang/test/CodeGenHLSL/builtins/fmod.hlsl
M clang/test/CodeGenHLSL/builtins/frac-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/frac.hlsl
M clang/test/CodeGenHLSL/builtins/isinf-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/isinf.hlsl
M clang/test/CodeGenHLSL/builtins/isnan.hlsl
M clang/test/CodeGenHLSL/builtins/length.hlsl
M clang/test/CodeGenHLSL/builtins/lerp-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/lerp.hlsl
M clang/test/CodeGenHLSL/builtins/mad.hlsl
M clang/test/CodeGenHLSL/builtins/normalize-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/normalize.hlsl
M clang/test/CodeGenHLSL/builtins/radians-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/radians.hlsl
M clang/test/CodeGenHLSL/builtins/rcp.hlsl
M clang/test/CodeGenHLSL/builtins/reflect.hlsl
M clang/test/CodeGenHLSL/builtins/refract.hlsl
M clang/test/CodeGenHLSL/builtins/rsqrt-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/rsqrt.hlsl
M clang/test/CodeGenHLSL/builtins/sign.hlsl
M clang/test/CodeGenHLSL/builtins/sinh.hlsl
M clang/test/CodeGenHLSL/builtins/smoothstep.hlsl
M clang/test/CodeGenHLSL/builtins/step-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/step.hlsl
M clang/test/CodeGenHLSL/builtins/tan-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/tan.hlsl
M clang/test/CodeGenHLSL/builtins/tanh-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/tanh.hlsl
M clang/test/CodeGenHLSL/resources/RWBuffer-imageformat.hlsl
M clang/test/CodeGenHLSL/resources/StructuredBuffers-methods-ps.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-CalculateLevelOfDetail.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-Gather.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-GetDimensions.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-Load.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-Mips.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-Sample.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-SampleBias.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-SampleCmp.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-SampleCmpLevelZero.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-SampleGrad.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-SampleLevel.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-Subscript.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-default-explicit-binding.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-default.hlsl
R clang/test/CodeGenHLSL/resources/Texture2D-shorthand-contexts.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-CalculateLevelOfDetail.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-Gather.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-Load.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-Mips.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-Sample.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-SampleBias.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-SampleCmp.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-SampleCmpLevelZero.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-SampleGrad.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-SampleLevel.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-Subscript.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-default-explicit-binding.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-default.hlsl
R clang/test/CodeGenHLSL/resources/Texture2DArray-shorthand-contexts.hlsl
A clang/test/CodeGenHLSL/resources/Textures-CalculateLevelOfDetail.hlsl
A clang/test/CodeGenHLSL/resources/Textures-Gather.hlsl
A clang/test/CodeGenHLSL/resources/Textures-GetDimensions.hlsl
A clang/test/CodeGenHLSL/resources/Textures-Load.hlsl
A clang/test/CodeGenHLSL/resources/Textures-Mips.hlsl
A clang/test/CodeGenHLSL/resources/Textures-Sample.hlsl
A clang/test/CodeGenHLSL/resources/Textures-SampleBias.hlsl
A clang/test/CodeGenHLSL/resources/Textures-SampleCmp.hlsl
A clang/test/CodeGenHLSL/resources/Textures-SampleCmpLevelZero.hlsl
A clang/test/CodeGenHLSL/resources/Textures-SampleGrad.hlsl
A clang/test/CodeGenHLSL/resources/Textures-SampleLevel.hlsl
A clang/test/CodeGenHLSL/resources/Textures-Subscript.hlsl
A clang/test/CodeGenHLSL/resources/Textures-default-explicit-binding.hlsl
A clang/test/CodeGenHLSL/resources/Textures-default.hlsl
A clang/test/CodeGenHLSL/resources/Textures-shorthand-contexts.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_geps.hlsl
M clang/test/CodeGenHLSL/semantics/semantic.explicit-mix-builtin.vs.hlsl
M clang/test/CoverageMapping/default-method.cpp
M clang/test/DebugInfo/CXX/verbose-trap.cpp
A clang/test/Driver/Inputs/resource_dir/lib/cygwin/libclang_rt.builtins-x86_64.a
A clang/test/Driver/Inputs/resource_dir_with_amdgpu_per_target_subdir/lib/amdgpu-amd-amdhsa/libclang_rt.profile.a
A clang/test/Driver/Inputs/resource_dir_with_per_target_subdir/lib/x86_64-pc-windows-cygnus/libclang_rt.builtins.a
M clang/test/Driver/aarch64-features.c
M clang/test/Driver/aarch64-fmv.c
M clang/test/Driver/aarch64-security-options.c
M clang/test/Driver/amdgpu-toolchain.c
A clang/test/Driver/cygwin-print-file-name.c
M clang/test/Driver/darwin-target-variant-sdk-version.c
M clang/test/Driver/dxc_debug.hlsl
M clang/test/Driver/dxc_hlsl-rootsig-ver.hlsl
M clang/test/Driver/linux-ld.c
M clang/test/Driver/mingw-sysroot.cpp
M clang/test/Driver/openmp-invalid-target-id.c
M clang/test/Driver/spirv-amd-toolchain.c
A clang/test/ExtractAPI/availability_typedef_anonymous_record.c
A clang/test/ExtractAPI/objc_nullability.m
M clang/test/Headers/gpuintrin.c
A clang/test/Misc/amdgcn.unsupported_core_3.1.cl
M clang/test/OpenMP/spirv_target_codegen_noexceptions.cpp
A clang/test/PCH/unused-local-typedef-determinism.cpp
M clang/test/ParserHLSL/access_specifiers.hlsl
M clang/test/ParserHLSL/hlsl_contained_type_attr.hlsl
M clang/test/ParserHLSL/hlsl_contained_type_attr_error.hlsl
M clang/test/ParserHLSL/hlsl_is_array_attr.hlsl
M clang/test/ParserHLSL/hlsl_is_array_attr_error.hlsl
M clang/test/ParserHLSL/hlsl_is_rov_attr.hlsl
M clang/test/ParserHLSL/hlsl_is_rov_attr_error.hlsl
M clang/test/ParserHLSL/hlsl_raw_buffer_attr.hlsl
M clang/test/ParserHLSL/hlsl_raw_buffer_attr_error.hlsl
M clang/test/ParserHLSL/hlsl_resource_class_attr.hlsl
M clang/test/ParserHLSL/hlsl_resource_class_attr_error.hlsl
M clang/test/ParserHLSL/hlsl_resource_dimension_attr.hlsl
M clang/test/ParserHLSL/hlsl_resource_dimension_attr_error.hlsl
M clang/test/ParserHLSL/semantic_parsing.hlsl
M clang/test/ParserHLSL/semantic_parsing_define.hlsl
M clang/test/Preprocessor/aarch64-target-features.c
A clang/test/Sema/LifetimeSafety/annotation-suggestions-fixits.c
M clang/test/Sema/LifetimeSafety/invalidations.cpp
M clang/test/Sema/LifetimeSafety/safety.cpp
M clang/test/Sema/builtin-memcpy.c
M clang/test/Sema/builtin-object-size.c
M clang/test/Sema/warn-fortify-source.c
A clang/test/Sema/warn-stringop-overread-fortify.c
A clang/test/Sema/warn-stringop-overread.c
M clang/test/SemaCXX/enable_if.cpp
M clang/test/SemaCXX/using-decl-templates.cpp
M clang/test/SemaCXX/warn-memset-bad-sizeof.cpp
A clang/test/SemaCXX/warn-unused-local-typedef-deterministic-order.cpp
M clang/test/SemaHLSL/Availability/attr-deprecated.hlsl
M clang/test/SemaHLSL/BuiltIns/binary-compat-overload-warnings.hlsl
M clang/test/SemaHLSL/BuiltIns/fma-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/matrix-constructors-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/ternary-compat-overload-warnings.hlsl
M clang/test/SemaHLSL/BuiltIns/unary-compat-overload-warnings.hlsl
M clang/test/SemaHLSL/BuiltIns/vec-scalar-compat-overload-warnings.hlsl
M clang/test/SemaHLSL/BuiltIns/vector-constructors-errors.hlsl
M clang/test/SemaHLSL/Language/InitIncompleteArrays.hlsl
M clang/test/SemaHLSL/Language/InitLists.hlsl
M clang/test/SemaHLSL/Language/NoVirtual.hlsl
M clang/test/SemaHLSL/Language/OutputParameters.hlsl
M clang/test/SemaHLSL/Language/TemplateOutArg.hlsl
M clang/test/SemaHLSL/Resources/ConstantBuffers.hlsl
M clang/test/SemaHLSL/Resources/RWTexture2D-mips-errors.hlsl
M clang/test/SemaHLSL/Resources/RWTexture2D-unsupported-methods-errors.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-CalculateLevelOfDetail.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-GetDimensions.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-Load-errors.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-SampleBias.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-SampleCmp.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-SampleCmpLevelZero.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-SampleGrad.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-SampleLevel.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-Sema.hlsl
R clang/test/SemaHLSL/Resources/Texture2D-Subscript.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-CalculateLevelOfDetail.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-GetDimensions.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-SampleBias.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-SampleCmp.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-SampleCmpLevelZero.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-SampleGrad.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-SampleLevel.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-Sema.hlsl
R clang/test/SemaHLSL/Resources/Texture2DArray-Subscript.hlsl
A clang/test/SemaHLSL/Resources/Textures-CalculateLevelOfDetail.hlsl
A clang/test/SemaHLSL/Resources/Textures-GetDimensions.hlsl
A clang/test/SemaHLSL/Resources/Textures-Load-errors.hlsl
A clang/test/SemaHLSL/Resources/Textures-SampleBias.hlsl
A clang/test/SemaHLSL/Resources/Textures-SampleCmp.hlsl
A clang/test/SemaHLSL/Resources/Textures-SampleCmpLevelZero.hlsl
A clang/test/SemaHLSL/Resources/Textures-SampleGrad.hlsl
A clang/test/SemaHLSL/Resources/Textures-SampleLevel.hlsl
A clang/test/SemaHLSL/Resources/Textures-Sema.hlsl
A clang/test/SemaHLSL/Resources/Textures-Subscript.hlsl
M clang/test/SemaHLSL/Semantics/semantic.explicit-mix-builtin-vs.hlsl
M clang/test/SemaHLSL/Semantics/semantic.explicit-mix-location-2.hlsl
M clang/test/SemaHLSL/Semantics/semantic.explicit-mix-location.hlsl
M clang/test/SemaHLSL/Semantics/valid_entry_parameter.hlsl
M clang/test/SemaHLSL/Semantics/vertexid.vs.hlsl
R clang/test/SemaHLSL/Texture2D-Gather.hlsl
R clang/test/SemaHLSL/Texture2D-GatherCmp-Vulkan.hlsl
R clang/test/SemaHLSL/Texture2D-mips-errors.hlsl
R clang/test/SemaHLSL/Texture2DArray-Gather.hlsl
R clang/test/SemaHLSL/Texture2DArray-GatherCmp-Vulkan.hlsl
R clang/test/SemaHLSL/Texture2DArray-mips-errors.hlsl
A clang/test/SemaHLSL/Textures-Gather.hlsl
A clang/test/SemaHLSL/Textures-GatherCmp-Vulkan.hlsl
A clang/test/SemaHLSL/Textures-mips-errors.hlsl
M clang/test/SemaHLSL/Types/short-errors.hlsl
M clang/test/SemaHLSL/entry_shader.hlsl
M clang/test/SemaHLSL/num_threads.hlsl
M clang/test/SemaHLSL/prohibit_reference.hlsl
M clang/test/SemaHLSL/vk.spec-constant.error.hlsl
M clang/test/SemaOpenCL/extension-version.cl
M clang/test/SemaTemplate/class-template-spec.cpp
R clang/test/Templight/templight-deduced-func.cpp
R clang/test/Templight/templight-default-arg-inst.cpp
R clang/test/Templight/templight-default-func-arg.cpp
R clang/test/Templight/templight-default-template-arg.cpp
R clang/test/Templight/templight-empty-entries-fix.cpp
R clang/test/Templight/templight-exception-spec-func.cpp
R clang/test/Templight/templight-explicit-template-arg.cpp
R clang/test/Templight/templight-memoization.cpp
R clang/test/Templight/templight-nested-memoization.cpp
R clang/test/Templight/templight-nested-template-instantiation.cpp
R clang/test/Templight/templight-one-instantiation.cpp
R clang/test/Templight/templight-prior-template-arg.cpp
M clang/test/lit.cfg.py
M clang/tools/cir-opt/cir-opt.cpp
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
M clang/tools/clang-scan-deps/Opts.td
M clang/tools/clang-ssaf-linker/CMakeLists.txt
M clang/tools/clang-ssaf-linker/SSAFLinker.cpp
A clang/tools/clang-ssaf-linker/StaticLibraryCreateCLI.cpp
A clang/tools/clang-ssaf-linker/StaticLibraryCreateCLI.h
M clang/unittests/AST/SourceLocationTest.cpp
M clang/unittests/Basic/AtomicLineLoggerTest.cpp
M clang/unittests/CIR/CMakeLists.txt
A clang/unittests/CIR/IntTypeABIAlignTest.cpp
M clang/unittests/DependencyScanning/InProcessModuleCacheTest.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M clang/unittests/ScalableStaticAnalysis/Analyses/PointerFlow/PointerFlowTest.cpp
M clang/unittests/Serialization/InMemoryModuleCacheTest.cpp
M clang/unittests/Serialization/ModuleCacheTest.cpp
M clang/unittests/Tooling/RecursiveASTVisitorTests/CXXMethodDecl.cpp
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/cmake/Modules/CompilerRTUtils.cmake
M compiler-rt/cmake/base-config-ix.cmake
M compiler-rt/cmake/builtin-config-ix.cmake
A compiler-rt/docs/ASanABI.md
R compiler-rt/docs/ASanABI.rst
A compiler-rt/docs/BuildingCompilerRT.md
R compiler-rt/docs/BuildingCompilerRT.rst
A compiler-rt/docs/TestingGuide.md
R compiler-rt/docs/TestingGuide.rst
M compiler-rt/lib/asan/asan_interceptors.cpp
M compiler-rt/lib/builtins/CMakeLists.txt
M compiler-rt/lib/memprof/memprof_allocator.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_common_syscalls.inc
M compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_internal.h
M compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_libcdep.cpp
M compiler-rt/lib/sanitizer_common/tests/sanitizer_symbolizer_test.cpp
M compiler-rt/lib/tsan/rtl/tsan_interface.h
M compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
M compiler-rt/lib/tsan/rtl/tsan_platform.h
M compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp
M compiler-rt/lib/ubsan/ubsan_diag.cpp
A compiler-rt/test/asan/TestCases/Darwin/atos-canary-symbolize.cpp
M compiler-rt/test/asan/TestCases/Windows/issue64990.cpp
M compiler-rt/test/lit.common.cfg.py
A compiler-rt/test/memprof/TestCases/memprof_histogram_tail_clear.cpp
A compiler-rt/test/memprof/TestCases/memprof_nonhistogram_tail_clear.cpp
A compiler-rt/test/msan/Linux/syscalls_setgroups.cpp
M compiler-rt/test/profile/Linux/counter_promo_for.c
M compiler-rt/test/profile/Linux/counter_promo_while.c
M compiler-rt/test/profile/gcov-__gcov_flush-terminate.c
M compiler-rt/test/sanitizer_common/android_commands/android_common.py
M compiler-rt/test/ubsan/TestCases/Integer/suppressions-nested-calls.c
M cross-project-tests/CMakeLists.txt
A cross-project-tests/dtlto/remote-options.test
M flang-rt/CMakeLists.txt
M flang-rt/lib/runtime/cudadevice.f90
M flang/docs/CMakeLists.txt
A flang/docs/CommandGuide/index.md
R flang/docs/CommandGuide/index.rst
M flang/docs/FortranStandardsSupport.md
M flang/include/flang/Evaluate/call.h
M flang/include/flang/Evaluate/fold.h
M flang/include/flang/Evaluate/shape.h
M flang/include/flang/Evaluate/traverse.h
M flang/include/flang/Evaluate/type.h
M flang/include/flang/Lower/CUDA.h
M flang/include/flang/Lower/OpenMP.h
M flang/include/flang/Lower/PFTBuilder.h
M flang/include/flang/Lower/Support/ReductionProcessor.h
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/include/flang/Semantics/expression.h
M flang/include/flang/Semantics/openmp-utils.h
M flang/include/flang/Support/Fortran-features.h
M flang/lib/Evaluate/call.cpp
M flang/lib/Evaluate/characteristics.cpp
M flang/lib/Evaluate/fold-implementation.h
M flang/lib/Evaluate/fold.cpp
M flang/lib/Evaluate/formatting.cpp
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Evaluate/shape.cpp
M flang/lib/Evaluate/tools.cpp
M flang/lib/Evaluate/type.cpp
M flang/lib/Lower/Allocatable.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertCall.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/PFTBuilder.cpp
M flang/lib/Lower/Support/ReductionProcessor.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/CodeGen/TargetRewrite.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.cpp
M flang/lib/Optimizer/OpenACC/Support/RegisterOpenACCExtensions.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFDeviceFuncTransform.cpp
M flang/lib/Parser/openacc-parsers.cpp
M flang/lib/Parser/program-parsers.cpp
M flang/lib/Semantics/check-acc-structure.cpp
M flang/lib/Semantics/check-acc-structure.h
M flang/lib/Semantics/check-call.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/check-omp-variant.cpp
M flang/lib/Semantics/expression.cpp
M flang/lib/Semantics/mod-file.cpp
M flang/lib/Semantics/mod-file.h
M flang/lib/Semantics/openmp-utils.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/lib/Support/Fortran-features.cpp
M flang/test/Driver/fakeflang.F
A flang/test/Evaluate/fold-conditional-arg.f90
M flang/test/Fir/CUDA/cuda-constructor-2.f90
M flang/test/Fir/CUDA/cuda-constructor.f90
A flang/test/Fir/CUDA/cuda-device-func-transform-aio.mlir
A flang/test/Fir/CUDA/cuda-register-allocator-0.f90
A flang/test/Fir/CUDA/cuda-register-allocator-1.f90
A flang/test/Fir/create-box-codegen.fir
M flang/test/Fir/fir-ops.fir
M flang/test/Fir/invalid.fir
A flang/test/Lower/CUDA/cuda-gpu-unified.cuf
R flang/test/Lower/CUDA/cuda-implicit-managed-alloc.cuf
M flang/test/Lower/CUDA/cuda-init.cuf
A flang/test/Lower/CUDA/cuda-managed-func-result.cuf
A flang/test/Lower/OpenMP/Todo/declare-reduction-allocatable-trivial.f90
R flang/test/Lower/OpenMP/Todo/declare-reduction-operator-multiple-types.f90
R flang/test/Lower/OpenMP/Todo/declare-reduction-operator-use-assoc.f90
R flang/test/Lower/OpenMP/Todo/multiple-types-declare_reduction.f90
R flang/test/Lower/OpenMP/Todo/taskwait-depend.f90
M flang/test/Lower/OpenMP/declare-reduction-character-allocatable.f90
M flang/test/Lower/OpenMP/declare-reduction-initializer-component.f90
M flang/test/Lower/OpenMP/declare-reduction-initializer-defined-assign.f90
M flang/test/Lower/OpenMP/declare-reduction-initializer-rhs-call.f90
M flang/test/Lower/OpenMP/declare-reduction-intrinsic-op.f90
A flang/test/Lower/OpenMP/declare-reduction-intrinsic-same-name-different-scope.f90
M flang/test/Lower/OpenMP/declare-reduction-logical-init.f90
A flang/test/Lower/OpenMP/declare-reduction-merge-hermetic.f90
A flang/test/Lower/OpenMP/declare-reduction-merge-version-skew.f90
A flang/test/Lower/OpenMP/declare-reduction-name-type-token-collision.f90
A flang/test/Lower/OpenMP/declare-reduction-named-renamed.f90
A flang/test/Lower/OpenMP/declare-reduction-named-separate-rename.f90
A flang/test/Lower/OpenMP/declare-reduction-named-use-assoc.f90
M flang/test/Lower/OpenMP/declare-reduction-no-initializer-derived.f90
M flang/test/Lower/OpenMP/declare-reduction-no-initializer-intrinsic.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-collide.f90
M flang/test/Lower/OpenMP/declare-reduction-operator-derived.f90
M flang/test/Lower/OpenMP/declare-reduction-operator-host-assoc.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-merged.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-multiple-types.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-renamed.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-collide-unused.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-combiners.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-hermetic.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-intrinsic-all.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-intrinsic-collide.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-intrinsic.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-multitype-partial.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-reexport.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-remerge.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-rename-remerge.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-submodule.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate-unused-unsupported.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-separate.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-use-assoc.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-use-only-nonreduction.f90
M flang/test/Lower/OpenMP/declare-reduction-operator.f90
M flang/test/Lower/OpenMP/declare-reduction-same-name-different-scope.f90
A flang/test/Lower/OpenMP/declare-reduction-shadows-intrinsic-multiple-types.f90
A flang/test/Lower/OpenMP/declare-reduction-shadows-intrinsic-separate.f90
A flang/test/Lower/OpenMP/declare-reduction-shadows-intrinsic-use-assoc.f90
M flang/test/Lower/OpenMP/declare-reduction-shadows-intrinsic.f90
A flang/test/Lower/OpenMP/declare-reduction-special-separate-reexport.f90
M flang/test/Lower/OpenMP/declare-reduction-target-intrinsic.f90
A flang/test/Lower/OpenMP/multiple-types-declare_reduction.f90
M flang/test/Lower/OpenMP/omp-declare-reduction-combsub.f90
M flang/test/Lower/OpenMP/omp-declare-reduction-derivedtype.f90
M flang/test/Lower/OpenMP/omp-declare-reduction-initsub.f90
M flang/test/Lower/OpenMP/omp-declare-reduction.f90
A flang/test/Lower/OpenMP/taskwait-depend.f90
A flang/test/Lower/global-initialization-parens.f90
A flang/test/Lower/pre-fir-tree-assigned-goto.f90
A flang/test/Lower/pre-fir-tree-multiway-branch.f90
M flang/test/Lower/pre-fir-tree02.f90
M flang/test/Parser/acc-unparse.f90
M flang/test/Semantics/OpenACC/acc-loop-routine-call.f90
A flang/test/Semantics/OpenMP/declare-reduction-ambiguous.f90
M flang/test/Semantics/OpenMP/metadirective-loop-applicability.f90
M flang/test/Semantics/OpenMP/metadirective-loop-nest.f90
M flang/test/Semantics/conditional-arg.f90
A flang/test/Transforms/OpenACC/acc-implicit-declare-type-descriptor-create-box.fir
M flang/tools/CMakeLists.txt
M flang/tools/bbc/bbc.cpp
M flang/tools/fakeflang/CMakeLists.txt
R flang/tools/fakeflang/ensure_flang_exists.cmake
M flang/tools/fakeflang/fakeflang.cpp
M flang/tools/flang-driver/CMakeLists.txt
M flang/unittests/Semantics/OpenMPUtils.cpp
M libc/CMakeLists.txt
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/config/baremetal/aarch64/entrypoints.txt
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/aarch64/headers.txt
M libc/config/linux/arm/headers.txt
M libc/config/linux/i386/headers.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/riscv/headers.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/config/linux/x86_64/headers.txt
M libc/docs/CMakeLists.txt
M libc/docs/headers/stdfix.rst
R libc/docs/headers/time.rst
M libc/hdr/CMakeLists.txt
A libc/hdr/sys_select_macros.h
A libc/hdr/sys_wait_macros.h
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/fd_set.h
A libc/hdr/types/struct_rusage.h
A libc/hdr/types/struct_utsname.h
M libc/include/CMakeLists.txt
A libc/include/alloca.yaml
M libc/include/llvm-libc-macros/CMakeLists.txt
A libc/include/llvm-libc-macros/alloca-macros.h
M libc/include/llvm-libc-macros/netinet-in-macros.h
M libc/include/llvm-libc-types/struct_sockaddr_storage.h
M libc/include/stdfix.yaml
M libc/include/sys/time.yaml
M libc/include/time.yaml
M libc/src/__support/CPP/CMakeLists.txt
M libc/src/__support/CPP/simd.h
M libc/src/__support/FPUtil/Hypot.h
M libc/src/__support/File/linux/CMakeLists.txt
M libc/src/__support/File/linux/dir.cpp
M libc/src/__support/File/linux/file.cpp
M libc/src/__support/OSUtil/linux/CMakeLists.txt
M libc/src/__support/OSUtil/linux/auxv.h
M libc/src/__support/fixed_point/CMakeLists.txt
M libc/src/__support/fixed_point/fx_bits.h
M libc/src/__support/fixed_point/fx_rep.h
M libc/src/__support/freelist.cpp
M libc/src/__support/freelist_heap.h
M libc/src/__support/math/CMakeLists.txt
M libc/src/__support/math/acos.h
M libc/src/__support/math/acosbf16.h
M libc/src/__support/math/acosf.h
M libc/src/__support/math/acospif.h
M libc/src/__support/math/asin.h
M libc/src/__support/math/asin_utils.h
M libc/src/__support/math/asinbf16.h
M libc/src/__support/math/asinf.h
M libc/src/__support/math/asinpi.h
M libc/src/__support/math/asinpif.h
M libc/src/__support/math/atan2f.h
M libc/src/__support/math/atan2f16.h
M libc/src/__support/math/atan_utils.h
M libc/src/__support/math/atanf.h
M libc/src/__support/math/hypot.h
R libc/src/__support/math/inv_trigf_utils.h
M libc/src/__support/mathvec/CMakeLists.txt
A libc/src/__support/mathvec/acosf.h
A libc/src/__support/mathvec/acoshf.h
A libc/src/__support/mathvec/acospif.h
A libc/src/__support/mathvec/asinf.h
A libc/src/__support/mathvec/asinhf.h
A libc/src/__support/mathvec/asinpif.h
A libc/src/__support/mathvec/atanf.h
A libc/src/__support/mathvec/atanhf.h
A libc/src/__support/mathvec/cbrtf.h
M libc/src/__support/mathvec/common_constants.h
A libc/src/__support/mathvec/cosf.h
A libc/src/__support/mathvec/coshf.h
A libc/src/__support/mathvec/cospif.h
A libc/src/__support/mathvec/erff.h
A libc/src/__support/mathvec/exp10f.h
A libc/src/__support/mathvec/exp10m1f.h
A libc/src/__support/mathvec/exp2f.h
A libc/src/__support/mathvec/exp2m1f.h
M libc/src/__support/mathvec/expf.h
M libc/src/__support/mathvec/expf_utils.h
A libc/src/__support/mathvec/expm1f.h
A libc/src/__support/mathvec/log10f.h
A libc/src/__support/mathvec/log1pf.h
A libc/src/__support/mathvec/log2f.h
A libc/src/__support/mathvec/logf.h
A libc/src/__support/mathvec/rsqrtf.h
A libc/src/__support/mathvec/sinf.h
A libc/src/__support/mathvec/sinhf.h
A libc/src/__support/mathvec/sinpif.h
A libc/src/__support/mathvec/sqrtf.h
A libc/src/__support/mathvec/tanf.h
A libc/src/__support/mathvec/tanhf.h
A libc/src/__support/mathvec/tanpif.h
M libc/src/__support/threads/linux/CMakeLists.txt
M libc/src/__support/threads/linux/thread.cpp
M libc/src/mathvec/CMakeLists.txt
A libc/src/mathvec/abi_prefix.h
A libc/src/mathvec/acosf.h
A libc/src/mathvec/acoshf.h
A libc/src/mathvec/acospif.h
A libc/src/mathvec/asinf.h
A libc/src/mathvec/asinhf.h
A libc/src/mathvec/asinpif.h
A libc/src/mathvec/atanf.h
A libc/src/mathvec/atanhf.h
A libc/src/mathvec/cbrtf.h
A libc/src/mathvec/cosf.h
A libc/src/mathvec/coshf.h
A libc/src/mathvec/cospif.h
A libc/src/mathvec/erff.h
A libc/src/mathvec/exp10f.h
A libc/src/mathvec/exp10m1f.h
A libc/src/mathvec/exp2f.h
A libc/src/mathvec/exp2m1f.h
M libc/src/mathvec/expf.h
A libc/src/mathvec/expm1f.h
M libc/src/mathvec/generic/CMakeLists.txt
A libc/src/mathvec/generic/acosf.cpp
A libc/src/mathvec/generic/acoshf.cpp
A libc/src/mathvec/generic/acospif.cpp
A libc/src/mathvec/generic/asinf.cpp
A libc/src/mathvec/generic/asinhf.cpp
A libc/src/mathvec/generic/asinpif.cpp
A libc/src/mathvec/generic/atanf.cpp
A libc/src/mathvec/generic/atanhf.cpp
A libc/src/mathvec/generic/cbrtf.cpp
A libc/src/mathvec/generic/cosf.cpp
A libc/src/mathvec/generic/coshf.cpp
A libc/src/mathvec/generic/cospif.cpp
A libc/src/mathvec/generic/erff.cpp
A libc/src/mathvec/generic/exp10f.cpp
A libc/src/mathvec/generic/exp10m1f.cpp
A libc/src/mathvec/generic/exp2f.cpp
A libc/src/mathvec/generic/exp2m1f.cpp
M libc/src/mathvec/generic/expf.cpp
A libc/src/mathvec/generic/expm1f.cpp
A libc/src/mathvec/generic/log10f.cpp
A libc/src/mathvec/generic/log1pf.cpp
A libc/src/mathvec/generic/log2f.cpp
A libc/src/mathvec/generic/logf.cpp
A libc/src/mathvec/generic/rsqrtf.cpp
A libc/src/mathvec/generic/sinf.cpp
A libc/src/mathvec/generic/sinhf.cpp
A libc/src/mathvec/generic/sinpif.cpp
A libc/src/mathvec/generic/sqrtf.cpp
A libc/src/mathvec/generic/tanf.cpp
A libc/src/mathvec/generic/tanhf.cpp
A libc/src/mathvec/generic/tanpif.cpp
A libc/src/mathvec/log10f.h
A libc/src/mathvec/log1pf.h
A libc/src/mathvec/log2f.h
A libc/src/mathvec/logf.h
A libc/src/mathvec/rsqrtf.h
A libc/src/mathvec/sinf.h
A libc/src/mathvec/sinhf.h
A libc/src/mathvec/sinpif.h
A libc/src/mathvec/sqrtf.h
A libc/src/mathvec/tanf.h
A libc/src/mathvec/tanhf.h
A libc/src/mathvec/tanpif.h
M libc/src/sched/linux/CMakeLists.txt
M libc/src/sched/linux/sched_getaffinity.cpp
M libc/src/spawn/linux/CMakeLists.txt
M libc/src/spawn/linux/posix_spawn.cpp
M libc/src/stdfix/CMakeLists.txt
A libc/src/stdfix/divik.cpp
A libc/src/stdfix/divik.h
A libc/src/stdfix/divilk.cpp
A libc/src/stdfix/divilk.h
A libc/src/stdfix/divilr.cpp
A libc/src/stdfix/divilr.h
A libc/src/stdfix/divir.cpp
A libc/src/stdfix/divir.h
A libc/src/stdfix/diviuk.cpp
A libc/src/stdfix/diviuk.h
A libc/src/stdfix/diviulk.cpp
A libc/src/stdfix/diviulk.h
A libc/src/stdfix/diviulr.cpp
A libc/src/stdfix/diviulr.h
A libc/src/stdfix/diviur.cpp
A libc/src/stdfix/diviur.h
M libc/src/stdio/linux/CMakeLists.txt
M libc/src/stdio/linux/remove.cpp
M libc/src/stdlib/CMakeLists.txt
M libc/src/stdlib/baremetal/CMakeLists.txt
A libc/src/stdlib/baremetal/malloc_usable_size.cpp
A libc/src/stdlib/malloc_usable_size.h
M libc/src/sys/ipc/linux/CMakeLists.txt
M libc/src/sys/ipc/linux/ftok.cpp
R libc/src/sys/ipc/linux/kernel_statx.h
M libc/src/sys/mman/linux/CMakeLists.txt
M libc/src/sys/mman/linux/shm_unlink.cpp
M libc/src/sys/select/linux/CMakeLists.txt
M libc/src/sys/select/linux/select.cpp
M libc/src/sys/select/select.h
M libc/src/sys/time/CMakeLists.txt
A libc/src/sys/time/gettimeofday.h
M libc/src/sys/time/linux/CMakeLists.txt
A libc/src/sys/time/linux/gettimeofday.cpp
M libc/src/sys/time/linux/utimes.cpp
M libc/src/sys/utsname/linux/CMakeLists.txt
M libc/src/sys/utsname/linux/uname.cpp
M libc/src/sys/utsname/uname.h
M libc/src/sys/wait/linux/CMakeLists.txt
M libc/src/sys/wait/wait4.h
M libc/src/sys/wait/wait4Impl.h
M libc/src/time/CMakeLists.txt
R libc/src/time/gettimeofday.h
M libc/src/time/linux/CMakeLists.txt
R libc/src/time/linux/gettimeofday.cpp
M libc/src/unistd/linux/CMakeLists.txt
M libc/src/unistd/linux/gethostname.cpp
M libc/startup/linux/x86_64/CMakeLists.txt
M libc/startup/linux/x86_64/tls.cpp
M libc/test/UnitTest/HermeticTestUtils.cpp
M libc/test/include/CMakeLists.txt
A libc/test/include/alloca_test.cpp
M libc/test/include/netinet_in_test.cpp
M libc/test/src/__support/freelist_heap_test.cpp
M libc/test/src/math/smoke/hypot_test.cpp
M libc/test/src/mathvec/CMakeLists.txt
A libc/test/src/mathvec/UnitTestWrappers.h
A libc/test/src/mathvec/acosf_test.cpp
A libc/test/src/mathvec/acoshf_test.cpp
A libc/test/src/mathvec/acospif_test.cpp
A libc/test/src/mathvec/asinf_test.cpp
A libc/test/src/mathvec/asinhf_test.cpp
A libc/test/src/mathvec/asinpif_test.cpp
A libc/test/src/mathvec/atanf_test.cpp
A libc/test/src/mathvec/atanhf_test.cpp
A libc/test/src/mathvec/cbrtf_test.cpp
A libc/test/src/mathvec/cosf_test.cpp
A libc/test/src/mathvec/coshf_test.cpp
A libc/test/src/mathvec/cospif_test.cpp
A libc/test/src/mathvec/erff_test.cpp
M libc/test/src/mathvec/exhaustive/CMakeLists.txt
A libc/test/src/mathvec/exhaustive/acosf_test.cpp
A libc/test/src/mathvec/exhaustive/acoshf_test.cpp
A libc/test/src/mathvec/exhaustive/acospif_test.cpp
A libc/test/src/mathvec/exhaustive/asinf_test.cpp
A libc/test/src/mathvec/exhaustive/asinhf_test.cpp
A libc/test/src/mathvec/exhaustive/asinpif_test.cpp
A libc/test/src/mathvec/exhaustive/atanf_test.cpp
A libc/test/src/mathvec/exhaustive/atanhf_test.cpp
A libc/test/src/mathvec/exhaustive/cbrtf_test.cpp
A libc/test/src/mathvec/exhaustive/cosf_test.cpp
A libc/test/src/mathvec/exhaustive/coshf_test.cpp
A libc/test/src/mathvec/exhaustive/cospif_test.cpp
A libc/test/src/mathvec/exhaustive/erff_test.cpp
M libc/test/src/mathvec/exhaustive/exhaustive_test.h
A libc/test/src/mathvec/exhaustive/exp10f_test.cpp
A libc/test/src/mathvec/exhaustive/exp10m1f_test.cpp
A libc/test/src/mathvec/exhaustive/exp2f_test.cpp
A libc/test/src/mathvec/exhaustive/exp2m1f_test.cpp
M libc/test/src/mathvec/exhaustive/expf_test.cpp
A libc/test/src/mathvec/exhaustive/expm1f_test.cpp
A libc/test/src/mathvec/exhaustive/log10f_test.cpp
A libc/test/src/mathvec/exhaustive/log1pf_test.cpp
A libc/test/src/mathvec/exhaustive/log2f_test.cpp
A libc/test/src/mathvec/exhaustive/logf_test.cpp
A libc/test/src/mathvec/exhaustive/rsqrtf_test.cpp
A libc/test/src/mathvec/exhaustive/sinf_test.cpp
A libc/test/src/mathvec/exhaustive/sinhf_test.cpp
A libc/test/src/mathvec/exhaustive/sinpif_test.cpp
A libc/test/src/mathvec/exhaustive/sqrtf_test.cpp
A libc/test/src/mathvec/exhaustive/tanf_test.cpp
A libc/test/src/mathvec/exhaustive/tanhf_test.cpp
A libc/test/src/mathvec/exhaustive/tanpif_test.cpp
A libc/test/src/mathvec/exp10f_test.cpp
A libc/test/src/mathvec/exp10m1f_test.cpp
A libc/test/src/mathvec/exp2f_test.cpp
A libc/test/src/mathvec/exp2m1f_test.cpp
M libc/test/src/mathvec/expf_test.cpp
A libc/test/src/mathvec/expm1f_test.cpp
A libc/test/src/mathvec/log10f_test.cpp
A libc/test/src/mathvec/log1pf_test.cpp
A libc/test/src/mathvec/log2f_test.cpp
A libc/test/src/mathvec/logf_test.cpp
A libc/test/src/mathvec/rsqrtf_test.cpp
A libc/test/src/mathvec/sinf_test.cpp
A libc/test/src/mathvec/sinhf_test.cpp
A libc/test/src/mathvec/sinpif_test.cpp
A libc/test/src/mathvec/sqrtf_test.cpp
A libc/test/src/mathvec/tanf_test.cpp
A libc/test/src/mathvec/tanhf_test.cpp
A libc/test/src/mathvec/tanpif_test.cpp
M libc/test/src/stdfix/CMakeLists.txt
A libc/test/src/stdfix/DiviFxTest.h
A libc/test/src/stdfix/divik_test.cpp
A libc/test/src/stdfix/divilk_test.cpp
A libc/test/src/stdfix/divilr_test.cpp
A libc/test/src/stdfix/divir_test.cpp
A libc/test/src/stdfix/diviuk_test.cpp
A libc/test/src/stdfix/diviulk_test.cpp
A libc/test/src/stdfix/diviulr_test.cpp
A libc/test/src/stdfix/diviur_test.cpp
M libc/test/src/stdlib/CMakeLists.txt
M libc/test/src/stdlib/realpath_test.cpp
M libc/test/src/sys/socket/linux/CMakeLists.txt
M libc/test/src/sys/socket/linux/bind_test.cpp
M libc/test/src/sys/socket/linux/connect_accept_test.cpp
M libc/test/src/sys/socket/linux/listen_test.cpp
M libc/test/src/sys/socket/linux/sockaddr_storage_test.cpp
M libc/test/src/sys/socket/linux/socket_test_support.h
M libc/test/src/sys/socket/linux/sockname_test.cpp
M libc/test/src/sys/time/CMakeLists.txt
A libc/test/src/sys/time/gettimeofday_test.cpp
M libc/test/src/time/CMakeLists.txt
R libc/test/src/time/gettimeofday_test.cpp
A libc/utils/docgen/time.yaml
M libcxx/cmake/caches/Generic-llvm-libc.cmake
M libcxx/include/__algorithm/copy_n.h
M libcxx/include/__algorithm/for_each_n.h
M libcxx/include/__algorithm/generate_n.h
M libcxx/include/__algorithm/is_heap_until.h
M libcxx/include/__algorithm/ranges_for_each_n.h
M libcxx/include/__bit_reference
M libcxx/src/include/overridable_function.h
M libcxx/src/new.cpp
M libcxx/src/support/runtime/exception_pointer_msvc.ipp
A libcxx/test/benchmarks/algorithms/modifying/replace_copy.bench.cpp
A libcxx/test/benchmarks/algorithms/sorting/binary_search.bench.cpp
A libcxx/test/benchmarks/algorithms/sorting/equal_range.bench.cpp
M libcxx/test/benchmarks/algorithms/sorting/lower_upper_bound.bench.cpp
M libcxx/test/configs/llvm-libc++-llvm-libc.cfg.in
A libcxx/test/libcxx/algorithms/alg.nonmodifying/alg.foreach/assert.for_each_n.pass.cpp
A libcxx/test/libcxx/algorithms/alg.nonmodifying/alg.foreach/assert.ranges.for_each_n.pass.cpp
M libcxx/test/libcxx/atomics/builtin_clear_padding.pass.cpp
M libcxx/test/libcxx/language.support/support.dynamic/assert.nothrow_new_not_overridden_fno_exceptions.pass.cpp
M libcxx/test/libcxx/language.support/support.dynamic/new_dont_return_nullptr.pass.cpp
M libcxx/test/libcxx/thread/thread.condition/PR30202_notify_from_pthread_created_thread.pass.cpp
M libcxx/test/libcxx/thread/thread.threads/thread.thread.class/thread.thread.member/native_handle.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/copy_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/ranges.copy_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/fill_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/ranges.fill_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.generate/generate_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.generate/ranges_generate_n.pass.cpp
M libcxx/test/std/algorithms/alg.sorting/alg.heap.operations/is.heap/ranges_is_heap_until.pass.cpp
M libcxx/test/std/depr/depr.c.headers/wchar_h.compile.pass.cpp
M libcxx/test/std/depr/depr.c.headers/wctype_h.compile.pass.cpp
M libcxx/test/std/input.output/syncstream/osyncstream/thread/several_threads.pass.cpp
M libcxx/test/std/numerics/complex.number/complex.member.ops/divide_equal_complex.pass.cpp
M libcxx/test/std/numerics/complex.number/complex.ops/complex_divide_complex.pass.cpp
M libcxx/test/std/numerics/complex.number/complex.ops/scalar_divide_complex.pass.cpp
M libcxx/test/std/numerics/rand/rand.dist/rand.dist.bern/rand.dist.bern.bin/eval.PR44847.pass.cpp
M libcxx/test/std/numerics/rand/rand.dist/rand.dist.bern/rand.dist.bern.bin/io.pass.cpp
M libcxx/test/std/strings/c.strings/cwchar.pass.cpp
M libcxx/test/std/strings/c.strings/cwctype.pass.cpp
M libcxx/test/std/strings/string.conversions/to_wstring.pass.cpp
M libcxx/test/std/thread/thread.condition/notify_all_at_thread_exit_lwg3343.pass.cpp
M libcxx/test/std/thread/thread.threads/thread.thread.this/sleep_for.signals.pass.cpp
M libcxx/test/std/time/time.hash/time.hash_enabled.pass.cpp
M libcxx/utils/ci/images/libcxx_release_runners.txt
M libcxxabi/src/stdlib_new_delete.cpp
M libcxxabi/test/configs/llvm-libc++abi-llvm-libc.cfg.in
A libsycl/docs/CodingGuidelines.md
R libsycl/docs/CodingGuidelines.rst
A libsycl/docs/index.md
R libsycl/docs/index.rst
M libsycl/include/sycl/__impl/detail/kernel_arg_helpers.hpp
A libsycl/include/sycl/__impl/detail/linearization.hpp
M libsycl/include/sycl/__impl/detail/unified_range_view.hpp
A libsycl/include/sycl/__impl/group.hpp
A libsycl/include/sycl/__impl/memory_enums.hpp
A libsycl/include/sycl/__impl/nd_item.hpp
A libsycl/include/sycl/__impl/nd_range.hpp
M libsycl/include/sycl/__impl/queue.hpp
A libsycl/include/sycl/__impl/sub_group.hpp
M libsycl/include/sycl/__spirv/spirv_vars.hpp
M libsycl/include/sycl/sycl.hpp
M libsycl/src/detail/queue_impl.cpp
M libsycl/src/event.cpp
M libsycl/test/README.md
A libsycl/test/basic/group.cpp
A libsycl/test/basic/group_local_id.cpp
A libsycl/test/basic/linear_sub_group.cpp
A libsycl/test/basic/nd_range.cpp
M libsycl/test/basic/parallel_for_indexers.cpp
M libsycl/test/basic/queue_parallel_for_generic.cpp
A libsycl/test/basic/sub_group_by_value_semantics.cpp
A libsycl/test/basic/sub_group_common.cpp
M libsycl/unittests/event/event.cpp
M libsycl/unittests/mock/helpers.cpp
M libsycl/unittests/queue/sycl_kernel_launch.cpp
A libunwind/docs/BuildingLibunwind.md
R libunwind/docs/BuildingLibunwind.rst
M libunwind/docs/conf.py
A libunwind/docs/index.md
R libunwind/docs/index.rst
M lld/COFF/Driver.cpp
M lld/COFF/InputFiles.cpp
M lld/COFF/InputFiles.h
M lld/ELF/SyntheticSections.cpp
M lld/ELF/SyntheticSections.h
M lld/ELF/Writer.cpp
A lld/docs/DTLTO.md
R lld/docs/DTLTO.rst
A lld/docs/ELF/large_sections.md
R lld/docs/ELF/large_sections.rst
A lld/docs/ELF/linker_script.md
R lld/docs/ELF/linker_script.rst
A lld/docs/ELF/start-stop-gc.md
R lld/docs/ELF/start-stop-gc.rst
A lld/docs/ELF/warn_backrefs.md
R lld/docs/ELF/warn_backrefs.rst
A lld/docs/MachO/index.md
R lld/docs/MachO/index.rst
A lld/docs/MachO/ld64-vs-lld.md
R lld/docs/MachO/ld64-vs-lld.rst
A lld/docs/NewLLD.md
R lld/docs/NewLLD.rst
A lld/docs/ReleaseNotes.md
R lld/docs/ReleaseNotes.rst
A lld/docs/WebAssembly.md
R lld/docs/WebAssembly.rst
M lld/docs/conf.py
A lld/docs/error_handling_script.md
R lld/docs/error_handling_script.rst
A lld/docs/index.md
R lld/docs/index.rst
A lld/docs/missingkeyfunction.md
R lld/docs/missingkeyfunction.rst
A lld/docs/windows_support.md
R lld/docs/windows_support.rst
A lld/test/COFF/link-dll-arm64x.s
M lld/test/ELF/local-symbols-order.s
M lld/test/ELF/lto/parallel-internalize.ll
M lld/test/ELF/ppc64-local-entry.s
M lld/test/ELF/relocatable-comdat-multiple.s
M lld/test/ELF/relocatable-comdat2.s
M lld/test/ELF/relocatable-discard-locals.s
M lld/test/ELF/relocatable-gc.s
M lld/test/ELF/relocatable.s
M lld/test/ELF/strtab-nodedup.s
M lldb/bindings/interfaces.swig
M lldb/bindings/python/CMakeLists.txt
M lldb/bindings/python/python-wrapper.swig
M lldb/cmake/modules/FindPythonAndSwig.cmake
M lldb/docs/CMakeLists.txt
M lldb/docs/dil-expr-lang.ebnf
M lldb/docs/resources/test.md
M lldb/examples/python/delta.py
M lldb/examples/python/gdbremote.py
M lldb/examples/python/templates/operating_system.py
M lldb/examples/python/templates/scripted_breakpoint.py
M lldb/examples/python/templates/scripted_frame_provider.py
M lldb/examples/python/templates/scripted_hook.py
M lldb/examples/python/templates/scripted_platform.py
M lldb/examples/python/templates/scripted_process.py
A lldb/examples/python/templates/scripted_stackframe_recognizer.py
M lldb/examples/python/templates/scripted_thread_plan.py
M lldb/include/lldb/API/LLDB.h
M lldb/include/lldb/API/SBDefines.h
A lldb/include/lldb/API/SBProtocolServer.h
M lldb/include/lldb/Core/Section.h
M lldb/include/lldb/Host/common/DomainSocket.h
A lldb/include/lldb/Interpreter/Interfaces/ScriptedStackFrameRecognizerInterface.h
M lldb/include/lldb/Interpreter/ScriptInterpreter.h
M lldb/include/lldb/Target/StackFrameRecognizer.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/include/lldb/lldb-forward.h
A lldb/packages/Python/lldbsuite/support/xcode.py
M lldb/packages/Python/lldbsuite/test/dotest.py
M lldb/packages/Python/lldbsuite/test/dotest_args.py
M lldb/packages/Python/lldbsuite/test/lldbtest.py
M lldb/packages/Python/lldbsuite/test/lldbutil.py
M lldb/source/API/CMakeLists.txt
A lldb/source/API/SBProtocolServer.cpp
M lldb/source/API/SBSection.cpp
M lldb/source/Commands/CommandObjectMemory.cpp
M lldb/source/Expression/DWARFExpression.cpp
M lldb/source/Host/common/DomainSocket.cpp
M lldb/source/Interpreter/ScriptInterpreter.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ASTUtils.h
M lldb/source/Plugins/LanguageRuntime/CPlusPlus/CPPLanguageRuntime.cpp
M lldb/source/Plugins/ObjectFile/ELF/ELFHeader.cpp
M lldb/source/Plugins/ObjectFile/ELF/ELFHeader.h
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86.cpp
M lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_x86.h
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/CMakeLists.txt
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPythonInterface.cpp
A lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedStackFrameRecognizerPythonInterface.cpp
A lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedStackFrameRecognizerPythonInterface.h
M lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
M lldb/source/Plugins/SymbolFile/NativePDB/UdtRecordCompleter.cpp
M lldb/source/Plugins/SymbolLocator/DebugSymbols/SymbolLocatorDebugSymbols.cpp
M lldb/source/Plugins/TraceExporter/common/TraceHTR.h
A lldb/source/Plugins/TraceExporter/docs/htr.md
R lldb/source/Plugins/TraceExporter/docs/htr.rst
M lldb/source/Target/SectionLoadList.cpp
M lldb/source/Target/StackFrameRecognizer.cpp
M lldb/source/Target/Target.cpp
M lldb/source/ValueObject/DILEval.cpp
M lldb/test/API/commands/frame/recognizer/TestFrameRecognizer.py
M lldb/test/API/commands/frame/recognizer/recognizer.py
M lldb/test/API/commands/frame/var-dil/expr/Literals/TestFrameVarDILLiterals.py
M lldb/test/API/commands/frame/var-dil/expr/Literals/main.cpp
A lldb/test/API/commands/frame/var-dil/expr/NullptrVar/Makefile
A lldb/test/API/commands/frame/var-dil/expr/NullptrVar/TestFrameVarDILNullptrVar.py
A lldb/test/API/commands/frame/var-dil/expr/NullptrVar/main.c
M lldb/test/API/driver/longpath/TestLongPathDriver.py
M lldb/test/API/functionalities/longpath/TestLongPath.py
M lldb/test/API/functionalities/thread/finish-from-empty-func/TestEmptyFuncThreadStepOut.py
M lldb/test/API/functionalities/thread/finish-from-empty-func/main.c
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_breakpointLocations.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_logpoints.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setBreakpoints.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setExceptionBreakpoints.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setFunctionBreakpoints.py
M lldb/test/API/tools/lldb-dap/io/TestDAP_io.py
M lldb/test/API/tools/lldb-dap/launch/io/DAP_launch_io.py
M lldb/test/API/tools/lldb-dap/launch/io/TestDAP_launch_io_integratedTerminal.py
M lldb/test/API/tools/lldb-dap/launch/io/TestDAP_launch_io_internalConsole.py
M lldb/test/API/tools/lldb-dap/launch/io/main.cpp
M lldb/test/API/tools/lldb-dap/longpath/TestDAP_launch_longPath.py
M lldb/test/Shell/SymbolFile/NativePDB/Inputs/globals-fundamental.lldbinit
M lldb/test/Shell/SymbolFile/NativePDB/globals-fundamental.cpp
A lldb/test/Shell/SymbolFile/NativePDB/static-class-constants.cpp
M lldb/test/Shell/helper/toolchain.py
M lldb/tools/lldb-server/lldb-gdbserver.cpp
M lldb/tools/lldb-test/lldb-test.cpp
M lldb/unittests/API/CMakeLists.txt
A lldb/unittests/API/SBProtocolServerTest.cpp
M lldb/unittests/Expression/DWARFExpressionTest.cpp
M lldb/unittests/Host/SocketTest.cpp
M lldb/unittests/Process/gdb-remote/GDBRemoteCommunicationServerLLGSTest.cpp
M lldb/unittests/ScriptInterpreter/Python/PythonTestSuite.cpp
M lldb/unittests/Utility/UriParserTest.cpp
A llvm-libgcc/docs/LLVMLibgcc.md
R llvm-libgcc/docs/LLVMLibgcc.rst
M llvm-libgcc/generate_version_script.py
M llvm/CMakeLists.txt
M llvm/cmake/modules/LLVMExternalProjectUtils.cmake
M llvm/docs/AMDGPUDMAOperations.md
M llvm/docs/CommandGuide/lit.rst
M llvm/docs/LFI.rst
M llvm/docs/LangRef.md
M llvm/docs/ReleaseNotes.md
M llvm/docs/TableGen/ProgRef.rst
M llvm/include/llvm-c/Orc.h
M llvm/include/llvm/ADT/BitVector.h
M llvm/include/llvm/ADT/Eytzinger.h
M llvm/include/llvm/ADT/GenericConvergenceVerifier.h
M llvm/include/llvm/ADT/GenericCycleImpl.h
M llvm/include/llvm/ADT/GenericCycleInfo.h
M llvm/include/llvm/ADT/GenericUniformityImpl.h
M llvm/include/llvm/ADT/GenericUniformityInfo.h
M llvm/include/llvm/ADT/SmallBitVector.h
M llvm/include/llvm/Analysis/HashRecognize.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/GlobalISel/Utils.h
M llvm/include/llvm/CodeGen/LibcallLoweringInfo.h
M llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
M llvm/include/llvm/CodeGen/Rematerializer.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
M llvm/include/llvm/DWP/DWP.h
M llvm/include/llvm/DebugInfo/PDB/Native/LinePrinter.h
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/include/llvm/IR/CycleInfo.h
M llvm/include/llvm/IR/FixedMetadataKinds.def
M llvm/include/llvm/IR/GenericConvergenceVerifierImpl.h
M llvm/include/llvm/IR/Instructions.h
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/IR/Module.h
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/MC/MCLFIRewriter.h
M llvm/include/llvm/MC/MCObjectFileInfo.h
M llvm/include/llvm/MC/MCSchedule.h
M llvm/include/llvm/ObjectYAML/BBAddrMapYAML.h
M llvm/include/llvm/ObjectYAML/COFFYAML.h
M llvm/include/llvm/ObjectYAML/yaml2obj.h
M llvm/include/llvm/Support/LSP/Transport.h
M llvm/include/llvm/TargetParser/ARMTargetParserCommon.h
M llvm/lib/Analysis/CFG.cpp
M llvm/lib/Analysis/HashRecognize.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/UniformityAnalysis.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/lib/CodeGen/DwarfEHPrepare.cpp
M llvm/lib/CodeGen/EarlyIfConversion.cpp
M llvm/lib/CodeGen/ExpandIRInsts.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/LibcallLoweringInfo.cpp
M llvm/lib/CodeGen/MachineCycleAnalysis.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
M llvm/lib/CodeGen/Rematerializer.cpp
M llvm/lib/CodeGen/SafeStack.cpp
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/StackProtector.cpp
M llvm/lib/CodeGen/TargetInstrInfo.cpp
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/CodeGen/TargetSchedule.cpp
M llvm/lib/DWARFLinker/Parallel/DWARFLinkerCompileUnit.cpp
M llvm/lib/DWARFLinker/Parallel/DWARFLinkerUnit.h
M llvm/lib/DWP/DWP.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/CycleInfo.cpp
M llvm/lib/IR/Globals.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/Module.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/IR/VerifierAMDGPU.cpp
M llvm/lib/LTO/LTO.cpp
M llvm/lib/LineEditor/LineEditor.cpp
M llvm/lib/MC/MCDXContainerWriter.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/Object/GOFFObjectFile.cpp
M llvm/lib/ObjectYAML/BBAddrMapYAML.cpp
M llvm/lib/ObjectYAML/COFFEmitter.cpp
M llvm/lib/ObjectYAML/ELFEmitter.cpp
M llvm/lib/ObjectYAML/yaml2obj.cpp
M llvm/lib/Support/KnownBits.cpp
M llvm/lib/Support/LSP/Transport.cpp
M llvm/lib/TableGen/Record.cpp
M llvm/lib/Target/AArch64/AArch64.h
M llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
A llvm/lib/Target/AArch64/AArch64PTrueCoalescing.cpp
M llvm/lib/Target/AArch64/AArch64PassRegistry.def
M llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/CMakeLists.txt
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCLFIRewriter.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCLFIRewriter.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHWEvents.def
M llvm/lib/Target/AMDGPU/AMDGPUHWEvents.h
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
M llvm/lib/Target/AMDGPU/AMDGPUWaitcntUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUWaitcntUtils.h
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MIMGInstructions.td
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp
M llvm/lib/Target/DirectX/DXILWriter/DXILWriterPass.cpp
M llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCSchedule.td
M llvm/lib/Target/PowerPC/PPCSchedule440.td
M llvm/lib/Target/PowerPC/PPCScheduleA2.td
M llvm/lib/Target/PowerPC/PPCScheduleE500.td
M llvm/lib/Target/PowerPC/PPCScheduleE500mc.td
M llvm/lib/Target/PowerPC/PPCScheduleE5500.td
M llvm/lib/Target/PowerPC/PPCScheduleG3.td
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td
M llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/SPIRV/SPIRV.h
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/WebAssembly/CMakeLists.txt
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyAddMissingPrototypes.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyArgumentMove.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyCleanCodeAfterTrap.cpp
A llvm/lib/Target/WebAssembly/WebAssemblyCoalesceFeaturesAndStripAtomics.cpp
A llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyFixBrTableDefaults.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyFixFunctionBitcasts.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyNullifyDebugValueLists.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyOptimizeReturned.cpp
A llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyReduceToAnyAllTrue.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyRefTypeMem2Local.cpp
M llvm/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
M llvm/lib/Target/X86/X86CmovConversion.cpp
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/lib/TargetParser/ARMTargetParserCommon.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/IPO/FunctionImport.cpp
M llvm/lib/Transforms/IPO/Instrumentor.cpp
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
M llvm/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/lib/Transforms/Utils/AssignGUID.cpp
M llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
M llvm/lib/Transforms/Utils/CloneModule.cpp
M llvm/lib/Transforms/Utils/FixIrreducible.cpp
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
M llvm/lib/Transforms/Utils/SSAUpdater.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.h
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/runtimes/CMakeLists.txt
M llvm/test/Analysis/AliasSet/memset.ll
M llvm/test/Analysis/CostModel/AMDGPU/sin.ll
M llvm/test/Analysis/HashRecognize/cyclic-redundancy-check.ll
M llvm/test/Analysis/KernelInfo/enable-kernel-info/amdgpu.test
M llvm/test/Analysis/KernelInfo/flat-addrspace/amdgpu.test
M llvm/test/Analysis/KernelInfo/launch-bounds/amdgpu.ll
M llvm/test/Analysis/KernelInfo/openmp/README.md
M llvm/test/Analysis/KernelInfo/openmp/amdgpu.ll
M llvm/test/Analysis/ScalarEvolution/exit-count-non-strict.ll
M llvm/test/Analysis/ScalarEvolution/incorrect-exit-count.ll
M llvm/test/Assembler/atomic.ll
M llvm/test/Assembler/callbr.ll
A llvm/test/Assembler/invalid-load-store-atomic-elementwise.ll
A llvm/test/Bitcode/atomic-load-store-elementwise.ll
M llvm/test/Bitcode/compatibility.ll
A llvm/test/CodeGen/AArch64/GlobalISel/combine-fdiv-inlineasm-operand.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
A llvm/test/CodeGen/AArch64/GlobalISel/knownbits-vashr.mir
M llvm/test/CodeGen/AArch64/O3-pipeline.ll
M llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
M llvm/test/CodeGen/AArch64/sign-return-address.ll
A llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-bf16.ll
R llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc-bf16.ll
A llvm/test/CodeGen/AArch64/sve-fixed-length-fp-trunc-bf16.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-64-128bit-loads.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-64-128bit-stores.ll
A llvm/test/CodeGen/AArch64/sve-ptrue-coalesce.mir
A llvm/test/CodeGen/AArch64/windows-pac-invalid-a-key.ll
M llvm/test/CodeGen/AArch64/wineh-bti.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-add-nullptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ashr-narrow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fabs-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsub-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-itofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-lshr-narrow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-redundant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-neg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-amount-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-illegal-types.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-shlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic-shlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shifts.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-narrow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-shift.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.compr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.barrier.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbl-b32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-br.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel-system-sgprs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fixed-function-abi-vgpr-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-readnone-intrinsic-callsite.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-zext-vec-index.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/knownbits-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-amdgcn-fdiv-fast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-store-s16-true16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpyinline.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memmove.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memset.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memsetinline.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptr-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrmask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sbfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-constant-32bit.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-s16-true16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-strict_fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trap-gfx11.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ubfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx7.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx8-plus.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-constant-32bit.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.dispatch.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fract.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.frexp.mant.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.cd.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.implicit.ptr.buffer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.p1.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.live.mask.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mul24.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.queue.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.integer-minmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.setreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.sleep.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.softwqm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.strictwqm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wwm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.atomic.cmpxchg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.inline.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memmove.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.inline.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant32bit.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-divergent.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-legalize-range-metadata.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-divergent.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer-wrong-insert-point.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/merge-buffer-stores.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/min3-max3-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs-i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mmra.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/no-cse-nonlocal-convergent-instrs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/no-ctlz-from-umul-to-lshr-in-postlegalizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/no-ctlz-from-umul-to-lshr-in-postlegalizer.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/no-legalize-atomic.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/or.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-buildvector-identities.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-divrem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-merge.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-reassoc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-sextload-from-sextinreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-trunc-bitcast-buildvector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-unmerge-undef.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-zextload-from-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-load-and-mask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-sbfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-ubfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-divrem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-fptrunc_fpext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-redundant-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-sext_inreg-to-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-shuffle.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/promote-dependency-on-invariant-result.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-minmax-const.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-fmed3-minmax-const.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-redundant-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-umed3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.subdword.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx942.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.v2f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-minmax-uminmax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-uinc-udec-wrap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi-sat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui-sat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbankselect.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-whole-wave-functions.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sbfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/select-merge-values-build-vector-s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/selected-inst-flags.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shader-epilogs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector-pointer-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-divergent-addr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-uniform-addr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-weird-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/true16-merge-values-s16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/trunc-brc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/trunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/twoaddr-extract-dyn-v7f64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ubfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/umed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-ptr-add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/v_bfe_i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/xor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll
M llvm/test/CodeGen/AMDGPU/InlineAsmCrash.ll
M llvm/test/CodeGen/AMDGPU/add-max.ll
M llvm/test/CodeGen/AMDGPU/add_i128.ll
M llvm/test/CodeGen/AMDGPU/add_i64.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-initializer-unsupported.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-initializer.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/alignbit-pat.ll
M llvm/test/CodeGen/AMDGPU/allow-check.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-flat-scratch-init-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-intrinsic-missing-nocallback.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-min-agpr-alloc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-nocallback-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-trap-leaf.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-log.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-function-calls-option.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-llvm-debuginfo-analyzer.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn-codegen.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-uniform-waterfall.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-uniform-intrinsic-combine.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-uniform-temporal-divergence.ll
M llvm/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll
M llvm/test/CodeGen/AMDGPU/atomic-optimizer-promote-i8.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimization_split_dt_update.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_dpp_lds_expected_active_lanes.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-globalisel.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll
M llvm/test/CodeGen/AMDGPU/attributor-wwm.ll
M llvm/test/CodeGen/AMDGPU/barrier-elimination.ll
M llvm/test/CodeGen/AMDGPU/bf16-math.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
M llvm/test/CodeGen/AMDGPU/branch-uniformity.ll
M llvm/test/CodeGen/AMDGPU/call-constant.ll
M llvm/test/CodeGen/AMDGPU/call-constexpr.ll
M llvm/test/CodeGen/AMDGPU/call-encoding.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir
M llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll
M llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
M llvm/test/CodeGen/AMDGPU/coalescer-identical-values-undef.mir
M llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir
M llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
M llvm/test/CodeGen/AMDGPU/coalescer_remat.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf-broken.mir
M llvm/test/CodeGen/AMDGPU/collapse-endcf.mir
M llvm/test/CodeGen/AMDGPU/collapse-endcf2.mir
M llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll
M llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
M llvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir
M llvm/test/CodeGen/AMDGPU/commute-compares.ll
M llvm/test/CodeGen/AMDGPU/commute_modifiers.ll
M llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll
M llvm/test/CodeGen/AMDGPU/convergent-inlineasm.ll
M llvm/test/CodeGen/AMDGPU/convergent.mir
M llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir
M llvm/test/CodeGen/AMDGPU/cttz-elts.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll
M llvm/test/CodeGen/AMDGPU/dce-disjoint-intervals.mir
M llvm/test/CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll
M llvm/test/CodeGen/AMDGPU/debug-independence-revertScheduling.ll
M llvm/test/CodeGen/AMDGPU/debug-independence-scheduleRegion.ll
M llvm/test/CodeGen/AMDGPU/debug-value.ll
M llvm/test/CodeGen/AMDGPU/debug-value2.ll
M llvm/test/CodeGen/AMDGPU/debug_frame.ll
M llvm/test/CodeGen/AMDGPU/default_amdhsa_code_object_version.ll
M llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir
M llvm/test/CodeGen/AMDGPU/disable-preload-kernargs.ll
M llvm/test/CodeGen/AMDGPU/div-rem-fast-path.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-bfe-isel.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-bitreverse.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-ctpop.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-min-max.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-not-isel.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
M llvm/test/CodeGen/AMDGPU/do-not-unify-divergent-exit-nodes-with-musttail.ll
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-flat-scratch-svs.mir
M llvm/test/CodeGen/AMDGPU/enable-no-signed-zeros-fp-math.ll
M llvm/test/CodeGen/AMDGPU/endcf-loop-header.ll
M llvm/test/CodeGen/AMDGPU/endpgm-dce.mir
M llvm/test/CodeGen/AMDGPU/expert_scheduling_gfx12.mir
M llvm/test/CodeGen/AMDGPU/extload-align.ll
M llvm/test/CodeGen/AMDGPU/extract-load-i1.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector.ll
M llvm/test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll
M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fadd-fma-fmul-combine.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir
M llvm/test/CodeGen/AMDGPU/fix-vgpr-copies.mir
M llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll
M llvm/test/CodeGen/AMDGPU/fold-cndmask.mir
M llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir
M llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir
M llvm/test/CodeGen/AMDGPU/fold-fmul-to-neg-abs.ll
M llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
M llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir
M llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir
M llvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
M llvm/test/CodeGen/AMDGPU/fold-implicit-operand.mir
M llvm/test/CodeGen/AMDGPU/fold-over-exec.mir
M llvm/test/CodeGen/AMDGPU/fold-readlane.mir
M llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address-codegen.ll
M llvm/test/CodeGen/AMDGPU/fp-to-int-to-fp.ll
M llvm/test/CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir
M llvm/test/CodeGen/AMDGPU/freeze-other-uses-issue-198094.ll
M llvm/test/CodeGen/AMDGPU/generic-targets-require-v6.ll
M llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir
M llvm/test/CodeGen/AMDGPU/global-alias.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/global_smrd.ll
M llvm/test/CodeGen/AMDGPU/hoist-cond.ll
M llvm/test/CodeGen/AMDGPU/hsa-generic-target-features.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-deduced-arg-attr.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-1.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-3.ll
M llvm/test/CodeGen/AMDGPU/huge-number-operand-folds.mir
M llvm/test/CodeGen/AMDGPU/i1-copies-rpo.mir
M llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-phi-uniform-branch.ll
M llvm/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll
M llvm/test/CodeGen/AMDGPU/implicitarg-attributes.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/inline-calls.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-sgmask.ll
M llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir
M llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/invalid-inline-asm-constraint-crash.ll
M llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll
M llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
M llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
M llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll
M llvm/test/CodeGen/AMDGPU/issue120256-annotate-constexpr-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/issue176578.ll
M llvm/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll
M llvm/test/CodeGen/AMDGPU/kernel_code_t_recurse.ll
M llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/knownbits-recursion.ll
M llvm/test/CodeGen/AMDGPU/lcssa-optnone.ll
M llvm/test/CodeGen/AMDGPU/lds-alignment.ll
M llvm/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll
M llvm/test/CodeGen/AMDGPU/lds-size.ll
M llvm/test/CodeGen/AMDGPU/liveness.mir
M llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.compr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdiv.fast.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.2dmsaa.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.hsa.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.u24.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.legacy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getpc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.chain.arg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.format.i8.xfail.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sudot4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sudot8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/loop-vector-sink.ll
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.xfail.mir
M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-constexpr-alias.ll
M llvm/test/CodeGen/AMDGPU/lower-intrinsics-barriers.ll
M llvm/test/CodeGen/AMDGPU/lower-intrinsics-cluster-barrier.ll
M llvm/test/CodeGen/AMDGPU/lower-intrinsics-split-barriers.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-check-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir
M llvm/test/CodeGen/AMDGPU/machinelicm-copy-like-instrs.mir
M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
M llvm/test/CodeGen/AMDGPU/madak-inline-constant.mir
M llvm/test/CodeGen/AMDGPU/madmk-madak-encoding-size.ll
M llvm/test/CodeGen/AMDGPU/madmk.ll
M llvm/test/CodeGen/AMDGPU/max-sgprs.ll
M llvm/test/CodeGen/AMDGPU/mcp-use-before-def.mir
M llvm/test/CodeGen/AMDGPU/mem-builtins.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/memset-pattern.ll
M llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir
M llvm/test/CodeGen/AMDGPU/merge-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-m0.mir
M llvm/test/CodeGen/AMDGPU/mesa_regression.ll
M llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir
M llvm/test/CodeGen/AMDGPU/movrels-bug.mir
M llvm/test/CodeGen/AMDGPU/new-pm-machine-analysis.mir
M llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll
M llvm/test/CodeGen/AMDGPU/no-limit-coalesce.mir
M llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll
M llvm/test/CodeGen/AMDGPU/not-scalarize-volatile-load.ll
M llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll
M llvm/test/CodeGen/AMDGPU/nullptr.ll
M llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir
M llvm/test/CodeGen/AMDGPU/opencl-image-metadata.ll
M llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/opt_exec_copy_fold.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-def-after-use.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir
M llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-bf16.ll
M llvm/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll
M llvm/test/CodeGen/AMDGPU/peephole-opt-regseq-removal.mir
M llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permlane16_var-op-sel.ll
M llvm/test/CodeGen/AMDGPU/pr155452.ll
M llvm/test/CodeGen/AMDGPU/preserve-user-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/prevent-fmul-hoist-ir.ll
M llvm/test/CodeGen/AMDGPU/printf_builtin.ll
M llvm/test/CodeGen/AMDGPU/printf_nobuiltin.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-budget-exhausted.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-shufflevector.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/propagate-amdgpu-cluster-dims.ll
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll
M llvm/test/CodeGen/AMDGPU/rcp_iflag.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll
M llvm/test/CodeGen/AMDGPU/reduce-saveexec.mir
M llvm/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll
M llvm/test/CodeGen/AMDGPU/reduction.ll
M llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir
M llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir
M llvm/test/CodeGen/AMDGPU/regcoalescer-resolve-lane-conflict-by-subranges.mir
M llvm/test/CodeGen/AMDGPU/register-count-comments.ll
M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.mir
M llvm/test/CodeGen/AMDGPU/remat-dead-subreg.mir
M llvm/test/CodeGen/AMDGPU/rename-disconnected-bug.ll
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-dbg.mir
M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir
M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-phi.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.gfx950.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
M llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sched.barrier.inverted.mask.ll
M llvm/test/CodeGen/AMDGPU/schedule-global-loads.ll
M llvm/test/CodeGen/AMDGPU/schedule-physregdeps.mir
M llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdivrem24.ll
M llvm/test/CodeGen/AMDGPU/sdivrem64.r600.ll
M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
M llvm/test/CodeGen/AMDGPU/select-opt.ll
M llvm/test/CodeGen/AMDGPU/set-wave-priority.ll
M llvm/test/CodeGen/AMDGPU/setcc-select-hi32mask.ll
M llvm/test/CodeGen/AMDGPU/setcc-select.ll
M llvm/test/CodeGen/AMDGPU/setcc-sext.ll
M llvm/test/CodeGen/AMDGPU/setcc.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
M llvm/test/CodeGen/AMDGPU/sgpr-to-vreg1-copy.mir
M llvm/test/CodeGen/AMDGPU/sgprcopies.ll
M llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
M llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir
M llvm/test/CodeGen/AMDGPU/si-i1-copies.mir
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-kill.ll
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir
M llvm/test/CodeGen/AMDGPU/si-lower-i1-copies.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-cycle-header.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-body.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-latch.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-multi-entry-cycle.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir
M llvm/test/CodeGen/AMDGPU/simplifydemandedbits-recursion.ll
M llvm/test/CodeGen/AMDGPU/skip-branch-taildup-ret.mir
M llvm/test/CodeGen/AMDGPU/skip-branch-trap.ll
M llvm/test/CodeGen/AMDGPU/spill-before-exec.mir
M llvm/test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll
M llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
M llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
M llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir
M llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll
M llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll
M llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
M llvm/test/CodeGen/AMDGPU/splitkit-nolivesubranges.mir
M llvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/AMDGPU/stop-tail-duplicate-cfg-intrinsic.mir
M llvm/test/CodeGen/AMDGPU/subreg-intervals.mir
M llvm/test/CodeGen/AMDGPU/subreg_interference.mir
M llvm/test/CodeGen/AMDGPU/tail-dup-bundle.mir
M llvm/test/CodeGen/AMDGPU/trap.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-f64-to-f16.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-regsequence.mir
M llvm/test/CodeGen/AMDGPU/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udivrem24.ll
M llvm/test/CodeGen/AMDGPU/udivrem64.r600.ll
M llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
M llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll
M llvm/test/CodeGen/AMDGPU/unpack-non-coissue-insts-post-ra-scheduler.mir
M llvm/test/CodeGen/AMDGPU/unsupported-av-load.ll
M llvm/test/CodeGen/AMDGPU/unsupported-av-store.ll
M llvm/test/CodeGen/AMDGPU/unsupported-calls.ll
M llvm/test/CodeGen/AMDGPU/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/AMDGPU/valu-i1.ll
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
M llvm/test/CodeGen/AMDGPU/vector-legalizer-divergence.ll
M llvm/test/CodeGen/AMDGPU/verify-sop.mir
M llvm/test/CodeGen/AMDGPU/vgpr-count-compute.ll
M llvm/test/CodeGen/AMDGPU/vgpr-count-graphics-chain.ll
M llvm/test/CodeGen/AMDGPU/vgpr-count-graphics.ll
M llvm/test/CodeGen/AMDGPU/vgpr-large-tuple-alloc-error.ll
A llvm/test/CodeGen/AMDGPU/vgpr-setreg-pred-block.mir
M llvm/test/CodeGen/AMDGPU/vgpr_constant64_to_sgpr.mir
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
M llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
M llvm/test/CodeGen/AMDGPU/vni8-live-reg-opt.ll
M llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
M llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-debug-non-first-terminators.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-no-redundant.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-trailing.mir
M llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll
M llvm/test/CodeGen/AMDGPU/wqm-debug-instr.mir
M llvm/test/CodeGen/AMDGPU/zext-i64-bit-operand.ll
M llvm/test/CodeGen/AMDGPU/zext-lid.ll
M llvm/test/CodeGen/ARM/select-imm.ll
M llvm/test/CodeGen/BPF/sink-min-max.ll
M llvm/test/CodeGen/DirectX/ContainerData/ContainerFlags.ll
A llvm/test/CodeGen/Hexagon/rdfopt-liveins-hang.mir
A llvm/test/CodeGen/LoongArch/lasx/issue207316.ll
M llvm/test/CodeGen/LoongArch/lasx/xvexth.ll
M llvm/test/CodeGen/LoongArch/lsx/vexth.ll
M llvm/test/CodeGen/MIR/AMDGPU/cfi-pseudos.mir
M llvm/test/CodeGen/MIR/AMDGPU/custom-pseudo-source-values.ll
M llvm/test/CodeGen/MIR/AMDGPU/dead-flag-on-use-operand-parse-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/instr-mmra-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/instr-mmra.mir
M llvm/test/CodeGen/MIR/AMDGPU/killed-flag-on-def-parse-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-min-num-agprs.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-metadata.mir
M llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir
M llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-expect-id.mir
M llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-parse.mir
M llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-undefine-matadata.mir
M llvm/test/CodeGen/MIR/AMDGPU/parse-cfi-unsigned-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-invalid-register-class-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-invalid-register-name-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-mfi.ll
M llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-stack-type-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/ptradd-flags.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_wait_alu-errors.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_wait_alu.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_wait_loadcnt_dscnt-errors.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_wait_loadcnt_dscnt.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_waitcnt-errors.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_waitcnt.mir
M llvm/test/CodeGen/MIR/AMDGPU/s_waitcnt_soft.mir
M llvm/test/CodeGen/MIR/AMDGPU/subreg-def-is-not-ssa.mir
M llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir
M llvm/test/CodeGen/MIR/AMDGPU/virtreg-uses-unallocatable-class.mir
M llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-bad-phys.mir
M llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-bad-split.mir
M llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-self-split.mir
M llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash.mir
A llvm/test/CodeGen/Mips/fake-use.ll
M llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
M llvm/test/CodeGen/NVPTX/atomicrmw-allow-ftz-atomics.ll
M llvm/test/CodeGen/NVPTX/atomicrmw-sm60.ll
M llvm/test/CodeGen/NVPTX/atomicrmw-sm70.ll
M llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll
M llvm/test/CodeGen/NVPTX/atomicrmw.py
M llvm/test/CodeGen/NVPTX/atomics.ll
A llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-xchg.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-xchg-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-xchg-rv64.mir
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
A llvm/test/CodeGen/RISCV/rvp-widening-convert-isel.ll
A llvm/test/CodeGen/RISCV/sched-model-load-latency.ll
A llvm/test/CodeGen/RISCV/sched-model-mispredict-penalty.ll
A llvm/test/CodeGen/RISCV/short-forward-branch-opt-zibi.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable-default-address-space.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable-init-expr.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable-multi-gve.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable-no-backing-var.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable-no-type.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable-path-null.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable-skip-static-member.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable-skip-type-not-in-regs.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable-static-member.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-global-variable.ll
M llvm/test/CodeGen/SPIRV/hlsl-resources/SignedBufferLoadStore.ll
M llvm/test/CodeGen/SPIRV/hlsl-resources/UnsignedBufferLoadStore.ll
A llvm/test/CodeGen/SPIRV/legalization/signed-narrow-int.ll
M llvm/test/CodeGen/SPIRV/sitofp-with-bool.ll
M llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll
M llvm/test/CodeGen/WebAssembly/add-prototypes.ll
M llvm/test/CodeGen/WebAssembly/lower-em-exceptions-allowed.ll
M llvm/test/CodeGen/X86/bitcnt-load-with-cmov.ll
M llvm/test/CodeGen/X86/bmi.ll
M llvm/test/CodeGen/X86/bmi2.ll
M llvm/test/CodeGen/X86/fmaddsub-combine.ll
M llvm/test/CodeGen/X86/fmsubadd-combine.ll
R llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt-i64.ll
R llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt.ll
R llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt-i64.ll
R llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt.ll
A llvm/test/CodeGen/X86/tailcall-i686-pic.ll
M llvm/test/CodeGen/X86/vpdpwssd.ll
M llvm/test/DebugInfo/AMDGPU/bitcast-store-combine-debugloc.ll
M llvm/test/DebugInfo/AMDGPU/cfi.ll
M llvm/test/DebugInfo/AMDGPU/code-pointer-size.ll
M llvm/test/DebugInfo/AMDGPU/dbg-value-sched-crash.ll
M llvm/test/DebugInfo/AMDGPU/debug-loc-copy.ll
M llvm/test/DebugInfo/AMDGPU/dwarfdump-relocs.ll
M llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-cfi-directives.s
M llvm/test/DebugInfo/AMDGPU/pointer-address-space.ll
M llvm/test/DebugInfo/AMDGPU/print-reg-name.s
M llvm/test/DebugInfo/AMDGPU/variable-locations.ll
M llvm/test/DebugInfo/AMDGPU/wqm-wwm-debug-loc.ll
A llvm/test/Instrumentation/Instrumentor/load_store_gpu_ind.json
A llvm/test/Instrumentation/Instrumentor/load_store_gpu_ind.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics-upgrade.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512dq-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512vl-intrinsics.ll
M llvm/test/MC/AArch64/LFI/guard-elim.s
M llvm/test/MC/AArch64/LFI/mem-lr.s
A llvm/test/MC/AArch64/LFI/pac-errors.s
A llvm/test/MC/AArch64/LFI/pac.s
M llvm/test/MC/AArch64/LFI/return.s
A llvm/test/MC/AMDGPU/amdhsa-kernel-prologue.s
M llvm/test/MC/AMDGPU/gfx13_asm_vds.s
M llvm/test/MC/AMDGPU/hsa-gfx1250-v4.s
M llvm/test/MC/AMDGPU/hsa-gfx1251-v4.s
M llvm/test/MC/Disassembler/WebAssembly/wasm.txt
A llvm/test/MC/Hexagon/relax-align.s
A llvm/test/TableGen/CodeEmitterBaseEncodingPool.td
M llvm/test/TableGen/HwModeEncodeAPInt.td
M llvm/test/TableGen/MacroFusion.td
M llvm/test/TableGen/true-false.td
A llvm/test/ThinLTO/X86/Inputs/cache-defined-globals-order.ll
A llvm/test/ThinLTO/X86/cache-defined-globals-order.ll
M llvm/test/Transforms/AggressiveInstCombine/AMDGPU/fold-consecutive-loads.ll
M llvm/test/Transforms/AggressiveInstCombine/AMDGPU/fold-loads-multiple-uses.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f32-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f32-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f64-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f64-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i32-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i32-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i64-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i64-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-mmra.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-private-gas.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2bf16-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2bf16-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2f16-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2f16-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomicrmw-flat-noalias-addrspace.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomicrmw-fp-vector.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomicrmw-integer-ops-0-to-add-0.ll
A llvm/test/Transforms/ConstraintElimination/and-negative.ll
M llvm/test/Transforms/ConstraintElimination/eq.ll
M llvm/test/Transforms/ConstraintElimination/induction-nowrap-from-scev-not-ir.ll
M llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-wrapping.ll
M llvm/test/Transforms/ConstraintElimination/ne.ll
M llvm/test/Transforms/ConstraintElimination/or-non-negative.ll
M llvm/test/Transforms/ConstraintElimination/reproducer-remarks.ll
M llvm/test/Transforms/ConstraintElimination/trunc.ll
A llvm/test/Transforms/IndVarSimplify/iv-widen-addrec-flag-inferred-late.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/phinode-address-infer.ll
M llvm/test/Transforms/InstCombine/AMDGPU/bitcast-fold-lane-ops.ll
M llvm/test/Transforms/InstCombine/AMDGPU/fmed3.ll
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.wave.shuffle.ll
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.wavefrontsize.ll
M llvm/test/Transforms/InstCombine/AMDGPU/mbcnt.ll
M llvm/test/Transforms/InstCombine/AMDGPU/rcp-contract-rsq.ll
M llvm/test/Transforms/InstCombine/AMDGPU/simplify-demanded-vector-elts-lane-intrinsics.ll
M llvm/test/Transforms/InstCombine/AMDGPU/trivially-uniform.ll
M llvm/test/Transforms/InstCombine/known-bits.ll
M llvm/test/Transforms/InstCombine/mul.ll
M llvm/test/Transforms/InstCombine/sincos.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/load-i1-misaligned.ll
A llvm/test/Transforms/LoopIdiom/AArch64/cyclic-redundancy-check.ll
A llvm/test/Transforms/LoopIdiom/RISCV/cyclic-redundancy-check.ll
A llvm/test/Transforms/LoopIdiom/X86/cyclic-redundancy-check.ll
M llvm/test/Transforms/LoopIdiom/cyclic-redundancy-check.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/different-addrspace-addressing-mode-loops.ll
A llvm/test/Transforms/LoopUnroll/full-unroll-scev-invalidation.ll
M llvm/test/Transforms/LoopVectorize/AMDGPU/buffer-fat-pointer.ll
M llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction-cost.ll
M llvm/test/Transforms/LoopVectorize/VPlan/RISCV/expand-scev.ll
M llvm/test/Transforms/LoopVectorize/VPlan/dissolve-replicate-regions.ll
M llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i16-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i32-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i64-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i8-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/handle-iptr-with-data-layout-to-not-assert.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-half.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2-indices-0u.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-01u.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-0uu.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-012u.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-01uu.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-0uuu.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-gather-i32-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-gather-i64-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-load-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-store-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i32.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i64.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i32.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i64.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i32.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i64.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i8.ll
M llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
A llvm/test/Transforms/LowerTypeTests/icall-branch-funnel-invalid-operand.ll
M llvm/test/Transforms/PhaseOrdering/constraint-eliminiation-interactions.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/exp2-vectorize.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/external-shuffle.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/extract-ordering.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/inst-count-heuristic.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/notriviallyvectorizableintrinsicoperands.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f16.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/vectorize-i8.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/zext-duplicate-shift.ll
A llvm/test/Transforms/SLPVectorizer/X86/loop-invariant-gather-inst-count.ll
A llvm/test/Transforms/SLPVectorizer/X86/masked-blended-loads.ll
M llvm/test/Transforms/SLPVectorizer/X86/mul-shl-nsw-intmin.ll
A llvm/test/Transforms/SLPVectorizer/sub-nsw-icmp-eq-zero-reorder.ll
A llvm/test/Transforms/SROA/sroa-self-referential-load.ll
M llvm/test/Transforms/SandboxVectorizer/AMDGPU/basic.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/amdgpu-large-lds-offset.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/rebuild-trunc.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/reorder-gep-inbounds.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/reorder-gep.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/reunite-exts-source-types.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/reunite-exts.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn.ll
M llvm/test/Transforms/VectorCombine/AMDGPU/combine-scalar-selects.ll
M llvm/test/Transforms/VectorCombine/AMDGPU/extract-insert-i8.ll
M llvm/test/Transforms/VectorCombine/AMDGPU/shuffles-of-length-changing-shuffles.ll
M llvm/test/Transforms/VectorCombine/X86/fold-signbit-reduction-cmp.ll
M llvm/test/Verifier/matrix-intrinsics.ll
A llvm/test/tools/llvm-dwp/SystemZ/big_endian_info_v5.s
M llvm/test/tools/llvm-dwp/X86/compress.test
M llvm/test/tools/llvm-reduce/mir/drop-ir-references.mir
M llvm/test/tools/llvm-reduce/mir/generic-vreg.mir
M llvm/test/tools/llvm-reduce/mir/infer-triple.mir
M llvm/test/tools/llvm-reduce/mir/input-file-does-not-exist.mir
M llvm/test/tools/llvm-reduce/mir/instr-reduce-dead-def.mir
M llvm/test/tools/llvm-reduce/mir/multiple-functions.mir
M llvm/test/tools/llvm-reduce/mir/preserve-block-info.mir
M llvm/test/tools/llvm-reduce/mir/preserve-frame-info.mir
M llvm/test/tools/llvm-reduce/mir/preserve-func-info.mir
M llvm/test/tools/llvm-reduce/mir/preserve-machine-function-info-amdgpu.mir
M llvm/test/tools/llvm-reduce/mir/preserve-max-call-frame-size.mir
M llvm/test/tools/llvm-reduce/mir/preserve-mem-operands.mir
M llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir
M llvm/test/tools/llvm-reduce/mir/reduce-instruction-flags.mir
M llvm/test/tools/llvm-reduce/mir/reduce-instruction-unreachable-block.mir
M llvm/test/tools/llvm-reduce/mir/reduce-register-defs.mir
M llvm/test/tools/llvm-reduce/mir/reduce-register-hints.mir
M llvm/test/tools/llvm-reduce/mir/reduce-register-masks.mir
M llvm/test/tools/llvm-reduce/mir/reduce-register-uses-generic.mir
M llvm/test/tools/llvm-reduce/mir/reduce-register-uses.mir
M llvm/test/tools/llvm-reduce/mir/remove-frame-destroy.mir
M llvm/test/tools/llvm-reduce/mir/subreg-def0.mir
M llvm/test/tools/llvm-reduce/mir/subreg-def1.mir
M llvm/test/tools/llvm-reduce/mir/tracks-reg-liveness.mir
M llvm/test/tools/llvm-reduce/mir/undef-virt-reg.mir
A llvm/test/tools/llvm-reduce/remove-funcs-inline-history.ll
M llvm/test/tools/llvm-split/AMDGPU/address-taken-externalize-with-call.ll
M llvm/test/tools/llvm-split/AMDGPU/address-taken-externalize.ll
M llvm/test/tools/llvm-split/AMDGPU/declarations.ll
M llvm/test/tools/llvm-split/AMDGPU/indirect-call-inline-asm-debug.ll
M llvm/test/tools/llvm-split/AMDGPU/indirect-call-inline-asm.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-cost-ranking.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependencies.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-duplication.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-external.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-indirect-callee-md.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-indirect.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-overridable.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-global-variables-noexternal.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-global-variables.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-load-balancing.ll
M llvm/test/tools/llvm-split/AMDGPU/kernels-no-dependencies.ll
M llvm/test/tools/llvm-split/AMDGPU/large-kernels-merging-weak_odr.ll
M llvm/test/tools/llvm-split/AMDGPU/large-kernels-merging.ll
M llvm/test/tools/llvm-split/AMDGPU/non-kernels-dependencies.ll
M llvm/test/tools/llvm-split/AMDGPU/non-kernels-dependency-indirect.ll
M llvm/test/tools/llvm-split/AMDGPU/preserve-globals.ll
M llvm/test/tools/llvm-split/AMDGPU/recursive-search-2.ll
M llvm/test/tools/llvm-split/AMDGPU/recursive-search-8.ll
A llvm/test/tools/yaml2obj/COFF/output-limit.yaml
M llvm/tools/llvm-reduce/deltas/ReduceFunctions.cpp
M llvm/tools/yaml2obj/yaml2obj.cpp
M llvm/unittests/ADT/BitVectorTest.cpp
M llvm/unittests/ADT/EytzingerTest.cpp
M llvm/unittests/CodeGen/GlobalISel/GISelUtilsTest.cpp
M llvm/unittests/CodeGen/RematerializerTest.cpp
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M llvm/unittests/FuzzMutate/StrategiesTest.cpp
M llvm/unittests/IR/MetadataTest.cpp
M llvm/unittests/IR/PatternMatch.cpp
M llvm/unittests/IR/VerifierTest.cpp
M llvm/unittests/Target/AMDGPU/AMDGPUMCExprTest.cpp
M llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
M llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.h
M llvm/unittests/Target/AMDGPU/CSETest.cpp
M llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp
M llvm/unittests/Target/AMDGPU/ExecMayBeModifiedBeforeAnyUse.cpp
M llvm/unittests/Target/AMDGPU/GCNRegPressureTest.cpp
M llvm/unittests/Target/AMDGPU/PALMetadata.cpp
M llvm/unittests/Target/AMDGPU/UniformityAnalysisTest.cpp
M llvm/unittests/Transforms/Utils/CodeExtractorTest.cpp
M llvm/utils/TableGen/CodeEmitterGen.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.h
M llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.cpp
M llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.h
M llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp
M llvm/utils/TableGen/RegisterBankEmitter.cpp
M llvm/utils/gn/README.rst
M llvm/utils/gn/build/BUILD.gn
M llvm/utils/gn/build/BUILDCONFIG.gn
M llvm/utils/gn/build/buildflags.gni
M llvm/utils/gn/build/symlink_or_copy.gni
M llvm/utils/gn/build/toolchain/BUILD.gn
M llvm/utils/gn/secondary/BUILD.gn
M llvm/utils/gn/secondary/bolt/tools/driver/BUILD.gn
M llvm/utils/gn/secondary/clang-tools-extra/clang-doc/tool/BUILD.gn
M llvm/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn
M llvm/utils/gn/secondary/clang-tools-extra/clangd/xpc/framework/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/ScalableStaticAnalysis/Analyses/BUILD.gn
M llvm/utils/gn/secondary/clang/tools/clang-ssaf-linker/BUILD.gn
M llvm/utils/gn/secondary/clang/tools/driver/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/CIR/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/ScalableStaticAnalysis/BUILD.gn
M llvm/utils/gn/secondary/lld/tools/lld/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-ar/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-cxxfilt/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-debuginfod-find/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-debuginfod/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-dwp/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-libtool-darwin/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-lipo/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-ml/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-nm/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-objcopy/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-objdump/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-rc/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-readobj/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-readtapi/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-size/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-strings/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-symbolizer/BUILD.gn
M llvm/utils/lit/lit/LitConfig.py
M llvm/utils/lit/lit/TestingConfig.py
M llvm/utils/lit/lit/cl_arguments.py
M llvm/utils/lit/lit/main.py
A llvm/utils/lit/tests/Inputs/pass-env/lit.cfg
A llvm/utils/lit/tests/Inputs/pass-env/test.txt
A llvm/utils/lit/tests/pass-env.py
M llvm/utils/profcheck-xfail.txt
M mlir/include/mlir/Conversion/Passes.h
M mlir/include/mlir/Conversion/Passes.td
A mlir/include/mlir/Conversion/SCFToAffine/SCFToAffine.h
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCCGAttributes.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCCGOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsCG.h
M mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.h
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/lib/Conversion/CMakeLists.txt
M mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp
A mlir/lib/Conversion/SCFToAffine/CMakeLists.txt
A mlir/lib/Conversion/SCFToAffine/SCFToAffine.cpp
M mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/lib/Dialect/NVGPU/IR/NVGPUDialect.cpp
A mlir/lib/Dialect/OpenACC/Transforms/ACCCGToGPU.cpp
M mlir/lib/Dialect/OpenACC/Transforms/CMakeLists.txt
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsCG.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.7
[skip ci]
Compare: https://github.com/llvm/llvm-project/compare/d9d8502ecaa9...14bb933c87a1
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