[all-commits] [llvm/llvm-project] 38104c: [LLVM][SVE] Add MachineInst pass to coalesce PTRUE...

[Paul Walker via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 38104cf836c3903647c917a5b251e938f4eadbb9
      https://github.com/llvm/llvm-project/commit/38104cf836c3903647c917a5b251e938f4eadbb9
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2026-07-17 (Fri, 17 Jul 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64.h
    A llvm/lib/Target/AArch64/AArch64PTrueCoalescing.cpp
    M llvm/lib/Target/AArch64/AArch64PassRegistry.def
    M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
    M llvm/lib/Target/AArch64/CMakeLists.txt
    M llvm/test/CodeGen/AArch64/O3-pipeline.ll
    A llvm/test/CodeGen/AArch64/sve-ptrue-coalesce.mir

  Log Message:
  -----------
  [LLVM][SVE] Add MachineInst pass to coalesce PTRUE instructions. (#204820)

SVE predicate registers contain a bit for each byte of a data register.
When operating on bigger element types the overlaping predicate bits are
grouped together but typically only the least-significant-bit is read as
part of the operation. This means the value of the other bits does not
affect the operation, making it possible to use the result of PTRUE for
a larger element typed operation, assuming the predicate patterns are
equivalent. For example:

  ADD_S (PTRUE_H 31), Z0, Z1 == ADD_S (PTRUE_S 31), Z0, Z1

AArch64PTrueCoalescingPass uses this fact to reduce the number of PTRUE
instructions in a function, with the general trend towards needing a
single PTRUE based on the smallest element type in use.

NOTE: The pass will be enabled by default using a dedicated PR to make
it easier to revert if something goes wrong.



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