[all-commits] [llvm/llvm-project] f2ef56: [AMDGPU] Refactor GFX11 VALU Mask Hazard Waitcnt M...

[Carl Ritson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f2ef5670cf70371153caeb0ebbeae2323a61f8e0
      https://github.com/llvm/llvm-project/commit/f2ef5670cf70371153caeb0ebbeae2323a61f8e0
  Author: Carl Ritson <carl.ritson at amd.com>
  Date:   2026-07-17 (Fri, 17 Jul 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
    M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_dpp_lds_expected_active_lanes.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
    M llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir
    M llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
    M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir

  Log Message:
  -----------
  [AMDGPU] Refactor GFX11 VALU Mask Hazard Waitcnt Merging (#169213)

Move GFX11 SGPR VALU mask hazard waitcnt merging to the a forward scan
within the AMDGPUWaitSGPRHazard pass.
This simplifies the hazard recognizer code and allows merging of waitcnt
instructions in cases where SGPRs unaffected by pending writes are used.
In turn this greatly decreasing numbers of waits inserted in sequences
of V_CMP instructions writing SGPRs improving VALU pipeline performance.



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