[all-commits] [llvm/llvm-project] 7812fe: [RISCV][P-ext] Add RISCVISD::PWZIP for RV32. (#210...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7812fef524a0aef0b34599c2eb81b66843fbcdd8
      https://github.com/llvm/llvm-project/commit/7812fef524a0aef0b34599c2eb81b66843fbcdd8
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2026-07-16 (Thu, 16 Jul 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
    A llvm/test/CodeGen/RISCV/rvp-widening-convert-isel.ll

  Log Message:
  -----------
  [RISCV][P-ext] Add RISCVISD::PWZIP for RV32. (#210134)

This node takes 2 32-bit vector inputs and produces a 64-bit vector
result. By extracting the subvector during lowering, we expose more
opportunities for optimizations.



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