[all-commits] [llvm/llvm-project] c9ec54: [RISCV] Add DUMMY_REG_PAIR_WITH_X0->GPR copy to co...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c9ec54a8a781166546c1001a8bfb2448fbacda44
      https://github.com/llvm/llvm-project/commit/c9ec54a8a781166546c1001a8bfb2448fbacda44
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2026-07-16 (Thu, 16 Jul 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/test/CodeGen/RISCV/rvp-simd-64.ll

  Log Message:
  -----------
  [RISCV] Add DUMMY_REG_PAIR_WITH_X0->GPR copy to copyPhysReg. (#209964)

The register coalescer can convert (extract_subreg x0_pair, sub_gpr_odd)
to a read of DUMMY_REG_PAIR_WITH_X0. This patch treats it the same as a
copy from X0.

I don't know if this is a good long term fix, but I think it's ok for
now. I will continue to look for other options.



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