[all-commits] [llvm/llvm-project] 65180a: [VPlan] Relax address constraints during stride an...

[Mel Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 65180a50117244b4758e03175bed2dc34fc74f91
      https://github.com/llvm/llvm-project/commit/65180a50117244b4758e03175bed2dc34fc74f91
  Author: Mel Chen <mel.chen at sifive.com>
  Date:   2026-07-16 (Thu, 16 Jul 2026)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
    M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll

  Log Message:
  -----------
  [VPlan] Relax address constraints during stride analysis (#209168)

VPlanTransforms::convertToStridedAccesses() only handled loads whose
address was a VPWidenGEPRecipe, missing pointer-induction loops where
the address is computed differently. Analyze the address VPValue
directly so these cases are also converted to strided loads.

Fixed #207171



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