[all-commits] [llvm/llvm-project] cc79c8: [CIR][RISCV] Support Zihintntl builtins (#205468)

[Jianjian Guan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cc79c8cdc4e7f0a8a968e1d8c5b91b14ce1e183a
      https://github.com/llvm/llvm-project/commit/cc79c8cdc4e7f0a8a968e1d8c5b91b14ce1e183a
  Author: Jianjian Guan <jacquesguan at me.com>
  Date:   2026-07-16 (Thu, 16 Jul 2026)

  Changed paths:
    M clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
    M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
    M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVMIR.cpp
    A clang/test/CIR/CodeGenBuiltins/RISCV/riscv-zihintntl.c

  Log Message:
  -----------
  [CIR][RISCV] Support Zihintntl builtins (#205468)

Include __builtin_riscv_ntl_load and __builtin_riscv_ntl_store.



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