[all-commits] [llvm/llvm-project] b6059b: [MCSched] Allow tuning LoadLatency/MispredictPenal...

[Sam Elliott via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b6059b6ce21886c3f8644355ae9017cf3ba04aad
      https://github.com/llvm/llvm-project/commit/b6059b6ce21886c3f8644355ae9017cf3ba04aad
  Author: Sam Elliott <aelliott at qti.qualcomm.com>
  Date:   2026-07-15 (Wed, 15 Jul 2026)

  Changed paths:
    M llvm/include/llvm/CodeGen/BasicTTIImpl.h
    M llvm/include/llvm/CodeGen/TargetInstrInfo.h
    M llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
    M llvm/lib/CodeGen/EarlyIfConversion.cpp
    M llvm/lib/CodeGen/SelectOptimize.cpp
    M llvm/lib/CodeGen/TargetInstrInfo.cpp
    M llvm/lib/CodeGen/TargetSchedule.cpp
    M llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
    M llvm/lib/Target/ARM/ARMSubtarget.cpp
    M llvm/lib/Target/ARM/ARMSubtarget.h
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    M llvm/lib/Target/X86/X86CmovConversion.cpp
    A llvm/test/CodeGen/RISCV/sched-model-load-latency.ll
    A llvm/test/CodeGen/RISCV/sched-model-mispredict-penalty.ll

  Log Message:
  -----------
  [MCSched] Allow tuning LoadLatency/MispredictPenalty (#203139)

This means an existing scheduling model can be tweaked at runtime to
support an unknown processor rather than adding an entirely new model.

This is done with TargetSubtargetInfo so that specific targets can
override the relevant callbacks and the mechanism can eventually work
with LTO.



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