[all-commits] [llvm/llvm-project] 2c57ae: [SPIRV] Sign-extend operands of sign-sensitive ops...

[Faijul Amin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2c57ae5efb0159521287c80255e3a604f3b0dcfe
      https://github.com/llvm/llvm-project/commit/2c57ae5efb0159521287c80255e3a604f3b0dcfe
  Author: Faijul Amin <md.faijul.amin at intel.com>
  Date:   2026-07-15 (Wed, 15 Jul 2026)

  Changed paths:
    M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
    M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
    A llvm/test/CodeGen/SPIRV/legalization/signed-narrow-int.ll

  Log Message:
  -----------
  [SPIRV] Sign-extend operands of sign-sensitive ops on sub-pow2 widths (#203661)

## Problem

Without extensions, `SPIRVPreLegalizer` widens sub-pow2 scalars (`s4`,
`s24`, ...) to the next legal width by relabeling the LLT only — no
sign-extension is inserted. Sign-sensitive ops (signed `G_ICMP`,
`G_ASHR`, `G_SDIV`, `G_SREM`) then read the sign bit at the wrong
position. As a result `icmp slt i4 %x, 0` always returned `false` even
for negative `i4`.

## Fix

- `SPIRVLegalizerInfo.cpp`: declare `G_SEXT_INREG.lower()` so the
legalizer expands it to `(x << k) ashr k`.
- `SPIRVPreLegalizer.cpp`: before the widening loop, emit `G_SEXT_INREG`
on each value operand of a sign-sensitive MI whose original width is
sub-pow2.
## Test

`llvm/test/CodeGen/SPIRV/legalization/signed-narrow-int.ll` covers `icmp
slt`/`ashr`/`sdiv`/`srem` on `i4`, `icmp slt` on `i24`, and negative
cases (`icmp ult`, `lshr`) that must not emit sign-extension shifts



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications