[all-commits] [llvm/llvm-project] ee08b1: AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu...

Matt Arsenault via All-commits all-commits at lists.llvm.org
Wed Jul 15 08:51:52 PDT 2026 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ee08b1c5553cd558458b9570646038b9422ca397
      https://github.com/llvm/llvm-project/commit/ee08b1c5553cd558458b9570646038b9422ca397
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-15 (Wed, 15 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-add-nullptr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ashr-narrow.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fabs-fneg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fcanonicalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsub-fneg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-itofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-lshr-narrow.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-redundant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-neg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-amount-zext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-illegal-types.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-shlsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic-shlsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shifts.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-narrow.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-shift.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.barrier.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbl-b32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitcast.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-br.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fixed-function-abi-vgpr-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-readnone-intrinsic-callsite.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-zext-vec-index.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/knownbits-ptrtoint.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-amdgcn-fdiv-fast.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpyinline.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memmove.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memset.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memsetinline.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values-build-vector.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrtoint.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.implicit.ptr.buffer.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.inline.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memmove.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.inline.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/merge-buffer-stores.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-reassoc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-select.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/selected-inst-flags.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector-pointer-crash.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll

  Log Message:
  -----------
  AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (53) (#209779)

Fold the explicit -mcpu subtarget into the amdgpu subarch triple on
llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 ->
-mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu
following the default-subtarget pinning. Codegen output is unchanged.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)



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