[all-commits] [llvm/llvm-project] 3a6048: Revert "[ARM] Use .reloc for weak symbols in PIC m...
Aiden Grossman via All-commits
all-commits at lists.llvm.org
Wed Jul 15 07:04:02 PDT 2026
Branch: refs/heads/users/boomanaiden154/main.webassembly-port-webassemblynullifydebugvaluelistspass
Home: https://github.com/llvm/llvm-project
Commit: 3a6048dbea15390c20e4ea063ffed2c2610fcaaf
https://github.com/llvm/llvm-project/commit/3a6048dbea15390c20e4ea063ffed2c2610fcaaf
Author: Tony Guillot <tony.guillot at protonmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/test/CodeGen/ARM/elf-preemption.ll
M llvm/test/CodeGen/ARM/weak-hidden-pic.ll
Log Message:
-----------
Revert "[ARM] Use .reloc for weak symbols in PIC mode instead of GOT indirection" (#208968)
There is a few breakages between `clang-armv8-quick` failing the
`Interpreter/execute-weak.cpp` test and bots failing linking
`libclang_rt.atomic.so`.
Reverts llvm/llvm-project#208372
Commit: e9e21f520ccd8f4c292686dfdeb04eae080110e3
https://github.com/llvm/llvm-project/commit/e9e21f520ccd8f4c292686dfdeb04eae080110e3
Author: Adam Scott <adamscott200322 at gmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/avx512-calling-conv.ll
M llvm/test/CodeGen/X86/avx512-ext.ll
M llvm/test/CodeGen/X86/avx512-insert-extract.ll
M llvm/test/CodeGen/X86/avx512-load-store.ll
M llvm/test/CodeGen/X86/avx512-mask-op.ll
M llvm/test/CodeGen/X86/avx512-masked_memop-16-8.ll
M llvm/test/CodeGen/X86/avx512fp16-mov.ll
M llvm/test/CodeGen/X86/build-vector-128.ll
M llvm/test/CodeGen/X86/build-vector-256.ll
M llvm/test/CodeGen/X86/build-vector-512.ll
R llvm/test/CodeGen/X86/buildvec-strided-loads.ll
M llvm/test/CodeGen/X86/masked_gather_scatter_widen.ll
M llvm/test/CodeGen/X86/vector-compress.ll
Log Message:
-----------
Revert [X86] EltsFromConsecutiveLoads - handle trunc(wideload()) patterns (#199371) (#208960)
Reverts llvm/llvm-project#199371.
The strided path emits wide loads without checking that the widened
range is dereferenceable. The last wide load reads up to (stride -
element) bytes past the last element and faults when the data ends at a
page boundary. Flagged by @nikic in
https://github.com/llvm/llvm-project/pull/199371#issuecomment-4947406318.
Reproducer on current main **MADE WITH CLAUDE OPUS**
strided.ll, 8 x i16 at a 4 byte stride, the source only touches bytes
[0, 30):
```llvm
define void @strided8i16(ptr %p, ptr %out) {
%g0 = getelementptr inbounds i8, ptr %p, i64 0
%g1 = getelementptr inbounds i8, ptr %p, i64 4
%g2 = getelementptr inbounds i8, ptr %p, i64 8
%g3 = getelementptr inbounds i8, ptr %p, i64 12
%g4 = getelementptr inbounds i8, ptr %p, i64 16
%g5 = getelementptr inbounds i8, ptr %p, i64 20
%g6 = getelementptr inbounds i8, ptr %p, i64 24
%g7 = getelementptr inbounds i8, ptr %p, i64 28
%v0 = load i16, ptr %g0, align 1
%v1 = load i16, ptr %g1, align 1
%v2 = load i16, ptr %g2, align 1
%v3 = load i16, ptr %g3, align 1
%v4 = load i16, ptr %g4, align 1
%v5 = load i16, ptr %g5, align 1
%v6 = load i16, ptr %g6, align 1
%v7 = load i16, ptr %g7, align 1
%r0 = insertelement <8 x i16> undef, i16 %v0, i32 0
%r1 = insertelement <8 x i16> %r0, i16 %v1, i32 1
%r2 = insertelement <8 x i16> %r1, i16 %v2, i32 2
%r3 = insertelement <8 x i16> %r2, i16 %v3, i32 3
%r4 = insertelement <8 x i16> %r3, i16 %v4, i32 4
%r5 = insertelement <8 x i16> %r4, i16 %v5, i32 5
%r6 = insertelement <8 x i16> %r5, i16 %v6, i32 6
%r7 = insertelement <8 x i16> %r6, i16 %v7, i32 7
store <8 x i16> %r7, ptr %out, align 1
ret void
}
```
driver.c, puts the 30 data bytes flush against a PROT_NONE page:
```c
#include <sys/mman.h>
#include <unistd.h>
#include <string.h>
#include <stdint.h>
#include <stdio.h>
void strided8i16(void *p, void *out);
int main(void) {
long pg = sysconf(_SC_PAGESIZE);
char *m = mmap(0, 2*pg, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0);
mprotect(m + pg, pg, PROT_NONE); /* unmapped guard page right after */
memset(m, 0x11, pg);
char *p = m + pg - 30; /* data [0,30) ends exactly at page end */
uint16_t out[8];
strided8i16(p, out); /* source touches only bytes [0,30) */
printf(" returned OK, out[0]=%u\n", out[0]);
return 0;
}
```
```
$ llc -mtriple=x86_64-unknown-linux-gnu -mattr=+avx2 -filetype=obj strided.ll -o strided.o
$ cc driver.c strided.o -o repro
$ ./repro; echo "exit: $?"
Segmentation fault (core dumped)
exit: 139
$ llc -mtriple=x86_64-unknown-linux-gnu -mattr=+sse2 -filetype=obj strided.ll -o strided_sse2.o
$ cc driver.c strided_sse2.o -o repro_sse2
$ ./repro_sse2; echo "exit: $?"
returned OK, out[0]=4369
exit: 0
```
With +avx2 the fold fires and emits a 32 byte `vmovdqu (%rdi), %ymm0`
over the 30 byte footprint. With plain sse2 the buildvector stays scalar
and only the accessed bytes are read.
Commit: 9dffcd2752af16a09eeb4131f90a1a0fe2b76a1f
https://github.com/llvm/llvm-project/commit/9dffcd2752af16a09eeb4131f90a1a0fe2b76a1f
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2026-07-11 (Sat, 11 Jul 2026)
Changed paths:
M lld/ELF/Writer.cpp
M lld/test/ELF/aarch64-reloc-pauth.s
Log Message:
-----------
[PAC][lld] Properly handle `.relr.auth.dyn` -> `.rela.dyn` movement (#195649)
Address the following issues reported in #171475:
1. Proper adjustment of `__rela_iplt_end` address if a move from
`.relr.auth.dyn` to `.rela.dyn` took place
2. Set `__rela_iplt_start` properly if prior to such movement from
`.relr.auth.dyn`, the `.rela.dyn` was empty
3. Allocate enough space for both RELA* and AARCH64_AUTH_RELR* tags in
the `.dynamic` section in case we end up with both `.relr.auth.dyn` and
`.rela.dyn`. If one of the sections becomes empty - just pad the
`.dynamic` section with null tags in the end.
Resolves #171475
---------
Co-authored-by: Jessica Clarke <jrtc27 at jrtc27.com>
Commit: 77929619bc93b86e99f6ae6a9b10ef85a27c4c18
https://github.com/llvm/llvm-project/commit/77929619bc93b86e99f6ae6a9b10ef85a27c4c18
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/EvalEmitter.h
M clang/utils/TableGen/ClangOpcodesEmitter.cpp
Log Message:
-----------
[clang][bytecode] Remove EvalEmitter::OpPC (#208988)
We pass this when evaluting opcodes in EvalEmitter, but we never set it
to anything, so the underlying pointer is always null and we later and
up using the source location of the expression we're evaluating.
This seems to only cause problems when Statement expressions are
involved so far.
Commit: 02a38835c2f0cea609290ead1280d1102042081f
https://github.com/llvm/llvm-project/commit/02a38835c2f0cea609290ead1280d1102042081f
Author: amosher-nvidia <amosher at nvidia.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M lld/ELF/LinkerScript.cpp
A lld/test/ELF/linkerscript/tbss-addr-expr.s
Log Message:
-----------
[lld][ELF] Allow explicit address expressions on .tbss output sections (#196447)
D107208 allows consecutive SHF_TLS SHT_NOBITS (.tbss) output sections by
making
each .tbss start at the end address of the previous one
(state->tbssAddr). This
happens unconditionally, so an explicit output section address
(`.tbss ADDR : { ... }`) is silently ignored, unlike GNU ld.
Apply the tbssAddr fallback only when the section has no address
expression.
Some embedded/RTOS applications link the kernel and several mutually
isolated
tasks into a single ELF and require every section, .tbss included, to
sit at a
specific address matching the memory map. Placing a task's .tbss in its
own
protected region is a security boundary: one task must not be able to
modify
another's TLS. Previously lld placed .tbss adjacent to .text in RX
memory
instead of where the linker script directed it, in RW memory.
Commit: 359b99c85332edc17ab5cdbcfb7d272d24509f60
https://github.com/llvm/llvm-project/commit/359b99c85332edc17ab5cdbcfb7d272d24509f60
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/InstructionsState-is-invalid-0.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/commute.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/div-like-mixed-with-undefs.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/externally-used-copyables.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/extract-subvector-long-input.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/extractelements-to-shuffle.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/fma-conversion-multi-use-guard.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/fma-reduce-regression.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/fmulladd.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/gather-buildvector-with-minbitwidth-user.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/gather-cost.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/gather-reduce.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr2.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/landing_pad.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/loadi8.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/long-non-power-of-2.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/matmul.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/memory-runtime-checks.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/non-inst-abs-sub-copyable-value.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/non-power-of-2-with-adjusted-gathers.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/phi-node-bitwidt-op-not.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/recalc-copyable-node.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/reduce-fadd.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/reorder-fmuladd-crash.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/reused-scalar-repeated-in-node.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/scalarization-overhead.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/shuffle-vectors-mask-size.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/slp-extval-struct-operand-no-scalar-reuse.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/slp-fma-loss.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/spillcost-loop-backedge.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/spillcost-noreturn-block.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-loads.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/transpose-with-constants.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/trunc-insertion.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/tsc-s116.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/tsc-s352.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/unique_values.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/uselistorder.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vec3-calls.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vec3-reorder-reshuffle.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vectorizable-selects-uniform-cmps.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/inst-count-heuristic.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/notriviallyvectorizableintrinsicoperands.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/packed-math.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f16.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/basic-strided-loads.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/buildvector-all-external-scalars.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/fmuladd_width_prop.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/gather-insert-point-restore.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/gather-node-with-no-users.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/loads-ordering.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/mixed-extracts-types.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/non-commutative-second-arg-only-copyable.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/partial-vec-invalid-cost.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reductions.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/remark-zext-incoming-for-neg-icmp.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/remarks-insert-into-small-vector.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reordered-buildvector-scalars.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reordered-interleaved-loads.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/revec-strided-load.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reversed-strided-node-with-external-ptr.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/rotated-strided-loads.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/runtime-strided-stores.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/scatter-vectorize-reversed.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/select-profitability.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/shuffled-gather-casted.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/smax-reduction-unsigned-missing-sign.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/smin-reduction-unsigned-missing-sign.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/smin-signed-zextended.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/split-vectorize-parent-for-copyables.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-indices.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-use-ptr.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/strided-unsupported-type.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/trunc-bv-multi-uses.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/unsigned-icmp-signed-op.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/unsigned-node-trunc-with-signed-users.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/cmp-ptr-minmax.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/ext-alt-node-must-ext.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/ext-not-resized-op-resized.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-root-trunc.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-trunc.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/non-power-2-subvector-extract.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/pr34619.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/reductions-fadd.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/reductions-fmin-fmax.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/reductions-fmul.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/reuse-non-power-of-2-reorder.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/vec-elt-insertion.ll
M llvm/test/Transforms/SLPVectorizer/WebAssembly/or-reduction-zero-test.ll
M llvm/test/Transforms/SLPVectorizer/WebAssembly/simd-splat-shuffle-cost.ll
M llvm/test/Transforms/SLPVectorizer/X86/PR35628_1.ll
M llvm/test/Transforms/SLPVectorizer/X86/PR35628_2.ll
M llvm/test/Transforms/SLPVectorizer/X86/PR35777.ll
M llvm/test/Transforms/SLPVectorizer/X86/PR39774.ll
M llvm/test/Transforms/SLPVectorizer/X86/PR40310.ll
M llvm/test/Transforms/SLPVectorizer/X86/add-sub-nsw-intmin.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-cmp-swapped-pred.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-opcode-strict-bitwidth-than-main.ll
M llvm/test/Transforms/SLPVectorizer/X86/ashr-main-opcode-copyables.ll
M llvm/test/Transforms/SLPVectorizer/X86/bad-reduction.ll
M llvm/test/Transforms/SLPVectorizer/X86/barriercall.ll
M llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle.ll
M llvm/test/Transforms/SLPVectorizer/X86/broadcast-load-cost.ll
M llvm/test/Transforms/SLPVectorizer/X86/broadcast.ll
M llvm/test/Transforms/SLPVectorizer/X86/broadcast_long.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-reused-with-bv-subvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-same-lane-insert.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-schedule-for-subvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-shuffle-with-root.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-shuffle.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-store-chains.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-with-reuses.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvectors-parent-phi-nodes.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvectors-with-same-parents.ll
M llvm/test/Transforms/SLPVectorizer/X86/bv-root-part-of-graph.ll
M llvm/test/Transforms/SLPVectorizer/X86/bv-shuffle-mask.ll
M llvm/test/Transforms/SLPVectorizer/X86/c-ray.ll
M llvm/test/Transforms/SLPVectorizer/X86/call.ll
M llvm/test/Transforms/SLPVectorizer/X86/cast-operand-extracted.ll
M llvm/test/Transforms/SLPVectorizer/X86/cmp-after-intrinsic-call-minbitwidth.ll
M llvm/test/Transforms/SLPVectorizer/X86/cmp-as-alternate-ops.ll
M llvm/test/Transforms/SLPVectorizer/X86/cmp_sel.ll
M llvm/test/Transforms/SLPVectorizer/X86/commutable-member-in-non-commutable-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/commutable-node-with-non-sched-parent.ll
M llvm/test/Transforms/SLPVectorizer/X86/commutative-copyable-external-phi-use.ll
M llvm/test/Transforms/SLPVectorizer/X86/commutativity.ll
M llvm/test/Transforms/SLPVectorizer/X86/compare-node-with-reuses.ll
M llvm/test/Transforms/SLPVectorizer/X86/compare-reduce.ll
M llvm/test/Transforms/SLPVectorizer/X86/complex-fma-combine.ll
M llvm/test/Transforms/SLPVectorizer/X86/control-dependence.ll
M llvm/test/Transforms/SLPVectorizer/X86/conversion-fp16.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable-child-node-used-outside.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable-non-inst-in-stores.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable-operand-non-scheduled-parent-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable-operands-reordering.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable-phi-scheduled-non-copyable.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable-phi-used-non-copyable.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable-reduced-erased.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable-used-outside-with-immediate-op.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable-with-non-scheduled-parent-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable-with-used-outside-bb.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable_reorder.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyables-with-parent-scalars-in-phis.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_bullet.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_clear_undefs.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_cmpop.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_dequeue.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_mandeltext.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_scheduling-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_scheduling.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_sim4b1.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_vectorizeTree.ll
M llvm/test/Transforms/SLPVectorizer/X86/cse.ll
M llvm/test/Transforms/SLPVectorizer/X86/debug-counter.ll
M llvm/test/Transforms/SLPVectorizer/X86/debug-info-salvage.ll
M llvm/test/Transforms/SLPVectorizer/X86/delayed-gather-emission.ll
M llvm/test/Transforms/SLPVectorizer/X86/deleted-inst-reduction-attempt.ll
M llvm/test/Transforms/SLPVectorizer/X86/deleted-instructions-clear.ll
M llvm/test/Transforms/SLPVectorizer/X86/deleted-node-with-copyable-operands.ll
M llvm/test/Transforms/SLPVectorizer/X86/diamond.ll
M llvm/test/Transforms/SLPVectorizer/X86/diamond_broadcast_extra_shuffle.ll
M llvm/test/Transforms/SLPVectorizer/X86/div-possibly-extended-with-poisons.ll
M llvm/test/Transforms/SLPVectorizer/X86/dot-product.ll
M llvm/test/Transforms/SLPVectorizer/X86/entries-different-vf.ll
M llvm/test/Transforms/SLPVectorizer/X86/entries-shuffled-diff-sizes.ll
M llvm/test/Transforms/SLPVectorizer/X86/entry-no-bundle-but-extra-use-on-vec.ll
M llvm/test/Transforms/SLPVectorizer/X86/expanded-binop-doesnotneedschedule-user.ll
M llvm/test/Transforms/SLPVectorizer/X86/expanded-operand-already-scheduled.ll
M llvm/test/Transforms/SLPVectorizer/X86/expected-prof-consecutive-access.ll
M llvm/test/Transforms/SLPVectorizer/X86/ext-used-scalar-different-bitwidth.ll
M llvm/test/Transforms/SLPVectorizer/X86/external-bin-op-user.ll
M llvm/test/Transforms/SLPVectorizer/X86/external-reduced-value-vectorized.ll
M llvm/test/Transforms/SLPVectorizer/X86/external_user.ll
M llvm/test/Transforms/SLPVectorizer/X86/extract-scalar-from-undef.ll
M llvm/test/Transforms/SLPVectorizer/X86/extract-subvector-long-input.ll
M llvm/test/Transforms/SLPVectorizer/X86/extract-used-in-many-nodes.ll
M llvm/test/Transforms/SLPVectorizer/X86/extract_in_tree_user.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractcost.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractelement-multi-register-use.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractelement-multiple-uses.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractelement-single-use-many-nodes.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractelement.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractelements-subnodes-same-index.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractelements-with-undef-vector.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractelemets-extended-by-poison.ll
M llvm/test/Transforms/SLPVectorizer/X86/extracts-non-extendable.ll
M llvm/test/Transforms/SLPVectorizer/X86/fabs-cost-softfp.ll
M llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
M llvm/test/Transforms/SLPVectorizer/X86/full-match-with-poison-scalar.ll
M llvm/test/Transforms/SLPVectorizer/X86/full-matched-bv-with-subvectors.ll
M llvm/test/Transforms/SLPVectorizer/X86/full-non-schedulable-overlap.ll
M llvm/test/Transforms/SLPVectorizer/X86/gather-move-out-of-loop.ll
M llvm/test/Transforms/SLPVectorizer/X86/gather-node-same-as-vect-but-order.ll
M llvm/test/Transforms/SLPVectorizer/X86/gather-with-cmp-user.ll
M llvm/test/Transforms/SLPVectorizer/X86/gathered-delayed-nodes-with-reused-user.ll
M llvm/test/Transforms/SLPVectorizer/X86/gathered-loads-non-full-reg.ll
M llvm/test/Transforms/SLPVectorizer/X86/gathered-node-with-in-order-parent.ll
M llvm/test/Transforms/SLPVectorizer/X86/hoist.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
M llvm/test/Transforms/SLPVectorizer/X86/icmp-altopcode-after-reordering.ll
M llvm/test/Transforms/SLPVectorizer/X86/identity-match-splat-less-defined.ll
M llvm/test/Transforms/SLPVectorizer/X86/in-tree-user.ll
M llvm/test/Transforms/SLPVectorizer/X86/insert-after-bundle.ll
M llvm/test/Transforms/SLPVectorizer/X86/insert-subvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/insertelement-with-copyable-args.ll
M llvm/test/Transforms/SLPVectorizer/X86/insertvalue.ll
M llvm/test/Transforms/SLPVectorizer/X86/inst_size_bug.ll
M llvm/test/Transforms/SLPVectorizer/X86/inversed-icmp-to-gather.ll
M llvm/test/Transforms/SLPVectorizer/X86/landing-pad-for-split-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/landing_pad.ll
M llvm/test/Transforms/SLPVectorizer/X86/load-merge-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/load-merge.ll
M llvm/test/Transforms/SLPVectorizer/X86/lookahead.ll
M llvm/test/Transforms/SLPVectorizer/X86/loopinvariant.ll
M llvm/test/Transforms/SLPVectorizer/X86/malformed_phis.ll
M llvm/test/Transforms/SLPVectorizer/X86/many-uses-parent-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/matched-bv-schedulable.ll
M llvm/test/Transforms/SLPVectorizer/X86/matched-gather-part-of-combined.ll
M llvm/test/Transforms/SLPVectorizer/X86/matched-nodes-updated.ll
M llvm/test/Transforms/SLPVectorizer/X86/matched-shuffled-entries.ll
M llvm/test/Transforms/SLPVectorizer/X86/matching-gather-nodes-phi-users.ll
M llvm/test/Transforms/SLPVectorizer/X86/matching-insert-point-for-nodes.ll
M llvm/test/Transforms/SLPVectorizer/X86/memory-runtime-checks.ll
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-cast.ll
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-drop-wrapping-flags.ll
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-icmp-to-trunc.ll
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-transformed-operand.ll
M llvm/test/Transforms/SLPVectorizer/X86/minbw-bitcast-to-fp.ll
M llvm/test/Transforms/SLPVectorizer/X86/minimum-sizes.ll
M llvm/test/Transforms/SLPVectorizer/X86/mul-shl-nsw-intmin.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-extracts-bv-combined.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-node-for-copyable-parent.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-node-reuse-in-bv.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-node-user-with-copyable-ops.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-nodes-to-shuffle.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-parent-instr-copyable-regular.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-use-bitcasted-reduction.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi_user.ll
M llvm/test/Transforms/SLPVectorizer/X86/no_alternate_divrem.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-commutative-op-in-commutative-inst.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-power-2-num-elems-reused.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-bswap.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-order-detection.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-reduced-select-of-bits.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-before-main.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-instructions-become-schedulable.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-parent-multi-copyables.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-split-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-user-different-bb.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-scheduled-inst-extern-use.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-scheduled-inst-reused-as-last-inst.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-vectorizable-inst-operand.ll
M llvm/test/Transforms/SLPVectorizer/X86/odd_store.ll
M llvm/test/Transforms/SLPVectorizer/X86/opaque-ptr.ll
M llvm/test/Transforms/SLPVectorizer/X86/operand-reorder-with-copyables.ll
M llvm/test/Transforms/SLPVectorizer/X86/operandorder.ll
M llvm/test/Transforms/SLPVectorizer/X86/ordered-reduction-root-deleted.ll
M llvm/test/Transforms/SLPVectorizer/X86/ordered-reductions.ll
M llvm/test/Transforms/SLPVectorizer/X86/ordering-bug.ll
M llvm/test/Transforms/SLPVectorizer/X86/original-inst-scheduled-after-copyable.ll
M llvm/test/Transforms/SLPVectorizer/X86/parent-node-schedulable-with-multi-copyables.ll
M llvm/test/Transforms/SLPVectorizer/X86/parent-node-split-non-schedulable.ll
M llvm/test/Transforms/SLPVectorizer/X86/parent-phi-node-reordered.ll
M llvm/test/Transforms/SLPVectorizer/X86/phi-node-bitwidt-op-not.ll
M llvm/test/Transforms/SLPVectorizer/X86/phi-node-with-cycle.ll
M llvm/test/Transforms/SLPVectorizer/X86/phi.ll
M llvm/test/Transforms/SLPVectorizer/X86/phi3.ll
M llvm/test/Transforms/SLPVectorizer/X86/phi_landingpad.ll
M llvm/test/Transforms/SLPVectorizer/X86/phi_overalignedtype.ll
M llvm/test/Transforms/SLPVectorizer/X86/phis-different-order.ll
M llvm/test/Transforms/SLPVectorizer/X86/poor-throughput-seeds.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr27163.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr35497.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr40522.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr42022-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr42022.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr44067-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr44067.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr46983.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr47629.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr47642.ll
M llvm/test/Transforms/SLPVectorizer/X86/propagate-mmra.ll
M llvm/test/Transforms/SLPVectorizer/X86/recalc-copyable-operand-deps-non-scheduled-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/recalc-copyable-operand-deps-shared-inst.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-bswap-with-larger-reduced-type.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-val-extracted-and-externally-used.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-value-replace-extractelement-cost.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-value-replace-extractelement.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-value-stored.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-across-different-bb.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-bool-logic-op-inside.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-copyable-reused-scalars.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-same-vals.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-shl1-add-merge.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-with-removed-extracts.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction2.ll
M llvm/test/Transforms/SLPVectorizer/X86/redux-feed-buildvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/remark-partial-loads-vectorize.ll
M llvm/test/Transforms/SLPVectorizer/X86/remark_gather-load-redux-cost.ll
M llvm/test/Transforms/SLPVectorizer/X86/remark_not_all_parts.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder-possible-strided-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder-reused-subvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder_diamond_match.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder_phi.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder_with_external_users.ll
M llvm/test/Transforms/SLPVectorizer/X86/replaced-external-in-reduction.ll
M llvm/test/Transforms/SLPVectorizer/X86/resched.ll
M llvm/test/Transforms/SLPVectorizer/X86/reschedule-only-scheduled.ll
M llvm/test/Transforms/SLPVectorizer/X86/resized-bv-values-non-power-of2-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/reused-extract-scalar-lanes.ll
M llvm/test/Transforms/SLPVectorizer/X86/reused-extracts.ll
M llvm/test/Transforms/SLPVectorizer/X86/reused-last-instruction-in-split-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/reused-mask-with-poison-index.ll
M llvm/test/Transforms/SLPVectorizer/X86/reused-reductions-with-minbitwidth.ll
M llvm/test/Transforms/SLPVectorizer/X86/reused-scalars-in-buildvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/reused-undefs.ll
M llvm/test/Transforms/SLPVectorizer/X86/revec-fma-vectorize.ll
M llvm/test/Transforms/SLPVectorizer/X86/revec-non-power-2-to-power-2-large-vect.ll
M llvm/test/Transforms/SLPVectorizer/X86/revec-reduced-value-replace-extractelement.ll
M llvm/test/Transforms/SLPVectorizer/X86/revec-scalar-insertelement.ll
M llvm/test/Transforms/SLPVectorizer/X86/same-last-instruction-different-parents.ll
M llvm/test/Transforms/SLPVectorizer/X86/same-operands-but-copyable.ll
M llvm/test/Transforms/SLPVectorizer/X86/same-values-sub-node-with-poisons.ll
M llvm/test/Transforms/SLPVectorizer/X86/saxpy.ll
M llvm/test/Transforms/SLPVectorizer/X86/scatter-vectorize-reorder-non-empty.ll
M llvm/test/Transforms/SLPVectorizer/X86/scatter-vectorize-reorder.ll
M llvm/test/Transforms/SLPVectorizer/X86/schedule_budget.ll
M llvm/test/Transforms/SLPVectorizer/X86/select-copyable-cmp-poison.ll
M llvm/test/Transforms/SLPVectorizer/X86/select-logical-or-and-i1-vector.ll
M llvm/test/Transforms/SLPVectorizer/X86/select-reduction-op.ll
M llvm/test/Transforms/SLPVectorizer/X86/shl-compatible-with-add.ll
M llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation.ll
M llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation5.ll
M llvm/test/Transforms/SLPVectorizer/X86/shuffle-mask-emission.ll
M llvm/test/Transforms/SLPVectorizer/X86/sibling-loops-mismatched-tripcount.ll
M llvm/test/Transforms/SLPVectorizer/X86/simplebb.ll
M llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/sitofp-minbitwidth-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
M llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll
M llvm/test/Transforms/SLPVectorizer/X86/slp-throttle.ll
M llvm/test/Transforms/SLPVectorizer/X86/small-graph-diff-block-instructions.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-load8_2_unord_geps.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-node-full-match.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-node-last-inst-vectorized.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-node-no-reorder-copy.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-node-num-operands.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-node-parent-operands-in-spill.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-node-reduce-root.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-node-reorder-node-with-ops.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-node-reused-in-later-vector.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-node-throttled.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-vector-operand-with-reuses.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-vectorize-gathered-def-after-use.ll
M llvm/test/Transforms/SLPVectorizer/X86/stacksave-dependence.ll
M llvm/test/Transforms/SLPVectorizer/X86/store-load-forward-conflict.ll
M llvm/test/Transforms/SLPVectorizer/X86/stores_vectorize.ll
M llvm/test/Transforms/SLPVectorizer/X86/struct-return-extract-dominance.ll
M llvm/test/Transforms/SLPVectorizer/X86/struct-return-ordering-stress.ll
M llvm/test/Transforms/SLPVectorizer/X86/subvector-minbitwidth-unsigned-value.ll
M llvm/test/Transforms/SLPVectorizer/X86/supernode.ll
M llvm/test/Transforms/SLPVectorizer/X86/tiny-tree.ll
M llvm/test/Transforms/SLPVectorizer/X86/trunc-store-value-ty-not-power-of-2.ll
M llvm/test/Transforms/SLPVectorizer/X86/trunced-buildvector-scalar-extended.ll
M llvm/test/Transforms/SLPVectorizer/X86/uitofp-with-signed-value-bitwidth.ll
M llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll
M llvm/test/Transforms/SLPVectorizer/X86/user-node-with-same-last-instr.ll
M llvm/test/Transforms/SLPVectorizer/X86/user-with-multi-copyable-ops.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec3-calls.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec3-gather-some-loads.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec3-reorder-reshuffle.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias_external_insert_shuffled.ll
M llvm/test/Transforms/SLPVectorizer/X86/vect-gather-same-nodes.ll
M llvm/test/Transforms/SLPVectorizer/X86/vectorize-pair-path.ll
M llvm/test/Transforms/SLPVectorizer/X86/vectorize-widest-phis.ll
M llvm/test/Transforms/SLPVectorizer/X86/whole-registers-compare.ll
M llvm/test/Transforms/SLPVectorizer/X86/xor-combined-opcode.ll
M llvm/test/Transforms/SLPVectorizer/X86/xor-with-zero-and-incompat.ll
M llvm/test/Transforms/SLPVectorizer/abs-overflow-incorrect-minbws.ll
M llvm/test/Transforms/SLPVectorizer/alt-cmp-vectorize.ll
M llvm/test/Transforms/SLPVectorizer/alternate-cmp-swapped-pred-parent.ll
M llvm/test/Transforms/SLPVectorizer/alternate-non-profitable.ll
M llvm/test/Transforms/SLPVectorizer/bool-logical-op-reduction-with-poison.ll
M llvm/test/Transforms/SLPVectorizer/buildvector-nodes-dependency.ll
M llvm/test/Transforms/SLPVectorizer/call-arg-reduced-by-minbitwidth.ll
M llvm/test/Transforms/SLPVectorizer/consecutive-access.ll
M llvm/test/Transforms/SLPVectorizer/crash_exceed_scheduling.ll
M llvm/test/Transforms/SLPVectorizer/crash_extractelement_poison.ll
M llvm/test/Transforms/SLPVectorizer/diamond_broadcast.ll
M llvm/test/Transforms/SLPVectorizer/ext-after-phi-node.ll
M llvm/test/Transforms/SLPVectorizer/ext-int-reduced-not-operand.ll
M llvm/test/Transforms/SLPVectorizer/extended-vectorized-gathered-inst.ll
M llvm/test/Transforms/SLPVectorizer/external-user-instruction-minbitwidth.ll
M llvm/test/Transforms/SLPVectorizer/extract-many-users-buildvector.ll
M llvm/test/Transforms/SLPVectorizer/extractelement-insertpoint.ll
M llvm/test/Transforms/SLPVectorizer/extracts-with-undefs.ll
M llvm/test/Transforms/SLPVectorizer/freeze-signedness-missed.ll
M llvm/test/Transforms/SLPVectorizer/gather_extract_from_vectorbuild.ll
M llvm/test/Transforms/SLPVectorizer/gathered-consecutive-loads-different-types.ll
M llvm/test/Transforms/SLPVectorizer/insert-element-build-vector-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/insert-element-build-vector.ll
M llvm/test/Transforms/SLPVectorizer/insert-shuffle.ll
M llvm/test/Transforms/SLPVectorizer/insertelement-across-zero.ll
M llvm/test/Transforms/SLPVectorizer/insertelement-postpone.ll
M llvm/test/Transforms/SLPVectorizer/insertelement-uses-vectorized-index.ll
M llvm/test/Transforms/SLPVectorizer/int-bitcast-minbitwidth.ll
M llvm/test/Transforms/SLPVectorizer/jumbled_store_crash.ll
M llvm/test/Transforms/SLPVectorizer/last-buildvector-node.ll
M llvm/test/Transforms/SLPVectorizer/materialize-vector-of-consts.ll
M llvm/test/Transforms/SLPVectorizer/minbitwidth-multiuse-with-insertelement.ll
M llvm/test/Transforms/SLPVectorizer/minbitwidth-user-not-min.ll
M llvm/test/Transforms/SLPVectorizer/multi-node-vectorized-insts.ll
M llvm/test/Transforms/SLPVectorizer/multi-uses-with-deps-in-first.ll
M llvm/test/Transforms/SLPVectorizer/operand-is-reduced-val.ll
M llvm/test/Transforms/SLPVectorizer/partial-register-extract.ll
M llvm/test/Transforms/SLPVectorizer/phi-undef-input.ll
M llvm/test/Transforms/SLPVectorizer/postponed_gathers.ll
M llvm/test/Transforms/SLPVectorizer/reduced-gathered-vectorized.ll
M llvm/test/Transforms/SLPVectorizer/reorder-clustered-node.ll
M llvm/test/Transforms/SLPVectorizer/reordered-top-scalars.ll
M llvm/test/Transforms/SLPVectorizer/reordering-single-phi.ll
M llvm/test/Transforms/SLPVectorizer/reschedule.ll
M llvm/test/Transforms/SLPVectorizer/resized-alt-shuffle-after-minbw.ll
M llvm/test/Transforms/SLPVectorizer/return.ll
M llvm/test/Transforms/SLPVectorizer/reudction-or-non-poisoned.ll
M llvm/test/Transforms/SLPVectorizer/reused-buildvector-matching-vectorized-node.ll
M llvm/test/Transforms/SLPVectorizer/revec.ll
M llvm/test/Transforms/SLPVectorizer/root-trunc-extract-reuse.ll
M llvm/test/Transforms/SLPVectorizer/same-scalar-in-same-phi-extract.ll
M llvm/test/Transforms/SLPVectorizer/semanticly-same.ll
M llvm/test/Transforms/SLPVectorizer/shrink_after_reorder2.ll
M llvm/test/Transforms/SLPVectorizer/shuffle-multivector.ll
M llvm/test/Transforms/SLPVectorizer/shufflebuilder-bug.ll
M llvm/test/Transforms/SLPVectorizer/slp-deleted-inst.ll
M llvm/test/Transforms/SLPVectorizer/slp-max-phi-size.ll
M llvm/test/Transforms/SLPVectorizer/splat-buildvector.ll
M llvm/test/Transforms/SLPVectorizer/stores-non-ordered.ll
M llvm/test/Transforms/SLPVectorizer/unknown-entries.ll
M llvm/test/Transforms/SLPVectorizer/vectorize-reorder-alt-shuffle.ll
M llvm/test/Transforms/SLPVectorizer/zext-incoming-for-neg-icmp.ll
Log Message:
-----------
[SLP] Use constant 64-bit indices for Extract/InsertElement (#208957)
The canonical form preferred by instCombine is to use 64-bit values for
constant index in ExtractElement and InsertElement.
Commit: 76f0d4693463ec2c09b4e14eca8f96020bb710e6
https://github.com/llvm/llvm-project/commit/76f0d4693463ec2c09b4e14eca8f96020bb710e6
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M lld/test/ELF/aarch64-reloc-pauth.s
M lld/test/ELF/pack-dyn-relocs-relr-loop.s
Log Message:
-----------
[ELF,test] Improve .relr.auth.dyn -> .rela.dyn movement coverage (#208991)
Test two behaviors of #195649 that were unasserted:
- .dynamic shrinks when all .relr.auth.dyn entries are moved to a
non-empty .rela.dyn. Check the section header size: readelf -d stops
at the first DT_NULL and cannot show stale padding. This subsumes
empty-relr.s (a size-neutral tag swap, which passed even without the
fix), so remove it.
- An empty .rela.dyn is removed when .relr.auth.dyn is unused. Assert
this in pack-dyn-relocs-relr-loop.s.
Commit: 7215a1a19c13c79e66a9e8661aa7798cb3261b94
https://github.com/llvm/llvm-project/commit/7215a1a19c13c79e66a9e8661aa7798cb3261b94
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/fence-noalias-metadata.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-vectors-complex.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/missing-alignment.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/opaque_ptr.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/pointer-elements.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/unaligned-buffer.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/vectorize-redund-loads.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/4x2xhalf.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/extend-chain.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill-cleanup.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill-invariant.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill-with-redundant-elements.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/load-store-256-bit.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/masked-store.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/propagate-invariance-metadata.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/vectorize_i8.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/correct-order.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/massive_indirection.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/opaque-ptr.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/or-disjoint-nested-add.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/or-disjoint-zext.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/scev-range-zext.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-nested-add-inseltpoison.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-nested-add.ll
M llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-redund-loads.ll
M llvm/test/Transforms/LoadStoreVectorizer/int_sideeffect.ll
Log Message:
-----------
[LoadStoreVectorizer] Use constant 64-bit indices for Extract/InsertElement (#208941)
The canonical form preferred by instCombine is to use 64-bit values for
constant index in ExtractElement and InsertElement.
Commit: 2aab89554cbf800bf50928fe7b1b3de2cbd41b26
https://github.com/llvm/llvm-project/commit/2aab89554cbf800bf50928fe7b1b3de2cbd41b26
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c
M clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
M clang/test/CodeGen/AArch64/neon-2velem.c
M clang/test/CodeGen/AArch64/neon-extract.c
M clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c
M clang/test/CodeGen/AArch64/neon-ldst-one.c
M clang/test/CodeGen/AArch64/neon-misc.c
M clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
M clang/test/CodeGen/AArch64/neon-vcmla.c
M clang/test/CodeGen/AArch64/neon/fused-multiply.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
M clang/test/CodeGen/AArch64/v8.5a-neon-frint3264-intrinsic.c
M clang/test/CodeGen/arm-neon-vst.c
M clang/test/CodeGen/arm64_vdupq_n_f64.c
M clang/test/CodeGen/arm_neon_intrinsics.c
M clang/test/CodeGen/cx-complex-range-real.c
M clang/test/CodeGen/cx-complex-range.c
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/test/DebugInfo/Generic/assignment-tracking/sroa/vec-2.ll
M llvm/test/Transforms/SROA/basictest.ll
M llvm/test/Transforms/SROA/prefer-integer-partition.ll
M llvm/test/Transforms/SROA/sroa-common-type-fail-promotion.ll
M llvm/test/Transforms/SROA/struct-to-vector-fp-store-only-tail.ll
M llvm/test/Transforms/SROA/vector-conversion.ll
M llvm/test/Transforms/SROA/vector-promotion-rmw-cannot-tree-merge.ll
M llvm/test/Transforms/SROA/vector-promotion.ll
Log Message:
-----------
[SROA] Use constant 64-bit indices for Extract/InsertElement (#208918)
The canonical form preferred by instCombine is to use 64-bit values for
constant index in ExtractElement and InsertElement.
Commit: e62c0cb076fbcb70752530571726944648a48829
https://github.com/llvm/llvm-project/commit/e62c0cb076fbcb70752530571726944648a48829
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/test/PCH/cxx20-template-args.cpp
Log Message:
-----------
[clang][bytecode] Fix comparing `TemplateParamObjectDecl`s (#208734)
1) When creating the global variables for them, always use the first
decl
2) When converting null pointers to `APValue`, don't cast the nullptr
base to `Expr` or `ValueDecl`. Use `LValueBase()` instead, so the
internal `PointerUnion` has an all-zeros value as `getOpaqueValue()`. If
we don't do this, we run into problems with merging of
`TemplateParamObjectDecls` because they don't compare equal via
`::Profile()`.
Commit: 25a5b7869cd13698f7556af6b4084cca835ae988
https://github.com/llvm/llvm-project/commit/25a5b7869cd13698f7556af6b4084cca835ae988
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/include/llvm/IR/PatternMatch.h
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Vectorize/LoopIdiomVectorize.cpp
Log Message:
-----------
[PatternMatch] Add capturing m_Phi matcher (NFC) (#208949)
Add a new capturing m_Phi matcher and use it in some patterns instead of
manually casting/checking if operand is a phi.
PR: https://github.com/llvm/llvm-project/pull/208949
Commit: af812fc18a8ab488bf8b70f9b8ae19bbdd1aea48
https://github.com/llvm/llvm-project/commit/af812fc18a8ab488bf8b70f9b8ae19bbdd1aea48
Author: 陈子昂 <2802328816 at qq.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M clang/lib/Headers/riscv_packed_simd.h
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/CodeGen/RISCV/rvp-widening-convert.ll
Log Message:
-----------
[Clang][RISCV][P-ext] Support packed widening convert intrinsics (#208394)
This patch implements all packed widening convert intrinsics using
general vector operations. Low widening conversions use
`__builtin_convertvector`, while high-half conversions use general
shuffles.
The generated code for high-half conversions is correct but not yet
optimal.
Commit: 4c7948d06c93e8d233cd4733fd4107f3b68bc7bc
https://github.com/llvm/llvm-project/commit/4c7948d06c93e8d233cd4733fd4107f3b68bc7bc
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
Revert "[VPlan] Re-use VPSlotTracker when printing recipes for costs (NFC)." (#209003)
Reverts llvm/llvm-project#203386.
This causes a large compile-time regression.
Commit: a34cb573eae65f48f0e51147289e042a86b55d16
https://github.com/llvm/llvm-project/commit/a34cb573eae65f48f0e51147289e042a86b55d16
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/CStringChecker.cpp
A clang/test/Analysis/string-search-modeling.c
Log Message:
-----------
[analyzer] Model strchr/strrchr/memchr/strstr/strpbrk/strchrnul (#207267)
CStringChecker did not model these buffer-search functions, so the
engine bound each call to a fresh conjured symbol unrelated to the source.
As a consequence, we could not track the origin of the returned pointer,
thus the fact that it shares provenance of the source pointer.
Fixes #203260
Assisted-by: Claude Opus 4.8
Commit: 97bceede1059b67d3491011f415856f32de21c9c
https://github.com/llvm/llvm-project/commit/97bceede1059b67d3491011f415856f32de21c9c
Author: Hongyu Chen <xxs_chy at outlook.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rvp-srl-bitcast-bv.ll
M llvm/test/CodeGen/RISCV/rvp-zip.ll
Log Message:
-----------
[RISCV][P-ext] Improve the codegen for unzip-like shuffle and buildvector (#208763)
This patch selects `pncvt*`/`unzip*` for unzip-like patterns.
On RV32, we select packed narrow shift for i8x4 and i16x2 BUILD_VECTOR
that are equivalent to deinterleave shuffle.
On RV64, we select packed unzip for i8x4 and i16x2 deinterleave shuffle.
Apart from the packed unzip intrinsics, this patch also adds support for
the codegen of two-source unzip.
Commit: a06b1c9f4bd49af7e2c68cacf5922136906bb335
https://github.com/llvm/llvm-project/commit/a06b1c9f4bd49af7e2c68cacf5922136906bb335
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt-c/Logging.h
M orc-rt/lib/executor/CMakeLists.txt
A orc-rt/lib/executor/Logging_printf.cpp
M orc-rt/test/CMakeLists.txt
M orc-rt/test/regression/lit.cfg.py
A orc-rt/test/regression/logging/lit.local.cfg
A orc-rt/test/regression/logging/printf-backend/bad-level.test
A orc-rt/test/regression/logging/printf-backend/debug-compiled-out.test
A orc-rt/test/regression/logging/printf-backend/debug-level.test
A orc-rt/test/regression/logging/printf-backend/format.test
A orc-rt/test/regression/logging/printf-backend/level-off.test
A orc-rt/test/regression/logging/printf-backend/lit.local.cfg
A orc-rt/test/regression/logging/printf-backend/output-redirect.test
A orc-rt/test/regression/logging/printf-backend/runtime-level.test
M orc-rt/test/tools/CMakeLists.txt
A orc-rt/test/tools/orc-rt-log-check.cpp
Log Message:
-----------
[orc-rt] Add printf logging backend (#209006)
Implement the printf backend, selected at configure-time with
ORC_RT_LOG_BACKEND=printf. Messages are written to stderr, or to the
file named by the ORC_RT_LOG_OUTPUT environment variable.
The ORC_RT_LOG environment variable sets the runtime level floor (error,
warning, info, debug, or off) -- only messages at or above it are shown.
When unset it defaults to warning, so warnings and errors are shown and
info and debug are opt-in. The runtime floor cannot go below the
compile-time ORC_RT_LOG_LEVEL floor (the lowest level built in).
Also add regression tests, driven by a new orc-rt-log-check tool that
reports the compiled-in backend and levels (which lit exposes as
features) and emits a message at each level.
Commit: 3187f2659848d0cfadc9caa601215afb8bd9b242
https://github.com/llvm/llvm-project/commit/3187f2659848d0cfadc9caa601215afb8bd9b242
Author: Zinovy Nis <zinovy.nis at gmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M clang-tools-extra/clang-tidy/modernize/UseStringViewCheck.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-string-view.cpp
Log Message:
-----------
[clang-tidy] Modernize-use-string-view: fix todo for ternary (#209008)
Add a support for any-depth ternary expressions
Commit: 3f2d8eb20a8d86d9aeea75a00e21a4ecff0a5234
https://github.com/llvm/llvm-project/commit/3f2d8eb20a8d86d9aeea75a00e21a4ecff0a5234
Author: Lukas <43409484+hertelukas at users.noreply.github.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
M llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
M llvm/lib/Transforms/Utils/FixIrreducible.cpp
M llvm/lib/Transforms/Utils/UnifyLoopExits.cpp
A llvm/test/Transforms/FixIrreducible/multiedge.ll
M llvm/test/Transforms/UnifyLoopExits/basic.ll
A llvm/test/Transforms/UnifyLoopExits/multiedge.ll
Log Message:
-----------
[FixIrreducible][UnifyLoopExits] Fix callbr multiedge splitting (#207598)
This fixes a bug where splitting `callbr` multiedges corrupts the
successor's PHI nodes.
Originally, the first split edge would replace all incoming edges from
the `callbr` block with the newly introduced target block by using
`replacePhiUsesWith`. Later edges would create new target blocks and
would try to update their edge's PHI as well, but would not find it,
leading to a corrupted PHI node.
To fix this, it is theoretically only necessary to ensure that exactly
one PHI argument is replaced per split edge. However, as all the PHI
nodes must have the same argument for every edge from one predecessor, a
single target block suffices, through which all traffic can be routed,
which will be especially useful for switches, where multiedges are
common.
[Trunk crashing](https://godbolt.org/z/4MM5eMrW5)
Found while working on PR #206567, cc @ro-i.
Commit: b82a9a57e72c29a5e8fc81109a62eb827fa5d8f0
https://github.com/llvm/llvm-project/commit/b82a9a57e72c29a5e8fc81109a62eb827fa5d8f0
Author: Gábor Horváth <xazax.hun at gmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/benchmarks/CMakeLists.txt
A llvm/benchmarks/ImmutableSetBuildBM.cpp
M llvm/include/llvm/ADT/ImmutableSet.h
Log Message:
-----------
[ADT] Fuse the two post-mutation tree walks in ImutAVLFactory (#208907)
Commit: f99f2a582e947af3f20580fa2674ca0c6bde1b2c
https://github.com/llvm/llvm-project/commit/f99f2a582e947af3f20580fa2674ca0c6bde1b2c
Author: Benedek Kaibas <82393336+benedekaibas at users.noreply.github.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt
A clang/lib/StaticAnalyzer/Checkers/LifetimeModeling.cpp
A clang/lib/StaticAnalyzer/Checkers/LifetimeModeling.h
M clang/lib/StaticAnalyzer/Checkers/UseAfterLifetimeEnd.cpp
M clang/test/Analysis/debug-lifetime-bound.cpp
M clang/test/Analysis/lifetime-bound.cpp
Log Message:
-----------
[analyzer] Implement LifetimeModeling checker and refactor UseAfterLifetimeEnd (#205951)
Commit: 7c2f4db828e5b9fd391c7f69bdd7dfe866b41bc0
https://github.com/llvm/llvm-project/commit/7c2f4db828e5b9fd391c7f69bdd7dfe866b41bc0
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M orc-rt/lib/executor/CMakeLists.txt
A orc-rt/lib/executor/Environment.cpp
A orc-rt/lib/executor/Environment.h
M orc-rt/lib/executor/Logging_printf.cpp
Log Message:
-----------
[orc-rt] Add internal secureGetenv utility and use it in the printf b… (#209014)
…ackend
orc_rt::secureGetenv is like getenv, but returns null when the process
is running with elevated privileges (e.g. a set-user-ID or set-group-ID
program), so that a variable in an attacker-controlled environment
cannot influence a privileged host. On libcs where privilege can't be
checked (anything other than glibc or the BSDs/macOS), it fails secure
and returns null, so those environment variables are ignored until a
branch for the platform is added.
Switch the printf logging backend to read ORC_RT_LOG and
ORC_RT_LOG_OUTPUT through secureGetenv, so a redirected log file or
level can't be forced via the environment in a privileged process.
Note that running the ORC runtime in a process with elevated privileges
is extremely risky (since the JIT'd code will typically inherit these
elevated privileges), and expected to be rare. Exercise extreme caution
with such setups.
Commit: a259ffb45c84f930d3ad810dd4ddde50c2667766
https://github.com/llvm/llvm-project/commit/a259ffb45c84f930d3ad810dd4ddde50c2667766
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/minmax-main-opcode-copyables-cost.ll
A llvm/test/Transforms/SLPVectorizer/X86/minmax-main-opcode-copyables.ll
Log Message:
-----------
[SLP][NFC]Add tests for copyables in minmax int intrinsics, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209021
Commit: 7206149c21b420a3aa5a0c9a78f1a1ad6ff8ed89
https://github.com/llvm/llvm-project/commit/7206149c21b420a3aa5a0c9a78f1a1ad6ff8ed89
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M clang/unittests/Lex/PPMemoryAllocationsTest.cpp
Log Message:
-----------
[NFC][clang] Adjust PPMemoryAllocationsTest threshold for ASan (#209024)
PPMemoryAllocationsTest.PPMacroDefinesAllocations measures the memory
footprint of the preprocessor allocator and asserts a strict threshold
of 130.0 bytes per define.
When built with ASan, the allocator adds redzones to allocations,
which increases the total memory reported by `getTotalMemory()` and
causes the test to fail (reporting ~136.8 bytes per define).
Adjust the threshold to 145.0 bytes per define when built with ASan
(detected via `LLVM_ADDRESS_SANITIZER_BUILD`) to account for this
overhead while maintaining the strict limit for standard builds.
Assisted-by: Gemini
Commit: 97e24c8d1cfd7259733ef4b3476f4429402415fb
https://github.com/llvm/llvm-project/commit/97e24c8d1cfd7259733ef4b3476f4429402415fb
Author: darkbuck <michael.hliao at gmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M clang/test/CIR/CodeGenBuiltins/builtin-fpclassify.c
M clang/test/CIR/CodeGenBuiltins/builtin-isfpclass.c
M clang/test/CIR/CodeGenBuiltins/builtin-isinf-sign.c
Log Message:
-----------
[CIR] Fix lit tests after is.fpclass pretty printing. NFC (#209026)
Commit: 715cf355b1324117a4456cd79bd05df39f65643c
https://github.com/llvm/llvm-project/commit/715cf355b1324117a4456cd79bd05df39f65643c
Author: savchart <metaartem at protonmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/test/clang-tidy/checkers/readability/Inputs/identifier-naming-macro-argument/.clang-tidy
A clang-tools-extra/test/clang-tidy/checkers/readability/Inputs/identifier-naming-macro-argument/include/macro.h
A clang-tools-extra/test/clang-tidy/checkers/readability/Inputs/identifier-naming-macro-argument/subdir/.clang-tidy
A clang-tools-extra/test/clang-tidy/checkers/readability/identifier-naming-macro-argument.cpp
Log Message:
-----------
[clang-tidy] Fix identifier-naming style lookup in macro arguments (#206809)
Problem statement: the var lambda parameter was written inside a macro
argument. The declaration location was treated as a macro location, and
the filename lookup returned an empty filename for that location.
Fix: use a file location for the style lookup. Alternative options
considered were spelling location and expansion location.
Fixes #154957
Assisted-by: GPT
---------
Co-authored-by: Zeyi Xu <mitchell.xu2 at gmail.com>
Co-authored-by: Baranov Victor <bar.victor.2002 at gmail.com>
Commit: 4e15b551e06b188f8280c752b29e13ac53ddb70a
https://github.com/llvm/llvm-project/commit/4e15b551e06b188f8280c752b29e13ac53ddb70a
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M lld/include/lld/Common/BPSectionOrdererBase.inc
M lld/test/ELF/bp-section-orderer.s
M lld/test/MachO/bp-section-orderer-errs.s
Log Message:
-----------
[lld] Report missing --irpgo-profile file instead of asserting (#209028)
When --irpgo-profile names a missing file, takeError() asserts
```
ld.lld: error: No such file or directory
ld.lld: Error.h:686: ... Assertion `!HasError && "Cannot get value when an error exists!"' failed.
```
Check the Expected before use. Fixes #203761
Co-authored-by: Peter Chen J. <peter941221 at gmail.com>
Co-authored-by: Peter Chen J. <peter941221 at gmail.com>
Commit: 5790cc0f6c7f1570f8cca222c19801a6c7c2f076
https://github.com/llvm/llvm-project/commit/5790cc0f6c7f1570f8cca222c19801a6c7c2f076
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/docs/LangRef.md
M llvm/lib/IR/Instructions.cpp
Log Message:
-----------
[IR] Use constant 64-bit indices for Extract/InsertElement (#208996)
The canonical form preferred by instCombine is to use 64-bit values for
constant index in ExtractElement and InsertElement
Commit: ede6a16b1bc4a870ff6180caeb87b727699cd9c1
https://github.com/llvm/llvm-project/commit/ede6a16b1bc4a870ff6180caeb87b727699cd9c1
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
Log Message:
-----------
[PowerPC] Use constant 64-bit indices for Extract/InsertElement (#209015)
The canonical form preferred by instCombine is to use 64-bit values for
constant index in ExtractElement and InsertElement.
Commit: 66e9ac6aeab326e5d4f6e0c1cbdbc31bda5dec0e
https://github.com/llvm/llvm-project/commit/66e9ac6aeab326e5d4f6e0c1cbdbc31bda5dec0e
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
Log Message:
-----------
[InstCombine] Use constant 64-bit indices for InsertElement (#209017)
The canonical form preferred by instCombine is to use 64-bit values for
constant index in InsertElement.
Commit: 83d95d89c520656306130b461252cd0ed9b4f542
https://github.com/llvm/llvm-project/commit/83d95d89c520656306130b461252cd0ed9b4f542
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
Log Message:
-----------
[SimplifyLibCalls] Use constant 64-bit indices for ExtractElement (#209020)
The canonical form preferred by instCombine is to use 64-bit values for
constant index in ExtractElement.
Commit: 3a27d292c353328a9a03422319ff1c0b9264648b
https://github.com/llvm/llvm-project/commit/3a27d292c353328a9a03422319ff1c0b9264648b
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M lld/ELF/MarkLive.cpp
M lld/ELF/Writer.cpp
Log Message:
-----------
[ELF] Move markUsedLocalSymbols from Writer to markLive. NFC (#209035)
markUsedLocalSymbols (https://reviews.llvm.org/D77807) sets the USED
flag on local symbols referenced by relocations so that -r/--emit-relocs
with --discard-{locals,all} preserves them in the symbol table.
Move the scan into markLive's !gcSections branch to be closer to
MarkLive::resolveReloc. The scan now iterates sections via relsOrRelas,
handling CREL uniformly, and runs in parallel.
This is a step toward fixing #160789
Commit: 937ac000a69012546d851638b1410cfe9f07980f
https://github.com/llvm/llvm-project/commit/937ac000a69012546d851638b1410cfe9f07980f
Author: Stefan Gränitz <stefan.graenitz at gmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Debuginfod/BuildIDFetcher.cpp
M llvm/lib/HTTP/HTTPClient.cpp
A llvm/test/tools/llvm-debuginfod-find/Inputs/delay_req.py
M llvm/test/tools/llvm-debuginfod-find/headers-winhttp.test
A llvm/test/tools/llvm-debuginfod-find/timeout.test
M llvm/tools/llvm-debuginfod-find/llvm-debuginfod-find.cpp
Log Message:
-----------
[llvm][HTTP] Apply WinHTTP timeout setting after WinHttpOpen (#188969)
`setTimeout()` required the session handle, but it was only created
inside `HTTPClient::perform()`. This patch stores the incoming value and
applies it after the session handle is created with `WinHttpOpen()`.
---------
Co-authored-by: Nerixyz <nerixdev at outlook.de>
Commit: fafd0de9e4a84921cce55ea8c6da05b515006fa2
https://github.com/llvm/llvm-project/commit/fafd0de9e4a84921cce55ea8c6da05b515006fa2
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/copyable-addsub-reorder.ll
Log Message:
-----------
[SLP][NFC]Add a test with incorrect add/sub operands reorder, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209039
Commit: 2fdc877f7209a32d9632aafe75d2d61199a7089f
https://github.com/llvm/llvm-project/commit/2fdc877f7209a32d9632aafe75d2d61199a7089f
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/copyable-addsub-reorder.ll
Log Message:
-----------
[SLP] Fix miscompile from unsafe operand-order normalization
IsCommutative(MainOp) is also true for a Sub/FSub feeding only
fabs/icmp-eq-0, but that doesn't make every lane swappable: a
converted Add/FAdd lane's operand order is fixed to preserve its
value, and swapping it into a native Sub/FSub's layout negates it.
Re-check each lane before swapping instead of trusting MainOp's.
Fixes #208944
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209041
Commit: 5485d624eb95bb7a753c6088e452d32d0bd0c03d
https://github.com/llvm/llvm-project/commit/5485d624eb95bb7a753c6088e452d32d0bd0c03d
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M lld/ELF/MarkLive.cpp
M lld/test/ELF/emit-relocs-discard-locals.s
Log Message:
-----------
[ELF] --discard-{locals,all}: mark local symbols referenced by retained non-SHF_ALLOC sections (#209042)
With --gc-sections, mark() does not scan relocations of retained
non-SHF_ALLOC sections, so local symbols referenced only by such
sections (e.g. .L symbols in .debug_str_offsets referenced by
.debug_info) do not get the USED flag.
-r/--emit-relocs with --discard-{locals,all} would discard the symbols
and rewrite relocations to reference the null symbol, corrupting DWARF
in the output. This is common on RISC-V, where
RISCVELFObjectWriter::needsRelocateWithSymbol returns true, but is also
possible on other targets with --reloc-section-sym=none.
Call markUsedLocalSymbols from the retention loop (introduced by
#209035)
to set the flag.
Fix #160789
Commit: 36876394a96b053a03aecacec566eadc292d7053
https://github.com/llvm/llvm-project/commit/36876394a96b053a03aecacec566eadc292d7053
Author: Nerixyz <nerixdev at outlook.de>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/test/tools/llvm-debuginfod-find/Inputs/delay_req.py
Log Message:
-----------
[llvm][HTTP] Increase request handler sleep (#209038)
Fixup for
https://github.com/llvm/llvm-project/pull/188969#issuecomment-4952185708.
The issue is likely the same as I described in
https://github.com/llvm/llvm-project/pull/192061#issuecomment-4926882131
where WinHTTP doesn't time out immediately but adds some delay. The fix
here is to increase the sleep in the mock server.
Commit: 65735abd4d0af888840929be6356628a05eaa179
https://github.com/llvm/llvm-project/commit/65735abd4d0af888840929be6356628a05eaa179
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/add-sub-nuw.ll
Log Message:
-----------
[SLP][NFC]Add a test with incorrect nuw propagation in add/sub vectorization, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209045
Commit: 927878dab67545e7448a82921446e339b6b55f79
https://github.com/llvm/llvm-project/commit/927878dab67545e7448a82921446e339b6b55f79
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/add-sub-nuw.ll
Log Message:
-----------
[SLP] Drop nuw when add/sub interchange negates a nonzero constant
sub nuw X, C requires X u>= C, but add nuw X, -C requires X u< C, so
nuw must always be dropped on interchange.
Fixes #209023
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209047
Commit: b8d37cbc139a5adcd56611c21850e02600e560f2
https://github.com/llvm/llvm-project/commit/b8d37cbc139a5adcd56611c21850e02600e560f2
Author: David Green <david.green at arm.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
M llvm/test/CodeGen/AArch64/verify-imm.mir
M llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
Log Message:
-----------
[AArch64] Add an OPERAND_IMM_UINT8 operand type. (#209050)
This helps verify that certain operands are in the correct range, in
this case
0-255.
Commit: 5566928ef0b0788da6582ea3bcc8ab9ae416e80f
https://github.com/llvm/llvm-project/commit/5566928ef0b0788da6582ea3bcc8ab9ae416e80f
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
A llvm/test/Analysis/LoopAccessAnalysis/wide-pointer-index-distance.ll
Log Message:
-----------
[LAA] Bail out of dependence analysis when distance exceeds 64 bits. (#209052)
isDependent extracts the dependence distance into 64 bit integers.
Bail out conservatively when the constant distance or the signed minimum
distance needs more than 64 bits.
Commit: 349542f7e122b8fda1d60f0b37c8f92ad65635d6
https://github.com/llvm/llvm-project/commit/349542f7e122b8fda1d60f0b37c8f92ad65635d6
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
Log Message:
-----------
[VPlan] Add strided access test with disjoint or. (NFC) (#209051)
Currently this is missed by VPlan SCEV due to disjoint OR not being
handled.
Commit: 62377815c4cc03130608158a8d51cc37e4549288
https://github.com/llvm/llvm-project/commit/62377815c4cc03130608158a8d51cc37e4549288
Author: David Green <david.green at arm.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/test/CodeGen/AArch64/verify-imm.mir
M llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
Log Message:
-----------
[AArch64] Add an OPERAND_IMM_UINT5 operand type. (#209057)
This helps verify that certain operands are in the correct range, in
this case
0-31.
Commit: fd6524963bf1ec6b4d2c688337af8f9f41562575
https://github.com/llvm/llvm-project/commit/fd6524963bf1ec6b4d2c688337af8f9f41562575
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
A llvm/test/Transforms/LoopVectorize/outer-loop-atomic.ll
Log Message:
-----------
[VPlan] Handle AtomicRMW/AtomicCmpXchg/Fence in outer loop creation. (#209031)
Teach VPInstruction::getNumOperandsForOpcode about AtomicRMW,
AtomicCmpXchg and Fence, so VPlan construction over an outer loop that
still contains these operations does not crash before later legality
rejects the loop.
Fixes crashes in the added tests.
Commit: bb4aea6303e7470be3ccd37db9398fc9b8f03f50
https://github.com/llvm/llvm-project/commit/bb4aea6303e7470be3ccd37db9398fc9b8f03f50
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
A llvm/test/Analysis/ScalarEvolution/ptrtoint-special-pointers.ll
M llvm/test/Transforms/GVN/ptrtoaddr.ll
A llvm/test/Transforms/IndVarSimplify/AArch64/expand-ptrtoaddr-reuse-ptrtoint.ll
Log Message:
-----------
[SCEV,GVN] Add additional ptrtoaddr tests (NFC) (#209049)
Extend test coverage with files with mixied ptrtoaddr/ptrtoint, as well
as wide pointers.
Extra test coverage for
https://github.com/llvm/llvm-project/pull/180244.
Commit: d036d309eebee3ac0b8077f0cc6e3a318bc0e6ab
https://github.com/llvm/llvm-project/commit/d036d309eebee3ac0b8077f0cc6e3a318bc0e6ab
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M lld/test/MachO/bp-section-orderer-errs.s
Log Message:
-----------
[test] Add REQUIRES: aarch64 (#209058)
Commit: 0188651ae4a0d38f014fc315f182aa813a73dfbe
https://github.com/llvm/llvm-project/commit/0188651ae4a0d38f014fc315f182aa813a73dfbe
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-signed-icmp-const.ll
Log Message:
-----------
[SLP][NFC]Add a test with the incorrect const trunc in signed compare, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209059
Commit: fe85b5be435add42d83d85e09059ae2e6e0896e4
https://github.com/llvm/llvm-project/commit/fe85b5be435add42d83d85e09059ae2e6e0896e4
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-signed-icmp-const.ll
Log Message:
-----------
[SLP] Fix miscompile from truncating signed icmp constant
getActiveBits() ignores sign, so a positive constant needing the
narrower type's top bit was truncated to a negative value. Use
getSignificantBits() for signed comparisons.
Fixes #209010
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209061
Commit: 9083925dadb45d99836b75ac0354265d6cbd46ab
https://github.com/llvm/llvm-project/commit/9083925dadb45d99836b75ac0354265d6cbd46ab
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M lld/test/ELF/retain-symbols-file.s
M lld/test/ELF/retain-und.s
Log Message:
-----------
[ELF,test] Modernize --retain-symbols-file tests (#209062)
Switch to llvm-readelf, compact FileCheck directives, and
split-file-style naming. Prepares for a --retain-symbols-file behavior
change.
Commit: b6e77d6af14b6b4d0d98248c1579b1be0194187a
https://github.com/llvm/llvm-project/commit/b6e77d6af14b6b4d0d98248c1579b1be0194187a
Author: Wenju He <wenju.he at intel.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/unittests/ScalableStaticAnalysis/Analyses/OperatorNewDelete/OperatorNewDeletePointersExtractorTest.cpp
Log Message:
-----------
[Clang][Test] Fix -Wctad-maybe-unsupported in OperatorNewDeletePointersExtractorTest.cpp (#209012)
Fix warning: `'std::set' may not intend to support class template
argument deduction [-Wctad-maybe-unsupported]`, which is error under
-Werror.
std::set{*PtrId} does implicitly deduce to std::set<EntityId>, but it
is not explicit or user-defined CATD guide. Opt-in warning
-Wctad-maybe-unsupported flags it as maybe unsafe and unintended. The
warning is enabled at
https://github.com/llvm/llvm-project/blob/9083925dadb4/llvm/cmake/modules/HandleLLVMOptions.cmake#L977
Relates to #206600.
Commit: c847ddf8f18d3edde84fa99bf9d15511a7978cdd
https://github.com/llvm/llvm-project/commit/c847ddf8f18d3edde84fa99bf9d15511a7978cdd
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M lld/ELF/Writer.cpp
M lld/unittests/AsLibELF/CMakeLists.txt
A lld/unittests/AsLibELF/OutputStream.cpp
Log Message:
-----------
[ELF] Write the output to lld::outs() when -o is - (#209064)
When the output file is "-", write the image to lld::outs() (the
stdoutOS
argument of lld::elf::link()) instead of committing the
FileOutputBuffer,
which writes to the process's stdout. This lets lld used as a library
capture
the output in a raw_ostream without an open syscall.
This reimplements the stale #72061 and adds a unittest.
Commit: 7d24dfa5f29e1794e452aadaa27f994f15568763
https://github.com/llvm/llvm-project/commit/7d24dfa5f29e1794e452aadaa27f994f15568763
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lld/docs/ReleaseNotes.rst
Log Message:
-----------
ReleaseNotes: add lld/ELF notes (#209066)
Summarize `git log origin/release/22.x..main` entries, excluding
cherry-picked notes `git rev-list main..origin/release/22.x -- lld/ELF`,
following the style of my previous release notes.
Commit: c7812f661d843e666c6ab3ab9c4a33b83e930c29
https://github.com/llvm/llvm-project/commit/c7812f661d843e666c6ab3ab9c4a33b83e930c29
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/copyable-repeated-operand-partial-commutativity.ll
Log Message:
-----------
[SLP] Fix crash from repeated operand with mixed commutativity
A value used as both a commutable and non-commutable operand of the
same call got double-counted in dependency tracking, adding a
dependency scheduling never releases and tripping an assertion.
Fixes #209005
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209067
Commit: 692d89dc02deb30d14bcaa2dbb2ed91ea8f88acd
https://github.com/llvm/llvm-project/commit/692d89dc02deb30d14bcaa2dbb2ed91ea8f88acd
Author: aokblast <aokblast at FreeBSD.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lldb/source/Host/freebsd/Host.cpp
Log Message:
-----------
[LLDB][FreeBSD] Fill pgid and sid in ProcessInfo (#209009)
These two fields are required by HostTest.cpp. Although I don't see any
usecase, we add these two fields to prevent failure.
Commit: 461f0b699c8dbcafaec0e4b2d171d42ee05f6999
https://github.com/llvm/llvm-project/commit/461f0b699c8dbcafaec0e4b2d171d42ee05f6999
Author: aokblast <aokblast at FreeBSD.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lldb/include/lldb/Host/JSONTransport.h
Log Message:
-----------
[LLDB] Fix use-after-free destroying a Binder from its OnClosed handler (#209019)
transport::Binder::OnClosed() holds m_mutex (a recursive_mutex) while
invoking m_disconnect_handler. In the MCP server, that handler removes
the disconnected client, which owns the transport and therefore the
Binder itself. As a result, the Binder -- and its m_mutex -- are
destroyed while the scoped_lock in OnClosed still holds the lock.
This is a use-after-free everywhere, as the lock guard later unlocks
freed memory.
Move the disconnect handler out of the critical section and release the
lock before invoking it, so the Binder can be safely destroyed without
holding or destroying a locked mutex.
Commit: 171ba71128eec9f1859bb995c597dcff296ee730
https://github.com/llvm/llvm-project/commit/171ba71128eec9f1859bb995c597dcff296ee730
Author: Thrrreeee <shijinrui at bytedance.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M bolt/lib/Rewrite/DWARFRewriter.cpp
M bolt/test/X86/dwarf4-cross-cu-ranges.test
M bolt/test/X86/dwarf5-debug-names-cross-cu.s
Log Message:
-----------
[BOLT] fix DIE traversal incorrect loop termination condition. (#208450)
The DIE traversal loop in partitionCUs() used an incorrect termination
condition, causing it to read past the end of the CU. Fix the loop to
stop at NextCUOffset so traversal no longer runs beyond the unit's
boundary.
Fixed [#208440](https://github.com/llvm/llvm-project/issues/208440).
Commit: e6673bd0377104b681ad9f456f3b7742c8f3a9a9
https://github.com/llvm/llvm-project/commit/e6673bd0377104b681ad9f456f3b7742c8f3a9a9
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/CMakeLists.txt
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.cpp
A llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.h
Log Message:
-----------
[SLP][Modularization][NFC] Extract type and constant helpers into SLPUtils (1/3) (#206881)
As we discussed on RFC:
https://discourse.llvm.org/t/modularizing-slpvectorizer-cpp/90922
This patch introduces the SLPVectorizer/ subdirectory and adds
SLPUtils.{h,cpp} under namespace llvm::slpvectorizer, then moves the
type and constant query helpers into it:
- isConstant
- isVectorLikeInstWithConstOps
- isSplat
- allConstant
- allSameBlock
- allSameType
- allSameOpcode
- getNumElements
- getPartNumElems
- getNumElems
- getInsertExtractIndex
- getExtractIndex
Commit: d91a1e88891d9737535198137c73632f57cc629a
https://github.com/llvm/llvm-project/commit/d91a1e88891d9737535198137c73632f57cc629a
Author: Yihan Wang <yronglin777 at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M .github/workflows/libcxx-build-and-test.yaml
Log Message:
-----------
[libc++] Switch use llvm-premerge-libcxx-runner (#208928)
Signed-off-by: yronglin <yronglin777 at gmail.com>
Co-authored-by: Aiden Grossman <aidengrossman at google.com>
Commit: d8df9b5e925c580f076779e5cbfe2bffc451c3b6
https://github.com/llvm/llvm-project/commit/d8df9b5e925c580f076779e5cbfe2bffc451c3b6
Author: ejose02 <ejose at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M flang/lib/Semantics/check-call.cpp
A flang/test/Semantics/call48.f90
Log Message:
-----------
[Flang] Fix for the spurious error for VOLATILE actual argument in implicit interface CALL (#192605)
Fixes #191343
Replaced the error with warning. Now it permits calling an external
procedure with implicit interface and passing a volatile argument. There
will be a warning that the procedure should have an explicit interface.
In addition to fixing the VOLATILE error, I updated the semantic check
for the ASYNCHRONOUS attribute. Both attributes were incorrectly
throwing a hard error when used as actual arguments in an implicit
interface call. According to the Fortran 2018 standard, an explicit
interface is only mandatory when the dummy argument has the VOLATILE or
ASYNCHRONOUS attribute. Since the standard doesn't restrict actual
arguments in this scenario, I downgraded both to emit a
-Wimplicit-interface-actual warning instead.
Commit: b1c56fb53a9c76d6b045ede49083b647ae049ffe
https://github.com/llvm/llvm-project/commit/b1c56fb53a9c76d6b045ede49083b647ae049ffe
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt-c/Logging.h
M orc-rt/lib/executor/CMakeLists.txt
A orc-rt/lib/executor/Logging_oslog.cpp
M orc-rt/test/regression/lit.cfg.py
A orc-rt/test/regression/logging/os_log/delivery.test
A orc-rt/test/regression/logging/os_log/lit.local.cfg
A orc-rt/test/regression/logging/os_log/no-printf-output.test
M orc-rt/test/tools/orc-rt-log-check.cpp
Log Message:
-----------
[orc-rt] Add os_log logging backend (Darwin only) (#209081)
Implement the os_log backend, selected with ORC_RT_LOG_BACKEND=os_log.
With this backend selected, the ORC_RT_LOG macros expand at the call
site to os_log_with_type. Each ORC runtime log level maps to an
os_log_type_t (error -> ERROR, warning -> DEFAULT, info -> INFO, debug
-> DEBUG). The compile-time ORC_RT_LOG_LEVEL floor still applies, but
runtime filtering is left to the system (e.g. `log config`), so the
printf backend's ORC_RT_LOG and ORC_RT_LOG_OUTPUT have no effect.
Records go to the "org.llvm.orc-rt" subsystem with the category as the
os_log category. (Per-category handles are created on first use and
cached).
Add regression tests under test/regression/logging/os_log:
no-printf-output.test checks that the backend produces no console
output, and an opt-in delivery test (llvm-lit --param
run-os-log-tests=1) scrapes `log show` to confirm records reach the
expected subsystem and category.
Commit: 9b9f44d1c55ca4f3e8d6d5d9350ef872e000df0a
https://github.com/llvm/llvm-project/commit/9b9f44d1c55ca4f3e8d6d5d9350ef872e000df0a
Author: Kazu Hirata <kazu at google.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
A llvm/include/llvm/ADT/Eytzinger.h
M llvm/unittests/ADT/CMakeLists.txt
A llvm/unittests/ADT/EytzingerTest.cpp
Log Message:
-----------
[ADT] Introduce EytzingerTableSpan (#208885)
This patch introduces EytzingerTableSpan, a non-owning view of a buffer
formatted as a complete binary search tree in Eytzinger (breadth-first)
order.
RFC:
https://discourse.llvm.org/t/rfc-faster-sample-profile-loading/90957/7
Assisted-by: Antigravity
Commit: fd17f88189525a81488294912bff8b9f429585a2
https://github.com/llvm/llvm-project/commit/fd17f88189525a81488294912bff8b9f429585a2
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
Log Message:
-----------
[RISCV][P-ext] Replace RISCVISD::PPAIRE_DB with RISCVISD::PPAIRE. NFC (#208980)
This replaces RISCVISD::PPAIRE_DB with the RISCVISD::PPAIRE added by
#208763.
This adds two CONCAT_VECTORS and two EXTRACT_SUBVECTORs during lowering
instead of waiting until isel to form the GPR pairs.
Commit: 11112ed9b7eb7deb69b97178a0c4921e6222049c
https://github.com/llvm/llvm-project/commit/11112ed9b7eb7deb69b97178a0c4921e6222049c
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M libc/src/__support/CPP/expected.h
M libc/test/src/__support/CPP/CMakeLists.txt
A libc/test/src/__support/CPP/expected_test.cpp
Log Message:
-----------
[libc] Make cpp::expected::operator bool explicit (#208681)
Without explicit, expected<T, E> implicitly converts to bool in all
sorts of unexpected contexts (e.g. `EXPECT_EQ(ErrorOr<int>(47), 1)`),
and also deviates from std::expected in C++23.
While in there, add basic unit tests for expected and unexpected (we
didn't have any tests for this utility yet), and update the file header.
Assisted by Gemini.
Commit: 26e34c6896626f0874a1eface84b8fb25111f4b0
https://github.com/llvm/llvm-project/commit/26e34c6896626f0874a1eface84b8fb25111f4b0
Author: Justin Lebar <justin.lebar at gmail.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/IR/Constants.cpp
M llvm/test/Transforms/TailCallElim/accum_recursion.ll
M llvm/test/Transforms/TailCallElim/tre-minmax-intrinsic.ll
Log Message:
-----------
[IR] Handle vector tys in ConstantExpr::getIntrinsicIdentity for smin/max. (#208367)
The code was using getIntegerBitWidth() when it should have been using
getScalarSizeInBits(). This resulted in an assert in debug builds, and
who-knows-what in opt builds.
Reproducer:
```
define <4 x i32> @f(<4 x i32> %a, i32 %b) {
%c = call <4 x i32> @f(<4 x i32> %a, i32 %b)
%m = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %c, <4 x i32> %a)
ret <4 x i32> %m
}
$ opt -passes=tailcallelim repro.ll
Casting.h:572: Assertion `isa<To>(Val) && "cast<Ty>() argument of
incompatible type!"' failed.
```
Bug found and fixed by Claude Mythos 5.
Commit: 3f80df8698145f0188f305b748e60e70bf942d3d
https://github.com/llvm/llvm-project/commit/3f80df8698145f0188f305b748e60e70bf942d3d
Author: Sergey Shcherbinin <sscherbinin at nvidia.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M bolt/test/X86/match-blocks-with-pseudo-probes-inline.test
M bolt/test/X86/pseudoprobe-decoding-inline.test
M bolt/test/X86/pseudoprobe-decoding-noinline.test
A llvm/test/tools/llvm-profgen/AArch64/aarch64-disassemble-all-features.test
A llvm/test/tools/llvm-profgen/AArch64/lit.local.cfg
A llvm/test/tools/llvm-profgen/ARM/Inputs/etm-opencsd.yaml
A llvm/test/tools/llvm-profgen/ARM/etm-arch.test
A llvm/test/tools/llvm-profgen/ARM/etm-opencsd.test
A llvm/test/tools/llvm-profgen/ARM/lit.local.cfg
R llvm/test/tools/llvm-profgen/Inputs/artificial-branch.perfscript
R llvm/test/tools/llvm-profgen/Inputs/callback-external-addr.perfbin
R llvm/test/tools/llvm-profgen/Inputs/callback-external-addr.perfscript
R llvm/test/tools/llvm-profgen/Inputs/coff-profile.exe
R llvm/test/tools/llvm-profgen/Inputs/coff-profile.pdb
R llvm/test/tools/llvm-profgen/Inputs/coff-profile.perfscript
R llvm/test/tools/llvm-profgen/Inputs/cold-profile-trimming.raw.prof
R llvm/test/tools/llvm-profgen/Inputs/coroutine.perfbin
R llvm/test/tools/llvm-profgen/Inputs/coroutine.perfscript
R llvm/test/tools/llvm-profgen/Inputs/cs-interrupt.perfscript
R llvm/test/tools/llvm-profgen/Inputs/cs-invalid-ret-addr.perfscript
R llvm/test/tools/llvm-profgen/Inputs/cs-preinline-cost.perfbin
R llvm/test/tools/llvm-profgen/Inputs/cs-preinline-cost.perfscript
R llvm/test/tools/llvm-profgen/Inputs/css-pgo-perf.script
R llvm/test/tools/llvm-profgen/Inputs/dap-perf-trace.txt
R llvm/test/tools/llvm-profgen/Inputs/dap-pie.bin
R llvm/test/tools/llvm-profgen/Inputs/dap.bin
R llvm/test/tools/llvm-profgen/Inputs/etm-opencsd.yaml
R llvm/test/tools/llvm-profgen/Inputs/external-address.perfscript
R llvm/test/tools/llvm-profgen/Inputs/filter-ambiguous-profile.prof
R llvm/test/tools/llvm-profgen/Inputs/fs-discriminator-probe.perfbin
R llvm/test/tools/llvm-profgen/Inputs/fs-discriminator-probe.raw.prof
R llvm/test/tools/llvm-profgen/Inputs/fs-discriminator.perfbin
R llvm/test/tools/llvm-profgen/Inputs/fs-discriminator.raw.prof
R llvm/test/tools/llvm-profgen/Inputs/func-split.perfbin
R llvm/test/tools/llvm-profgen/Inputs/func-split.perfscript
R llvm/test/tools/llvm-profgen/Inputs/inline-cs-noprobe.perfbin
R llvm/test/tools/llvm-profgen/Inputs/inline-cs-noprobe.perfscript
R llvm/test/tools/llvm-profgen/Inputs/inline-cs-pseudoprobe.perfbin
R llvm/test/tools/llvm-profgen/Inputs/inline-cs-pseudoprobe.perfscript
R llvm/test/tools/llvm-profgen/Inputs/inline-noprobe.perfbin
R llvm/test/tools/llvm-profgen/Inputs/inline-noprobe.perfscript
R llvm/test/tools/llvm-profgen/Inputs/inline-noprobe2.perfbin
R llvm/test/tools/llvm-profgen/Inputs/inline-noprobe2.perfscript
R llvm/test/tools/llvm-profgen/Inputs/invalid-range.perfscript
R llvm/test/tools/llvm-profgen/Inputs/lbr-perf-for-dap.script
R llvm/test/tools/llvm-profgen/Inputs/missing-dwarf.exe
R llvm/test/tools/llvm-profgen/Inputs/multi-load-segs.perfbin
R llvm/test/tools/llvm-profgen/Inputs/multi-load-segs.perfscript
R llvm/test/tools/llvm-profgen/Inputs/noinline-cs-noprobe.aggperfscript
R llvm/test/tools/llvm-profgen/Inputs/noinline-cs-noprobe.perfbin
R llvm/test/tools/llvm-profgen/Inputs/noinline-cs-noprobe.perfscript
R llvm/test/tools/llvm-profgen/Inputs/noinline-cs-pseudoprobe.aggperfscript
R llvm/test/tools/llvm-profgen/Inputs/noinline-cs-pseudoprobe.perfbin
R llvm/test/tools/llvm-profgen/Inputs/noinline-cs-pseudoprobe.perfscript
R llvm/test/tools/llvm-profgen/Inputs/noinline-tailcall-probe.perfbin
R llvm/test/tools/llvm-profgen/Inputs/noinline-tailcall-probe.perfscript
R llvm/test/tools/llvm-profgen/Inputs/noprobe.aggperfscript
R llvm/test/tools/llvm-profgen/Inputs/noprobe.mmap.perfscript
R llvm/test/tools/llvm-profgen/Inputs/noprobe.perfbin
R llvm/test/tools/llvm-profgen/Inputs/noprobe.perfscript
R llvm/test/tools/llvm-profgen/Inputs/out-of-bounds.raw.prof
R llvm/test/tools/llvm-profgen/Inputs/pie-dap-perf.txt
R llvm/test/tools/llvm-profgen/Inputs/pie-lbr-perf.script
R llvm/test/tools/llvm-profgen/Inputs/profile-density-cs.raw.prof
R llvm/test/tools/llvm-profgen/Inputs/profile-density.raw.prof
R llvm/test/tools/llvm-profgen/Inputs/recursion-compression-noprobe.perfbin
R llvm/test/tools/llvm-profgen/Inputs/recursion-compression-noprobe.perfscript
R llvm/test/tools/llvm-profgen/Inputs/recursion-compression-pseudoprobe-nommap.perfscript
R llvm/test/tools/llvm-profgen/Inputs/recursion-compression-pseudoprobe.perfbin
R llvm/test/tools/llvm-profgen/Inputs/recursion-compression-pseudoprobe.perfscript
R llvm/test/tools/llvm-profgen/Inputs/split-dwarf-single.exe
R llvm/test/tools/llvm-profgen/Inputs/split-dwarf-single.o.yaml
R llvm/test/tools/llvm-profgen/Inputs/split-dwarf-split.dwo.yaml
R llvm/test/tools/llvm-profgen/Inputs/split-dwarf-split.exe
R llvm/test/tools/llvm-profgen/Inputs/symbolize.ll
R llvm/test/tools/llvm-profgen/Inputs/symbolize.perfbin
R llvm/test/tools/llvm-profgen/Inputs/truncated-pseudoprobe.ll
R llvm/test/tools/llvm-profgen/Inputs/truncated-pseudoprobe.perfbin
R llvm/test/tools/llvm-profgen/Inputs/truncated-pseudoprobe.perfscript
R llvm/test/tools/llvm-profgen/Inputs/unique-linkage-name-dwarf.perfbin
R llvm/test/tools/llvm-profgen/Inputs/unique-linkage-name-dwarf.perfscript
R llvm/test/tools/llvm-profgen/Inputs/unique-linkage-name-probe.perfbin
R llvm/test/tools/llvm-profgen/Inputs/unique-linkage-name-probe.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/artificial-branch.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/callback-external-addr.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/callback-external-addr.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/coff-profile.exe
A llvm/test/tools/llvm-profgen/X86/Inputs/coff-profile.pdb
A llvm/test/tools/llvm-profgen/X86/Inputs/coff-profile.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/cold-profile-trimming.raw.prof
A llvm/test/tools/llvm-profgen/X86/Inputs/coroutine.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/coroutine.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/cs-interrupt.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/cs-invalid-ret-addr.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/cs-preinline-cost.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/cs-preinline-cost.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/css-pgo-perf.script
A llvm/test/tools/llvm-profgen/X86/Inputs/dap-perf-trace.txt
A llvm/test/tools/llvm-profgen/X86/Inputs/dap-pie.bin
A llvm/test/tools/llvm-profgen/X86/Inputs/dap.bin
A llvm/test/tools/llvm-profgen/X86/Inputs/external-address.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/filter-ambiguous-profile.prof
A llvm/test/tools/llvm-profgen/X86/Inputs/fs-discriminator-probe.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/fs-discriminator-probe.raw.prof
A llvm/test/tools/llvm-profgen/X86/Inputs/fs-discriminator.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/fs-discriminator.raw.prof
A llvm/test/tools/llvm-profgen/X86/Inputs/func-split.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/func-split.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/inline-cs-noprobe.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/inline-cs-noprobe.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/inline-cs-pseudoprobe.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/inline-cs-pseudoprobe.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/inline-noprobe.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/inline-noprobe.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/inline-noprobe2.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/inline-noprobe2.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/invalid-range.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/lbr-perf-for-dap.script
A llvm/test/tools/llvm-profgen/X86/Inputs/missing-dwarf.exe
A llvm/test/tools/llvm-profgen/X86/Inputs/multi-load-segs.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/multi-load-segs.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/noinline-cs-noprobe.aggperfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/noinline-cs-noprobe.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/noinline-cs-noprobe.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/noinline-cs-pseudoprobe.aggperfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/noinline-cs-pseudoprobe.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/noinline-cs-pseudoprobe.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/noinline-tailcall-probe.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/noinline-tailcall-probe.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/noprobe.aggperfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/noprobe.mmap.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/noprobe.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/noprobe.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/out-of-bounds.raw.prof
A llvm/test/tools/llvm-profgen/X86/Inputs/pie-dap-perf.txt
A llvm/test/tools/llvm-profgen/X86/Inputs/pie-lbr-perf.script
A llvm/test/tools/llvm-profgen/X86/Inputs/profile-density-cs.raw.prof
A llvm/test/tools/llvm-profgen/X86/Inputs/profile-density.raw.prof
A llvm/test/tools/llvm-profgen/X86/Inputs/recursion-compression-noprobe.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/recursion-compression-noprobe.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/recursion-compression-pseudoprobe-nommap.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/recursion-compression-pseudoprobe.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/recursion-compression-pseudoprobe.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/split-dwarf-single.exe
A llvm/test/tools/llvm-profgen/X86/Inputs/split-dwarf-single.o.yaml
A llvm/test/tools/llvm-profgen/X86/Inputs/split-dwarf-split.dwo.yaml
A llvm/test/tools/llvm-profgen/X86/Inputs/split-dwarf-split.exe
A llvm/test/tools/llvm-profgen/X86/Inputs/symbolize.ll
A llvm/test/tools/llvm-profgen/X86/Inputs/symbolize.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/truncated-pseudoprobe.ll
A llvm/test/tools/llvm-profgen/X86/Inputs/truncated-pseudoprobe.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/truncated-pseudoprobe.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/unique-linkage-name-dwarf.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/unique-linkage-name-dwarf.perfscript
A llvm/test/tools/llvm-profgen/X86/Inputs/unique-linkage-name-probe.perfbin
A llvm/test/tools/llvm-profgen/X86/Inputs/unique-linkage-name-probe.perfscript
A llvm/test/tools/llvm-profgen/X86/afdo-with-vtable-pie.test
A llvm/test/tools/llvm-profgen/X86/afdo-with-vtable.test
A llvm/test/tools/llvm-profgen/X86/callback-external-addr.test
A llvm/test/tools/llvm-profgen/X86/coff-profile.test
A llvm/test/tools/llvm-profgen/X86/cold-profile-trimming-symbolized.test
A llvm/test/tools/llvm-profgen/X86/cold-profile-trimming.test
A llvm/test/tools/llvm-profgen/X86/context-depth.test
A llvm/test/tools/llvm-profgen/X86/coroutine.test
A llvm/test/tools/llvm-profgen/X86/cs-extbinary.test
A llvm/test/tools/llvm-profgen/X86/cs-external-address.test
A llvm/test/tools/llvm-profgen/X86/cs-interrupt.test
A llvm/test/tools/llvm-profgen/X86/cs-invalid-ret-addr.test
A llvm/test/tools/llvm-profgen/X86/cs-preinline-cost.test
A llvm/test/tools/llvm-profgen/X86/cs-preinline-sample-profile.test
A llvm/test/tools/llvm-profgen/X86/cs-preinline.test
A llvm/test/tools/llvm-profgen/X86/cs-tailcall.test
A llvm/test/tools/llvm-profgen/X86/disassemble.test
A llvm/test/tools/llvm-profgen/X86/etm-non-arm.test
A llvm/test/tools/llvm-profgen/X86/filter-ambiguous-profile.test
A llvm/test/tools/llvm-profgen/X86/fname-canonicalization.test
A llvm/test/tools/llvm-profgen/X86/fs-discriminator-probe.test
A llvm/test/tools/llvm-profgen/X86/fs-discriminator.test
A llvm/test/tools/llvm-profgen/X86/func-split.test
A llvm/test/tools/llvm-profgen/X86/inline-cs-noprobe.test
A llvm/test/tools/llvm-profgen/X86/inline-cs-pseudoprobe.test
A llvm/test/tools/llvm-profgen/X86/inline-force-dwarf.test
A llvm/test/tools/llvm-profgen/X86/inline-noprobe.test
A llvm/test/tools/llvm-profgen/X86/inline-noprobe2.test
A llvm/test/tools/llvm-profgen/X86/inline-probe-afdo.test
A llvm/test/tools/llvm-profgen/X86/inline-pseudoprobe.test
A llvm/test/tools/llvm-profgen/X86/invalid-perfscript.test
A llvm/test/tools/llvm-profgen/X86/invalid-range.test
A llvm/test/tools/llvm-profgen/X86/lit.local.cfg
A llvm/test/tools/llvm-profgen/X86/merge-cold-profile.test
A llvm/test/tools/llvm-profgen/X86/missing-dwarf.test
A llvm/test/tools/llvm-profgen/X86/mmapEvent.test
A llvm/test/tools/llvm-profgen/X86/multi-load-segs.test
A llvm/test/tools/llvm-profgen/X86/noinline-cs-noprobe.test
A llvm/test/tools/llvm-profgen/X86/noinline-cs-pseudoprobe.test
A llvm/test/tools/llvm-profgen/X86/noinline-noprobe.test
A llvm/test/tools/llvm-profgen/X86/noinline-pseudoprobe.test
A llvm/test/tools/llvm-profgen/X86/profile-density.test
A llvm/test/tools/llvm-profgen/X86/pseudo-probe-desc-mismatch.test
A llvm/test/tools/llvm-profgen/X86/pseudoprobe-decoding-discriminator.test
A llvm/test/tools/llvm-profgen/X86/pseudoprobe-decoding.test
A llvm/test/tools/llvm-profgen/X86/recursion-compression-noprobe.test
A llvm/test/tools/llvm-profgen/X86/recursion-compression-pseudoprobe.test
A llvm/test/tools/llvm-profgen/X86/separate-debuginfo-binary.test
A llvm/test/tools/llvm-profgen/X86/split-dwarf.test
A llvm/test/tools/llvm-profgen/X86/symbolize.test
A llvm/test/tools/llvm-profgen/X86/truncated-pseudoprobe.test
A llvm/test/tools/llvm-profgen/X86/update-samples.test
R llvm/test/tools/llvm-profgen/aarch64-disassemble-all-features.test
R llvm/test/tools/llvm-profgen/afdo-with-vtable-pie.test
R llvm/test/tools/llvm-profgen/afdo-with-vtable.test
R llvm/test/tools/llvm-profgen/callback-external-addr.test
R llvm/test/tools/llvm-profgen/coff-profile.test
R llvm/test/tools/llvm-profgen/cold-profile-trimming-symbolized.test
R llvm/test/tools/llvm-profgen/cold-profile-trimming.test
R llvm/test/tools/llvm-profgen/context-depth.test
R llvm/test/tools/llvm-profgen/coroutine.test
R llvm/test/tools/llvm-profgen/cs-extbinary.test
R llvm/test/tools/llvm-profgen/cs-external-address.test
R llvm/test/tools/llvm-profgen/cs-interrupt.test
R llvm/test/tools/llvm-profgen/cs-invalid-ret-addr.test
R llvm/test/tools/llvm-profgen/cs-preinline-cost.test
R llvm/test/tools/llvm-profgen/cs-preinline-sample-profile.test
R llvm/test/tools/llvm-profgen/cs-preinline.test
R llvm/test/tools/llvm-profgen/cs-tailcall.test
R llvm/test/tools/llvm-profgen/disassemble.test
R llvm/test/tools/llvm-profgen/etm-arch.test
R llvm/test/tools/llvm-profgen/etm-opencsd.test
R llvm/test/tools/llvm-profgen/filter-ambiguous-profile.test
R llvm/test/tools/llvm-profgen/fname-canonicalization.test
R llvm/test/tools/llvm-profgen/fs-discriminator-probe.test
R llvm/test/tools/llvm-profgen/fs-discriminator.test
R llvm/test/tools/llvm-profgen/func-split.test
R llvm/test/tools/llvm-profgen/inline-cs-noprobe.test
R llvm/test/tools/llvm-profgen/inline-cs-pseudoprobe.test
R llvm/test/tools/llvm-profgen/inline-force-dwarf.test
R llvm/test/tools/llvm-profgen/inline-noprobe.test
R llvm/test/tools/llvm-profgen/inline-noprobe2.test
R llvm/test/tools/llvm-profgen/inline-probe-afdo.test
R llvm/test/tools/llvm-profgen/inline-pseudoprobe.test
R llvm/test/tools/llvm-profgen/invalid-perfscript.test
R llvm/test/tools/llvm-profgen/invalid-range.test
M llvm/test/tools/llvm-profgen/lit.local.cfg
R llvm/test/tools/llvm-profgen/merge-cold-profile.test
R llvm/test/tools/llvm-profgen/missing-dwarf.test
R llvm/test/tools/llvm-profgen/mmapEvent.test
R llvm/test/tools/llvm-profgen/multi-load-segs.test
R llvm/test/tools/llvm-profgen/noinline-cs-noprobe.test
R llvm/test/tools/llvm-profgen/noinline-cs-pseudoprobe.test
R llvm/test/tools/llvm-profgen/noinline-noprobe.test
R llvm/test/tools/llvm-profgen/noinline-pseudoprobe.test
R llvm/test/tools/llvm-profgen/profile-density.test
R llvm/test/tools/llvm-profgen/pseudo-probe-desc-mismatch.test
R llvm/test/tools/llvm-profgen/pseudoprobe-decoding-discriminator.test
R llvm/test/tools/llvm-profgen/pseudoprobe-decoding.test
R llvm/test/tools/llvm-profgen/recursion-compression-noprobe.test
R llvm/test/tools/llvm-profgen/recursion-compression-pseudoprobe.test
R llvm/test/tools/llvm-profgen/separate-debuginfo-binary.test
R llvm/test/tools/llvm-profgen/split-dwarf.test
R llvm/test/tools/llvm-profgen/symbolize.test
R llvm/test/tools/llvm-profgen/truncated-pseudoprobe.test
R llvm/test/tools/llvm-profgen/update-samples.test
Log Message:
-----------
[llvm-profgen][test] Split tests by target architecture (#207724)
The top-level llvm-profgen lit configuration previously disabled the
entire test directory unless the X86 target was registered. As a result,
target-independent tests and tests for ARM and AArch64 also implicitly
depended on X86.
Split target-specific tests and inputs into X86, ARM, and AArch64
directories with per-directory lit.local.cfg files. Leave help.test at
the top level because it is target-independent. Existing X86 tests
remain guarded by X86 and run as before, while ARM and AArch64 tests no
longer require the X86 target. The X86 non-ARM ETM rejection case also
no longer requires the ARM target; it only requires X86 and OpenCSD.
Split the former etm-arch.test into ARM/etm-arch.test, containing the
two ARM-specific checks, and X86/etm-non-arm.test, containing the
existing X86 rejection check. The tested inputs and expected diagnostics
are preserved.
Update match-blocks-with-pseudo-probes-inline.test,
pseudoprobe-decoding-inline.test, and pseudoprobe-decoding-noinline.test
in BOLT to refer to the relocated X86 inputs. All other llvm-profgen
tests and inputs are pure renames.
This does not change llvm-profgen runtime behavior; it only removes
unnecessary cross-target dependencies from its test suite.
This is a preparatory change for extending llvm-profgen profiling
support to AArch64 and for introducing the universal profile-guided
automatic software loop data prefetcher described in the RFC:
https://discourse.llvm.org/t/rfc-universal-profile-guided-automatic-software-loop-data-prefetcher-for-llvm/90916
Commit: 6e7afc10170d711659cbbf0dc25e81f457bda409
https://github.com/llvm/llvm-project/commit/6e7afc10170d711659cbbf0dc25e81f457bda409
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt-c/Logging.h
Log Message:
-----------
[orc-rt] Remove doxygen comments from logging implemenetation APIs (#209086)
These APIs are intended for internal consumption by the ORC runtime's
logging system: plain comments are more appropriate here than doxygen
comments.
Commit: 2bcb848904ae3a2bd7bd3bfb8a8f562529ccb318
https://github.com/llvm/llvm-project/commit/2bcb848904ae3a2bd7bd3bfb8a8f562529ccb318
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt-c/Logging.h
Log Message:
-----------
[orc-rt] Require ORC_RT_LOG format strings to be string literals (#209090)
os_log needs the format string as a literal (it builds format metadata
at the call site), while the none and printf backends accept a runtime
const char*. That mismatch let a non-literal format compile on
none/printf and fail only on an os_log build. Enforce the literal
requirement uniformly in the ORC_RT_LOG macro via an unevaluated
sizeof("" ...) check, so it is caught at the call site on every backend.
Commit: a0f98011c4a82aab540fe9efa68aafb251a3b1b7
https://github.com/llvm/llvm-project/commit/a0f98011c4a82aab540fe9efa68aafb251a3b1b7
Author: Sam Elliott <aelliott at qti.qualcomm.com>
Date: 2026-07-12 (Sun, 12 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVMacroFusion.td
M llvm/test/CodeGen/RISCV/features-info.ll
A llvm/test/CodeGen/RISCV/xqci-macro-fusions.mir
Log Message:
-----------
[RISCV] Fuse QC_E_LI to Loads/Store (#208134)
The QC Access relocations require the `qc.e.li` to be adjacent to its
load/store. This ensures that happens, and allows more relaxation
opportunities.
Commit: fb8c7da5b86b9911e1ae677e147bead6e9b115b8
https://github.com/llvm/llvm-project/commit/fb8c7da5b86b9911e1ae677e147bead6e9b115b8
Author: Matthias Wippich <mfwippich at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/include/clang/Basic/IdentifierTable.h
M clang/include/clang/Basic/TokenKinds.h
Log Message:
-----------
[clang][NFC] move TokenKey to TokenKinds.h (#208867)
This patch moves the `TokenKey` enum closer to where it's actually used.
This is in preparation to generate it from tablegen once the definition
has been moved.
Commit: ca970f3bb3ce41365dfc85049db44489c88cb0a5
https://github.com/llvm/llvm-project/commit/ca970f3bb3ce41365dfc85049db44489c88cb0a5
Author: Luke Lau <luke at igalia.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/test/Transforms/LoopVectorize/simplify-reverse-reverse.ll
Log Message:
-----------
[VPlan] Simplify reverses through unary ops (fneg) (#208257)
By marking fneg as elementwise
Commit: f97cdc4aaad6990f6c9adfad50f67acf9c5349ac
https://github.com/llvm/llvm-project/commit/f97cdc4aaad6990f6c9adfad50f67acf9c5349ac
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPC.td
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll
Log Message:
-----------
[PowerPC] Specify inlining behavior in TableGen (#206938)
Remove the custom areInlineCompatible() implementation and specify the
inlining behavior in TableGen instead.
I've tried to classify these to the best of my ability. Most features
stay at InlineDefault with the usual "caller can have more features than
callee" semantics. Tuning features are InlineIgnore. This includes all
the directive features, which, as far as I can tell, are only used for
tuning heuristics.
I also marked a few InlineMustMatch/InlineInverse, though I'm not
particularly confident on which ones are required to match.
Commit: 2119e359b1f968da94ff27a4078d569e18903aef
https://github.com/llvm/llvm-project/commit/2119e359b1f968da94ff27a4078d569e18903aef
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lld/ELF/LinkerScript.cpp
A lld/test/ELF/gnu-build-attributes.s
Log Message:
-----------
[lld][ELF] Concatenate .gnu.build.attributes.* sections (#208737)
ld.bfd/ld.gold have been concatenating the GNU build attribute sections
since 2018:
https://gitlab.com/gnutools/binutils-gdb/-/commit/7d8a31665739412395f6dd370d2279acd322e78e
Do the same in LLD. These do not have a dedicated section type or flags,
so this is handled by the name-based logic. (Peculiarly, there used to
be SHF_GNU_BUILD_NOTE, but it was removed again.)
Not concatenating these results in a huge number of sections, which
breaks tools like `file`.
Commit: 56e62e539eb65ebe4ec9fc6de0328fea21ae86fd
https://github.com/llvm/llvm-project/commit/56e62e539eb65ebe4ec9fc6de0328fea21ae86fd
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
M llvm/test/CodeGen/WebAssembly/simd-arith.ll
M llvm/test/CodeGen/WebAssembly/simd-relaxed-fmax.ll
M llvm/test/CodeGen/WebAssembly/simd-relaxed-fmin.ll
M llvm/test/CodeGen/WebAssembly/vector-reduce.ll
Log Message:
-----------
[WebAssembly] Use generic pseudo_fmin/pseudo_fmax opcodes (#208454)
The pmin/pmax instructions are equivalent to these with operands
swapped.
The existing matching code for these instructions was incorrect, because
it failed to handle signed zeros and NaNs properly. You can't treat
strict and non-strict comparisons the same in this context.
Commit: 32f3f9dfce7ba9042ebfe7b42e72139454d29672
https://github.com/llvm/llvm-project/commit/32f3f9dfce7ba9042ebfe7b42e72139454d29672
Author: ayrai-gb <ayrai at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/X86/propagate_ir_flags.ll
Log Message:
-----------
[SLP][NFC] Pre-commit tests for select IR-flag/metadata propagation (#208150)
Pre-commits regression tests for an upcoming SLPVectorizer fix (see
#207982). These IR shapes are currently vectorized by SLP, and the
vectorization is functionally correct but when a bundle of
scalar`select` instructions is vectorized, the resulting vector `select`
drops the fast-math flags (and other IR flags/metadata such as
`!unpredictable`) that were common to every scalar lane.
This NFC patch records the current (buggy) behavior so that the
follow-up fix's diff is limited to the behavioural change: `select_nnan`
currently loses `nnan` on the vectorized select, while
`select_not_all_nnan` (one lane missing `nnan`) correctly has none.
Co-authored-by: Ayush Rai <Ayush.Rai at amd.com>
Commit: 2de67c330a9739e559f88de9874d4cba3ffc50ca
https://github.com/llvm/llvm-project/commit/2de67c330a9739e559f88de9874d4cba3ffc50ca
Author: David Green <david.green at arm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
M llvm/test/CodeGen/AArch64/peephole-insert-subreg.mir
M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
Log Message:
-----------
[AArch64] Clear kill flags from visitINSvi64lane (#209096)
If we replace a reg, we can have more uses meaning the kill flags are no
longer
valid. Make sure we remove them in case.
Commit: f48baca733790625d08b7bbfb64ada65516c06f3
https://github.com/llvm/llvm-project/commit/f48baca733790625d08b7bbfb64ada65516c06f3
Author: Alon Filler <alonfiller at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lld/docs/NewLLD.rst
Log Message:
-----------
[Docs][NFC] Fix a few typos in NewLLD.rst (#193569)
Commit: c47d1cf955f607fea1d089b9e05aedf8867231ff
https://github.com/llvm/llvm-project/commit/c47d1cf955f607fea1d089b9e05aedf8867231ff
Author: jeanPerier <jperier at nvidia.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIRTypes.td
M flang/lib/Optimizer/Dialect/FIRType.cpp
A flang/test/Fir/derived-type-aliases.fir
Log Message:
-----------
[flang][FIR] implement asm alias interface for fir.type under option (#208665)
FIR is extremely verbose with derived types because the type lists all
the component names and types, so in case of nested derived type, the
type length in the assembly may grow over thousands of characters.
This patch implements the `getAlias` that allows using the fir.type name
as the MLIR type alias. This significantly reduce the IR size in
application with derived type.
I am planning to enable this by default, but there will be some churn in
the lit test, so I am first adding it under a developer option.
Assisted-by: Cursor
Commit: 3a61e727bc056024bdf4960e914ec6651fd41a72
https://github.com/llvm/llvm-project/commit/3a61e727bc056024bdf4960e914ec6651fd41a72
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
M llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
M llvm/test/CodeGen/ARM/estimate-size-copy.mir
Log Message:
-----------
[ARM][Thumb1] Improve EstimateFunctionSizeInBytes accuracy (#203318)
The estimate of a function size now includes (what I hope are) upper
bounds on the size of the prologue and epilogue; adds size estimates for
some pseudo-instructions that were previously counted as 0; and
increases the estimates for things that were previously optimistic, such
as assuming no constant pool entry ever needs to be duplicated. The
estimation function is also passed extra information to use for
adjusting its estimates, such as the BigFrameOffsets flag which makes
some pseudos have much longer expansions.
Background:
EstimateFunctionSizeInBytes is supposed to estimate how large a Thumb1
function will end up, in advance of actually doing the full code
generation. It must overestimate rather than underestimating, because
large functions need a special precaution (namely, making sure LR is
stacked, so that BL can be used for an intra-function long branch). In
multiple cases recently it has underestimated, leading to a crash later
in code generation, when ARMConstantIslandsPass needs to insert an
intra-function BL and finds that it isn't safe to corrupt LR.
Discussion on Discourse suggested that it's OK to overestimate by quite
a large factor, because any significantly large function won't be badly
impacted by a push of LR that turns out to be unnecessary. The main
place where we want to leave out those unnecessary pushes is _really_
small leaf functions, where the extra push and pop might be a
significant fraction of the whole call.
Commit: 1651159f32cfcf82ecbb364dbf879e97b53d8060
https://github.com/llvm/llvm-project/commit/1651159f32cfcf82ecbb364dbf879e97b53d8060
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M mlir/tools/mlir-irdl-to-cpp/CMakeLists.txt
M mlir/tools/mlir-src-sharder/CMakeLists.txt
Log Message:
-----------
[MLIR] Install missing standalone helper tools (#205066)
Standalone MLIR installs CMake package files that can reference helper
executables needed by downstream builds. Most helper tools already have
install paths available through existing LLVM tool and utility install
options, but `mlir-src-sharder` does not pass an install destination to
`add_tablegen` and `mlir-irdl-to-cpp` does not define an install rule.
Install those two missing helpers.
Co-authored-by: Luca Fancellu <luca.fancellu at arm.com>
Commit: 6e8a4ce8343f2d489f5ecdca5cd443a584f77e71
https://github.com/llvm/llvm-project/commit/6e8a4ce8343f2d489f5ecdca5cd443a584f77e71
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lldb/docs/resources/build.md
Log Message:
-----------
[lldb][docs] Make it clear that we require SWIG >= 4 (#208687)
We said this in "Preliminaries", but later had a note about SWIG < 4. So
if you hadn't read
the first part properly, it looked like we allow < 4.
We do not, so I've removed the note about < 4 and
added SWIG to the "Optional Dependencies" table
for extra emphasis.
Commit: cec7cf4c3dd71068495245111553e4fba3d35c5e
https://github.com/llvm/llvm-project/commit/cec7cf4c3dd71068495245111553e4fba3d35c5e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll
M llvm/test/CodeGen/AMDGPU/bug-multi-operands-to-update-after-fold.mir
M llvm/test/CodeGen/AMDGPU/bug-pk-f32-imm-fold.mir
M llvm/test/CodeGen/AMDGPU/bug-sdag-emitcopyfromreg.ll
M llvm/test/CodeGen/AMDGPU/bug-sdag-scheduler-cycle.ll
M llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir
M llvm/test/CodeGen/AMDGPU/bug-v4f64-subvector.ll
M llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll
M llvm/test/CodeGen/AMDGPU/build-vector-insert-elt-infloop.ll
M llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
M llvm/test/CodeGen/AMDGPU/build_vector.gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/bundle-breaks-phy-liveness.mir
M llvm/test/CodeGen/AMDGPU/bundle-latency.mir
M llvm/test/CodeGen/AMDGPU/bypass-div.ll
M llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg-bfloat.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-c-function.ll
M llvm/test/CodeGen/AMDGPU/call-defs-mode-register.ll
M llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
M llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
M llvm/test/CodeGen/AMDGPU/call-return-types.ll
M llvm/test/CodeGen/AMDGPU/call-skip.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/call-waw-waitcnt.mir
M llvm/test/CodeGen/AMDGPU/callbr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/callbr.ll
M llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-entry.ll
M llvm/test/CodeGen/AMDGPU/cc-inreg-sgpr0-3-mismatch.ll
M llvm/test/CodeGen/AMDGPU/cc-sgpr-limit.ll
M llvm/test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-smem.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll
M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/chain-node-divergence-update-crash-issue-173885.ll
M llvm/test/CodeGen/AMDGPU/change-scc-to-vcc.mir
M llvm/test/CodeGen/AMDGPU/check-subtarget-features.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/clmul.ll
M llvm/test/CodeGen/AMDGPU/cluster-dims.ll
M llvm/test/CodeGen/AMDGPU/cluster-flat-loads-postra.mir
M llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/cmp_shrink.mir
M llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
M llvm/test/CodeGen/AMDGPU/coalesce-identity-copies-undef-subregs.mir
M llvm/test/CodeGen/AMDGPU/coalesce-into-dead-subreg-copies.mir
M llvm/test/CodeGen/AMDGPU/coalesce-liveout-undef-copy.mir
M llvm/test/CodeGen/AMDGPU/coalesce-vgpr-alignment.ll
M llvm/test/CodeGen/AMDGPU/coalescer-avoid-coalesce-class-with-no-registers.ll
M llvm/test/CodeGen/AMDGPU/coalescer-avoid-coalesce-class-with-no-registers.mir
M llvm/test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir
M llvm/test/CodeGen/AMDGPU/coalescer-remat-dead-use.mir
M llvm/test/CodeGen/AMDGPU/coalescer-removepartial-extend-undef-subrange.mir
M llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir
M llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir
M llvm/test/CodeGen/AMDGPU/coalescer-subranges-prune-kill-copy.mir
M llvm/test/CodeGen/AMDGPU/coalescer-undef-subreg-use-invalid-lanemask.mir
M llvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir
M llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll
M llvm/test/CodeGen/AMDGPU/coalescing-subreg-was-undef-but-became-def.mir
M llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir
M llvm/test/CodeGen/AMDGPU/coalescing_makes_lanes_undef.mir
M llvm/test/CodeGen/AMDGPU/code-object-v3.ll
M llvm/test/CodeGen/AMDGPU/code-size-estimate-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
M llvm/test/CodeGen/AMDGPU/code-size-estimate.mir
M llvm/test/CodeGen/AMDGPU/codegen-internal-only-func.ll
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrmode-sext.ll
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null-vector.ll
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
M llvm/test/CodeGen/AMDGPU/coexec-rewrite-mfma.ll
M llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
M llvm/test/CodeGen/AMDGPU/coexec-sched-flavor-classification.mir
M llvm/test/CodeGen/AMDGPU/coexec-sched-warning.mir
M llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll
M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps_nnan.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (9) (#208893)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 6e42e25efa9856d360fb38ef3a6e7a7c3334dd33
https://github.com/llvm/llvm-project/commit/6e42e25efa9856d360fb38ef3a6e7a7c3334dd33
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/combine-ftrunc.ll
M llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll
M llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll
M llvm/test/CodeGen/AMDGPU/commute-frame-index-operand.mir
M llvm/test/CodeGen/AMDGPU/commute-op-sel.mir
M llvm/test/CodeGen/AMDGPU/commute-shifts.ll
M llvm/test/CodeGen/AMDGPU/commute-vop3.mir
M llvm/test/CodeGen/AMDGPU/compute-known-bits-nofpclass.ll
M llvm/test/CodeGen/AMDGPU/computeKnownBits-scalar-to-vector-crash.ll
M llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll
M llvm/test/CodeGen/AMDGPU/concat_vectors.ll
M llvm/test/CodeGen/AMDGPU/consecutive-loads-in-branch.ll
M llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
M llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
M llvm/test/CodeGen/AMDGPU/constant-fold-mi-operands.ll
M llvm/test/CodeGen/AMDGPU/constrained-shift.ll
M llvm/test/CodeGen/AMDGPU/convergence-laneops.ll
M llvm/test/CodeGen/AMDGPU/convergence-tokens.ll
M llvm/test/CodeGen/AMDGPU/copy-hoist-no-spills.ll
M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir
M llvm/test/CodeGen/AMDGPU/copy-overlap-vgpr-kill.mir
M llvm/test/CodeGen/AMDGPU/copy-phys-reg-implicit-operand-kills-subregs.mir
M llvm/test/CodeGen/AMDGPU/copy-to-reg-frameindex.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg.ll
M llvm/test/CodeGen/AMDGPU/copy-vgpr-clobber-spill-vgpr.mir
M llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir
M llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
M llvm/test/CodeGen/AMDGPU/copysign-simplify-demanded-bits.ll
M llvm/test/CodeGen/AMDGPU/copysign-to-disjoint-or-combine.ll
M llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/cse-convergent.ll
M llvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll
M llvm/test/CodeGen/AMDGPU/csr-gfx10.ll
M llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir
M llvm/test/CodeGen/AMDGPU/ctls.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/ctpop.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/cube.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/cvt_flr_i32_f32.ll
M llvm/test/CodeGen/AMDGPU/cvt_rpi_i32_f32.ll
M llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence.ll
M llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-mullohi.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-multi-memop.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-select.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-v1i8-extractvecelt-crash.ll
M llvm/test/CodeGen/AMDGPU/dbg-info-inline-at.ll
M llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir
M llvm/test/CodeGen/AMDGPU/dbg-value-starts-sched-region.mir
M llvm/test/CodeGen/AMDGPU/dead-frame-index-dbg-value.ll
M llvm/test/CodeGen/AMDGPU/dead-lane.mir
M llvm/test/CodeGen/AMDGPU/dead-machine-elim-after-dead-lane.ll
M llvm/test/CodeGen/AMDGPU/dead_bundle.mir
M llvm/test/CodeGen/AMDGPU/dead_copy.mir
M llvm/test/CodeGen/AMDGPU/debug-frame.ll
M llvm/test/CodeGen/AMDGPU/debug-independence-dead-mi-elimination.mir
M llvm/test/CodeGen/AMDGPU/debug-independence-exec-masking.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir
M llvm/test/CodeGen/AMDGPU/debug.ll
M llvm/test/CodeGen/AMDGPU/default-flat-work-group-size-overrides-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/direct-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/disable_form_clauses.ll
M llvm/test/CodeGen/AMDGPU/div-rem-by-constant-64.ll
M llvm/test/CodeGen/AMDGPU/div-rem-fast-path.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/diverge-extra-formal-args.ll
M llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll
M llvm/test/CodeGen/AMDGPU/diverge-switch-default.ll
M llvm/test/CodeGen/AMDGPU/divergence-at-use.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-negsubinlineconst.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-xnor.ll
M llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
M llvm/test/CodeGen/AMDGPU/divrem24-assume.ll
M llvm/test/CodeGen/AMDGPU/do-not-fold-copy.mir
M llvm/test/CodeGen/AMDGPU/dpp_combine-true16.mir
M llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
M llvm/test/CodeGen/AMDGPU/dpp_combine_gfx1250.mir
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (10) (#208894)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 9e8b030aa80b78abaa054b5f75c36f51d1995088
https://github.com/llvm/llvm-project/commit/9e8b030aa80b78abaa054b5f75c36f51d1995088
Author: Hugo Trachino <hugo.trachino at huawei.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/test/Dialect/Linalg/flatten-elementwise.mlir
M mlir/test/Dialect/Linalg/flatten-unsupported.mlir
Log Message:
-----------
[MLIR][Linalg] Fix FlattenElementwiseOp on broadcasted linalgs (#207005)
Applying FlattenElementwiseLinalgOp on Broadcasted linalg would break.
This transformation is not valid for those usecase, so I added a
condition to exit gracefully instead.
Commit: abd72b0eb7807a98c261a6cac35a969f954a76cd
https://github.com/llvm/llvm-project/commit/abd72b0eb7807a98c261a6cac35a969f954a76cd
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
A offload/test/offloading/fortran/target-teams-if-runtime-init.f90
M openmp/device/src/Kernel.cpp
Log Message:
-----------
[OpenMP] Publish target-init team state with acq_rel barrier (#208701)
In __kmpc_target_init, thread 0 initializes the team state in LDS
(HasThreadState = 0, ThreadStates = nullptr) and then releases the other
threads with synchronize::threadsAligned(atomic::relaxed). Because the
relaxed ordering emits no memory fence, the initializing LDS stores are
not guaranteed to be visible to the worker threads before they proceed.
A worker thread can then read the uninitialized team state and produce
wrong results or crash. This is the flow that causes the race as I
understand it.
```
__kmpc_target_init (Kernel.cpp:107)
-> initializeRuntime (Kernel.cpp:38)
-> state::init (State.cpp:286)
-> TeamState.init(IsSPMD) (State.cpp:295)
-> HasThreadState = false (State.cpp:248) // <-- the value later read stale
ThreadStates = nullptr (State.cpp:296)
-> synchronize::threadsAligned(atomic::relaxed) (Kernel.cpp:115) // <-- insufficient barrier:
// relaxed emits no fence, so the state stores above are not published to the other threads
... worker threads continue past the barrier ...
__kmpc_parallel_60 (Parallelism.cpp:143)
if (OMP_UNLIKELY(!if_expr || state::HasThreadState || ...)) (Parallelism.cpp:158)
^ reads HasThreadState from LDS; a stale/unpublished value (!= 0)
diverts the worker onto the wrong (serialized) path
```
The fix changes the barrier at Kernel.cpp:115 from atomic::relaxed to
atomic::acq_rel so that the memory fences are emitted.
Reproducing the problem requires an `if` clause with a non-constant
condition on the target region. The worker's read of HasThreadState
originates from the serialized-region check in __kmpc_parallel_60. When
the `if` condition is constant (or absent), the optimizer can prove that
branch is dead and eliminates the HasThreadState load entirely, so the
race has nothing to observe. A non-constant `if` keeps if_expr, and
hence the LDS read alive, exposing the problem.
I have added a Fortran offload regression test that launches a target
region many times to make the timing-dependent race likely to surface.
Fixes https://github.com/llvm/llvm-project/issues/208698.
Assisted-by: Cursor
Commit: 3de2e4a3f11390db0c026f54edf86bd8f6997947
https://github.com/llvm/llvm-project/commit/3de2e4a3f11390db0c026f54edf86bd8f6997947
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/literals.cpp
Log Message:
-----------
[clang][bytecode] diagnose reads from non-constant local variables... (#208990)
... if we're in the bottom frame.
Commit: 13dbff365eabc45fcc26a36ef077f52b6e168347
https://github.com/llvm/llvm-project/commit/13dbff365eabc45fcc26a36ef077f52b6e168347
Author: ShashwathiNavada <shashwathinavada at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
A flang/test/Lower/OpenMP/unroll-partial01.f90
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/test/Dialect/OpenMP/cli-unroll-partial.mlir
M mlir/test/Dialect/OpenMP/invalid.mlir
A mlir/test/Target/LLVMIR/openmp-unroll-partial01.mlir
A mlir/test/Target/LLVMIR/openmp-unroll-partial02.mlir
Log Message:
-----------
[Flang][Openmp] Implement support for partial in unroll construct (#206642)
As described in section 9.2.2 of openmp 5.2 spec, the patch implements
support for partial in unroll construct.
Commit: e3e15695a0e9b1acd3a4821cdeea353ce951f5da
https://github.com/llvm/llvm-project/commit/e3e15695a0e9b1acd3a4821cdeea353ce951f5da
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/dpp64_combine.ll
M llvm/test/CodeGen/AMDGPU/dpp64_combine.mir
M llvm/test/CodeGen/AMDGPU/dpp_combine.ll
M llvm/test/CodeGen/AMDGPU/dpp_combine.mir
M llvm/test/CodeGen/AMDGPU/drop-mem-operand-move-smrd.ll
M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll
M llvm/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll
M llvm/test/CodeGen/AMDGPU/ds-read2-write2-debug-info.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/ds-vectorization-alignment.ll
M llvm/test/CodeGen/AMDGPU/ds_gws_align.ll
M llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll
M llvm/test/CodeGen/AMDGPU/ds_read2-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/ds_read2_offset_order.ll
M llvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll
M llvm/test/CodeGen/AMDGPU/ds_read2st64.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2_a_v.ll
M llvm/test/CodeGen/AMDGPU/ds_write2st64.ll
M llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
M llvm/test/CodeGen/AMDGPU/dual-source-blend-export.ll
M llvm/test/CodeGen/AMDGPU/dummy-regalloc-priority-advisor.mir
M llvm/test/CodeGen/AMDGPU/dumpcode.ll
M llvm/test/CodeGen/AMDGPU/duplicate-attribute-indirect.ll
M llvm/test/CodeGen/AMDGPU/dvgpr-vgpr-count-propagation-direct-chain.ll
M llvm/test/CodeGen/AMDGPU/dvgpr-vgpr-count-propagation-indirect.ll
M llvm/test/CodeGen/AMDGPU/dvgpr-vgpr-count-propagation.ll
M llvm/test/CodeGen/AMDGPU/dvgpr_sym.ll
M llvm/test/CodeGen/AMDGPU/dvgpr_sym_fail_too_many_block_size_16.ll
M llvm/test/CodeGen/AMDGPU/dvgpr_sym_fail_too_many_block_size_16_anon.ll
M llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
M llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
M llvm/test/CodeGen/AMDGPU/early-if-convert-cost.ll
M llvm/test/CodeGen/AMDGPU/early-if-convert.ll
M llvm/test/CodeGen/AMDGPU/early-inline-alias.ll
M llvm/test/CodeGen/AMDGPU/early-inline.ll
M llvm/test/CodeGen/AMDGPU/early-lis-two-address-partial-def.mir
M llvm/test/CodeGen/AMDGPU/early-tailduplicator-nophis.mir
M llvm/test/CodeGen/AMDGPU/early-tailduplicator-terminator.mir
M llvm/test/CodeGen/AMDGPU/early-term.mir
M llvm/test/CodeGen/AMDGPU/eh_frame.ll
M llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
M llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll
M llvm/test/CodeGen/AMDGPU/elf-header-flags-xnack.ll
M llvm/test/CodeGen/AMDGPU/elf-header-osabi.ll
M llvm/test/CodeGen/AMDGPU/elf-note-null-terminator.ll
M llvm/test/CodeGen/AMDGPU/elf.ll
M llvm/test/CodeGen/AMDGPU/elf.metadata.ll
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-u32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-scc-clobber.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.ll
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir
M llvm/test/CodeGen/AMDGPU/else.ll
M llvm/test/CodeGen/AMDGPU/emit-high-vgprs.mir
M llvm/test/CodeGen/AMDGPU/empty-function.ll
M llvm/test/CodeGen/AMDGPU/empty-text.ll
M llvm/test/CodeGen/AMDGPU/enable-scratch-only-dynamic-stack.ll
M llvm/test/CodeGen/AMDGPU/entry-function-cfi.mir
M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
M llvm/test/CodeGen/AMDGPU/expand-atomicrmw-syncscope.ll
M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
M llvm/test/CodeGen/AMDGPU/expand-si-indirect.mir
M llvm/test/CodeGen/AMDGPU/expand-waitcnt-profiling-no-outstanding.ll
M llvm/test/CodeGen/AMDGPU/expand-waitcnt-profiling.ll
M llvm/test/CodeGen/AMDGPU/expert_scheduling_gfx12.mir
M llvm/test/CodeGen/AMDGPU/expert_scheduling_gfx1250.mir
M llvm/test/CodeGen/AMDGPU/export-cluster-postra.mir
M llvm/test/CodeGen/AMDGPU/extend-bit-ops-i16.ll
M llvm/test/CodeGen/AMDGPU/extend-phi-subrange-not-in-parent.mir
M llvm/test/CodeGen/AMDGPU/extend-wwm-virt-reg-liveness.mir
M llvm/test/CodeGen/AMDGPU/extload-private.ll
M llvm/test/CodeGen/AMDGPU/extload.ll
M llvm/test/CodeGen/AMDGPU/extra-lds-size.ll
M llvm/test/CodeGen/AMDGPU/extra-sroa-after-unroll.ll
M llvm/test/CodeGen/AMDGPU/extract-i8-codegen.ll
M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
M llvm/test/CodeGen/AMDGPU/extract-vector-elt-binop-build-vector.ll
M llvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/fabs-known-signbit-combine-fast-fdiv-lowering.ll
M llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (11) (#208895)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: b4698d8d53e9b228bd84676ae83637b52a30d0e9
https://github.com/llvm/llvm-project/commit/b4698d8d53e9b228bd84676ae83637b52a30d0e9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fadd.ll
M llvm/test/CodeGen/AMDGPU/fadd64.ll
M llvm/test/CodeGen/AMDGPU/fast-ra-kills-vcc.mir
M llvm/test/CodeGen/AMDGPU/fast-regalloc-bundles.mir
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll
M llvm/test/CodeGen/AMDGPU/fastregalloc-illegal-subreg-physreg.mir
M llvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir
M llvm/test/CodeGen/AMDGPU/fastregalloc-sgpr-only.mir
M llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.bf16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fceil.ll
M llvm/test/CodeGen/AMDGPU/fceil64.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcmp64.ll
M llvm/test/CodeGen/AMDGPU/fconst64.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/fdiv-nofpexcept.ll
M llvm/test/CodeGen/AMDGPU/fdiv.bf16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll
M llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll
M llvm/test/CodeGen/AMDGPU/fdot2.ll
M llvm/test/CodeGen/AMDGPU/fence-barrier-latency.ll
M llvm/test/CodeGen/AMDGPU/fence-barrier.ll
M llvm/test/CodeGen/AMDGPU/fence-lds-read2-write2.ll
M llvm/test/CodeGen/AMDGPU/ffloor.f64.ll
M llvm/test/CodeGen/AMDGPU/ffloor.ll
M llvm/test/CodeGen/AMDGPU/finalizebundle.mir
M llvm/test/CodeGen/AMDGPU/fix-crash-valu-hazard.ll
M llvm/test/CodeGen/AMDGPU/fix-frame-ptr-reg-copy-livein.ll
M llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-fake16.mir
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-gfx12-fake16.mir
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-gfx12-true16.mir
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16.mir
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-nondeterminism.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-phi-block-end-iterator-debugloc.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-phi-regression-av-classes.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-phi-regression-issue130646-issue130119.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-phi-regression-issue130646.mir
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-readfirstlane-av-register-regression.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-sgpr32-to-vgpr16.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-vgpr16-to-spgr32.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-wmma-scale-lo256.mir
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-wwm.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-wwm.mir
M llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/flat-address-space.ll
M llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-error-unsupported-gpu-hsa.ll
M llvm/test/CodeGen/AMDGPU/flat-for-global-subtarget-feature.ll
M llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir
M llvm/test/CodeGen/AMDGPU/flat-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/flat-offset-bug.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-alloca-issue-155902.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi-gfx1250.mir
M llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi.mir
M llvm/test/CodeGen/AMDGPU/flat-scratch-i8-i16.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/float-sopc-vopc.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp.ll
M llvm/test/CodeGen/AMDGPU/fma-combine.ll
M llvm/test/CodeGen/AMDGPU/fma-mix.gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fma.f64.ll
M llvm/test/CodeGen/AMDGPU/fma.ll
M llvm/test/CodeGen/AMDGPU/fmac.sdwa.ll
M llvm/test/CodeGen/AMDGPU/fmad-formation-fmul-distribute-denormal-mode.ll
M llvm/test/CodeGen/AMDGPU/fmamk_fmaak-t16.mir
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (12) (#208896)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: b5e94d5ffca8fe3d7b063af48d9535d7b13af66a
https://github.com/llvm/llvm-project/commit/b5e94d5ffca8fe3d7b063af48d9535d7b13af66a
Author: Jean-Didier PAILLEUX <jean-didier.pailleux at sipearl.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/Builder/MIFCommon.h
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/Builder/MIFCommon.cpp
M flang/lib/Optimizer/Dialect/MIF/MIFOps.cpp
M flang/lib/Optimizer/Transforms/MIFOpConversion.cpp
M flang/test/Lower/MIF/image_index.f90
Log Message:
-----------
[flang][MIF] Fix lowering sub argument in IMAGE_INDEX #208318 (#208544)
This PR fixes issue #208318, which did not correctly prepare the SUB
argument for IMAGE_INDEX in the correct type.
Commit: d097c2b764460284b186636b547573d309eaba8d
https://github.com/llvm/llvm-project/commit/d097c2b764460284b186636b547573d309eaba8d
Author: disservin <disservin.social at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/IR/Verifier.cpp
Log Message:
-----------
[IR][NFC] Add parentheses around logical AND (#208512)
Fixes a `-Wparentheses` warning about unclear priority of operators.
Commit: d62c903ffd049da2a80acc7f0c0671447adc76f7
https://github.com/llvm/llvm-project/commit/d62c903ffd049da2a80acc7f0c0671447adc76f7
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M libcxx/test/benchmarks/containers/string.bench.cpp
Log Message:
-----------
[libc++] Refactor the string benchmarks (#185397)
Fixes #179696
Commit: 95f1eab03f35545eb308246376541a7150a7a4e4
https://github.com/llvm/llvm-project/commit/95f1eab03f35545eb308246376541a7150a7a4e4
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/test/CodeGen/RISCV/double-previous-failure.ll
A llvm/test/CodeGen/RISCV/jump-cond-merging-optsize.ll
M llvm/test/CodeGen/RISCV/jump-is-expensive.ll
M llvm/test/CodeGen/RISCV/or-is-add.ll
M llvm/test/CodeGen/RISCV/rvv/pr93587.ll
M llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll
M llvm/test/CodeGen/RISCV/select-and.ll
M llvm/test/CodeGen/RISCV/select-or.ll
M llvm/test/CodeGen/RISCV/setcc-logic.ll
Log Message:
-----------
[RISCV] Add getJumpConditionMergingParams to support branch condition merging (#206897)
Override `getJumpConditionMergingParams` so that
`shouldKeepJumpConditionsTogether`
can decide whether to keep `br (and/or cond1, cond2)` merged into a
single
branch or split it into two branches, based on a configurable cost
threshold.
Previously RISC-V used the default cost `{-1, -1, -1}`, which always
split
the conditions. Now it returns a base cost calculated from
`MispredictPenalty`
(via scaling it down by an assumed misprediction rate 25%).
These values are controllable via
`riscv-br-merging-base-cost/-likely-bias/-unlikely-bias`.
This is another approach to #191158 when `TuneJumpIsExpensive` is not
set.
Commit: f8b07132c195ce2823f6a54cd978301af8c6d551
https://github.com/llvm/llvm-project/commit/f8b07132c195ce2823f6a54cd978301af8c6d551
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
Log Message:
-----------
[NFC][SPIR-V] Add emitSimpleExecutionMode helper to dedup single imm OpExecutionMode emission (#208674)
Commit: d0ac84b54b90c03f0ba54b7f1b75b43941d7a6b1
https://github.com/llvm/llvm-project/commit/d0ac84b54b90c03f0ba54b7f1b75b43941d7a6b1
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lldb/test/API/functionalities/gdb_remote_client/TestXMLRegisterFlags.py
Log Message:
-----------
[lldb][test] Fix XML register info test (#209124)
Missed by #208838, which is a follow up to #188049 which changed the
alignment rules.
Some of these tests have incorrect outputs now
and I will fix that later. For now at least
they pass again.
XML related tests are not being run in CI,
which I will also address later.
Commit: dc8ee15f2bbc5b18316f071c5ae746bd95609ade
https://github.com/llvm/llvm-project/commit/dc8ee15f2bbc5b18316f071c5ae746bd95609ade
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
M mlir/test/Conversion/SPIRVToLLVM/arithmetic-ops-to-llvm.mlir
Log Message:
-----------
[mlir][SPIR-V] Add SPIRVToLLVM conversion for SNegate (#206950)
Commit: 19f997320131c3d01e8ee32e1f22ee98a1ee0ec7
https://github.com/llvm/llvm-project/commit/19f997320131c3d01e8ee32e1f22ee98a1ee0ec7
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
Log Message:
-----------
[NFC][SPIR-V] Remove unused LowLevelType parameter from buildLoadInst (#208428)
Commit: 717615829bba4035897a4ebdbdef919f31529762
https://github.com/llvm/llvm-project/commit/717615829bba4035897a4ebdbdef919f31529762
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/typeid.cpp
Log Message:
-----------
[clang][bytecode] Improve diagnostics on typeid field access (#209101)
Do some extra work to extract the requested field name.
Commit: da138053e78c5af7b83f49674b4e190e1803102d
https://github.com/llvm/llvm-project/commit/da138053e78c5af7b83f49674b4e190e1803102d
Author: Ayokunle Amodu <ayokunle321 at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
A clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx1250.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-vi-f16.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
Log Message:
-----------
[CIR][AMDGPU] Add support for AMDGCN rcp builtins (#197447)
Adds codegen for the following AMDGCN reciprocal builtins:
- __builtin_amdgcn_rcp (double)
- __builtin_amdgcn_rcpf (float)
- __builtin_amdgcn_rcph (half)
- __builtin_amdgcn_rcp_bf16 (bfloat16)
These are lowered to the corresponding `llvm.amdgcn.rcp` intrinsic.
Commit: a0df86deb4295ff9ebebe54eb515bc49a7fb65f8
https://github.com/llvm/llvm-project/commit/a0df86deb4295ff9ebebe54eb515bc49a7fb65f8
Author: Mark Zhuang <mark.zhuang at spacemit.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVProcessors.td
Log Message:
-----------
[RISCV] Add TuneNoDefaultUnroll to spacemit-x100 (#209069)
In the spec2k6int tests, some subtests improved while others
regressed. The overall score shows a 0.7% gain. Given that
most OoO CPUs enable this feature by default, also enable
it by default for X100.
Commit: cb71fefb2258fdd00747043a9c322f95d684b000
https://github.com/llvm/llvm-project/commit/cb71fefb2258fdd00747043a9c322f95d684b000
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/divs-with-scalable-vfs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fold-tail-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-no-dotprod.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-multiexit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-runtime-check-size-based-threshold.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-too-many-deps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-counting-down.ll
M llvm/test/Transforms/LoopVectorize/RISCV/conditional-scalar-assignment.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dbg-tail-folding-by-evl.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/early-exit-live-out.ll
M llvm/test/Transforms/LoopVectorize/RISCV/fminimumnum.ll
M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-masked-access.ll
M llvm/test/Transforms/LoopVectorize/RISCV/iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-bin-unary-ops-args.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-div.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-iv32.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-masked-loadstore.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-safe-dep-distance.ll
M llvm/test/Transforms/LoopVectorize/RISCV/transform-narrow-interleave-to-widen-memory.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
M llvm/test/Transforms/LoopVectorize/X86/pr35432.ll
M llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
M llvm/test/Transforms/LoopVectorize/cast-induction.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
M llvm/test/Transforms/LoopVectorize/find-last.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/induction-ptrcasts.ll
M llvm/test/Transforms/LoopVectorize/invalidate-scev-at-scope-after-vectorization.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-align.ll
M llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
M llvm/test/Transforms/LoopVectorize/pr125278.ll
M llvm/test/Transforms/LoopVectorize/pr37248.ll
M llvm/test/Transforms/LoopVectorize/pr38697.ll
M llvm/test/Transforms/LoopVectorize/reduction-small-size.ll
M llvm/test/Transforms/LoopVectorize/replace-first-order-recurrence-by-versioned-iv.ll
M llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll
M llvm/test/Transforms/LoopVectorize/scev-exit-phi-invalidation.ll
M llvm/test/Transforms/LoopVectorize/scev-predicate-reasoning.ll
M llvm/test/Transforms/LoopVectorize/trip-count-expansion-may-introduce-ub.ll
M llvm/test/Transforms/LoopVectorize/vplan-native-path-inner-loop-with-runtime-checks.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/indvars-vectorization.ll
Log Message:
-----------
[VPlan] Expand SCEV min/max via scalar intrinsic VPInstructions. (#207842)
Use the VPInstruction::Intrinsic opcode to expand min/max SCEV
expressions to LLVM min/max intrinsics as VPInstructions.
The operands are chained in reverse order, matching SCEVExpander's
expansion of min/max expressions.
This helps to clean up another set of duplicated vscale calls.
Depends on https://github.com/llvm/llvm-project/pull/207541
Depends on https://github.com/llvm/llvm-project/pull/207836
PR: https://github.com/llvm/llvm-project/pull/207842
Commit: 6461bd3749dc09698b76c3349e7b4befab7f7f9b
https://github.com/llvm/llvm-project/commit/6461bd3749dc09698b76c3349e7b4befab7f7f9b
Author: Le Gia Bao <legiabao7300 at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M polly/lib/Support/ScopHelper.cpp
A polly/test/CodeGen/issue205137.ll
Log Message:
-----------
[Polly] Fix infinite recursion in `ScopExpander::visitAddRecExpr` (#206063)
visitUnknown follow VMap, call GenSE.getSCEV() on the mapped value, and
get back the original AddRec, recursing visitAddRecExpr infinitely.
Insert the result into SCEVCache before calling visit() to cut
recursion.
Fixes #205137.
Commit: 5db1f5442ef0c9bcb2f4ca362361daaf2a76acfb
https://github.com/llvm/llvm-project/commit/5db1f5442ef0c9bcb2f4ca362361daaf2a76acfb
Author: maflcko <6399679+maflcko at users.noreply.github.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
A compiler-rt/test/ubsan/TestCases/Integer/Inputs/make_signed.h
A compiler-rt/test/ubsan/TestCases/Integer/Inputs/wrappers.h
A compiler-rt/test/ubsan/TestCases/Integer/suppressions-nested-calls.c
Log Message:
-----------
compiler-rt: ubsan: Add suppressions test for nested functions (#206962)
This is a test-only change to increase the test coverage of UBSan to
clarify that named suppressions only apply to the function itself and do
not cover (possibly inlined) called functions.
The background is that, while trying to fix
https://github.com/llvm/llvm-project/issues/132533, I discovered missing
test coverage and possibly confused myself into a wrong fix in
https://github.com/llvm/llvm-project/pull/206735#discussion_r3505816693
So I think it could make sense to add test coverage for the case that I
broke, which serves as a reference baseline ground truth.
---------
Co-authored-by: MarcoFalke <*~=`'#}+{/-|&$^_ at 721217.xyz>
Commit: 6d026ea1d89795532c7ead1e57676bd1d1018afb
https://github.com/llvm/llvm-project/commit/6d026ea1d89795532c7ead1e57676bd1d1018afb
Author: Carl Ritson <carl.ritson at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard-attrs.mir
Log Message:
-----------
[AMDGPU] Remove option to disable SGPR hazard waits (#208720)
This was useful when initially implemented, but probably be removed now.
Commit: 13e9cc22ce4edfd4b1347d6bed9cd95868e2d4f4
https://github.com/llvm/llvm-project/commit/13e9cc22ce4edfd4b1347d6bed9cd95868e2d4f4
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/test/Driver/print-enabled-extensions/riscv-spacemit-a100.c
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Driver/riscv-cpus.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrFormats.td
M llvm/lib/Target/RISCV/RISCVInstrFormatsSpacemitV.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXSpacemiT.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/test/CodeGen/RISCV/features-info.ll
A llvm/test/MC/RISCV/xsmtvdotii-invalid.s
A llvm/test/MC/RISCV/xsmtvdotii-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Support spacemit vsmtvdotii extensions (#202533)
SPEC: https://github.com/spacemit-com/docs-ai/blob/main/en/architecture/ime_extension.md
Commit: 8cb0e63054ce96860b12d68218eb67c97bc6c378
https://github.com/llvm/llvm-project/commit/8cb0e63054ce96860b12d68218eb67c97bc6c378
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/test/MC/AArch64/SME2p3/luti6-diagnostics.s
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
Log Message:
-----------
[AArch64][llvm][tablegen] Restrict luti6 assembly (4 regs, 8-bit) to 0 <= Zn <= 7 (#200751)
The `luti6` instruction (four registers, 8-bit) should only allow
assembly of `0 <= Zn <= 7`, since there's only 3 bits for `Zn`. It
actually allows > 7:
```
luti6 { z0.b - z3.b }, zt0, { z8 - z10 }
```
which produces a duplicate encoding to the following:
```
luti6 { z0.b - z3.b }, zt0, { z0 - z2 }
```
Update tablegen to handle the inferred register-class naming
collision caused by adding the explicit z0-z7 ZPR3 class.
Commit: 3966381ccbd135e34b44a746187ac6c5140df4cd
https://github.com/llvm/llvm-project/commit/3966381ccbd135e34b44a746187ac6c5140df4cd
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lldb/source/Core/DumpRegisterValue.cpp
M lldb/test/API/functionalities/gdb_remote_client/TestXMLRegisterFlags.py
M lldb/test/API/linux/aarch64/permission_overlay/TestAArch64LinuxPOE.py
Log Message:
-----------
[lldb] Correct alignment of register fields (#209140)
In #188049 the alignment of register names for the raw value part "pc =
0x..." changed.
This resulted in many register fields being 2 spaces off where they
should be, because the stream we were printing to had a 2 space indent
set where it had none before.
This is actually a bug in the original field formatting code. It assumed
the stream had no indent level of its own. So the fix is to indent using
the stream (the 2 spaces), then indent to where the register name ends.
Commit: 6c009ff4b39ec2a0233c40c87f8f3709e9dc2eff
https://github.com/llvm/llvm-project/commit/6c009ff4b39ec2a0233c40c87f8f3709e9dc2eff
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
M llvm/test/CodeGen/AMDGPU/fmax3.f64.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.v2f16.ll
M llvm/test/CodeGen/AMDGPU/fmaxnum.f64.ll
M llvm/test/CodeGen/AMDGPU/fmaxnum.ll
M llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
M llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.v2f16.ll
M llvm/test/CodeGen/AMDGPU/fminnum.f64.ll
M llvm/test/CodeGen/AMDGPU/fminnum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fmul.ll
M llvm/test/CodeGen/AMDGPU/fmul64.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f64.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.v2f16.ll
M llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines-gfx1200.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.legal.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.si.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs-v2f32.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg-fold-legalize-dag-increase-insts.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir
M llvm/test/CodeGen/AMDGPU/fold-cndmask-wave32.mir
M llvm/test/CodeGen/AMDGPU/fold-commute-sgpr.mir
M llvm/test/CodeGen/AMDGPU/fold-fabs.ll
M llvm/test/CodeGen/AMDGPU/fold-fmaak-bug.ll
M llvm/test/CodeGen/AMDGPU/fold-freeze-fmul-to-fma.ll
M llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
M llvm/test/CodeGen/AMDGPU/fold-imm-copy-agpr.mir
M llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
M llvm/test/CodeGen/AMDGPU/fold-imm-pk64.mir
M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AMDGPU/fold-literal-multiple-gfx10.mir
M llvm/test/CodeGen/AMDGPU/fold-multiple-commute.mir
M llvm/test/CodeGen/AMDGPU/fold-multiple.mir
M llvm/test/CodeGen/AMDGPU/fold-omod-crash.mir
M llvm/test/CodeGen/AMDGPU/fold-operands-frame-index-agpr.mir
M llvm/test/CodeGen/AMDGPU/fold-operands-frame-index.gfx10.mir
M llvm/test/CodeGen/AMDGPU/fold-operands-frame-index.mir
M llvm/test/CodeGen/AMDGPU/fold-operands-order.mir
M llvm/test/CodeGen/AMDGPU/fold-operands-remove-m0-redef.mir
M llvm/test/CodeGen/AMDGPU/fold-operands-s-add-copy-to-vgpr.mir
M llvm/test/CodeGen/AMDGPU/fold-operands-scalar-fmac.mir
M llvm/test/CodeGen/AMDGPU/fold-reload-into-exec.mir
M llvm/test/CodeGen/AMDGPU/fold-reload-into-m0.mir
M llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir
M llvm/test/CodeGen/AMDGPU/fold-sgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/fold-sgpr-multi-imm.mir
M llvm/test/CodeGen/AMDGPU/fold-short-64-bit-literals.mir
M llvm/test/CodeGen/AMDGPU/fold-vgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/fold-vgpr-phyreg.mir
M llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-clear-kill-flags.mir
M llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-skips-non-reg.mir
M llvm/test/CodeGen/AMDGPU/fold_acc_copy_into_valu.mir
M llvm/test/CodeGen/AMDGPU/folding-of-i32-as-i64.mir
M llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address.ll
M llvm/test/CodeGen/AMDGPU/force-wait-after-always-gds.mir
M llvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx1200.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx950.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.f64.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.f64.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fp_trunc_store_fp32_to_bf16.ll
M llvm/test/CodeGen/AMDGPU/fp_trunc_store_fp64_to_bf16.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (13) (#208897)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: d76f677c075b71e2a5c2ee35539992d753258e2a
https://github.com/llvm/llvm-project/commit/d76f677c075b71e2a5c2ee35539992d753258e2a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-image-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-num-flat-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-num-global-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fpenv.ll
M llvm/test/CodeGen/AMDGPU/fpext-free.ll
M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
M llvm/test/CodeGen/AMDGPU/fpext.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui_uitofp.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
M llvm/test/CodeGen/AMDGPU/fract.f64.ll
M llvm/test/CodeGen/AMDGPU/fract.ll
M llvm/test/CodeGen/AMDGPU/frame-index-elimination-tied-operand.mir
M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
M llvm/test/CodeGen/AMDGPU/frame-index.mir
M llvm/test/CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir
M llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/freeze-binary.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/frexp-constant-fold.ll
M llvm/test/CodeGen/AMDGPU/fshl-scalar-shift-zero.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
M llvm/test/CodeGen/AMDGPU/fsub-as-fneg-src-modifier.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/fsub.ll
M llvm/test/CodeGen/AMDGPU/fsub64.ll
M llvm/test/CodeGen/AMDGPU/ftrunc.f64.ll
M llvm/test/CodeGen/AMDGPU/ftrunc.ll
M llvm/test/CodeGen/AMDGPU/function-alignment.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-args.ll
M llvm/test/CodeGen/AMDGPU/function-call-relocs.ll
M llvm/test/CodeGen/AMDGPU/function-esm2-prologue-epilogue.ll
M llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
M llvm/test/CodeGen/AMDGPU/function-returns.ll
M llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll
M llvm/test/CodeGen/AMDGPU/gcn-reg-pressure-true16-integer-overflow.mir
M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
M llvm/test/CodeGen/AMDGPU/gds-atomic.ll
M llvm/test/CodeGen/AMDGPU/gds-unsupported.ll
M llvm/test/CodeGen/AMDGPU/gep-address-space.ll
M llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
M llvm/test/CodeGen/AMDGPU/gep-flags-stack-offsets.ll
M llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/gfx10-twoaddr-fma.mir
M llvm/test/CodeGen/AMDGPU/gfx10-vop-literal.ll
M llvm/test/CodeGen/AMDGPU/gfx10plus-wavefront-sgpr-count.ll
M llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir
M llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_loads.ll
M llvm/test/CodeGen/AMDGPU/gfx90a-enc.ll
M llvm/test/CodeGen/AMDGPU/gfx942-hazards.mir
M llvm/test/CodeGen/AMDGPU/global-address.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-scan.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global_atomic_optimizer_fp_rtn.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_iterative_scan.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_iterative_scan_fp.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_optimizer_fp_no_rtn.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (14) (#209117)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: b0158bbd4fec69feda78752270573e505d53ddcf
https://github.com/llvm/llvm-project/commit/b0158bbd4fec69feda78752270573e505d53ddcf
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M orc-rt/test/CMakeLists.txt
M orc-rt/test/regression/init.test
M orc-rt/test/regression/lit.cfg.py
M orc-rt/tools/CMakeLists.txt
A orc-rt/tools/ogre/CMakeLists.txt
A orc-rt/tools/ogre/ogre.cpp
R orc-rt/tools/orc-executor/CMakeLists.txt
R orc-rt/tools/orc-executor/orc-executor.cpp
Log Message:
-----------
[orc-rt] Rename orc-executor to ogre (#209143)
The ORC Generic Runtime Environment (OGRE) will serve as our canonical
"blank executor" program: A program that simply listens for an ORC
controller connection, then runs whatever program is provided to it by
the controller.
Commit: 3081049a69f85dd4079a959c4e50c6ccf9f691d0
https://github.com/llvm/llvm-project/commit/3081049a69f85dd4079a959c4e50c6ccf9f691d0
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lldb/include/lldb/Core/Opcode.h
M lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
M lldb/unittests/Disassembler/CMakeLists.txt
A lldb/unittests/Disassembler/x86/TestGetOpcodeOversized.cpp
Log Message:
-----------
[lldb] Don't build an opcode from a failed disassembly (#208279)
lldb does not check if the instruction was decoded correctly. This
causes the following assert to hit:
https://github.com/llvm/llvm-project/blob/06499c927e5012166f4553c58f8af593521ea14d/lldb/include/lldb/Core/Opcode.h#L214
due to a buffer overflow. This happens when starting `lldb-dap` on
Windows with `lldb-server`.
This patch clamps the instruction size to the maximum possible
instruction size possible to avoid the assert to hit. It also adds a
regression test.
Related:
- https://github.com/llvm/llvm-project/pull/208277.
Commit: efd160260d8437710714d8a3ba9301f45d61ee95
https://github.com/llvm/llvm-project/commit/efd160260d8437710714d8a3ba9301f45d61ee95
Author: Aleksandr Popov <42888396+aleks-tmb at users.noreply.github.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/single_early_exit_zext_trip_count.ll
Log Message:
-----------
[SCEV][NFC] Address post-merge comments on precommit test (#209094)
Drop unnecessary atomic/unordered loads, unify block label naming.
Follow-up to b33af86b032e (#208784).
Commit: a5fc1d68f995744af71b91663e9f46910d9345ca
https://github.com/llvm/llvm-project/commit/a5fc1d68f995744af71b91663e9f46910d9345ca
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clang-doc/BUILD.gn
A llvm/utils/gn/secondary/clang-tools-extra/clang-doc/markdown/BUILD.gn
Log Message:
-----------
[gn] port cc048e80b670 more (#209156)
00cd65638a7cf attempted this, but it was incomplete.
Commit: a4364df185433cd37b793aa4ff64cba1c72dcbda
https://github.com/llvm/llvm-project/commit/a4364df185433cd37b793aa4ff64cba1c72dcbda
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/invalid.cpp
Log Message:
-----------
[clang][bytecode] Handle invalid function in CXXInheritedCtorInitExpr (#209138)
Commit: db28e48d67e3b0c44d88be9ea2d28eca2d239a9a
https://github.com/llvm/llvm-project/commit/db28e48d67e3b0c44d88be9ea2d28eca2d239a9a
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Core/RangeConstraintManager.cpp
M clang/test/Analysis/ArrayBound/assumption-reporting.c
M clang/test/Analysis/bitwise-shift-common.c
M clang/test/Analysis/constant-folding.c
M clang/test/Analysis/malloc.c
M clang/test/Analysis/string.c
Log Message:
-----------
[analyzer] Smarter range inference for {+,-,*} (#209048)
SymbolicRangeInferrer previously fell back to the full range of the
result type for BO_Add, BO_Sub and BO_Mul, discarding any constraints
known about the operands.
This caused a false positive in optin.taint.TaintedAlloc: a bounded
tainted value multiplied by a constant
(e.g. `malloc(groups * sizeof(gid_t))` with `groups` bounded) was
treated as unbounded whenever the multiplication was done in a wide
(e.g. 64-bit size_t) type, because the operand's range was lost. A
32-bit multiplication accidentally avoided the warning only because the
narrow result type already bounds the value below SIZE_MAX/4. Fixes
#173113
---
With `inferFromCorners` we compute the smallest and largest possible
outcome of the two range sets for `LHS {+,-,*} RHS`. If fails for some
reason, it falls back to the previous behavior and takes [MIN, MAX] for
type T - the most conservative range.
This patch also covers some pre-existing FIXMEs in the tests. I didn't
evaluate this change - however, I think it's harmless.
Assisted-by: Claude Opus 4.8
Commit: 3ae6937d0491665c2f47505e71e53ce5ef758424
https://github.com/llvm/llvm-project/commit/3ae6937d0491665c2f47505e71e53ce5ef758424
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/Basic/BUILD.gn
Log Message:
-----------
[gn build] Port 1b879464b362 (#209147)
Commit: 7a9bbe00493434ad70bd3de0840c980fd88abde6
https://github.com/llvm/llvm-project/commit/7a9bbe00493434ad70bd3de0840c980fd88abde6
Author: rdevshp <rdevshp at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/BasicValueFactory.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/SMTConstraintManager.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/SMTConv.h
M clang/lib/StaticAnalyzer/Core/BasicValueFactory.cpp
M clang/lib/StaticAnalyzer/Core/Z3CrosscheckVisitor.cpp
A clang/test/Analysis/z3/z3-logicalexpr-eval.c
M clang/test/Analysis/z3/z3-unarysymexpr.c
Log Message:
-----------
[analyzer] Fix unary/binary op support for SMT symbolic execution (#205078)
SMT symbolic execution:
The patch fixes unary op support, converts operands of logical operators
to boolean in getBinExpr, and clears the hasComparison flag in
getSymExpr when a boolean operand is converted to a non-bool integer.
This PR allows C functions like
```
int f(int x, int y) {
if (~(x && y))
return 0;
return 1;
}
```
to be analyzed with `-cc1 -analyze -analyzer-checker=core
-analyzer-constraints=z3`
Fixes #205037.
Assisted-by: Codex
Commit: cc11dd4aa650abce746953c4c243427c2a6d16cc
https://github.com/llvm/llvm-project/commit/cc11dd4aa650abce746953c4c243427c2a6d16cc
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/ScalableStaticAnalysis/Analyses/BUILD.gn
Log Message:
-----------
[gn build] Port 3bc47c8dc927 (#209148)
Commit: fb0563958e113bf9d384284ec2be1a73cfe7ff3e
https://github.com/llvm/llvm-project/commit/fb0563958e113bf9d384284ec2be1a73cfe7ff3e
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Driver/BUILD.gn
Log Message:
-----------
[gn build] Port 640079288c5e (#209149)
Commit: af30b76228e315fac32b8cf0b8282841d839c365
https://github.com/llvm/llvm-project/commit/af30b76228e315fac32b8cf0b8282841d839c365
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/ADT/BUILD.gn
Log Message:
-----------
[gn build] Port 9b9f44d1c55c (#209150)
Commit: ff331ac51c37746f5f3ea9679f791992e3d93918
https://github.com/llvm/llvm-project/commit/ff331ac51c37746f5f3ea9679f791992e3d93918
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/lld/unittests/AsLibELF/BUILD.gn
Log Message:
-----------
[gn build] Port c847ddf8f18d (#209151)
Commit: 6da5260422379a53aadc0aedacded102fcff3fac
https://github.com/llvm/llvm-project/commit/6da5260422379a53aadc0aedacded102fcff3fac
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Sema/BUILD.gn
Log Message:
-----------
[gn build] Port d09048a46401 (#209152)
Commit: d9a5286ac41e54ed8aa73b61a8f173a9d0460085
https://github.com/llvm/llvm-project/commit/d9a5286ac41e54ed8aa73b61a8f173a9d0460085
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/unittests/CIR/BUILD.gn
Log Message:
-----------
[gn build] Port d1dbd484ada2 (#209153)
Commit: 4df8add1fd27371378285cd68cbfd3474e3f84b5
https://github.com/llvm/llvm-project/commit/4df8add1fd27371378285cd68cbfd3474e3f84b5
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Transforms/Vectorize/BUILD.gn
Log Message:
-----------
[gn build] Port e6673bd03771 (#209154)
Commit: e2dee8e8d047f858b03d451c37b3cc21dcefe69c
https://github.com/llvm/llvm-project/commit/e2dee8e8d047f858b03d451c37b3cc21dcefe69c
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Checkers/BUILD.gn
Log Message:
-----------
[gn build] Port f99f2a582e94 (#209155)
Commit: 477bb26c7c0c5eee0491ce058968ce3c4b89623b
https://github.com/llvm/llvm-project/commit/477bb26c7c0c5eee0491ce058968ce3c4b89623b
Author: Joel Walker <theagingboy05 at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sat.mir
Log Message:
-----------
[GlobalISel] Add G_SADDSAT/G_UADDSAT/G_SSUBSAT/G_USUBSAT to computeKnownBits (#209075)
Add known-bits handling for the saturating arithmetic opcodes G_SADDSAT,
G_UADDSAT, G_SSUBSAT and G_USUBSAT in GISelValueTracking, using the
existing
`KnownBits::{sadd,uadd,ssub,usub}_sat` helpers - the same ones
ValueTracking
uses for the corresponding IR intrinsics. (On the SelectionDAG side only
`ISD::USUBSAT` is currently handled.)
The new test covers exact constant folding, all four saturation clamps
(255, 127, 0, -128), partially known operands, a vector case, and fully
unknown operands. Without the change, all of these results are unknown.
Part of #150515.
---
Assisted by Claude (Anthropic).
Commit: 308393ede14cc8533d1be122b5df88bf9ba4173b
https://github.com/llvm/llvm-project/commit/308393ede14cc8533d1be122b5df88bf9ba4173b
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/load-cast-context.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vscale-fixed.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll
Log Message:
-----------
[LV] Allow scalable epilogue VFs matching the MainLoop VF (#208686)
This effectively limited scalable epilogue VFs to the MainLoopVF/2, as
all VFs are powers-of-two. This restriction does not exist for fixed
vector VFs. This could result in worse VF selections for scalable
epilogues (at high interleave counts), or in many cases only fixed
vectors selected (as there would be no allowed scalable VF in
ProfitableVFs).
Commit: 8a337c88d64e8d3fe918ae9fdc740fadbba2368c
https://github.com/llvm/llvm-project/commit/8a337c88d64e8d3fe918ae9fdc740fadbba2368c
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
Log Message:
-----------
Revert "[SPIR-V] Simplify and fix sign-extension bug in convertCharsToWord (#207769)" (#209162)
This reverts commit 503f0ca19cfcc9c0c88d6918939a2c0038ad0498.
This is obviously incorrect on big endian architectures.
Commit: 16bd5ce1184bb5683ea96290478e5912cf2975b9
https://github.com/llvm/llvm-project/commit/16bd5ce1184bb5683ea96290478e5912cf2975b9
Author: Alex Bradbury <asb at igalia.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
M llvm/test/CodeGen/AArch64/arm64ec-hybrid-patchable.ll
Log Message:
-----------
Reland [AArch64] Copy x4/x5 vararg payload into the x64 stack in Arm64EC exit thunks (#208453)
Reland llvm/llvm-project#190933, which was reverted by
llvm/llvm-project#198540 due to an EXPENSIVE_CHECKS build failure.
The fix relative to the reverted patch is to do the memcpy before the
final CALLSEQ_START for the dispatch call, avoiding nested call-frame
pseudos if memcpy lowers to a call.
Original commit message:
Currently the x4/x5 in a variadic Arm64EC exit thunks are treated by
LLVM like any other outgoing arguments. x4/x5 contain a pointer to the
first stack parameter and the size of the parameters passed on the
stack, and the generated exit thunk must memcpy these to the x86-64
stack. Current MSVC does this correctly.
Rather than introducing a new entry to the CallingConv enum, we mark the
call as vararg in AArch64ArmECCallLowering so that the lowering logic in
AArch64ISelLowering.cpp can recognise this case, perform the necessary
memcpy, and drop the x4/x5 arguments.
LLVM should additionally ensure that x0-x3 are mirrored to f0-f3 in
order to match the Windows x86-64 vararg ABI, but that change is left
for a follow-up patch.
Commit: 5595710093f7f8b9cdb0ff4f8d7400e58bde09b2
https://github.com/llvm/llvm-project/commit/5595710093f7f8b9cdb0ff4f8d7400e58bde09b2
Author: Jean-Didier PAILLEUX <jean-didier.pailleux at sipearl.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M flang/include/flang/Lower/MultiImageFortran.h
M flang/include/flang/Optimizer/Builder/MIFCommon.h
M flang/include/flang/Optimizer/Dialect/MIF/MIFOps.td
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/MultiImageFortran.cpp
M flang/lib/Optimizer/Builder/MIFCommon.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
A flang/lib/Optimizer/Transforms/EmitMIFGlobalCtors.cpp
M flang/test/Fir/basic-program.fir
M flang/test/Lower/MIF/coarray_allocation4.f90
M flang/test/Lower/MIF/coarray_allocation5.f90
Log Message:
-----------
[Flang][MIF] Allocation of NON-ALLOCATABLE SAVE coarray (#205847)
The goal of this PR is to add support for allocating NON-allocatable
coarrays that are not in the `Main` program.
All allocations will be performed in a function called
`__mif_save_coarrays_allocate`. If this function exists, then
LLVM::GlobalCtors is created (or modified).
The initialization of the MIF with `mif.init` is moved too in a
GlobalCtors with a priority of 0 to ensure that the initialization takes
place before any MIF allocations.
---------
Co-authored-by: Dan Bonachea <dobonachea at lbl.gov>
Commit: 40f2fda52c4b3b110f38acded24521217473d106
https://github.com/llvm/llvm-project/commit/40f2fda52c4b3b110f38acded24521217473d106
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/session_helpers.py
M lldb/test/API/tools/lldb-dap/variables/TestDAP_variables.py
M lldb/test/API/tools/lldb-dap/variables/children/TestDAP_variables_children.py
Log Message:
-----------
[lldb-dap] Migrate all DAP variables test. (#208215)
migrate TestDAP_variables and TestDAP_variables_children.
Commit: fff064e93d144a6499efcf091e1f226d144e514f
https://github.com/llvm/llvm-project/commit/fff064e93d144a6499efcf091e1f226d144e514f
Author: aokblast <aokblast at FreeBSD.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/Interpreter/Interpreter.cpp
M clang/test/Interpreter/cxx20-modules.cppm
M clang/test/Interpreter/execute-pch.cpp
A clang/test/Interpreter/pch-pic-mismatch.cpp
A clang/test/Interpreter/pcm-pic-mismatch.cpp
Log Message:
-----------
[Clang][Interpreter] Enable PIC to avoid 32-bit relocation overflows (#201286)
In clang-repl, R_*_32 relocations are emitted as direct 32-bit
PC-relative references. A conventional static linker can resolve
references to external symbols through the GOT or copy relocations, but
clang-repl directly mmaps shared objects into memory, bypassing the
static linker.
As a result, these relocations may exceed their 32-bit range if a
referenced symbol is located more than 2 GB away from the JIT
allocation, which can occur on FreeBSD.
Enable PIC to force accesses to external data through the GOT, avoiding
the generation of direct 32-bit relocations that are subject to the 2 GB
addressing limit.
Commit: a624d9999cf1ac83aa1fe0820c9311de8106175e
https://github.com/llvm/llvm-project/commit/a624d9999cf1ac83aa1fe0820c9311de8106175e
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt/AllocAction.h
Log Message:
-----------
[orc-rt] Remove redundant [[nodiscard]] from runFinalizeActions. NFC. (#209163)
runFinalizeActions returns an Expected, which already carries a
nodiscard attribute.
Commit: 9325f22f1cf17a6f192519163dd449d684700d2a
https://github.com/llvm/llvm-project/commit/9325f22f1cf17a6f192519163dd449d684700d2a
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M mlir/cmake/modules/CMakeLists.txt
Log Message:
-----------
[MLIR] Normalize path separator in MLIRConfig.cmake (#208659)
Under Windows, the paths may contain `\` path separators.
`MLIR_TABLEGEN_EXE` is added into MLIRConfig.cmake where backslashes are
interpreted as escape characters. This results in syntax errors during
`find_package(MLIR)`.
Fix by using CMake-normalized paths (`/` separator under all platforms).
LLVM/Clang do not put their tablegen paths in their config files.
Commit: 1884c7565155b603ec3946718801f53b276876bb
https://github.com/llvm/llvm-project/commit/1884c7565155b603ec3946718801f53b276876bb
Author: lianjinfeng2003 <101249452+mygitljf at users.noreply.github.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-invalid.mlir
Log Message:
-----------
[mlir][tosa] Validate variable element types (#205873)
I changed the TOSA validation path so unsupported types report a normal
diagnostic instead of crashing.
Fixes #205710
Commit: 0f69d2804b9b2542fde2ecafbb23f1e8a8b48d86
https://github.com/llvm/llvm-project/commit/0f69d2804b9b2542fde2ecafbb23f1e8a8b48d86
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M libcxx/include/__iterator/segmented_iterator.h
Log Message:
-----------
[libc++][NFC] Remove unused includes from <__iterator/segmented_iterator.h> (#209105)
Commit: d4c6c8623e9bf9aa75ad049f55423223228116b3
https://github.com/llvm/llvm-project/commit/d4c6c8623e9bf9aa75ad049f55423223228116b3
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/loadi8.ll
M llvm/test/Transforms/SLPVectorizer/X86/runtime-alias-checks.ll
Log Message:
-----------
[SLP] Support memory runtime alias checks
Vectorize straight-line code blocked by runtime-checkable may-alias
dependencies by versioning the block. Drop the deps, and if the tree is
profitable, emit base-object address-range overlap checks branching to a
vector fast path or an original-order scalar fallback.
Fixes #201534
Reviewers: RKSimon, bababuck, hiraditya
Pull Request: https://github.com/llvm/llvm-project/pull/203631
Commit: 7f35300f0deb972606082122e4c7d76dda03203c
https://github.com/llvm/llvm-project/commit/7f35300f0deb972606082122e4c7d76dda03203c
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt/Compiler.h
M orc-rt/include/orc-rt/Error.h
Log Message:
-----------
[orc-rt] Replace ORC_RT_NODISCARD with [[nodiscard]]. NFCI. (#209169)
The ORC runtime requires C++17, so we can use the C++17 [[nodiscard]]
attribute directly, rather than going through a macro.
Commit: dc1273beba1c70cb74d03c760958ee625d8aecf5
https://github.com/llvm/llvm-project/commit/dc1273beba1c70cb74d03c760958ee625d8aecf5
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper.c
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/lib/Object/OffloadBinary.cpp
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
clang-linker-wrapper: Use AMDGPU::TargetID for device-image compatibility (#209135)
Previously the link compatibilty was based on a raw string match of the
triple + cpu name. Start parsing the triple, and use the compatibility
function. Start using AMDGPU::TargetID from TargetParser, as a step
towards removing clang's redundant TargetID handling.
Co-authored-by: Claude (Opus 4.8)
Commit: 254472bc2edd6d8ec536656368869e36c386a339
https://github.com/llvm/llvm-project/commit/254472bc2edd6d8ec536656368869e36c386a339
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M flang/CMakeLists.txt
Log Message:
-----------
[Flang][CMake] Use LLVM-declared LLVM_EXTERNAL_LIT (#208680)
LLVM_EXTERNAL_LIT is already declared by
https://github.com/llvm/llvm-project/blob/99fb741b6e0da866bf3c6000531104bff347d787/llvm/cmake/modules/AddLLVM.cmake#L2175.
Flang's redeclaration in standalone builds is redundant and breaks on
Windows because the filename there is `llvm-lit.py`.
Commit: a9ba4d3fd27a05b31adfeaab5dcd42d8e43c1931
https://github.com/llvm/llvm-project/commit/a9ba4d3fd27a05b31adfeaab5dcd42d8e43c1931
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/loadi8.ll
M llvm/test/Transforms/SLPVectorizer/X86/runtime-alias-checks.ll
Log Message:
-----------
Revert "[SLP] Support memory runtime alias checks"
This reverts commit d4c6c8623e9bf9aa75ad049f55423223228116b3 to address
postcommit review https://github.com/llvm/llvm-project/pull/203631?email_source=notifications&email_token=ABI45DXYNFIHECEWI5IGYJT5ETMNLA5CNFSNUABKM5UWIORPF5TWS5BNNB2WEL2QOVWGYUTFOF2WK43UKJSXM2LFO4XTINRYGQ4TAMRWGAZ2M4TFMFZW63VMON2GC5DFL5RWQYLOM5S2KZLWMVXHJLDGN5XXIZLSL5RWY2LDNM#pullrequestreview-4684902603
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209173
Commit: da0045a12dbc6cc5b07534ca9ddcceaef49f05de
https://github.com/llvm/llvm-project/commit/da0045a12dbc6cc5b07534ca9ddcceaef49f05de
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/global-constant.ll
M llvm/test/CodeGen/AMDGPU/global-directive.ll
M llvm/test/CodeGen/AMDGPU/global-extload-gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/global-extload-i16.ll
M llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-atomics.gfx1030.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-atomics.gfx908.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-store.ll
M llvm/test/CodeGen/AMDGPU/global-smrd-unknown.ll
M llvm/test/CodeGen/AMDGPU/global-variable-relocs.ll
M llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir
M llvm/test/CodeGen/AMDGPU/greedy-broken-ssa-verifier-error.mir
M llvm/test/CodeGen/AMDGPU/greedy-global-heuristic.mir
M llvm/test/CodeGen/AMDGPU/greedy-instruction-split-subrange.mir
M llvm/test/CodeGen/AMDGPU/greedy-liverange-priority.mir
M llvm/test/CodeGen/AMDGPU/greedy-remark-crash-unassigned-reg.mir
M llvm/test/CodeGen/AMDGPU/greedy-reverse-local-assignment.ll
M llvm/test/CodeGen/AMDGPU/group-image-instructions.ll
M llvm/test/CodeGen/AMDGPU/gv-const-addrspace.ll
M llvm/test/CodeGen/AMDGPU/gv-offset-folding.ll
M llvm/test/CodeGen/AMDGPU/gws-hazards.mir
M llvm/test/CodeGen/AMDGPU/gws_agpr.ll
M llvm/test/CodeGen/AMDGPU/half-alloca-promotion.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/hard-clause-limit-attr.mir
M llvm/test/CodeGen/AMDGPU/hard-clause-limit.mir
M llvm/test/CodeGen/AMDGPU/hard-clauses-gfx1250.mir
M llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx10.mir
M llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx11.mir
M llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx12.mir
M llvm/test/CodeGen/AMDGPU/hard-clauses-load-monitor.mir
M llvm/test/CodeGen/AMDGPU/hard-clauses.mir
M llvm/test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir
M llvm/test/CodeGen/AMDGPU/hazard-flat-instruction-valu-check.mir
M llvm/test/CodeGen/AMDGPU/hazard-getreg-waitalu.mir
M llvm/test/CodeGen/AMDGPU/hazard-gfx1250-flat-scr-hi.mir
M llvm/test/CodeGen/AMDGPU/hazard-hidden-bundle.mir
M llvm/test/CodeGen/AMDGPU/hazard-in-bundle.mir
M llvm/test/CodeGen/AMDGPU/hazard-inlineasm.mir
M llvm/test/CodeGen/AMDGPU/hazard-kill.mir
M llvm/test/CodeGen/AMDGPU/hazard-lds-addtid.mir
M llvm/test/CodeGen/AMDGPU/hazard-pass-ordering.mir
M llvm/test/CodeGen/AMDGPU/hazard-pseudo-machineinstrs.mir
M llvm/test/CodeGen/AMDGPU/hazard-recognizer-meta-insts.mir
M llvm/test/CodeGen/AMDGPU/hazard-recognizer-src-shared-base.ll
M llvm/test/CodeGen/AMDGPU/hazard-setreg-vgpr-msb-gfx1250.mir
M llvm/test/CodeGen/AMDGPU/hazard-shift64.mir
M llvm/test/CodeGen/AMDGPU/hazard.mir
M llvm/test/CodeGen/AMDGPU/hazards-gfx1250.mir
M llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
M llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir
M llvm/test/CodeGen/AMDGPU/high-bits-zeroed-16-bit-ops.mir
M llvm/test/CodeGen/AMDGPU/hip.extern.shared.array.ll
M llvm/test/CodeGen/AMDGPU/hsa-func-align.ll
M llvm/test/CodeGen/AMDGPU/hsa-globals.ll
M llvm/test/CodeGen/AMDGPU/hsa-group-segment.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-register-count.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-small.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-func-hidden-args-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-funcarg-hidden-args-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-kernarg-hidden-args-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-enqueue-kernel-.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ctor-dtor-list.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ir-full.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-heap-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-hidden-args-v4.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-hidden-args-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-present-asan.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-v4.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-images.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-multigrid-sync-arg-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v4.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-queueptr-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-resource-usage-function-ordering.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-uniform-workgroup-size-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-wavefrontsize.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-workgroup-processor-mode-v5.ll
M llvm/test/CodeGen/AMDGPU/huge-private-buffer.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-phi.ll
M llvm/test/CodeGen/AMDGPU/i1-divergent-phi-fix-sgpr-copies-assert.mir
M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
M llvm/test/CodeGen/AMDGPU/i128-add-carry-chain.ll
M llvm/test/CodeGen/AMDGPU/i1_copy_phi_with_phi_incoming_value.mir
M llvm/test/CodeGen/AMDGPU/i8-extract-cost-comparison.ll
M llvm/test/CodeGen/AMDGPU/icmp.i16.ll
M llvm/test/CodeGen/AMDGPU/icmp64.ll
M llvm/test/CodeGen/AMDGPU/idemponent-atomics.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (15) (#209118)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping
the redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: b719e2e27ce121bec3afcf96f4806c0592ce95a1
https://github.com/llvm/llvm-project/commit/b719e2e27ce121bec3afcf96f4806c0592ce95a1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot2-test.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4-test.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/iglp-no-clobber.ll
M llvm/test/CodeGen/AMDGPU/iglp.opt.reentry.ll
M llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir
M llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll
M llvm/test/CodeGen/AMDGPU/image-sample-waterfall.ll
M llvm/test/CodeGen/AMDGPU/image-schedule.ll
M llvm/test/CodeGen/AMDGPU/img-nouse-adjust.ll
M llvm/test/CodeGen/AMDGPU/imm.ll
M llvm/test/CodeGen/AMDGPU/imm16.ll
M llvm/test/CodeGen/AMDGPU/immv216.ll
M llvm/test/CodeGen/AMDGPU/implicit-arg-block-count.ll
M llvm/test/CodeGen/AMDGPU/implicit-arg-v5-opt.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernel-argument-alignment.ll
M llvm/test/CodeGen/AMDGPU/implicitarg-offset-attributes.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si-gfx9.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-set-from-other-function.ll
M llvm/test/CodeGen/AMDGPU/indirect-private-64.ll
M llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.ll
M llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.mir
M llvm/test/CodeGen/AMDGPU/infer-addrpace-pipeline.ll
M llvm/test/CodeGen/AMDGPU/infer-addrspace-flat-atomic.ll
M llvm/test/CodeGen/AMDGPU/infer-uniform-load-shader.ll
M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/inflate-av-remat-imm.mir
M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-agpr-negative-tests.mir
M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av.mir
M llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir
M llvm/test/CodeGen/AMDGPU/infloop-subrange-spill-inspect-subrange.mir
M llvm/test/CodeGen/AMDGPU/infloop-subrange-spill.mir
M llvm/test/CodeGen/AMDGPU/init-whole-wave-vgpr-count-large.ll
M llvm/test/CodeGen/AMDGPU/init-whole-wave-vgpr-count-leaf.ll
M llvm/test/CodeGen/AMDGPU/init-whole-wave-vgpr-count-use-inactive.ll
M llvm/test/CodeGen/AMDGPU/init-whole-wave-vgpr-count.ll
M llvm/test/CodeGen/AMDGPU/inline-asm-av-constraint-err.ll
M llvm/test/CodeGen/AMDGPU/inline-asm-av-constraint.ll
M llvm/test/CodeGen/AMDGPU/inline-asm-out-of-bounds-register.ll
M llvm/test/CodeGen/AMDGPU/inline-asm-reserved-regs.ll
M llvm/test/CodeGen/AMDGPU/inline-asm-vgpr-range-unsupported-width.ll
M llvm/test/CodeGen/AMDGPU/inline-asm-vgpr-sgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.ll
M llvm/test/CodeGen/AMDGPU/inline-attr.ll
M llvm/test/CodeGen/AMDGPU/inline-constraints.ll
M llvm/test/CodeGen/AMDGPU/inline-maxbb.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-16-fake16.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-16-true16.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-16.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-mismatched-size-error.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-packed.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-v16.ll
M llvm/test/CodeGen/AMDGPU/insert-branch-w32.mir
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-attr.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-literal.mir
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-parse.mir
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-wmma-xdl.mir
M llvm/test/CodeGen/AMDGPU/insert-delay-alu.mir
M llvm/test/CodeGen/AMDGPU/insert-handle-flat-vmem-ds.mir
M llvm/test/CodeGen/AMDGPU/insert-skip-from-vcc.mir
M llvm/test/CodeGen/AMDGPU/insert-skips-gfx10.mir
M llvm/test/CodeGen/AMDGPU/insert-skips-gfx12.mir
M llvm/test/CodeGen/AMDGPU/insert-skips-gfx1250.mir
M llvm/test/CodeGen/AMDGPU/insert-skips-gws.mir
M llvm/test/CodeGen/AMDGPU/insert-skips-ignored-insts.mir
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-callee.mir
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-fence-soft.mir
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-gfx12-wbinv.mir
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-hang.mir
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-merge.ll
M llvm/test/CodeGen/AMDGPU/insert_subreg.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.subtest-nosaddr.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.subtest-saddr.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir
M llvm/test/CodeGen/AMDGPU/inst-prefetch-hint.ll
M llvm/test/CodeGen/AMDGPU/inst-prefetch-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/integer-canonicalizing-src-modifiers.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/integer-select-src-modifiers.ll
M llvm/test/CodeGen/AMDGPU/internalize.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (16) (#209119)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx>
to the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa),
dropping the redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: db87fc87c7fd70f9e429439aeebbf9cd014dde54
https://github.com/llvm/llvm-project/commit/db87fc87c7fd70f9e429439aeebbf9cd014dde54
Author: Mikhail R. Gadelha <mikhail at igalia.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/riscv/headers.txt
M libc/config/linux/x86_64/entrypoints.txt
Log Message:
-----------
[libc][RISC-V] Enable additional entrypoints and headers (#208927)
Bring most of the already enabled libs for x86_64 to riscv.
Also, move two libs in x86_64 entrypoints.txt to keep the file sorted
alphabetically.
Commit: 62b7c7f547da4af492e85aa09b6feafc9b513f23
https://github.com/llvm/llvm-project/commit/62b7c7f547da4af492e85aa09b6feafc9b513f23
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/Passes/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 5595710 (#209165)
This fixes 5595710093f7f8b9cdb0ff4f8d7400e58bde09b2.
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=5595710093f7f8b9cdb0ff4f8d7400e58bde09b2
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 9e014de2d3cc674b548e321013bfe42e6f5485ab
https://github.com/llvm/llvm-project/commit/9e014de2d3cc674b548e321013bfe42e6f5485ab
Author: Tony Guillot <tony.guillot at protonmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaExpr.cpp
M clang/test/SemaCXX/attr-sentinel.cpp
Log Message:
-----------
[Clang] Fixed missing sentinel attribute diagnostic discrepancy with explicit object parameters (#208842)
When using the sentinel attribute on a variadic function with an
explicit object parameter, the missing sentinel attribute diagnostic
takes into account the explicit object parameter as an argument. It was
diagnosing `missing sentinel in function call` instead of `not enough
variable arguments in '%0' declaration to fit a sentinel`, compared to
other similar variadic functions.
Fixes #200007
Commit: 90d8af8caac360dca0fa28abbb5804dcbe694ef1
https://github.com/llvm/llvm-project/commit/90d8af8caac360dca0fa28abbb5804dcbe694ef1
Author: Kieran B <kieran.bailey at arm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
Log Message:
-----------
[Clang][AArch64] Add ACLE _n variants for svdot intrinsics (#208694)
Add missing _n variants for the svdot ACLE
intrinsics in arm_sve.td
Add CodeGen tests in acle_sve2p1_dot.c to verify
correct intrinsics are generated
List of Intrinsics:
- svdot_n_s32_s16
- svdot_n_u32_u16
- svdot_n_f32_f16
Commit: 7a8b26271b273ea36c1d68c97f4c87b63de4a2bd
https://github.com/llvm/llvm-project/commit/7a8b26271b273ea36c1d68c97f4c87b63de4a2bd
Author: quic-k <kushpal at qti.qualcomm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M libunwind/src/UnwindRegistersRestore.S
M libunwind/src/UnwindRegistersSave.S
Log Message:
-----------
[libunwind][Hexagon] Save/restore full r0-r7 in getcontext/jumpto (#208753)
The Hexagon save and restore routines dropped GPRs, producing an
incomplete context.
UnwindRegistersSave.S (__unw_getcontext): save r0-r7 (stores began at
__r[8]), drop a dead "r1 = memw(r30)" before the PC store, and return
UNW_ESUCCESS instead of a stale non-zero value.
UnwindRegistersRestore.S (jumpto): restore the missing r2-r7 (r0/r1 and
r8-r31 were already handled), and fix the stale "pointer is in r2"
comment (it is r0).
Signed-off-by: Kushal Pal <kushpal at qti.qualcomm.com>
Commit: ff599bba9d370bf58e4a34f9f29b4fb6234013f0
https://github.com/llvm/llvm-project/commit/ff599bba9d370bf58e4a34f9f29b4fb6234013f0
Author: quic-k <kushpal at qti.qualcomm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/Driver/ToolChains/Hexagon.cpp
M clang/test/Driver/hexagon-toolchain-picolibc.c
Log Message:
-----------
[Hexagon] Enable init-array by default for picolibc (#208639)
Picolibc uses the modern .init_array/.fini_array mechanism rather than
legacy .init/.fini sections. Extend UseInitArrayDefault in
HexagonToolChain::addClangTargetOptions to also return true when
--cstdlib=picolibc is selected, preventing -fno-use-init-array from
being passed to cc1.
Signed-off-by: Kushal Pal <kushpal at qti.qualcomm.com>
Commit: fc9a4afa9bdc406f1ce4e0dbc078734025ab2d9d
https://github.com/llvm/llvm-project/commit/fc9a4afa9bdc406f1ce4e0dbc078734025ab2d9d
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[WebAssembly] Port SelectionDAGISel to NewPM
Similar to other targets, for getting the NewPM rolling.
Reviewers: aheejin, sbc100, dschuff
Pull Request: https://github.com/llvm/llvm-project/pull/208982
Commit: c31455cd07c43ed02445f5b1f1057037f0503552
https://github.com/llvm/llvm-project/commit/c31455cd07c43ed02445f5b1f1057037f0503552
Author: Jake Egan <Jake.egan at ibm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M libcxx/src/filesystem/operations.cpp
A libcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.remove_all/bad_perms_parent.pass.cpp
Log Message:
-----------
[libc++] Fix filesystem::remove_all bug with read-only nested directory (#197104)
Consider a directory `parent/child`, where `parent` has read-only
permissions. Calling `remove_all` on `parent` is expected to fail with a
permission error, however it fails with a different error depending on
the platform (such as "error file exists" on AIX).
During the recursive removal, `unlinkat` is first called on the child
and fails with a permission error. Rather than returning, the function
continues and tries `unlinkat` on the parent and fails with a different
error depending on the platform. This error is returned instead of the
permission error. This PR makes the first encountered error be returned
instead.
According to the standard [fs.op.remove.all]:
> Effects: Recursively deletes the contents of p if it exists, then
> deletes file p itself, as if by POSIX remove.
The word "then" implies an ordering where deleting the contents of p
should be successful before deleting file p itself.
Fixes #197100.
Commit: 52511761bc80e96b7d07b4da71bb08c8f498dee1
https://github.com/llvm/llvm-project/commit/52511761bc80e96b7d07b4da71bb08c8f498dee1
Author: Wooseok Lee <wolee at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.h
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/test/CodeGen/AMDGPU/av-invalid-scope.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-invalid-syncscope.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir
Log Message:
-----------
[AMDGPU] Fix SSID merge in SIMemoryLegalizer to use smallest inclusiv… (#208300)
…e scope
SIMemOpAccess::constructFromMIWithMMO merged multiple MMO sync scopes by
calling isSyncScopeInclusion(A, B) and blindly overwriting SSID with B
when it returned false. This was correct when B strictly subsumes A, but
isSyncScopeInclusion returned false for both "A < B" and "A and B are
incomparable" -- e.g. agent-one-as (one-AS, agent level) vs workgroup
(cross-AS, workgroup level) live on different branches of the
two-dimensional scope lattice and neither subsumes the other. In the
incomparable case the resulting SSID depended on MMO order, silently
dropping agent-scope cache-management requirements.
Fix: replace isSyncScopeInclusion (std::optional<bool>) with
getMergedSyncScopeID (std::optional<SyncScope::ID>) which returns the
smallest scope inclusive of both inputs. The merged level is
max(level_A, level_B); if either input is cross-AS the result is also
cross-AS, since dropping cross-AS ordering would silently lose the
ordering guarantee for address spaces not covered by a one-AS scope.
Add tests in memory-legalizer-multiple-mem-operands-atomics.mir
verifying that a FLAT_ATOMIC_ADD with agent-one-as and workgroup MMOs
produces agent-scope cache ops (BUFFER_WBINVL1_VOL) regardless of MMO
order.
Commit: c42c7b47a634ab3f4455b0e8b17f2bbc3be022af
https://github.com/llvm/llvm-project/commit/c42c7b47a634ab3f4455b0e8b17f2bbc3be022af
Author: Anonmiraj <ezzibrahimx at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/Lex/PPDirectives.cpp
Log Message:
-----------
[clang][NFC] Skip macro source-location check for names that can't warn (#208862)
While profiling Linux headers, I noticed that
`Preprocessor::CheckMacroName` performs expensive source-location
queries for every macro, even when no diagnostic is possible. We can
avoid this overhead by only performing these checks when the macro name
is actually a reserved identifier or keyword, skipping them entirely for
ordinary macros.
| | basket Ir |
| --- | --- |
| before | 10,690,004,315 |
| after | 10,649,181,540 |
| **Δ** | **−40.8M (−0.38%)** |
this is a follow up to #137306 and #139492
Commit: aab2ff0b9096df1d5168e293c81b6653e759890d
https://github.com/llvm/llvm-project/commit/aab2ff0b9096df1d5168e293c81b6653e759890d
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/X86/avx512fp16-fmaxnum.ll
M llvm/test/CodeGen/X86/avx512fp16-fminnum.ll
Log Message:
-----------
[SDAG][X86] Form pseudo fmin/fmax from select_cc (#208717)
Create PSEUDO_FMIN/PSEUDO_FMAX from SELECT_CC in addition to
SELECT/VSELECT.
Unfortunately we can't just do this in the common SimplifySelectCC()
helper because of the StrictFP handling and need to handle all three
cases explicitly.
I ran into this trying to use the ops on s390x, but there are also some
avx512 cases that benefit, so I split out this generalization.
Commit: 592953beff733a1e28f6c6e5e39f948fb035a329
https://github.com/llvm/llvm-project/commit/592953beff733a1e28f6c6e5e39f948fb035a329
Author: Anonmiraj <ezzibrahimx at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/include/clang/Lex/Preprocessor.h
M clang/lib/Lex/Preprocessor.cpp
Log Message:
-----------
[clang][Diagnostics] Only record lexer check points when colors are enabled (#204926)
Only build lexer check points when colored diagnostics are enabled,
since that's the only case where they're ever used,
This should reduce the cost on larger builds.
| Commit | Basket Ir | Delta |
|---|---|---|
| 863b2c84 (Parent) | 30,240,576,150 | — |
| 718aac9f (Commit) | 30,336,607,185 | +0.318% |
| **+ this pr** | **30,279,772,621** | **+0.130%** |
**synthetic error file (12.3k lines, 300 errors):**
| Build | Error-TU Ir (colors on) | Δ vs commit |
|---|---|---|
| 718aac9f (Commit) | 1,386,488,658 | — |
| **+ this pr** | **1,387,140,588** | **+0.05%** |
Resolves #203764
---------
Co-authored-by: Timm Baeder <tbaeder at redhat.com>
Commit: ee71eb831b6090897df8ae4f843f4b14370131d5
https://github.com/llvm/llvm-project/commit/ee71eb831b6090897df8ae4f843f4b14370131d5
Author: StoeckOverflow <95052643+StoeckOverflow at users.noreply.github.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/include/clang/APINotes/APINotesReader.h
M clang/lib/APINotes/APINotesFormat.h
M clang/lib/APINotes/APINotesReader.cpp
M clang/lib/Sema/SemaAPINotes.cpp
A clang/test/APINotes/Inputs/Headers/WhereParametersSema.apinotes
A clang/test/APINotes/Inputs/Headers/WhereParametersSema.h
M clang/test/APINotes/Inputs/Headers/module.modulemap
A clang/test/APINotes/where-parameters-sema.cpp
Log Message:
-----------
[APINotes] Match function-like Where.Parameters in Sema (#205307)
This PR teaches Sema to apply function-like `Where.Parameters` selectors
for API notes.
It builds on #204147 by using the serialized `Where.Parameters` selector
keys in Sema. For each `FunctionDecl` / `CXXMethodDecl`, Sema derives an
exact parameter selector from the declaration’s `FunctionProtoType`.
Broad name-only API notes lookup still runs first, preserving existing
behavior. If Clang can form a parameter selector, Sema then performs an
exact selector lookup and applies that result second, allowing
overload-specific notes to refine same-name broad notes.
Tests:
- Adds end-to-end module APINotes Sema coverage (`.apinotes` source ->
binary APINotes -> reader lookup -> Sema matching -> AST result)
- Covers core matching behavior for global functions and C++ methods,
including same-name overloads, exact empty selectors, broad-plus-exact
coexistence and mismatched selectors
- Covers important edge cases: default arguments, static methods, alias
spellings remaining non-canonicalized, by-value `const`, namespaced
functions, and overloaded operators.
This PR does not add duplicate-selector or unmatched-selector
diagnostics. Those remain for a follow-up diagnostics PR.
**Note**: this PR was originally stacked on top of #204147. It has now
been rebased on top of main containing those changes, so the remaining
diff should reflect only the top commit specific to this PR.
Reviewers: @Xazax-hun @j-hui @egorzhdan
---------
Co-authored-by: John Hui <updog at j-hui.com>
Commit: 42aaca2c4a6d69b6334be102e41d185526915f8b
https://github.com/llvm/llvm-project/commit/42aaca2c4a6d69b6334be102e41d185526915f8b
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt/Session.h
M orc-rt/test/unit/SessionTest.cpp
Log Message:
-----------
[orc-rt] Add ReportErrorsViaSession utility. (#209177)
ReportErrorsViaSession is a function object constructed from a Session&
that forwards Errors to that Session's reportError method. It will be
used in upcoming patches to simplify some error reporting plumbing.
Commit: f88150e1d5fc8591b0d71619d02e5b553161c1f8
https://github.com/llvm/llvm-project/commit/f88150e1d5fc8591b0d71619d02e5b553161c1f8
Author: Andrey Pavlenko <andrey.a.pavlenko at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
M mlir/test/Conversion/VectorToXeGPU/transfer-read-to-xegpu.mlir
Log Message:
-----------
[MLIR][XeGPU][VectorToXeGPU] Fixed transposed transfer_read/write (#197281)
The problem was that adjustStridesForPermutation() permutes strides, but
they are required to compute base offset from transfer read indices.
Added optional argument to computeMemrefMeta() to preserve the original
strides.
Commit: 4c519c6e558a0cccf80c072ccf0822488968cbaf
https://github.com/llvm/llvm-project/commit/4c519c6e558a0cccf80c072ccf0822488968cbaf
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
Log Message:
-----------
[gn] port 375cc88b510150d (AMDGPU -gisel-extended-llt) (#209181)
Commit: 290601ed3e08a7e90b81b0b17cf45e1a435783a7
https://github.com/llvm/llvm-project/commit/290601ed3e08a7e90b81b0b17cf45e1a435783a7
Author: Stefan Gränitz <stefan.graenitz at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lldb/source/Plugins/SymbolLocator/SymStore/SymbolLocatorSymStore.cpp
M lldb/source/Plugins/SymbolLocator/SymStore/SymbolLocatorSymStoreProperties.td
M lldb/test/API/symstore/TestSymStore.py
Log Message:
-----------
[lldb] Make timeout for HTTP send/receive in SymbolLocatorSymStore configurable (#192061)
This patch adds the `plugin.symbol-locator.symstore.timeout` setting and
keeps the previously hard-coded value of 60 sections as the default. It
adds a test to check that the breakpoint doesn't resolve and we get the
correct warning message if the timeout hits.
---------
Co-authored-by: Nerixyz <nerixdev at outlook.de>
Commit: da1e5f1f6c096f360abe39ad2f7d235b6d270a70
https://github.com/llvm/llvm-project/commit/da1e5f1f6c096f360abe39ad2f7d235b6d270a70
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/DiagOutputUtils.h
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefCallArgsChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefLocalVarsChecker.cpp
M clang/test/Analysis/Checkers/WebKit/local-vars-checked-const-member.cpp
M clang/test/Analysis/Checkers/WebKit/local-vars-counted-const-member.cpp
M clang/test/Analysis/Checkers/WebKit/member-function-pointer-crash.cpp
M clang/test/Analysis/Checkers/WebKit/unchecked-local-vars.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-local-vars.cpp
M clang/test/Analysis/Checkers/WebKit/unretained-local-vars-arc.mm
M clang/test/Analysis/Checkers/WebKit/unretained-local-vars.mm
Log Message:
-----------
[alpha.webkit.UncheckedLocalVarsChecker] Improve the warning text (#208855)
This PR aligns UncheckedLocalVarsChecker and its variant's warning
message with the new warning format in
https://github.com/llvm/llvm-project/pull/202724.
Commit: ac370b8e838ada3dd482560c4b8a568e760f95b5
https://github.com/llvm/llvm-project/commit/ac370b8e838ada3dd482560c4b8a568e760f95b5
Author: Hugo Trachino <hugo.trachino at huawei.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/DecomposeGenericByUnfoldingPermutation.cpp
M mlir/test/Dialect/Linalg/specialize-generic-ops-fail.mlir
Log Message:
-----------
[MLIR][Linalg] Fix LinalgSpecializeGenericOpsPass for scalar inputs (#208466)
The test case added would crash because the Ranked Tensor-ness of
operands was assumed but never checked. This crash only happened when there
were multiple inputs as it must bail out somewhere else when there is only
1 input.
Commit: 24df1d13d9090e075b162bf81d1a34a408e54924
https://github.com/llvm/llvm-project/commit/24df1d13d9090e075b162bf81d1a34a408e54924
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/Template.h
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaLambda.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/TreeTransform.h
M clang/test/SemaTemplate/concepts-lambda.cpp
M clang/test/SemaTemplate/concepts.cpp
Log Message:
-----------
Reapply "[Clang] Transform lambda's constraints when instantiating parameter mapping (#207966)
This reapplies https://github.com/llvm/llvm-project/pull/195995
The last approach caused a regression because sometimes we transformed
the constraints of lambda expression too aggressively when we should
have preserved it.
The basic idea of this patch is to transform constraints of lambda
expressions when we instantiate the parameter mapping, thus the
evaluation can be emancipated from preserving outer template arguments.
Claude is used to help reduce the test case from #199209
Fixes https://github.com/llvm/llvm-project/issues/193944
Fixes https://github.com/llvm/llvm-project/issues/199209
Fixes https://github.com/llvm/llvm-project/issues/202957
Commit: fb0ffb1f5131018926e46a918744868c0d07abd7
https://github.com/llvm/llvm-project/commit/fb0ffb1f5131018926e46a918744868c0d07abd7
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
[AArch64] NFCI: Simplify LowerVectorFP_TO_INT_SAT (part 1) (#207198)
The lowering code tries to implement splitting by keeping two source
values SrcVal and SrcVal2 for the Lo/Hi part respectively.
This is a bit awkward, because SrcVal2 may not be set. It makes more
sense to generating new DAG nodes that will be lowered separately by the
lowering mechanism, which revisits the newly added (split sourceval)
nodes for lowering.
Commit: ada4f7cffcff8eba94a193cf85fe1fa828ed9ec5
https://github.com/llvm/llvm-project/commit/ada4f7cffcff8eba94a193cf85fe1fa828ed9ec5
Author: SiHuaN <liyongtai at iscas.ac.cn>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rvp-reverse.ll
Log Message:
-----------
[RISCV][P-ext] Improve RV64 v2i16 reverse codegen (#208664)
On RV64, v2i16 is widened to v4i16 before shuffle lowering. Recognize
the widened low-half reverse and select ppairoe.h directly instead of
rev16 followed by srli.
Commit: 695238ffaa64ac8f49e7da36d36c5170509007cc
https://github.com/llvm/llvm-project/commit/695238ffaa64ac8f49e7da36d36c5170509007cc
Author: Ariel-Burton <arielburton at yahoo.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
A clang/test/CodeGen/SystemZ/zos-check-lanuage.c
Log Message:
-----------
Write original source language when writing and reading AST (#208115)
FAIL: Clang :: Frontend/ast-main.c
FAIL: Clang :: Frontend/ast-main.cpp
were failing on z/OS; this change fixes these lit failures.
The issue here is that on z/OS the original source code language needs
to be passed through to the IR so that the backend can encode this
information in the PPA2 in the object file. That means that it needs to
be exported to the AST so that going from saved AST -> IR will carry the
language through.
Commit: c4cb2c0e763c304071e950e47dd0c25a7dcfbbca
https://github.com/llvm/llvm-project/commit/c4cb2c0e763c304071e950e47dd0c25a7dcfbbca
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M flang/CMakeLists.txt
Log Message:
-----------
[Flang] Multi-config CMake output paths in standalone builds (#208690)
When using a multi-config generator with CMake (such as "Ninja
Multi-Config" or any Visual Studio generator), the output path must be
specific to each config by having it include `${CMAKE_CFG_INTDIR}`.
`CMAKE_CFG_INTDIR` will just be `.` in single-config generators. Use the
same path as used by LLVM:
https://github.com/llvm/llvm-project/blob/cd662a7c4fb03a88d0e429a7fc8d8b470a812e2b/llvm/CMakeLists.txt#L562-L563
`LLVM_LIBDIR_SUFFIX` was seemingly forgotten in one of the paths.
This is not complete support (neither has LLVM). More paths would need
to be config-specific. In particular, `check-flang` does not work, but
at least one can build the executables.
Commit: cb6bccc33f46cba5bbdba5f3883acde1a1f4f83e
https://github.com/llvm/llvm-project/commit/cb6bccc33f46cba5bbdba5f3883acde1a1f4f83e
Author: A. Jiang <de34 at live.cn>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M libcxx/docs/Status/Cxx26Papers.csv
M libcxx/include/__mdspan/extents.h
M libcxx/include/__mdspan/mdspan.h
M libcxx/include/mdspan
M libcxx/include/span
M libcxx/test/std/containers/views/mdspan/extents/ctad.pass.cpp
M libcxx/test/std/containers/views/mdspan/mdspan/deduction.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/deduct.pass.cpp
Log Message:
-----------
[libc++] Backport P3029R1 Better `mdspan`'s CTAD to C++20/23 (#208132)
Also backport
- support for `T::value` of a reference type in `integral-constant-like`
from P2781R9 `std::constant_wrapper`, and
- LWG4351 _`integral-constant-like`_ needs more `remove_cvref_t`.
P3029R1 (and its further fixes) should be treated as a Defect Report
against C++20/23 to avoid behavior difference in different modes. Other
implementations will do or are already doing the same.
Commit: 31ccbe7007691bc6d2eb628dcd4ad1f264215322
https://github.com/llvm/llvm-project/commit/31ccbe7007691bc6d2eb628dcd4ad1f264215322
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
A llvm/test/Transforms/LoopVectorize/AArch64/masked-store-with-profile-info.ll
A llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-branch-weights.ll
A llvm/test/Transforms/LoopVectorize/replicate-region-branch-weights.ll
A llvm/test/Transforms/LoopVectorize/replicate-region-cost-probability.ll
Log Message:
-----------
[LV] Extend test coverage with branch probabilities (NFC). (#209182)
Add tests with branch probabilities, including cost printing tests for
replicate regions, VPlan printing tests and masked stores with
probabilities.
Commit: a1a806bb371550661aaee787d2a3622d9e84d528
https://github.com/llvm/llvm-project/commit/a1a806bb371550661aaee787d2a3622d9e84d528
Author: ioana ghiban <ioana.ghiban at arm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/MemRef/Transforms/Passes.td
M mlir/lib/Dialect/MemRef/Transforms/CMakeLists.txt
M mlir/lib/Dialect/MemRef/Transforms/ElideReinterpretCast.cpp
M mlir/test/Dialect/MemRef/elide-reinterpret-cast.mlir
Log Message:
-----------
[memref] Support non-scalar copies in `reinterpret_cast` elision (#203873)
Extends `memref-elide-reinterpret-cast` from scalar-only copy
transformation to also handle copies of effectively 1D and static
multidimensional regions.
The rewrite is limited to cases where each non-unit `reinterpret_cast`
result dimension maps directly to a distinct identity-layout source
dimension with the same stride and sufficient static size. This lets the
rewrite use each loop IV
directly as a source memref index. Cases where result strides do not
match source identity strides are left untouched because they would
require linearization/delinearization across source dimensions.
Assisted-by: Codex (refine implementation + tests). I reviewed all code
and tests before submission.
## Examples
Scalar copy, unchanged(*) behavior:
```mlir
// BEFORE
%view = memref.reinterpret_cast %dst
to offset: [1], sizes: [1, 1], strides: [1, 1]
: memref<1x108xf32> to memref<1x1xf32, strided<[1, 1], offset: 1>>
memref.copy %src, %view : memref<1x1xf32> to memref<1x1xf32, strided<[1, 1], offset: 1>>
// AFTER
%v = memref.load %src[%c0, %c0] : memref<1x1xf32>
memref.store %v, %dst[%c0, %c1] : memref<1x108xf32>
```
Effectively 1D copy:
```mlir
// BEFORE
%view = memref.reinterpret_cast %dst
to offset: [0], sizes: [1, 33, 1], strides: [1386, 42, 1]
: memref<1x33x42xf32> to memref<1x33x1xf32, strided<[1386, 42, 1]>>
memref.copy %src, %view : memref<1x33x1xf32> to memref<1x33x1xf32, strided<[1386, 42, 1]>>
// AFTER
scf.for %i = %c0 to %c33 step %c1 {
%v = memref.load %src[%c0, %i, %c0] : memref<1x33x1xf32>
memref.store %v, %dst[%c0, %i, %c0] : memref<1x33x42xf32>
}
```
Static 2D copy with offset becomes a nested loop with the static offset
folded into the `reinterpret_cast` source store indices.
```mlir
// BEFORE
%view = memref.reinterpret_cast %dst
to offset: [16], sizes: [1, 33, 4], strides: [1386, 42, 1]
: memref<1x33x42xf32>
to memref<1x33x4xf32, strided<[1386, 42, 1], offset: 16>>
memref.copy %src, %view
// AFTER
%c0 = arith.constant 0 : index
%c1 = arith.constant 1 : index
%c4 = arith.constant 4 : index
%c16 = arith.constant 16 : index
%c33 = arith.constant 33 : index
scf.for %i = %c0 to %c33 step %c1 {
scf.for %j = %c0 to %c4 step %c1 {
%v = memref.load %src[%c0, %i, %j]
memref.store %v, %dst[%c0, %i, %c16 + %j]
}
}
```
## Scope
Supported:
- ranked, static-shape copy source and `reinterpret_cast` source/result
memrefs
- identity-layout `reinterpret_cast` sources
- rank-preserving `reinterpret_cast`s
- scalar copies, including dynamic result strides because all result
indices are zero
- non-scalar copies where every non-unit result dimension has a static
stride matching a distinct source dimension with sufficient static size
- static offsets, delinearized into source indices
- dynamic offsets only when the `reinterpret_cast` source has at most
one non-unit dimension and the result has at most one mapped non-unit
dimension
Not addressed:
- unranked or dynamic-shape copy/reinterpret_cast operands
- non-identity-layout `reinterpret_cast` sources
- rank-changing `reinterpret_cast`s
- dynamic strides on non-unit result dimensions
- result dimensions whose strides do not match source identity strides
- result dimensions that reuse a source dimension or cross source
dimension boundaries
- dynamic offsets requiring runtime div/rem delinearization
## Correctness
Result indices are translated to source indices by direct dimension
mapping: each non-unit result dimension must have the same stride as a
distinct source dimension.
Static offsets are delinearized into source indices before rewriting.
Dynamic offsets are only accepted when they can be used directly in the
single non-unit source dimension.
Cases assumed invalid by `reinterpret_cast`/`copy` semantics are guarded
with assertions.
(*) NFC to scalar copy case, we're now only creating zero constants for
indices once.
Commit: 158938ccba7a91e709a2bd8c607eaefd271a102b
https://github.com/llvm/llvm-project/commit/158938ccba7a91e709a2bd8c607eaefd271a102b
Author: Sean Perry <perry at ca.ibm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/test/CodeGen/SystemZ/zos-ppa1-name.c
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
A llvm/test/CodeGen/SystemZ/zos-ppa1-name.ll
M llvm/test/CodeGen/SystemZ/zos-ppa1.ll
Log Message:
-----------
Change zos-ppa1-name attr to be the name used in ppa1 (#208870)
Change the meaning of the `zos-ppa1-name` attribute to pass the name of
the function to use in the PPA1. The symbol name used in the PAA1 will
be:
- if the function has the `zos-ppa1-name` attribute, use that value. An
empty string will be mean don't add the name to the PPA1
- otherwise use the function name.
The behaviour for asm labels and `#pragma map` (PR coming shortly) is to
use the function name used in the source code in the PPA1. A follow on
PR for clang will set `zos-ppa1-name` to the mangled name ignoring asm
label to implement the non-empty string part of the first bullet.
Commit: ee24ac00d874ce82eaf36431f9aeb2ad744bc3b8
https://github.com/llvm/llvm-project/commit/ee24ac00d874ce82eaf36431f9aeb2ad744bc3b8
Author: AZero13 <gfunni234 at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/AST/DeclCXX.cpp
M clang/test/CXX/drs/cwg15xx.cpp
M clang/test/CodeGenCXX/devirtualize-virtual-function-calls.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
[Clang] Allow devirtualization involving array subscripts with constant indices when the pointee type is known [CWG1504] (#207540)
By C++17 [expr.add]/6, if the array element type and the pointee type
are not similar, behavior is undefined.
Commit: 5b169798db9fc312f397e219f54253266fd518f3
https://github.com/llvm/llvm-project/commit/5b169798db9fc312f397e219f54253266fd518f3
Author: Liza Burakova <liza at chromium.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M libcxx/include/__thread/thread.h
Log Message:
-----------
[libc++] Add missing include to thread.h (#208740)
Change #195509 removed unused transitive includes, but missed adding
<__type_traits/is_integral.h> to thread.h. This caused errors
to Chromium rolls for libc++ as they caught the missing import.
Commit: cc048f0d5516923ea29e9887eb92da0456eeb331
https://github.com/llvm/llvm-project/commit/cc048f0d5516923ea29e9887eb92da0456eeb331
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M flang/include/flang/Lower/OpenMP.h
A flang/include/flang/Semantics/omp-declare-variant.h
M flang/include/flang/Semantics/symbol.h
M flang/lib/Lower/CMakeLists.txt
M flang/lib/Lower/CallInterface.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Semantics/check-omp-variant.cpp
A flang/test/Lower/OpenMP/Todo/declare-variant-structured-trait-property.f90
A flang/test/Lower/OpenMP/Todo/declare-variant-target-device.f90
R flang/test/Lower/OpenMP/Todo/declare-variant.f90
A flang/test/Lower/OpenMP/declare-variant-call.f90
A flang/test/Lower/OpenMP/declare-variant-construct.f90
A flang/test/Lower/OpenMP/declare-variant-device.f90
A flang/test/Lower/OpenMP/declare-variant-implementation.f90
A flang/test/Lower/OpenMP/declare-variant-module.f90
A flang/test/Lower/OpenMP/declare-variant-target-device.f90
M flang/test/Semantics/OpenMP/declare-variant.f90
Log Message:
-----------
[flang][OpenMP] Lowering support for declare variant. (#206988)
Add lowering support for OpenMP DECLARE VARIANT. Each directive is
recorded on its base procedure during the structure checks. During call
lowering, best variant is picked based on recorded selecter and context.
Note: this PR does not include module-file support for DECLARE VARIANT,
so cross-module variant resolution is not yet available; it will be
added in a follow-up PR.
Assisted by: Cursor
Commit: 6c632847812cba9b13a4e9d79187fb0026276521
https://github.com/llvm/llvm-project/commit/6c632847812cba9b13a4e9d79187fb0026276521
Author: rdevshp <rdevshp at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/test/Analysis/z3/z3-logicalexpr-eval.c
Log Message:
-----------
[analyzer] Fix stale z3 analyzer-constraints name in test z3-logicalexpr-eval.c (#209185)
z3 was recently renamed to unsupported-z3.
Change the analyzer-constraints to unsupported-z3 in the test file
z3-logicalexpr-eval.c
Commit: 13dcad3571ecf0fb72486a52db9ce2231577a457
https://github.com/llvm/llvm-project/commit/13dcad3571ecf0fb72486a52db9ce2231577a457
Author: Kyungtak Woo <kevinwkt at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/test/Driver/amdgpu-openmp-gpu-max-threads-per-block.c
Log Message:
-----------
[clang][OpenMP][test] Use -fopenmp=libomp explicitly in clang driver test (#209082)
Explicitly pass -fopenmp=libomp in the test to make it robust against
downstream configurations where the default OpenMP runtime is set to
something else (e.g., libgomp). Seems this is in alignment with other
tests in `clang/test/Driver`.
Commit: 03801323f6d9021469c9ece5442c526fc891447a
https://github.com/llvm/llvm-project/commit/03801323f6d9021469c9ece5442c526fc891447a
Author: Kyungtak Woo <kevinwkt at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lldb/test/API/functionalities/statusline/TestStatusline.py
Log Message:
-----------
[lldb][test] Fix TestStatusline path resolution in symlinked environments (#209083)
Fixes a test timeout in TestStatusline.py introduced in commit
a35565161078 (#208609) when running in environments with symlinked
source paths.
Commit: 3c8b4f94584e6d03e8445a70e9e8d8be7912afb7
https://github.com/llvm/llvm-project/commit/3c8b4f94584e6d03e8445a70e9e8d8be7912afb7
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
Log Message:
-----------
[analyzer][docs] CSA release notes for clang-23 (#207433)
The commits were gathered using:
```sh
git log --reverse --oneline llvmorg-23-init..llvm/main \
clang/lib/StaticAnalyzer clang/include/clang/StaticAnalyzer | \
grep -v NFC | grep -v OpenACC | grep -v -i revert | grep -v -i "webkit"
```
I used the `LLVM_ENABLE_SPHINX=ON` and `LLVM_ENABLE_DOXYGEN=ON` cmake
options to enable the `docs-clang-html` build target, which generates
the html into `build/tools/clang/docs/html/ReleaseNotes.html` of which I
attach the screenshots to let you judge if it looks all good or not.
I've swapped the PR links to the issue links when a PR was fixing an
open GitHub issue. Those issues anyway have a link to the PR inside.
Assisted-by: Claude Opus 4.8
Commit: 5e98ee7f78dd4febc473e338e929b1646082a4cb
https://github.com/llvm/llvm-project/commit/5e98ee7f78dd4febc473e338e929b1646082a4cb
Author: Matsu <47756807+khaki3 at users.noreply.github.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M mlir/lib/Dialect/OpenACC/Transforms/ACCIfClauseLowering.cpp
M mlir/test/Dialect/OpenACC/acc-if-clause-lowering.mlir
Log Message:
-----------
[mlir][acc] Preserve shared data operations during if-clause lowering (#208771)
Example:
```fortran
!$acc kernels present(grid, c) if(offload_on)
do nc = 1, grid%rc%ncol
c(1,nc) = 0
end do
c(1,1) = 0
!$acc end kernels
```
In this code, kernels restructuring can create compute constructs that
share data-entry operations with an enclosing data region. If-clause
lowering could rewrite or erase these shared operations, producing
invalid IR or duplicate erasure.
Fix: Preserve externally owned data operations, deduplicate cleanup, and
retain duplicate operand ordering while cloning local operations once.
Commit: 8eb718e1185ff72ff9fb8944b1f3f2f6c8cde292
https://github.com/llvm/llvm-project/commit/8eb718e1185ff72ff9fb8944b1f3f2f6c8cde292
Author: Prajwal KP <prajwal.kp.1817 at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/ExpandReductions.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmaximum.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fminimum.ll
M llvm/test/CodeGen/WebAssembly/vector-reduce.ll
M llvm/test/CodeGen/X86/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/X86/vector-reduce-fminimum.ll
M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll
Log Message:
-----------
[ExpandReductions] Expand fmaximum/fminimum reductions (#195169)
fixes #195111
Commit: 3f12bb1f25b88e338679c42ccaea11fe204a0e1c
https://github.com/llvm/llvm-project/commit/3f12bb1f25b88e338679c42ccaea11fe204a0e1c
Author: Brian Cain <brian.cain at oss.qualcomm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/Driver/ToolChains/Hexagon.cpp
M clang/test/Driver/hexagon-toolchain-linux.c
Log Message:
-----------
[Hexagon] Add scs multilib for -fsanitize=shadow-call-stack (#208833)
musl hexagon targets already select msan/asan library variants based on
the sanitizer in use; do the same for shadow-call-stack so that
-fsanitize=shadow-call-stack picks up usr/lib/scs.
Commit: d0ad2c694caf05793b243b0b3a8425c5ef78abdf
https://github.com/llvm/llvm-project/commit/d0ad2c694caf05793b243b0b3a8425c5ef78abdf
Author: David Zbarsky <dzbarsky at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/Frontend/CompilerInvocation.cpp
Log Message:
-----------
[clang] Reuse driver option strings in CompilerInvocation (#202632)
CompilerInvocation emits a second copy of clang/Options/Options.inc with
OPTTABLE_STR_TABLE_CODE only to implement lookupStrInTable(). The driver
OptTable already owns the identical string table.
On an arm64 Release build, fully stripped standalone clang shrinks from
94,570,224 to 94,537,216 bytes, saving 33,008 bytes (0.035%).
Work towards #202616
AI tool disclosure: Co-authored with OpenAI Codex.
Commit: 3ee76834fc9484080eee38964b4ebcb60442c8f8
https://github.com/llvm/llvm-project/commit/3ee76834fc9484080eee38964b4ebcb60442c8f8
Author: Jason Van Beusekom <jason.van-beusekom at hpe.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Optimizer/Builder/MutableBox.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
A flang/test/Fir/alloc-aligned-device.fir
A flang/test/Fir/alloc-aligned-omp.fir
A flang/test/Fir/alloc-aligned.fir
M flang/test/Fir/invalid.fir
M flang/test/Lower/CUDA/cuda-allocatable.cuf
M flang/test/Lower/HLFIR/allocatable-and-pointer-status-change.f90
M flang/test/Lower/HLFIR/custom-intrinsic.f90
M flang/test/Lower/HLFIR/intrinsic-dynamically-optional.f90
M flang/test/Lower/Intrinsics/show_descriptor.f90
M flang/test/Lower/OpenACC/acc-declare.f90
M flang/test/Lower/OpenMP/allocatable-array-bounds.f90
M flang/test/Lower/OpenMP/parallel-reduction-allocatable-array.f90
M flang/test/Lower/OpenMP/parallel-reduction-mixed.f90
M flang/test/Lower/OpenMP/wsloop-reduction-allocatable-array-minmax.f90
Log Message:
-----------
[Flang][Fir] Set default alignment to 64 on inlineAllocation for arrays (#208781)
In https://github.com/llvm/llvm-project/pull/206525 the runtime was set
to default alloctable and pointer arrays to 64byte alignment. In this commit
the inlineallocation case is handled.
The same approach was taken and an alignment attribute was added,
with logic to promote to aligned_alloc or posixMemalign for apple
targets, when requested alignment is greater than 16.
Of note alignof(std::max_align_t)) was not used as the runtime target
may be different than the compile target, so 16 was hardcoded as when to
use aligned_alloc
Assisted-by: Opus 4.8
Commit: bd27a8dd906a0cd5c56fe2117ced98ad6eae14e6
https://github.com/llvm/llvm-project/commit/bd27a8dd906a0cd5c56fe2117ced98ad6eae14e6
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZTargetStreamer.cpp
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZTargetStreamer.h
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.h
M llvm/test/CodeGen/SystemZ/zos-landingpad.ll
Log Message:
-----------
[SystemZ][z/OS] Move emission of PPA1 (#208543)
There is an interesting restriction during emission: emitting debug
information closes the text section. As result, emitting the delayed
PPA1 data does not work in the current place together with emitting
debug information. Since the PPA1 information is constant data, the
solution is to emit the data in the target strreamer, in
`emitConstantPools()`.
Commit: 2a74b20bb612c3f6695f30eb3648da33bfcf10a3
https://github.com/llvm/llvm-project/commit/2a74b20bb612c3f6695f30eb3648da33bfcf10a3
Author: Vassil Vassilev <v.g.vassilev at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/Basic/Attributes.cpp
M clang/unittests/AST/AttrTest.cpp
Log Message:
-----------
[Basic] Fix crash computing the spelling index of an unknown scoped attribute (#208909)
AttributeCommonInfo::getAttributeSpellingListIndex() aborts for an
unknown attribute that has a scope, such as [[ns::foo]]. It calls
calculateAttributeSpellingListIndex(), which runs name/scope
string-switches generated for the known attributes. Those switches
intentionally have no default: getScopeFromNormalizedScopeName() falls
off the end and hits llvm_unreachable ("Fell off the end of a
string-switch") for the unknown scope.
Any caller that asks a scoped unknown attribute for its spelling index
therefore crashes. An unrecognized attribute has no entry in those
tables and carries a single no-spelling, so short-circuit
calculateAttributeSpellingListIndex() for UnknownAttribute and return
index 0 before the switches run.
Add a unit test that constructs an unknown scoped AttributeCommonInfo
and asks for its spelling index; it aborts without the fix.
Commit: 4538987e5e9241af58246df18e625bfd7809cd04
https://github.com/llvm/llvm-project/commit/4538987e5e9241af58246df18e625bfd7809cd04
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M polly/lib/Analysis/ScopDetection.cpp
Log Message:
-----------
[Polly] Cast delinearization terms to matching types (#206711)
#204146 revealed that Polly can call `SCEVDivision::divide` with a
numerator and denominator of different types. I believe such divisions
are not meaningful and should be avoided. As far as I can tell, the root
cause is that `SCEVRemoveMax::rewrite` may collect terms whose types
differ from that of the original expression.
Before this patch, the terms gathered by `SCEVRemoveMax::rewrite` were
used for delinearization as they are. This patch applies
`getTruncateOrSignExtend` to them to matching their types with that of
the original expression.
Commit: 6ce86d47ca095f1f2c911520bc2c845ff09c5fba
https://github.com/llvm/llvm-project/commit/6ce86d47ca095f1f2c911520bc2c845ff09c5fba
Author: Anshil Gandhi <95053726+gandhi56 at users.noreply.github.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
A llvm/test/CodeGen/AMDGPU/eliminate-frame-index-flat-scratch-svs.mir
Log Message:
-----------
[NFC][AMDGPU] Simplify scratch address materialization in SVS frame index fallback (#208624)
The flat scratch SVS frame index fallback folded the offset in with
V_ADD_U32_e32 writing into FrameReg (an SGPR, an illegal VALU
destination) and added it to FrameReg instead of the scavenged
VGPR used as vaddr, so the offset never reached the address.
This commit asserts that there is no frame register in this block, and
simplifies code accordingly. Correctly materialize the offset into the
scavenged VGPR and emit a scratch instruction in SVS form.
Commit: 6733bc3026401bf84c391301313c7ea131bd9904
https://github.com/llvm/llvm-project/commit/6733bc3026401bf84c391301313c7ea131bd9904
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M flang/lib/Lower/OpenMP/Utils.cpp
Log Message:
-----------
[flang] Replace FlangOMPContext with OmpVariantMatchContext. (#209220)
The `FlangOMPContext` got replaced in 8e8e4e50f501b.
This fixes build after https://github.com/llvm/llvm-project/pull/206988.
Commit: ba61e4d1c110199ef07d7ef4c34c23bcc64b4b54
https://github.com/llvm/llvm-project/commit/ba61e4d1c110199ef07d7ef4c34c23bcc64b4b54
Author: LU-JOHN <John.Lu at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/divrem24-assume.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udivrem24.ll
Log Message:
-----------
[AMDGPU] Implement int div/rem by fp recip more efficiently (#204950)
Integer division q = a/b can be implemented by fp reciprocal with:
`fq = fa * recip(fb)`
fq is truncated to produce q. Due to fp rounding and reciprocal accuracy
issues fq can be too small and truncation can produce a value too small
by one.
If abs(a)<=0x400000, this underestimate can be guarded more efficiently
by calculating:
`fq=fa+1ulp/b`
If abs(a)<=0x400000, adding 1 ulp will increase a by at most 0.5, so the
calculated q will be the same. Adding 1ulp can be done with one integer
add.
Incrementing `fa` by 1 ulp was exhaustively tested for all dividend and
divisor combinations with values between [-0x400000,0x3FFFFF] with no
errors.
---------
Signed-off-by: John Lu <John.Lu at amd.com>
Commit: 9d34596f7338ca057ea94078c31bde6c8c9c60af
https://github.com/llvm/llvm-project/commit/9d34596f7338ca057ea94078c31bde6c8c9c60af
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/DiagOutputUtils.h
Log Message:
-----------
[clang][UncheckedLocalVarsChecker][NFC] Add missing headers (#209217)
After #208855 this fails compiling headers standalone due to incomplete
types, e.g. `error: member access into incomplete type 'ASTContext'`. It
works fine building the `.cpp` files but is not a
[standalone](https://llvm.org/docs/CodingStandards.html#self-contained-headers)
header.
Commit: f56c5d68b19376f27da236456861a462bcd8a973
https://github.com/llvm/llvm-project/commit/f56c5d68b19376f27da236456861a462bcd8a973
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefLambdaCapturesChecker.cpp
M clang/test/Analysis/Checkers/WebKit/unchecked-lambda-captures.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures-decl-protects-this-crash.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures.cpp
M clang/test/Analysis/Checkers/WebKit/unretained-lambda-captures-arc.mm
M clang/test/Analysis/Checkers/WebKit/unretained-lambda-captures.mm
Log Message:
-----------
[webkit.UncountedLambdaCapturesChecker] Improve the warning text (#209198)
This PR aligns webkit.UncountedLambdaCapturesChecker and its variant's
warning message with the new warning format in other checkers.
Commit: d2bf3af65d920de29a31f764959d67769f3587c6
https://github.com/llvm/llvm-project/commit/d2bf3af65d920de29a31f764959d67769f3587c6
Author: Corentin Jabot <corentinjabot at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Lex/Lexer.cpp
A clang/test/Preprocessor/GH101342.c
Log Message:
-----------
[Clang] Detects invalid unicode characters in token formed by `##` (#208757)
When parsing identifiers with invalid (non-xid_continue), we would emit
a diagnostics and continue, in an effort to improve recovery.
However, in raw mode we would not emit a diagnostic, but still continue.
So identifiers formed in raw mode could be gibberish.
We fixed that by not-continuing on error in raw mode.
Fixes #101342
Commit: c59378289002e1d12d649ef47708b900332141c7
https://github.com/llvm/llvm-project/commit/c59378289002e1d12d649ef47708b900332141c7
Author: Yanzuo Liu <zwuis at outlook.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CodeGen/CGExprCXX.cpp
A clang/test/CIR/CodeGenCXX/typeid-most-derived.cpp
M clang/test/CodeGenCXX/typeid-most-derived.cpp
Log Message:
-----------
[clang][CodeGen] Evaluate `typeid` operands which are the most derived objects (#208470)
Before this patch, `typeid` operands are not evaluated if they are the
most derived objects.
Before #196544, only `typeid(non-reference-var)` is considered to be the
most derived object, which doesn't have side effects obviously. So there
was no miscompilation.
Fixes #202051.
Commit: 6c5332d2d76df720a441bbbd1b0601f01114b4e3
https://github.com/llvm/llvm-project/commit/6c5332d2d76df720a441bbbd1b0601f01114b4e3
Author: Anshil Gandhi <95053726+gandhi56 at users.noreply.github.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
Log Message:
-----------
[NFC][AMDGPU] Add tests for eliminateFrameIndex (#208612)
Add MIR tests to cover all instances where a Vgpr needs to be scavenged
and used due to Sgpr scarcity, during elimination of frame indices.
Commit: 9bf20bdfc685477e349f335d1b128403342fc361
https://github.com/llvm/llvm-project/commit/9bf20bdfc685477e349f335d1b128403342fc361
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/include/clang/Frontend/SSAFOptions.h
M clang/include/clang/Options/Options.td
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/ScalableStaticAnalysis/Analyses/SSAFAnalysesCommon.cpp
M clang/lib/ScalableStaticAnalysis/Analyses/SSAFAnalysesCommon.h
M clang/test/Analysis/Scalable/command-line-interface.cpp
M clang/test/Analysis/Scalable/help.cpp
Log Message:
-----------
[clang][ssaf] Add --ssaf-include-local-entities flag (#209225)
This option allows including local entities in summaries.
This means that ContributorFinder can optionally include block-scope
(function-local) variables.
Parameters are intentionally skipped: they are exposed via their parent
function's USR + a parameter-index suffix in getEntityName, so
registering
them as independent contributors would be redundant.
Part §2 of rdar://179151023
Approved in #205351.
Co-authored-by: Jan Korous <jkorous at apple.com>
Co-authored-by: Claude Opus 4.7 <noreply at anthropic.com>
Commit: fd3d20f13f4d29eb99ada5fb9c6c87c6dee6ed17
https://github.com/llvm/llvm-project/commit/fd3d20f13f4d29eb99ada5fb9c6c87c6dee6ed17
Author: Garvit Gupta <garvgupt at qti.qualcomm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
A llvm/test/CodeGen/RISCV/xqcilo-addr-regimm26.ll
Log Message:
-----------
[RISCV] Add SelectAddrRegImm26 isel complex pattern for Xqcilo 26-bit load/store (#207363)
Introduce a dedicated SelectAddrRegImm26 ComplexPattern for the Qualcomm
Xqcilo large-offset load/store instructions (qc.e.lw/qc.e.sw), whose
offset
field is 26 bits wide, and use it in the QC48LdPat/QC48StPat patterns
instead
of the generic AddLike + simm26_nosimm12 match.
SelectAddrRegImm26 handles addresses of the form:
- simm12 offsets are left to the standard (shorter/compressible)
load/store.
- 26-bit (non-simm12) offsets fold directly into qc.e.lw/qc.e.sw.
- Offsets just outside the 26-bit range are split with ADDI plus a
folded 26-bit remainder.
Assisted by claude
Commit: 38033e2c2316dbb264264d9fb8be5c3b543b5c1e
https://github.com/llvm/llvm-project/commit/38033e2c2316dbb264264d9fb8be5c3b543b5c1e
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/unittests/ScalableStaticAnalysis/Analyses/PointerFlow/PointerFlowTest.cpp
M clang/unittests/ScalableStaticAnalysis/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp
Log Message:
-----------
[clang][ssaf][NFC] Add unittests for PointerFlow and UnsafeBufferUsage about local entities (#209227)
Part §6 of rdar://179151023
Depends on #209225.
Approved in #205351.
---------
Co-authored-by: Jan Korous <jkorous at apple.com>
Co-authored-by: Claude Opus 4.7 <noreply at anthropic.com>
Commit: 15d8e43e7d1efa0d0a86589e1e2c28dbe011e226
https://github.com/llvm/llvm-project/commit/15d8e43e7d1efa0d0a86589e1e2c28dbe011e226
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/ScalableStaticAnalysis/Analyses/CallGraph/CallGraphExtractor.cpp
A clang/test/Analysis/Scalable/call-graph-local-entities.cpp
A clang/test/Analysis/Scalable/local-entities.cpp
Log Message:
-----------
[clang][ssaf] Add FIXME that CallGraphExtractor does not honor IncludeLocalEntities (#209228)
Currently, CallGraph extractor does not honor IncludeLocalEntities and
it emits entities for block-scope callees - irrespective of what the
option is set to, such as:
- function-local declared lambdas
- function-local declared classes and their member functions
The new test file ensures that PointerFlow and UnsafeBufferUsage honors
the IncludeLocalEntities option.
Part §3 and §5 of rdar://179151023
Depends on #209225 and #209227.
Approved in #205351.
Co-authored-by: Jan Korous <jkorous at apple.com>
Co-authored-by: Claude Opus 4.7 <noreply at anthropic.com>
Commit: c5d5988520d90c77dfc279e86b1e052703d86960
https://github.com/llvm/llvm-project/commit/c5d5988520d90c77dfc279e86b1e052703d86960
Author: Rito Takeuchi <licht-t at outlook.jp>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/X86/div.ll
M llvm/test/Analysis/CostModel/X86/rem.ll
A llvm/test/Transforms/LoopVectorize/X86/idiv-by-const.ll
A llvm/test/Transforms/SLPVectorizer/X86/idiv-by-const.ll
Log Message:
-----------
[X86][CostModel] Add vXi64 divide/remainder-by-constant costs (#208491)
### What this does
Follow-up to #206983, which lowered `vXi64` `MULHU`/`MULHS`. Modified
the cost model to enable the vectorization:
1. `SDIV`/`SREM` for `v4i64`/`v8i64`, gated on AVX512DQ
`MULHS`'s low multiply is `vpmullq`. Without DQ, it scalarizes and can
be a performance regression. So, this PR adds
`AVX512DQ{UniformConst,Const}` tables which are consulted before the
AVX512/AVX2 ones. Then, non-DQ targets fall through to the scalarized
cost.
2. `UDIV`/`UREM` for `v4i64`/`v8i64` in the AVX2 and AVX512
For `UREM`, the multiply-back in the remainder `x - (x/C)*C` is a single
`vpmullq` with DQ, but another `vpmuludq` schoolbook without it. So, the
cheap DQ `UREM` entries in `AVX512DQ{UniformConst,Const}` overrides more
expensive AVX512/AVX2 ones.
Part of #37771.
### AI Usage Disclosure
This PR was prepared with the assistance of Claude Code.
Commit: 28366bc273fb734027a10dad2a6245665ac138f6
https://github.com/llvm/llvm-project/commit/28366bc273fb734027a10dad2a6245665ac138f6
Author: Luan Rabelo <96793857+Lu4nScr1pt1ng at users.noreply.github.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaDecl.cpp
M clang/test/Sema/enum.c
Log Message:
-----------
[clang] [Sema] Widen enumerators that overflow a _BitInt type (C23) (#208230)
When an enumerator has no explicit value and the previous enumerator has
a
_BitInt type whose maximum is reached, incrementing should widen to a
suitably sized standard integer type (C23 6.7.3.3p12 excludes
bit-precise
types from the widening). Clang instead kept the _BitInt type and let
the
value wrap around, with a misleading "not representable in the largest
integer type" warning.
The problem is in getNextLargerIntegralType: it compared candidate types
against the storage size of the previous type. A _BitInt(33) is stored
in
64 bits, so no standard type looked larger and the widening never
happened.
Comparing against the value width (getIntWidth) fixes it: the enumerator
now gets the next standard type that can hold the value, and the
behavior
matches GCC (verified against GCC 15.2).
For standard integer types getIntWidth equals getTypeSize, so this
changes
behavior only for bit-precise types.
The new tests in enum.c check the widened type and the value from inside
the enum definition, like the reproducer in the issue; they fail without
this change. Incrementing the max of a _BitInt(64) still warns, since no
standard type can hold that value, and that case is covered too.
Fixes #208163
Commit: 46951909a77676a30a285e60426ff897684703c1
https://github.com/llvm/llvm-project/commit/46951909a77676a30a285e60426ff897684703c1
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
R clang/test/CodeGen/SystemZ/zos-check-lanuage.c
Log Message:
-----------
Revert "Write original source language when writing and reading AST (#208115)" (#209230)
This reverts commit 695238ffaa64ac8f49e7da36d36c5170509007cc.
The new test is flaky, see comment on
https://github.com/llvm/llvm-project/pull/208115
Commit: 1d9a3c069b0b882e6651ece3f05bcb492c66567b
https://github.com/llvm/llvm-project/commit/1d9a3c069b0b882e6651ece3f05bcb492c66567b
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 9bf20bd (#209238)
This fixes 9bf20bdfc685477e349f335d1b128403342fc361.
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=9bf20bdfc685477e349f335d1b128403342fc361
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 633be471e811aea4c258afe4280db82393b4c484
https://github.com/llvm/llvm-project/commit/633be471e811aea4c258afe4280db82393b4c484
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/CMakeLists.txt
Log Message:
-----------
Revert "[CMake] Use minimum python version of 3.8 everywhere" (#209233)
Reverts llvm/llvm-project#208822.
We should avoid raising toolchain requirements immediately before
branching. Revert this now so it can be reapplied after branching.
Commit: c4076b002b072c73f781b191ae0ccc6c075df1d7
https://github.com/llvm/llvm-project/commit/c4076b002b072c73f781b191ae0ccc6c075df1d7
Author: Madhur Kumar <152476790+MadhurKumar004 at users.noreply.github.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir
M llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
Log Message:
-----------
[AMDGPU][GlobalISel] Combine rcp(sqrt(x)) into rsq for pseudo-scalar instructions (#198785)
This fixes "TODO: GlobalISel should generate v_s_rsq." give in file
"llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll"
Commit: ecf41975d04e0a7f5bb0d62dbafa7da6e4c9e3a3
https://github.com/llvm/llvm-project/commit/ecf41975d04e0a7f5bb0d62dbafa7da6e4c9e3a3
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/docs/LangRef.md
M llvm/include/llvm/ADT/APFloat.h
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Support/APFloat.cpp
M llvm/test/Verifier/arbitrary-fp-convert.ll
M llvm/unittests/ADT/APFloatTest.cpp
Log Message:
-----------
[Verifier] Clarify supported storage bit width for apfloat conversions (#209174)
Allow i4 for FP4, i6 for FP6 and i8 for FP8.
Assisted-by: Claude Code Opus 4.8
Commit: 62facd1645b504c95f2a82dd8a211f1c23e13b07
https://github.com/llvm/llvm-project/commit/62facd1645b504c95f2a82dd8a211f1c23e13b07
Author: Nerixyz <nerixdev at outlook.de>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/test/tools/llvm-debuginfod-find/timeout.test
Log Message:
-----------
[llvm][HTTP] Relax check for timeout error message (#209240)
When LLVM used curl to do HTTP requests, the timeout test failed even
though the request correctly timed out
(https://github.com/llvm/llvm-project/pull/188969#issuecomment-4960193683).
On curl, we prepend the error with `curl_easy_perform() failed: `
whereas with WinHTTP, the error is fixed as "Timeout was reached".
This PR relaxes the check to allow for the prefix in the curl case.
Commit: 83e914e56acb7795875be41bcbe9c7c036e897c4
https://github.com/llvm/llvm-project/commit/83e914e56acb7795875be41bcbe9c7c036e897c4
Author: Robert Imschweiler <robert.imschweiler at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M offload/test/lit.cfg
Log Message:
-----------
[offload][test] Add fallback to legacy AMDGPU triple library dir (#209131)
After the amdgcn-amd-amdhsa -> amdgpu-amd-amdhsa rename, look up the
device runtime libraries in the legacy directory when the runtime was
built under the old triple name.
Claude assisted with this patch.
Commit: 3122e20cfc7c1b8d103b435ecba27fc3172cb581
https://github.com/llvm/llvm-project/commit/3122e20cfc7c1b8d103b435ecba27fc3172cb581
Author: Scott Manley <rscottmanley at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACC.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACCCG.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCComputeLowering.cpp
Log Message:
-----------
[OpenACC] add isEffectivelySerial() to acc.parallel and acc.kernels (#209192)
Mirror the isEffectivelySerial() function in acc.compute_region to
acc.parallel and acc.kernel so this check is unified anywhere it needs
to be used, namely before ACCComputeLowering. Should be NFC
Commit: 690aacbf9d15569ec26843d6367f5cf6d5b26969
https://github.com/llvm/llvm-project/commit/690aacbf9d15569ec26843d6367f5cf6d5b26969
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/Scalar/GVN.h
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/test/Transforms/GVN/ptrtoaddr.ll
Log Message:
-----------
[GVN] Reuse dominating PtrToInt for PtrToAddr. (#209164)
A ptrtoaddr and a ptrtoint of the same pointer compute the same value
when the address width equals the pointer representation width. Reuse
a dominating ptrtoint in place of a ptrtoaddr.
This fixes a few end-to-end regressions with
https://github.com/llvm/llvm-project/pull/180244.
PR: https://github.com/llvm/llvm-project/pull/209164
Commit: f3671a14e499e376709fb68ae6b2bdd76fe91fdc
https://github.com/llvm/llvm-project/commit/f3671a14e499e376709fb68ae6b2bdd76fe91fdc
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M libc/cmake/modules/LLVMLibCArchitectures.cmake
M offload/cmake/caches/AMDGPUBot.cmake
M offload/cmake/caches/AMDGPULibcBot.cmake
M offload/cmake/caches/FlangOffload.cmake
M offload/cmake/caches/Offload.cmake
Log Message:
-----------
[AMDGPU] Fix cache files and builds after amdgcn->amdgpu conversion (#209247)
Summary:
Quite important that this works before the fork. The problem is that
CMake takes the string literally while rewriting it to amdgpu/
internally so the amdgcn/ directories do not appear.
Commit: 9cfd0411138b33ea11bfce22e41cd026e92120ca
https://github.com/llvm/llvm-project/commit/9cfd0411138b33ea11bfce22e41cd026e92120ca
Author: Luke Lau <luke at igalia.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-with-wide-ops-chained.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
A llvm/test/Transforms/LoopVectorize/interleaved-accesses-dead-member.ll
M llvm/test/Transforms/LoopVectorize/versioning-dead-load.ll
Log Message:
-----------
[VPlan] Don't bail creating interleave group if it has dead members (#208415)
This is an alternative to both #203555 and #205584.
To recap the issue:
1) The legacy cost model has the invariant that all CM_Interleave
widened groups will eventually be converted to a VPInterleaveGroup, so
it marks the addresses as uniform.
2) After #190191 a CM_Interleave isn't guaranteed to be converted to a
VPInterleaveGroup if it has dead members, and it breaks this assumption
in 1). So addresses aren't properly widened due to the uniform
assumption.
Rather than try to fix up the address, this just maintains the invariant
that a CM_Interleave will become a VPInterleaveGroup by not skipping
over groups with dead members.
While there's slightly less code involved, the main benefit of this
approach vs the others is that it keeps generating interleaved groups
instead of falling back to gathers/scatters, so we don't get a codegen
regression against 22.x.
Co-authored-by: Mel Chen <mel.chen at sifive.com>
Commit: ddd76138de9630eb018de68ef5cc0c9f486cb659
https://github.com/llvm/llvm-project/commit/ddd76138de9630eb018de68ef5cc0c9f486cb659
Author: Aleksandr Popov <42888396+aleks-tmb at users.noreply.github.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/test/Analysis/ScalarEvolution/zext-add-nsw-fold.ll
Log Message:
-----------
[SCEV][NFC] Add tests for generalized A + zext(C + X) fold (#209219)
Related to #208778
Commit: 7dd8867515732d1bc4a837edf6fe0658189398d3
https://github.com/llvm/llvm-project/commit/7dd8867515732d1bc4a837edf6fe0658189398d3
Author: Alex Langford <alangford at apple.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lldb/cmake/modules/AddLLDB.cmake
Log Message:
-----------
[lldb] Enforce usage of LINK_COMPONENTS and CLANG_LIBS (#208860)
LINK_COMPONENTS and CLANG_LIBS exist to correctly support the LLVM/Clang
dylib build configuration. Failure to enforce this will break LLDB when
built against libLLVM.dylib.
Commit: fa4cbcd7e8b912a85f96c61b6d6e332822d22e7e
https://github.com/llvm/llvm-project/commit/fa4cbcd7e8b912a85f96c61b6d6e332822d22e7e
Author: Fabian Parzefall <parzefall at meta.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/DIE.h
M llvm/unittests/CodeGen/DIETest.cpp
Log Message:
-----------
[CodeGen] Fix IntrusiveBackList::deleteNode (#207783)
Issue #207411 reported that IntrusiveBackList::deleteNode does not
delete the correct node if the deleted node is the last node of the
list. Fix by not short circuiting on `Last == &N`.
Additionally, fix three other minor defects: (1) Do not loop infinitely
if node is not in list. Check for sentinel edge. (2) Reset intrusive
list on deleted node to point to itself with sentinel edge. (3) Avoid
multiple template instantiations of the implementation of deleteNode by
moving it to its base class.
Closes #207411.
Commit: 54a1ef1cceb90ac9db6639d0a400afef1328995b
https://github.com/llvm/llvm-project/commit/54a1ef1cceb90ac9db6639d0a400afef1328995b
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Report PHI as opcode in getOpcodeOrIntrinsicID (#209250)
Avoid reporting Instruction::PHI as an intrinsic ID, fixing a bug
exposed in downstream CHERIoT.
Reported-by: Owen Anderson <resistor at mac.com>
Commit: de754b87a6c57b7d5ebb4cbd0fd9ef0c8ba7512d
https://github.com/llvm/llvm-project/commit/de754b87a6c57b7d5ebb4cbd0fd9ef0c8ba7512d
Author: Umang Yadav <29876643+umangyadav at users.noreply.github.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M mlir/lib/ExecutionEngine/CMakeLists.txt
M mlir/lib/ExecutionEngine/RocmRuntimeWrappers.cpp
Log Message:
-----------
[MLIR][ROCm] Build mlir_rocm_runtime STANDALONE (#205651)
Build `mlir_rocm_runtime` as a standalone runtime library by removing
its last
source-level dependency on LLVM support utilities.
`mlir_rocm_runtime` is intended to be loaded dynamically by tools such
as
`mlir-runner` via `--shared-libs`. However, `add_mlir_library` links
`LLVMSupport` by default unless the target is marked `STANDALONE`. The
ROCm
runtime was previously left on `DISABLE_PCH_REUSE` as a workaround
because
`RocmRuntimeWrappers.cpp` still used `llvm::SmallVector` and
`llvm::ArrayRef`
inside `mgpuMemHostRegisterMemRef`.
This patch replaces that small LLVM ADT use with equivalent plain C++
logic and
marks `mlir_rocm_runtime` `STANDALONE`, matching the CUDA runtime.
## Motivation
This follows the direction from prior upstream changes:
-
[`4edc9e2acf1d`](https://github.com/llvm/llvm-project/commit/4edc9e2acf1d9350ce4da77c93e8869f774a24e2)
/
[D108684](https://reviews.llvm.org/D108684), by Uday Bondhugula, removed
the
same `SmallVector`/`ArrayRef` dependency from CUDA's
`mgpuMemHostRegisterMemRef`, noting that the dependency on `LLVMSupport`
adds
unnecessary complexity for external users linking or loading the
runtime.
-
[`351ae0ca550c`](https://github.com/llvm/llvm-project/commit/351ae0ca550c791b0c504dfb7dcb4fd08480d98b)
/
[#182850](https://github.com/llvm/llvm-project/pull/182850) made several
dlopen-able MLIR runtime libraries `STANDALONE`, including
`mlir_cuda_runtime`, and left `mlir_rocm_runtime` on `DISABLE_PCH_REUSE`
only
because it still depended on `LLVMSupport`.
-
[`78f259fcc14b`](https://github.com/llvm/llvm-project/commit/78f259fcc14bb0a567d45ba394fcde48de2bc299)
/
[#182942](https://github.com/llvm/llvm-project/pull/182942) applied the
same
cleanup pattern to `mlir_levelzero_runtime` by removing a small
remaining LLVM
dependency and marking the runtime `STANDALONE`.
With the remaining LLVM ADT use removed from the ROCm wrapper, the
workaround is
no longer needed.
## Testing
Verified and tested downstream in rocMLIR.
No new upstream test is added. This is a build/linkage cleanup for a
runtime
library that is already exercised by the ROCm integration tests when
`MLIR_ENABLE_ROCM_RUNNER` is enabled.
The rewritten dense-stride computation in `mgpuMemHostRegisterMemRef` is
equivalent to the previous implementation and matches the existing CUDA
runtime
implementation.
## AI Assistance Disclosure
Assisted-by: GPT-5.5
I reviewed the generated content and verified the changes before
submitting,
including testing them downstream in rocMLIR.
---------
Co-authored-by: Cursor <cursoragent at cursor.com>
Commit: 84804d9a0bd7fcdaf8d218d3385b58d012c1129e
https://github.com/llvm/llvm-project/commit/84804d9a0bd7fcdaf8d218d3385b58d012c1129e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/test/CodeGen/AArch64/expand-vector-rot.ll
M llvm/test/CodeGen/AArch64/fsh.ll
M llvm/test/CodeGen/AArch64/funnel-shift-rot.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/ARM/funnel-shift-rot.ll
M llvm/test/CodeGen/Mips/funnel-shift-rot.ll
M llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll
M llvm/test/CodeGen/PowerPC/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/rotl-rotr.ll
Log Message:
-----------
[LegalizeTypes] Improve promotion of variable rotates. (#208610)
If the promoted type is at least 2x the original type, we can
concat the value with itself into the promoted bits and use a
shl/srl. This is easier than negating the shift amount for the
(or (shl), (srl)) expansion. This is what we do for promoting
funnel shifts and really a rotate is a special case of funnel shift.
Commit: 6a91acc642db38a6e214f1b917882c75d6fb728b
https://github.com/llvm/llvm-project/commit/6a91acc642db38a6e214f1b917882c75d6fb728b
Author: Matt <MattPD at users.noreply.github.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M flang/lib/Semantics/mod-file.cpp
A flang/test/Lower/OpenMP/declare-mapper-hermetic.f90
Log Message:
-----------
[flang][OpenMP] Keep hermetic embedded module parse tree alive (#207491)
Fix a use-after-free when lowering materializes an imported declare mapper or
declare reduction owned by a module embedded in a hermetic module file
(-fhermetic-module-files).
ModFileReader::Read resolved the embedded modules from a local parser::Program
that was destroyed when Read returned, leaving the symbols resolved from it
dangling. MapperDetails and UserReductionDetails hold raw parse-tree pointers, so
a consumer that later materializes such an imported declaration dereferenced
freed memory.
Retain the embedded parse tree in the SemanticsContext with SaveParseTree, as the
primary module's tree already is, so those pointers stay valid through lowering.
The new test covers materializing an imported declare mapper from an embedded
module.
Assisted-by: Claude Opus 4.8, GPT-5.5.
Commit: 3688619bd98b36a72da219cec5f44ecbe4bbfa97
https://github.com/llvm/llvm-project/commit/3688619bd98b36a72da219cec5f44ecbe4bbfa97
Author: Matt <MattPD at users.noreply.github.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M flang/lib/Semantics/mod-file.cpp
A flang/test/Semantics/OpenMP/declare-reduction-operator-modfile-reexport.f90
Log Message:
-----------
[flang][OpenMP] Do not emit a use-only item for an operator reduction in a module file (#207492)
Stop writing a module file that cannot be re-parsed (reading it crashes) when a
module re-exports a USE-associated user-defined operator declare reduction.
Such a reduction is represented by an internal symbol whose name is the mangled
operator (e.g. "op.remote." or "op.+"), which is not valid Fortran. The
module-file writer emitted it as a `use MODULE, only: op.remote.` item, which the
reader cannot parse. This affected both a plain re-export facade and an embedded
module in a hermetic module file.
Skip the use-only item for a reduction whose operator is itself re-exported (a
defined operator, or an intrinsic operator with a user interface): the reduction
is re-exported implicitly with that operator, which is emitted, and the reduction
resolver recovers it from there (FindUserReductionSymbol). This covers a
derived-type `operator(+)` reduction as well as a defined operator like
`.remote.`.
The test checks the re-exporting module file round-trips and that a consumer
reading it resolves the reduction through the operator.
Assisted-by: Claude Opus 4.8, GPT-5.5.
Commit: 67ebc4b221c3e94028b33004cd5cd08deee95048
https://github.com/llvm/llvm-project/commit/67ebc4b221c3e94028b33004cd5cd08deee95048
Author: Tom Stellard <tstellar at redhat.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M .github/workflows/release-binaries-all.yml
Log Message:
-----------
workflows/release-binaries-all: Test PRs that modify build_llvm_release.bat (#208769)
Commit: eb5bc2694a05229bb9270eb141cd8fa499a185c1
https://github.com/llvm/llvm-project/commit/eb5bc2694a05229bb9270eb141cd8fa499a185c1
Author: Emmett <emmettzhang2020 at outlook.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M libcxx/docs/Status/Cxx26Issues.csv
M libcxx/include/__memory/unique_ptr.h
A libcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.class/non_pointable.single.verify.cpp
Log Message:
-----------
[libc++][unique_ptr] Implement LWG 4144: Disallow unique_ptr<T&, D> (#209018)
Implement [LWG 4144](https://cplusplus.github.io/LWG/issue4144) by
explicitly rejecting `unique_ptr<T, D>` when `T*` is not a valid type.
This adds a pointability check and tests reference and abominable
function types.
Fixes #118359
Commit: 7633d1e7a0f33630e6d10c5640bf4ad35dc2c23d
https://github.com/llvm/llvm-project/commit/7633d1e7a0f33630e6d10c5640bf4ad35dc2c23d
Author: Paul Kirth <paulkirth at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang-tools-extra/clang-doc/CMakeLists.txt
R clang-tools-extra/clang-doc/markdown/CMakeLists.txt
R clang-tools-extra/clang-doc/markdown/Markdown.cpp
R clang-tools-extra/clang-doc/markdown/Markdown.h
M clang-tools-extra/unittests/clang-doc/CMakeLists.txt
R clang-tools-extra/unittests/clang-doc/MarkdownParserTest.cpp
Log Message:
-----------
[clang-doc] Remove Markdown library implementation (#209257)
The current implementation is unsatisfactory in many ways, and it is now
unclear if development of this library will continue any time soon. To
reduce maintenance and build cost, we should just remove it now before
the branch point, and come up with a more thoughtful design that
addresses the requirements for clang and clang-doc more completely.
This reverts commit cc048e80b670a5262500612069d1c2d065b53f15 and commit
b6976d223eeb40091685e3b20e9c41f42f6bd6e0.
Commit: cc615d117c7f942a508ceecedd519f2fe9921493
https://github.com/llvm/llvm-project/commit/cc615d117c7f942a508ceecedd519f2fe9921493
Author: Doug Wyatt <doug at sonosphere.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaFunctionEffects.cpp
M clang/test/Sema/attr-nonblocking-constraints.cpp
Log Message:
-----------
[clang][Sema] Function effect analysis was missing the implicit call to the destructor in a CXXDeleteExpr. (#184460)
Co-authored-by: Doug Wyatt <dwyatt at apple.com>
Commit: 9c8bdc79908f9b34207caa738185f877b6cae93e
https://github.com/llvm/llvm-project/commit/9c8bdc79908f9b34207caa738185f877b6cae93e
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/clang-tools-extra/clang-doc/BUILD.bazel
M utils/bazel/llvm-project-overlay/clang-tools-extra/unittests/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 7633d1e (#209268)
This fixes 7633d1e7a0f33630e6d10c5640bf4ad35dc2c23d.
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=7633d1e7a0f33630e6d10c5640bf4ad35dc2c23d
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 172464f2b665bd169658fbafb10e61c1882042ff
https://github.com/llvm/llvm-project/commit/172464f2b665bd169658fbafb10e61c1882042ff
Author: Paul Osmialowski <pawel.osmialowski at arm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/Interpreter/IncrementalExecutor.cpp
R clang/test/Interpreter/emulated-tls.cpp
M llvm/lib/ExecutionEngine/Orc/Layer.cpp
Log Message:
-----------
Revert "Reland "[ORC] Track __emutls_t definitions in IRMaterializationUnit" (#207161) (#208413)" (#209260)
This causes the failures on various CIs with various archs a day before
branching.
Commit: 39fefb706834fa8e171b0c699b6e91e4d4a0d831
https://github.com/llvm/llvm-project/commit/39fefb706834fa8e171b0c699b6e91e4d4a0d831
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/test/CodeGen/AArch64/elf-pauthabi.c
M clang/test/CodeGen/ptrauth-module-flags.c
M clang/test/CodeGenCXX/pfp-memcpy.cpp
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/test/CodeGen/AArch64/arm64-tls-dynamics.ll
M llvm/test/CodeGen/AArch64/basic-pic.ll
M llvm/test/CodeGen/AArch64/build-attributes-pauthabi.ll
M llvm/test/CodeGen/AArch64/elf-globals-pic.ll
M llvm/test/CodeGen/AArch64/extern-weak.ll
M llvm/test/CodeGen/AArch64/got-abuse.ll
M llvm/test/CodeGen/AArch64/note-gnu-property-elf-pauthabi.ll
M llvm/test/CodeGen/AArch64/ptrauth-elf-got-function-symbols.ll
M llvm/test/CodeGen/AArch64/tagged-globals-pic.ll
M llvm/test/CodeGen/AArch64/tiny-model-pic.ll
M llvm/test/CodeGen/AArch64/tiny-model-static.ll
Log Message:
-----------
[PAC][clang] Fix ptrauth module flags behavior (#204226)
The `Error` merge behavior only has effect when module flags values
mismatch, while it allows the flag being present in one module and
absent in another one. Thus, we were previously incorrectly treating
modules as compatible in case of presence of
`ptrauth-elf-got`/`ptrauth-sign-personality` in one module (meaning the
corresponding ptrauth feature is enabled) and its absence in another
module (meaning the corresponding ptrauth feature is disabled). Similar
problem was present for `aarch64-elf-pauthabi-{platform|version}` flags
as well.
This patch introduces the following.
1. Always emit `ptrauth-elf-got` module flag for AArch64 ELF targets and
`ptrauth-sign-personality` module flag for AArch64 Linux targets. The
value of the flags is either 0 or 1.
2. Always emit `aarch64-elf-pauthabi-platform` and
`aarch64-elf-pauthabi-version` module flags for AArch64 Linux targets
(with `aarch64-elf-pauthabi-platform` set to
`AARCH64_PAUTH_PLATFORM_LLVM_LINUX` constant). Previously, these were
only emitted with `aarch64-elf-pauthabi-version != 0` (0 value stands
for no ptrauth features enabled). To keep emitted binaries unchanged in
case of version value of 0, this case is filtered out by backend in
`AArch64AsmPrinter::emitStartOfAsmFile`.
Commit: d7063b00431358c0202a04e67f4824e20244b26f
https://github.com/llvm/llvm-project/commit/d7063b00431358c0202a04e67f4824e20244b26f
Author: lianjinfeng2003 <101249452+mygitljf at users.noreply.github.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Fix a crash on triple-bracket input like `[[[a]]` (#199103)
## Summary
`clang-format` aborts on triple-bracket input like `[[[a]]` with
`Assertion 'Left.isNot(tok::l_square)' failed.` This patch fixes the
crash by rejecting the C++ attribute classification when the candidate
`[[` is itself preceded by another `[`.
## Solution
Add one defensive check to `isCppAttribute` that mirrors the existing
ObjC-array-literal exclusion: bail out when `Tok.Previous` is another
`[`.
Fixes #199010
Commit: c3452bee412e97178ab04b924300f3953b4690f5
https://github.com/llvm/llvm-project/commit/c3452bee412e97178ab04b924300f3953b4690f5
Author: lntue <lntue at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/test/UnitTest/ErrnoSetterMatcher.h
M libc/test/src/sys/mman/linux/CMakeLists.txt
M libc/test/src/sys/mman/linux/madvise_test.cpp
M libc/test/src/sys/mman/linux/mincore_test.cpp
M libc/test/src/sys/mman/linux/mlock_test.cpp
M libc/test/src/sys/mman/linux/mremap_test.cpp
M libc/test/src/sys/mman/linux/posix_madvise_test.cpp
M libc/test/src/sys/socket/linux/sendrecvmmsg_test.cpp
M libc/test/src/sys/socket/linux/socketopt_test.cpp
M libc/test/src/sys/socket/linux/socketpair_test.cpp
M libc/test/src/unistd/pread_pwrite_test.cpp
M libc/test/src/unistd/read_write_test.cpp
Log Message:
-----------
[libc] Update some syscall tests to be more tolerance to QEMU behaviors. (#208920)
Also expand ErrnoSetterMatcher to allow multiple errnos.
This will allow us to enable riscv64 qemu precommit CI.
To be revisited next year to see whether those are still needed by then:
https://github.com/llvm/llvm-project/issues/209273
Assisted-by: Gemini 3.5 Flash
Commit: 69c3406d985a1d15bf537574c1a217f2b72b578e
https://github.com/llvm/llvm-project/commit/69c3406d985a1d15bf537574c1a217f2b72b578e
Author: Kewen Meng <Kewen.Meng at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M offload/ci/openmp-offload-amdgpu-libc-runtime.py
M offload/ci/openmp-offload-amdgpu-runtime.py
Log Message:
-----------
[OpenMP][AMDGPU][CI] Update build scripts for AMDGPU bots (#209274)
This should fix the error in bot:
https://lab.llvm.org/buildbot/#/builders/10/builds/31765
Commit: a9804ae41bceff2f169affa5b35506606a965880
https://github.com/llvm/llvm-project/commit/a9804ae41bceff2f169affa5b35506606a965880
Author: arhwx <arahwrm at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/AST/ExprConstant.cpp
A clang/test/SemaCXX/atomic-constexpr.cpp
Log Message:
-----------
[clang] Fix crash on subobject access through _Atomic in constant evaluation (#208923)
`findSubobject()` didn't look through `AtomicType` while walking a
designator, so reaching a subobject of an object wrapped in `_Atomic`
crashed: a null `CXXRecordDecl` deref for base classes (the segfault in
the issue) and a `cast<RecordType>` assertion for fields. The value of
an atomic object is already represented like a value of the underlying
type, so it's enough to look through the wrapper before dispatching on
the subobject kind.
The crash goes back to clang 9, and the new bytecode interpreter already
handles this correctly, but the test covers both evaluators anyway, at
C++14 (the earliest standard that can hit the crash) and at C++20 (so
`constinit` can verify the initializers are indeed constant).
Fixes #203328
Commit: f049aa1e9bc071fdf366baec337baa970b6b23c4
https://github.com/llvm/llvm-project/commit/f049aa1e9bc071fdf366baec337baa970b6b23c4
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/Driver/Driver.cpp
Log Message:
-----------
clang: Remove dead getConflictOffloadArchCombination virtual (#209271)
Commit: 3e1d5e38bd9383001a6a2abff2e0fdcdf1e8313f
https://github.com/llvm/llvm-project/commit/3e1d5e38bd9383001a6a2abff2e0fdcdf1e8313f
Author: Akshat Dalal <adalal at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
M llvm/test/Transforms/LowerMatrixIntrinsics/dot-product-float.ll
M llvm/test/Transforms/LowerMatrixIntrinsics/dot-product-int.ll
A llvm/test/Transforms/LowerMatrixIntrinsics/dot-product-volatile-align.ll
Log Message:
-----------
[LowerMatrixIntrinsics] Preserve volatile and alignment when flattening loads (#205759)
The dot-product flatten path rebuilt a matrix.column.major.load with
Builder.CreateLoad, dropping the volatile flag and the load's specified
alignment. Dropping volatile is a miscompile, and falling back to the
type's default ABI alignment can over-claim and fault on
alignment-sensitive targets.
We should instead use CreateAlignedLoad with the intrinsic's volatile
operand and getAlignForIndex, matching the non-fused load lowering in
loadMatrix() (the standard LowerColumnMajorLoad path), which already
preserves both.
Commit: ecac7b9e48cdc98f71c7c40c05055f7ebc652d98
https://github.com/llvm/llvm-project/commit/ecac7b9e48cdc98f71c7c40c05055f7ebc652d98
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
M lldb/test/API/lit.cfg.py
M lldb/test/CMakeLists.txt
M lldb/test/Shell/lit.cfg.py
Log Message:
-----------
[lldb][Windows] Default to lldb-server when libxml2 is available (#209258)
Select the debugging backend based on libxml2 availability, which is
required to parse the gdb-remote target description XML.
At runtime, `ProcessWindows::ShouldUseLLDBServer()` now honors an
explicit `LLDB_USE_LLDB_SERVER` environment variable if set, and
otherwise defaults to lldb-server when `LLDB_ENABLE_LIBXML2` is on,
falling back to the in-process Windows process plugin when it is not.
In the test suite, `LLDB_TEST_USE_LLDB_SERVER` now defaults to `ON` when
building on Windows with libxml2 available. The lit configs set
`LLDB_USE_LLDB_SERVER` explicitly to 1 or 0 so the test configuration is
authoritative regardless of the compiled-in default.
rdar://174236280
Commit: 9879da4f929d7948fc27af56cde0bc85f1d919e3
https://github.com/llvm/llvm-project/commit/9879da4f929d7948fc27af56cde0bc85f1d919e3
Author: Dan Bonachea <dobonachea at lbl.gov>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M flang/docs/FortranStandardsSupport.md
Log Message:
-----------
[flang][docs] Document multi-image support status (#209025)
Update `flang/docs/FortranStandardsSupport.md` to reflect the current
state of multi-image (coarray) feature support.
The previous list of multi-image features was incomplete, and several
multi-image features added in F2008 were inaccurately listed in the
F2018 section.
Recent PRs adding functionality now reflected in this document include:
* #205847
* #192944
* #182110
Older (pre-22) PRs adding functionality that was not previously
mentioned include:
* #154081
* #154166
Commit: eb3275a0c3808d2705969c7570675346737b31b8
https://github.com/llvm/llvm-project/commit/eb3275a0c3808d2705969c7570675346737b31b8
Author: David Green <david.green at arm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc-bf16.ll
Log Message:
-----------
[AArch64] Lower fixed width bf16 fpext (#209194)
This was previously hitting an error with a illegal
FP_EXTEND_MERGE_PASSTHRU being created but not selectable. Split
bf16->f64 fpext into bf16->f32 and f32->f64 fpext as we do elsewhere
(the first step has no rounding).
The codegen for loads is pretty inefficient because the load gets
expanded / scalarized.
Commit: 6bbd5a18f672a4e6cd19e2e2763d6877dd5f3832
https://github.com/llvm/llvm-project/commit/6bbd5a18f672a4e6cd19e2e2763d6877dd5f3832
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M libcxx/test/tools/clang_tidy_checks/abi_tag_on_virtual.cpp
M libcxx/test/tools/clang_tidy_checks/empty_namespaces.cpp
M libcxx/test/tools/clang_tidy_checks/header_exportable_declarations.cpp
M libcxx/test/tools/clang_tidy_checks/hide_from_abi.cpp
M libcxx/test/tools/clang_tidy_checks/libcpp_module.cpp
M libcxx/test/tools/clang_tidy_checks/robust_against_adl.cpp
M libcxx/test/tools/clang_tidy_checks/robust_against_operator_ampersand.cpp
M libcxx/test/tools/clang_tidy_checks/uglify_attributes.cpp
Log Message:
-----------
[libcxx] Avoid including deprecated ClangTidyModuleRegistry.h (#208945)
Deprecated in 1bcf74006bcf528d14377173dba459759d35c961. Causes warnings
during compilation and will presumably become an error.
Commit: 612e7ca85c53e85a7444bfc23e763a756a50f69a
https://github.com/llvm/llvm-project/commit/612e7ca85c53e85a7444bfc23e763a756a50f69a
Author: Ziqing Luo <ziqing_luo at apple.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
R clang/include/clang/ScalableStaticAnalysis/Analyses/OperatorNewDelete/OperatorNewDeletePointers.h
A clang/include/clang/ScalableStaticAnalysis/Analyses/TypeConstrainedPointers/TypeConstrainedPointers.h
M clang/include/clang/ScalableStaticAnalysis/BuiltinAnchorSources.def
M clang/lib/ScalableStaticAnalysis/Analyses/CMakeLists.txt
R clang/lib/ScalableStaticAnalysis/Analyses/OperatorNewDelete/OperatorNewDeletePointers.cpp
A clang/lib/ScalableStaticAnalysis/Analyses/TypeConstrainedPointers/TypeConstrainedPointers.cpp
R clang/test/Analysis/Scalable/OperatorNewDelete/Inputs/tu-summary-bad-id.json
R clang/test/Analysis/Scalable/OperatorNewDelete/Inputs/tu-summary-no-key.json
R clang/test/Analysis/Scalable/OperatorNewDelete/Inputs/tu-summary.json
R clang/test/Analysis/Scalable/OperatorNewDelete/Inputs/wpa-result-bad-id.json
R clang/test/Analysis/Scalable/OperatorNewDelete/Inputs/wpa-result-empty.json
R clang/test/Analysis/Scalable/OperatorNewDelete/Inputs/wpa-result-no-key.json
R clang/test/Analysis/Scalable/OperatorNewDelete/operator-new-delete.cpp
R clang/test/Analysis/Scalable/OperatorNewDelete/tu-summary-serialization.test
R clang/test/Analysis/Scalable/OperatorNewDelete/wpa-result-serialization.test
A clang/test/Analysis/Scalable/TypeConstrainedPointers/Inputs/tu-summary-bad-id.json
A clang/test/Analysis/Scalable/TypeConstrainedPointers/Inputs/tu-summary-no-key.json
A clang/test/Analysis/Scalable/TypeConstrainedPointers/Inputs/tu-summary.json
A clang/test/Analysis/Scalable/TypeConstrainedPointers/Inputs/wpa-result-bad-id.json
A clang/test/Analysis/Scalable/TypeConstrainedPointers/Inputs/wpa-result-empty.json
A clang/test/Analysis/Scalable/TypeConstrainedPointers/Inputs/wpa-result-no-key.json
A clang/test/Analysis/Scalable/TypeConstrainedPointers/tu-summary-serialization.test
A clang/test/Analysis/Scalable/TypeConstrainedPointers/type-constrained-pointers.cpp
A clang/test/Analysis/Scalable/TypeConstrainedPointers/wpa-result-serialization.test
R clang/unittests/ScalableStaticAnalysis/Analyses/OperatorNewDelete/OperatorNewDeletePointersExtractorTest.cpp
A clang/unittests/ScalableStaticAnalysis/Analyses/TypeConstrainedPointers/TypeConstrainedPointersExtractorTest.cpp
M clang/unittests/ScalableStaticAnalysis/CMakeLists.txt
Log Message:
-----------
[SSAF][NFC] Rename operator new/delete pointers analysis to TypeConstrainedPointers (#208577)
There will be more such pointer entities that must retain their type
during the clang-reforge transformation. Since they are extracted and
processed similarly, combining them into a single analysis simplifies
maintenance. Therefore, we are using TypeConstrainedPointers as the
umbrella name.
Commit: 7753c44fc3132e58ae3ee928958d51e2be6735e9
https://github.com/llvm/llvm-project/commit/7753c44fc3132e58ae3ee928958d51e2be6735e9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/Driver/ToolChains/CommonArgs.cpp
Log Message:
-----------
clang/AMDGPU: Remove StringSwitch over r600 aliases (#209256)
This will route to getArchNameR600 which should already handle
all the aliases.
Commit: 41388b1d74d4fa973db029de6ef89c03149bcb19
https://github.com/llvm/llvm-project/commit/41388b1d74d4fa973db029de6ef89c03149bcb19
Author: lntue <lntue at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M .github/workflows/libc-overlay-tests.yml
Log Message:
-----------
[libc] Add riscv64 qemu precommit CI for overlay mode. (#192816)
Commit: 76a21c86af48dc1f0c0fbcca33145c26a2ef328b
https://github.com/llvm/llvm-project/commit/76a21c86af48dc1f0c0fbcca33145c26a2ef328b
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
A .github/workflows/libcxx-benchmark-commit.yml
Log Message:
-----------
[libc++] Add a workflow to run libc++ benchmarks on historical commits (#208080)
This allows triggering a workflow that benchmarks a given commit on both
macOS and Linux, and optionally submits the results to a LNT instance
(by default lnt.llvm.org).
Triggering this workflow requires write access to the LLVM monorepo, so
the inputs can be trusted to a large extent.
The intent is for this workflow to be triggered semi-automatically by a
combination of scripts and manual intervention. For example, we can
reuse a script like libcxx/utils/ci/lnt/commit-watch to automatically
trigger the workflow on new commits, while also requesting new commits
when bisecting regressions, etc. Since workflows can be dispatched via
the Github API, this should easily be scriptable.
A few important improvements are currently missing from this workflow
and left for future patches:
- The ability to select only a subset of configurations to run
- Additional configurations, such as unstable ABI, hardening, etc.
Commit: 3287d11199c644193cbf5829d3786aec41723d28
https://github.com/llvm/llvm-project/commit/3287d11199c644193cbf5829d3786aec41723d28
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M .github/workflows/libcxx-pr-benchmark.yml
Log Message:
-----------
[libc++] Switch PR benchmark job to llvm-premerge-libcxx-runners (#209267)
Like #208928 but for the PR benchmarking job.
Commit: 2987984f1ec8f019f99c0f9f6de1930b609caba2
https://github.com/llvm/llvm-project/commit/2987984f1ec8f019f99c0f9f6de1930b609caba2
Author: Jackson Stogel <jtstogel at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M libc/include/limits.yaml
M libc/include/llvm-libc-macros/limits-macros.h
Log Message:
-----------
[libc] Define NAME_MAX in limits.h (#209296)
Defines the POSIX macro `NAME_MAX`. Will be used by `realpath` tests.
Commit: c09fc4b786a3a49c350cecc696e21473c86ba330
https://github.com/llvm/llvm-project/commit/c09fc4b786a3a49c350cecc696e21473c86ba330
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M libcxx/utils/libcxx/test/dsl.py
Log Message:
-----------
[libcxx][test] Fingerprint the compiler when memoizing results (#208311)
This fixes a cache invalidation problem with flag support checks when
rebasing & re-building the just-built clang.
Commit: 9367769576a73771e227a0921b2103792c5a69a9
https://github.com/llvm/llvm-project/commit/9367769576a73771e227a0921b2103792c5a69a9
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M lld/docs/ReleaseNotes.rst
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
[docs] Add ARM64X release notes (NFC) (#209249)
Commit: d90f3050c354b264c7156b8180b9ec1ab09c14c7
https://github.com/llvm/llvm-project/commit/d90f3050c354b264c7156b8180b9ec1ab09c14c7
Author: Ziqing Luo <ziqing_luo at apple.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/include/clang/ScalableStaticAnalysis/Analyses/TypeConstrainedPointers/TypeConstrainedPointers.h
M clang/lib/ScalableStaticAnalysis/Analyses/TypeConstrainedPointers/TypeConstrainedPointers.cpp
M clang/test/Analysis/Scalable/TypeConstrainedPointers/type-constrained-pointers.cpp
M clang/unittests/ScalableStaticAnalysis/Analyses/TypeConstrainedPointers/TypeConstrainedPointersExtractorTest.cpp
Log Message:
-----------
[SSAF][TypeConstrainedPointers] Add pointer parameters of 'main' as constrained pointers (#208578)
Similar to some pointer entities of operator new/delete overload
functions, pointer type parameters of the main function shall also
retain its type during clang-reforge transformation.
rdar://179151882
---------
Co-authored-by: Balázs Benics <benicsbalazs at gmail.com>
Commit: acbc7e571c3aa6f23672f84f5ea76cd41345a3a2
https://github.com/llvm/llvm-project/commit/acbc7e571c3aa6f23672f84f5ea76cd41345a3a2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/test/Misc/target-invalid-cpu-note/amdgcn.c
Log Message:
-----------
clang/AMDGPU: Validate -target-cpu in cc1 is valid for the subarch (#206481)
Restrict the reported list of valid target-cpus based on the triple's
subarch. This is more consistent with how other targets validate the
target CPU name. Currently we have split handling validating the target
name for the triple in both the driver and here. The driver based
diagnostic seems to be an amdgpu-ism in 2 different places (though there
is one arm validation emitting the same diagnostic). In the future we could
probably drop those.
Commit: 0661f6636a0a5a79635e99d98a239c2bba4ea2ed
https://github.com/llvm/llvm-project/commit/0661f6636a0a5a79635e99d98a239c2bba4ea2ed
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
A mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsReduction.h
M mlir/lib/Dialect/OpenACC/Utils/CMakeLists.txt
A mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsReduction.cpp
M mlir/unittests/Dialect/OpenACC/CMakeLists.txt
A mlir/unittests/Dialect/OpenACC/OpenACCUtilsReductionTest.cpp
Log Message:
-----------
[mlir][acc] Add reduction utilities for acc to gpu lowering (#209316)
In preparation for the pass that converts `acc.compute_region` to GPU
dialect, this PR adds several utilities which are used in that pass
related to reductions. Doing so to simplify review and to ensure that
unit testing is added for the utilities.
---------
Co-authored-by: Scott Manley <rscottmanley at gmail.com>
Commit: 51b2a5de73637e7d93cc066ced669d5db2bd8775
https://github.com/llvm/llvm-project/commit/51b2a5de73637e7d93cc066ced669d5db2bd8775
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
Log Message:
-----------
[RISCV][P-ext] Fix incorrect shift mask on variable shift instructions. (#209293)
The instructions are defined to read 5 bits regardless of element size.
I think we will also need to change the C intrinsics to allow 5 bit
shift amounts, but we can do that in a separate patch.
Commit: 4743729038650237f094073ad92edaa524a9261f
https://github.com/llvm/llvm-project/commit/4743729038650237f094073ad92edaa524a9261f
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 0661f66 (#209319)
This fixes 0661f6636a0a5a79635e99d98a239c2bba4ea2ed.
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=0661f6636a0a5a79635e99d98a239c2bba4ea2ed
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 5801213a1baaa750dd2c0152ca0e5288d447d908
https://github.com/llvm/llvm-project/commit/5801213a1baaa750dd2c0152ca0e5288d447d908
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
Log Message:
-----------
[ConstraintElim] Check loop pred & invariance before SCEV query (NFC) (#209314)
Move cheap checks (check for loop predecessor and invariance) before
more expensive SCEV queries.
This slightly reduces the number we need to unnecessarily construct SCEV
expressions.
Commit: 8d251a44830c869feb7d7d1db4fec8474f5a7ca8
https://github.com/llvm/llvm-project/commit/8d251a44830c869feb7d7d1db4fec8474f5a7ca8
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
Log Message:
-----------
[RISCV][P-ext] Move v2i16 and v4i8 extract_subvector handling to tablegen. NFC (#208863)
Commit: c6ebd7a2ced7fa3c984a857d6dcb433d95dd014d
https://github.com/llvm/llvm-project/commit/c6ebd7a2ced7fa3c984a857d6dcb433d95dd014d
Author: Erick Velez <erickvelez7 at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang-tools-extra/clang-doc/CMakeLists.txt
M clang-tools-extra/clang-doc/Generators.cpp
M clang-tools-extra/clang-doc/Generators.h
M clang-tools-extra/clang-doc/JSONGenerator.cpp
M clang-tools-extra/clang-doc/MDGenerator.cpp
R clang-tools-extra/clang-doc/MDMustacheGenerator.cpp
M clang-tools-extra/clang-doc/Representation.h
M clang-tools-extra/clang-doc/tool/ClangDocMain.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-doc/basic-project.mustache.test
M clang-tools-extra/test/clang-doc/basic-project.test
M clang-tools-extra/test/clang-doc/md/array-type.cpp
M clang-tools-extra/test/clang-doc/md/builtin_types.cpp
M clang-tools-extra/test/clang-doc/md/class-partial-specialization.cpp
M clang-tools-extra/test/clang-doc/md/comments-in-macros.cpp
M clang-tools-extra/test/clang-doc/md/enum.cpp
M clang-tools-extra/test/clang-doc/md/function-pointer-type.cpp
M clang-tools-extra/test/clang-doc/md/member-function-pointer-type.cpp
M clang-tools-extra/test/clang-doc/md/namespace.cpp
M clang-tools-extra/test/clang-doc/md/nested-pointer-qualifiers.cpp
M clang-tools-extra/test/clang-doc/md/templates.cpp
M clang-tools-extra/unittests/clang-doc/CMakeLists.txt
R clang-tools-extra/unittests/clang-doc/MDGeneratorTest.cpp
Log Message:
-----------
[clang-doc] Remove deprecated Markdown generator (#209071)
Commit: dd77cf572833b0ee31b9516d83cfcc0af932604d
https://github.com/llvm/llvm-project/commit/dd77cf572833b0ee31b9516d83cfcc0af932604d
Author: aokblast <aokblast at FreeBSD.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/test/Interpreter/pch-pic-mismatch.cpp
Log Message:
-----------
[Clang][Interpreter] Fix pch-pic-mismatch for darwin platforms (#209183)
Darwin enforce PIC by default and ignores all -fno-pic option. We calls
cc1 directly as its PIC level is 0 by default. This fixes the new
introduced test pch-pic-mismatch.cpp
Commit: c70795ccd5f74aad7f3af9490f8b12a92c39c709
https://github.com/llvm/llvm-project/commit/c70795ccd5f74aad7f3af9490f8b12a92c39c709
Author: Farid Zakaria <fmzakari at fb.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/include/llvm/MC/MCTargetOptions.h
M llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/MC/MCObjectFileInfo.cpp
M llvm/lib/MC/MCTargetOptions.cpp
M llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
A llvm/test/CodeGen/AArch64/large-eh-encoding.ll
A llvm/test/CodeGen/X86/large-eh-encoding.ll
A llvm/test/MC/AArch64/large-eh-encoding.s
A llvm/test/MC/X86/large-eh-encoding.s
Log Message:
-----------
[MC][CodeGen] Add --large-eh-encoding flag for x86_64 & Aarch64 ELF (#174508)
Add a --large-eh-encoding option that forces 8-byte (DW_EH_PE_sdata8)
pointer encodings for all x86_64 & aarch64 ELF EH sections: FDE CFI
encoding, personality, LSDA, and TType encodings.
This is useful for large binaries where .text may exceed 2GB, causing
relocation overflows in .eh_frame and .gcc_except_table even under the
small or medium code model. The cost is purely in section size (a few
extra bytes per FDE/LSDA entry) with no runtime performance impact.
Commit: 2dcec161f68761495cbd24f50cb0f9277600a5ac
https://github.com/llvm/llvm-project/commit/2dcec161f68761495cbd24f50cb0f9277600a5ac
Author: Kazu Hirata <kazu at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/include/llvm/ProfileData/SampleProfReader.h
M llvm/unittests/ProfileData/SampleProfTest.cpp
Log Message:
-----------
[ProfileData] Remove clear() from SampleProfileFuncOffsetTable (NFC) (#209301)
This patch deletes the default constructor of
SampleProfileFuncOffsetTable and removes its clear() method.
SampleProfileFuncOffsetTable is designed to lock its operational mode
(in-memory or on-disk) strictly at construction time and remain valid
throughout its lifetime. By deleting the default constructor and
removing clear(), we ensure that an instance never enters an
uninitialized or cleared state while kept alive.
When SampleProfileReader needs to discard or reload the table, it
resets and replaces the wrapping std::optional directly instead of
clearing the table in-place.
Assisted-by: Antigravity
Commit: 2d142ad3b6c3c105356ead9575c7998c924fc64b
https://github.com/llvm/llvm-project/commit/2d142ad3b6c3c105356ead9575c7998c924fc64b
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lldb/include/lldb/Host/Host.h
M lldb/source/Host/common/Host.cpp
M lldb/source/Host/macosx/objcxx/Host.mm
Log Message:
-----------
[lldb/Host] Add `foreground` argument to `Host::OpenFileInExternalEditor` (#209331)
Add an optional `bool foreground` parameter to
`Host::OpenFileInExternalEditor` so callers can choose whether opening
the file should bring the editor to the foreground.
The macOS implementation maps `foreground=true` to omitting
`kLSLaunchDontSwitch` in the Launch Services flags, so the editor is
brought forward on launch. On non-Apple platforms the stub still returns
`ENOTSUP`; the new parameter is added to its signature so it matches the
declaration.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: d8636be51e34eb221054b1f70f0c73a901849f31
https://github.com/llvm/llvm-project/commit/d8636be51e34eb221054b1f70f0c73a901849f31
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsCG.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsGPU.h
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsCG.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsGPU.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsCGTest.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsGPUTest.cpp
Log Message:
-----------
[mlir][acc] Add utilities for acc to gpu lowering (#209313)
In preparation for the pass that converts `acc.compute_region` to GPU
dialect, this PR adds several utilities which are used in that pass.
Doing so to simplify review and to ensure that unit testing is added for
each of the utilities.
Commit: 96ad6fc9e86d7cb2dbd0ad1646b40219fd6a8fda
https://github.com/llvm/llvm-project/commit/96ad6fc9e86d7cb2dbd0ad1646b40219fd6a8fda
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/Analysis/OpenACCSupport.h
M mlir/lib/Dialect/OpenACC/Analysis/OpenACCSupport.cpp
Log Message:
-----------
[mlir][acc] Add inline implementation for emitNYI (#209337)
Commit: d3e11d415a7dd7b594a023830df71500a272a8ca
https://github.com/llvm/llvm-project/commit/d3e11d415a7dd7b594a023830df71500a272a8ca
Author: Kewen Meng <Kewen.Meng at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M offload/ci/openmp-offload-amdgpu-libc-runtime.py
Log Message:
-----------
[OpenMP][AMDGPU][CI] Fix libc build (#209336)
This PR attempts to fix the error:
```
llvm-lit: /home/botworker/builds/openmp-offload-amdgpu-runtime-2/llvm.src/llvm/utils/lit/lit/discovery.py:273: warning: input '/home/botworker/builds/openmp-offload-amdgpu-runtime-2/build/llvm.build/runtimes/runtimes-amdgpu-amd-amdhsa-bins/libc/test' contained no tests
error: did not discover any tests for provided path(s)
```
According to lib/test/CMakeList.txt, we need to set
`CMAKE_CROSSCOMPILING_EMULATOR` to avoid early return in the cmake. It
only changes the build script instead of the parent cmake cache file.
Not sure if this is the optimal solution, but it works for us.
Commit: 71a5f82e6dcd2d544d594c21a0bebb35af621ee5
https://github.com/llvm/llvm-project/commit/71a5f82e6dcd2d544d594c21a0bebb35af621ee5
Author: Mike Kruskal <mkruskal at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_common_nolibc.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_dl.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_dl.h
M compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
M compiler-rt/lib/tsan/go/buildgo.sh
M compiler-rt/test/sanitizer_common/TestCases/Linux/dlopen_image_base.c
Log Message:
-----------
[compiler-rt] [sanitizer_common] Fix SIGSEGV in ForEachMappedRegion for DSOs with custom image base (#206299)
`ForEachMappedRegion` processes dynamic linker map entries to track
loaded segments. However, it assumes map->l_addr is the address of the
ELF header. For DSOs linked with a custom preferred image base offset
(e.g. -Wl,--image-base=0x4000000), `map->l_addr` contains the relocation
bias: `map->l_addr = actual_load_address - preferred_base`
In this case, map->l_addr points below the first loaded segment in
unmapped or PROT_NONE memory. Doing a read dereference at this address
triggers a SIGSEGV. Add a call to dladdr() on the dynamic section
pointer map->l_ld to obtain the true ELF header base address.
Likely fixes #84482 - which looks like the exact same stacktrace I was
debugging that led me to this fix
Also looks it may have shown up in #21068 - my case was also flaky, and
it only shows up if you build the so with custom base address
Assisted-by: Gemini
Commit: 311c23c1c611c8677f2131943f24884e0bce7e9d
https://github.com/llvm/llvm-project/commit/311c23c1c611c8677f2131943f24884e0bce7e9d
Author: Wenju He <wenju.he at intel.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/IPO/Attributor.cpp
Log Message:
-----------
[Attributor][NFC] Drop unused arg `AG` from runAttributor*OnFunctions (#209103)
Commit: 68d6e2a5c3991bb87ac65958bd044d268b1f6c30
https://github.com/llvm/llvm-project/commit/68d6e2a5c3991bb87ac65958bd044d268b1f6c30
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/source/Utility/Listener.cpp
Log Message:
-----------
[lldb] update the listener logs (#195850)
Add the event mask the listener is waiting for.
Commit: b5314610b4f318a3986069f3abc65eb6cf3a86fe
https://github.com/llvm/llvm-project/commit/b5314610b4f318a3986069f3abc65eb6cf3a86fe
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/include/clang/Basic/PointerAuthOptions.h
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/test/CodeGen/ptrauth-init-fini.c
M clang/test/CodeGen/ptrauth-module-flags.c
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64PointerAuth.h
A llvm/test/CodeGen/AArch64/ptrauth-init-fini-autoupgrade.ll
M llvm/test/CodeGen/AArch64/ptrauth-init-fini.ll
Log Message:
-----------
[AArch64][PAC] Handle signing of init/fini pointers in AsmPrinter (#193087)
Move signing of the contents of `@llvm.global_(ctors|dtors)` from Clang
frontend to the AsmPrinter at the end of the backend pipeline.
Signing of the pointers to init/fini functions in the backend fixes
registration of the constructors and destructors performed by the
optimizer or the backend.
This commit introduces two new module flags, `ptrauth-init-fini` and
`ptrauth-init-fini-address-discrimination`, mirroring corresponding
Clang options. The flags are semantically boolean, an absent flag is
treated as having the `false` value and the latter flag requires the
former one. The particular constant discriminator to use is not
configurable via module flags and is hardcoded to the value 0xD9D4 in
the `llvm/lib/Target/AArch64/AArch64PointerAuth.h` file.
Commit: 4d7e653b523027ffb67a6ee7e439392431cbee2d
https://github.com/llvm/llvm-project/commit/4d7e653b523027ffb67a6ee7e439392431cbee2d
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsCGTest.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsGPUTest.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsReductionTest.cpp
Log Message:
-----------
[mlir][acc] Fix leaks in cg unit tests (#209339)
Newly added tests are failing valgrind --leak-check=full:
https://github.com/llvm/llvm-project/pull/209313
https://github.com/llvm/llvm-project/pull/209316
This PR resolves the problem by ensuring that the insertion point is set
into an operation that is owned and deleted by the test.
Commit: 14f8cccd02974067d81b173551bc301a33e26429
https://github.com/llvm/llvm-project/commit/14f8cccd02974067d81b173551bc301a33e26429
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/test/CXX/drs/cwg5xx.cpp
Log Message:
-----------
[clang] Trivial: fix test followup to #208586 (#209340)
Removes the spell-check disable from `clang/test/CXX/drs/cwg5xx.cpp`,
works around spell check noise by renaming a declaration instead.
Commit: 89fc46ec511681a8fa56974295525d960538b88c
https://github.com/llvm/llvm-project/commit/89fc46ec511681a8fa56974295525d960538b88c
Author: Richard Smith <richard at metafoo.co.uk>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/compiler-rt/BUILD.bazel
Log Message:
-----------
Exclude libc math C++ builtins from compiler-rt Bazel overlay (#208861)
In CMake, addtf3.cpp is only compiled when COMPILER_RT_USE_LIBC_MATH is
ON, replacing addtf3.c. In the Bazel overlay, builtins_generic_srcs
globbed all lib/builtins/*.cpp without excluding addtf3.cpp, causing
compile failures when not using libc math.
Assisted-by: Gemini via Antigravity
Commit: 25d50e7a0fe4cf42ca9351fc95528ac3e3c7a463
https://github.com/llvm/llvm-project/commit/25d50e7a0fe4cf42ca9351fc95528ac3e3c7a463
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
R lldb/include/lldb/Interpreter/Interfaces/ScriptedStopHookInterface.h
M lldb/include/lldb/Interpreter/ScriptInterpreter.h
M lldb/include/lldb/Target/Target.h
M lldb/include/lldb/lldb-forward.h
M lldb/source/Plugins/ScriptInterpreter/Python/CMakeLists.txt
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedHookPythonInterface.h
R lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedStopHookPythonInterface.cpp
R lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedStopHookPythonInterface.h
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
M lldb/source/Target/Target.cpp
Log Message:
-----------
[lldb] Unify `ScriptedStopHookInterface` with `ScriptedHookInterface` (#209341)
`ScriptedHookInterface` already carries a `HandleStop` entry point, so
`ScriptedStopHookInterface` is a proper subset. Delete
`ScriptedStopHookInterface`, `ScriptedStopHookPythonInterface`, and
`ScriptInterpreter::CreateScriptedStopHookInterface`, and route
`Target::StopHookScripted` through `ScriptedHookInterface` /
`CreateScriptedHookInterface` instead.
The `target stop-hook add -P <classname>` command is unchanged; it now
constructs a `ScriptedHookInterface` internally, so any existing
`ScriptedStopHook` subclass keeps working as long as it exposes a
`handle_stop` method. New scripts should subclass `ScriptedHook`
directly (which is a superset).
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: 2609cdb07323adac773a1a77e42eb294cd1b815d
https://github.com/llvm/llvm-project/commit/2609cdb07323adac773a1a77e42eb294cd1b815d
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/BPF/BPF.h
M llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
M llvm/lib/Target/BPF/BPFPassRegistry.def
Log Message:
-----------
[BPF][NewPM] Port SelectionDAG ISel
Similar to MSP430 (f122acf2d0b8c806bfa7be81aea0344bfd6fc225).
This is part of getting BPF to work with the NewPM.
Reviewers: yonghong-song, aeubanks, eddyz87
Pull Request: https://github.com/llvm/llvm-project/pull/207638
Commit: a718d2ad092bec5b7fe81e043ad276cb6ae97a50
https://github.com/llvm/llvm-project/commit/a718d2ad092bec5b7fe81e043ad276cb6ae97a50
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
A llvm/lib/Target/BPF/BPFCodeGenPassBuilder.cpp
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
M llvm/lib/Target/BPF/BPFTargetMachine.h
M llvm/lib/Target/BPF/CMakeLists.txt
Log Message:
-----------
[BPF][NewPM] Introduce BPFCodeGenPassBuilder
Part of the transition to the NewPM for CodeGen. Similar to
f122acf2d0b8c806bfa7be81aea0344bfd6fc225.
Reviewers: eddyz87, yonghong-song, aeubanks
Pull Request: https://github.com/llvm/llvm-project/pull/207643
Commit: f4d2c6e772e60a05a915b6ecda1bf12e8dd6c2d3
https://github.com/llvm/llvm-project/commit/f4d2c6e772e60a05a915b6ecda1bf12e8dd6c2d3
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/BPF/BPF.h
M llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp
M llvm/lib/Target/BPF/BPFCodeGenPassBuilder.cpp
M llvm/lib/Target/BPF/BPFPassRegistry.def
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
M llvm/test/CodeGen/BPF/sink-min-max.ll
Log Message:
-----------
[BPF][NewPM] Port bpf-check-and-opt-ir
Standard pass porting. Part of the effort to make BPF work solely with
the new pass manager.
Reviewers: eddyz87, aeubanks, yonghong-song
Pull Request: https://github.com/llvm/llvm-project/pull/207787
Commit: ce5291e94b55bfb7d3bedd4d82684f50f9782847
https://github.com/llvm/llvm-project/commit/ce5291e94b55bfb7d3bedd4d82684f50f9782847
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/BPF/BPF.h
M llvm/lib/Target/BPF/BPFCodeGenPassBuilder.cpp
M llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp
M llvm/lib/Target/BPF/BPFPassRegistry.def
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
Log Message:
-----------
[BPF][NewPM] Port BPFMISimplifyPatchablePass
Standard pass porting. Needed to get the BPF backend fully working with
the NewPM.
Reviewers: aeubanks, eddyz87, yonghong-song
Pull Request: https://github.com/llvm/llvm-project/pull/207800
Commit: e7831765ca43e689d66a6e1fea6ac19edd7cc8c7
https://github.com/llvm/llvm-project/commit/e7831765ca43e689d66a6e1fea6ac19edd7cc8c7
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/BPF/BPF.h
M llvm/lib/Target/BPF/BPFCodeGenPassBuilder.cpp
M llvm/lib/Target/BPF/BPFMIPeephole.cpp
M llvm/lib/Target/BPF/BPFPassRegistry.def
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
Log Message:
-----------
[BPF][NewPM] Port BPFMIPeephole
Standard pass porting. Needed to make BPF work fully with the NewPM.
Reviewers: eddyz87, yonghong-song, aeubanks
Pull Request: https://github.com/llvm/llvm-project/pull/207805
Commit: 618b65a268a5f0df6405a18cad876f63e5721739
https://github.com/llvm/llvm-project/commit/618b65a268a5f0df6405a18cad876f63e5721739
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/BPF/BPF.h
M llvm/lib/Target/BPF/BPFMIPeephole.cpp
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
Log Message:
-----------
[BPF] Split stack argument psuedo expansion into a separate pass
This will make the NewPM implementation cleaner given now the two passes
are either required/optional rather than like BPFMIPreEmitPeepholePass
before, which was partially required (for stack argument psuedo
expansion), and optional for other peephole optimizations. I think this
is also a cleaner design in general.
Reviewers: aeubanks, eddyz87, yonghong-song
Pull Request: https://github.com/llvm/llvm-project/pull/207844
Commit: a5c6a7a6a172fc47e0c608497d7e0fe1166474c1
https://github.com/llvm/llvm-project/commit/a5c6a7a6a172fc47e0c608497d7e0fe1166474c1
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/bindings/python/CMakeLists.txt
M lldb/docs/CMakeLists.txt
A lldb/examples/python/templates/scripted_breakpoint.py
A lldb/examples/python/templates/scripted_hook.py
Log Message:
-----------
[lldb/script] Add scripted extension base-class templates for hooks and breakpoint resolvers (#209311)
This patch adds the Python base-class templates for `ScriptedHook` (a
unified base class that backs both `target hook add -P` and `target
stop-hook add -P`) and `ScriptedBreakpointResolver`, and wires them into
the Python bindings and docs CMake so every scriptable extension kind
has a template that the docs and future tooling can introspect.
The `ScriptedHook` template unifies what used to require separate
subclasses for target hooks and stop hooks: subclasses implement
`handle_stop` (required, so any hook is a valid stop-hook) and
optionally `handle_module_loaded` / `handle_module_unloaded`, which only
fire for hooks registered via `target hook add -P`.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: 670816cf58027f1bfea39ec0745b415bea0275a9
https://github.com/llvm/llvm-project/commit/670816cf58027f1bfea39ec0745b415bea0275a9
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/BPF/BPF.h
M llvm/lib/Target/BPF/BPFCodeGenPassBuilder.cpp
M llvm/lib/Target/BPF/BPFMIPeephole.cpp
M llvm/lib/Target/BPF/BPFPassRegistry.def
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
Log Message:
-----------
[BPF][NewPM] Port BPFMIExpandStackArgPseudosPass
Standard pass porting. Required to get BPF fully working with the NewPM.
Reviewers: eddyz87, aeubanks, yonghong-song
Pull Request: https://github.com/llvm/llvm-project/pull/207845
Commit: 6cde0bcec417016c82329d55401b0717de65f36d
https://github.com/llvm/llvm-project/commit/6cde0bcec417016c82329d55401b0717de65f36d
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/BPF/BPF.h
M llvm/lib/Target/BPF/BPFCodeGenPassBuilder.cpp
M llvm/lib/Target/BPF/BPFMIPeephole.cpp
M llvm/lib/Target/BPF/BPFPassRegistry.def
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
Log Message:
-----------
[BPF][NewPM] Port BPFMIPreEmitPeepholePass
Standard pass porting. This is needed for BPF to fully support the new
pass manager.
Reviewers: eddyz87, yonghong-song, aeubanks
Pull Request: https://github.com/llvm/llvm-project/pull/207847
Commit: 07a4eac758af73bf58b5ec9653a4950187774a18
https://github.com/llvm/llvm-project/commit/07a4eac758af73bf58b5ec9653a4950187774a18
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/BPF/BPF.h
M llvm/lib/Target/BPF/BPFCodeGenPassBuilder.cpp
M llvm/lib/Target/BPF/BPFMIChecking.cpp
M llvm/lib/Target/BPF/BPFPassRegistry.def
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
Log Message:
-----------
[BPF][NewPM] Port BPFMIPreEmitCheckingPass
Standard pass porting. Needed to make BPF fully support the NewPM.
Reviewers: yonghong-song, aeubanks, eddyz87
Pull Request: https://github.com/llvm/llvm-project/pull/207850
Commit: 7a756ba8edc8f762b26999008debd62103f8e267
https://github.com/llvm/llvm-project/commit/7a756ba8edc8f762b26999008debd62103f8e267
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/BPF/BPFAsmPrinter.cpp
M llvm/lib/Target/BPF/BPFAsmPrinter.h
M llvm/lib/Target/BPF/BPFCodeGenPassBuilder.cpp
Log Message:
-----------
[BPF][NewPM] Port AsmPrinter
This is necessary to make the new pass manager fully supported for BPF.
This should be the last patch in the series.
Reviewers: yonghong-song, arsenm, eddyz87
Pull Request: https://github.com/llvm/llvm-project/pull/207854
Commit: 252ad2052409a33eff59a149053ec90f7fae03df
https://github.com/llvm/llvm-project/commit/252ad2052409a33eff59a149053ec90f7fae03df
Author: Brian Cain <brian.cain at oss.qualcomm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M compiler-rt/lib/gwp_asan/optional/backtrace_linux_libc.cpp
Log Message:
-----------
[compiler-rt][GWP-ASan] Use no-op backtrace if execinfo.h missing (#201266)
Guard backtrace_linux_libc.cpp with __has_include(<execinfo.h>) so that
targets without it (e.g. musl libc) get null stubs instead of a build
failure.
Commit: 2b8488ac148f06657aa6ec18f1ee38c79b241635
https://github.com/llvm/llvm-project/commit/2b8488ac148f06657aa6ec18f1ee38c79b241635
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
[BPF][ProfCheck] Exclude sink-min-max.ll (#209352)
This was exposed by porting the pass to the NewPM, so just exclude it
for now.
Commit: 4058610aecb6d261f3ea1777dd5c0e531a5cc17e
https://github.com/llvm/llvm-project/commit/4058610aecb6d261f3ea1777dd5c0e531a5cc17e
Author: Brian Cain <brian.cain at oss.qualcomm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
Log Message:
-----------
[Hexagon] Register MachineKCFILegacy pass in LLVMInitializeHexagonTarget (#209245)
Hexagon's target-init function never called
initializeMachineKCFILegacyPass(PR), unlike X86, ARM, AArch64, and
RISCV. Since PassRegistry is process-wide and each target's init
function registers passes as a side effect when linked into the same
binary, whether test/CodeGen/Hexagon/kcfi.ll passed depended on whether
some other target providing that registration was also built into llc,
rather than on Hexagon's own configuration.
Commit: e2c8fa09872cfacba7f73599dcf8557971ebe865
https://github.com/llvm/llvm-project/commit/e2c8fa09872cfacba7f73599dcf8557971ebe865
Author: Amy Kwan <amy.kwan1 at ibm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Object/ArchiveWriter.cpp
A llvm/test/tools/llvm-ar/zos-write.test
M llvm/tools/llvm-ar/llvm-ar.cpp
Log Message:
-----------
[SystemZ][z/OS] Add z/OS archive writing support (#200087)
This patch implement z/OS archive writing in ArchiveWriter and adds the
option `llvm-ar --format=zos`.
Moreover, This patch teaches `llvm-ar` to emit z/OS-compatible archives
by:
- Detecting GOFF object files as z/OS members
- Writing z/OS member headers and archive magic
- Converting archive headers and symbol-name string tables to EBCDIC
- Emitting z/OS symbol table entries
- Using EBCDIC newline padding bytes
- Add a z/OS-specific workaround for empty symbol tables by emitting a
dummy blank symbol to satisfy binder requirements.
Commit: 6e5c97d417d1ec16c095aba6630995406dde1d87
https://github.com/llvm/llvm-project/commit/6e5c97d417d1ec16c095aba6630995406dde1d87
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt/AllocAction.h
R orc-rt/lib/executor/AllocAction.cpp
M orc-rt/lib/executor/CMakeLists.txt
M orc-rt/lib/executor/SimpleNativeMemoryMap.cpp
M orc-rt/test/unit/AllocActionTest.cpp
M orc-rt/test/unit/CommonTestUtils.h
Log Message:
-----------
[orc-rt] Hoist run-alloc-actions functions, add error reporting. (#209356)
Hoist runFinalizeActions and runDeallocActions into AllocAction.h and
turn them into function templates with a ReportErrorFn argument that
enables error reporting. This is used to report errors from dealloc
actions.
Update SimpleNativeMemoryMap to direct such errors to the Session via
ReportErrorsViaSession.
Add unit tests covering the new error-reporting paths.
Commit: 0c19355a6b3e88fcb98a398845735c6ae19a2142
https://github.com/llvm/llvm-project/commit/0c19355a6b3e88fcb98a398845735c6ae19a2142
Author: Nicolas Miller <nicolas.pierre.miller at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
M llvm/test/CodeGen/Hexagon/autohvx/conv-fp-fp.ll
Log Message:
-----------
[Hexagon] Fix fpround fp32 -> fp16 pattern (#199704)
The pattern was passing hi and lo in the wrong order to `vcvt` causing
the final output after `vdeal` to be incorrect.
Commit: 5b3fbf852e5d72d3a78ff4646a8ddad3c8d50536
https://github.com/llvm/llvm-project/commit/5b3fbf852e5d72d3a78ff4646a8ddad3c8d50536
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lldb/include/lldb/Core/PluginManager.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/source/Core/PluginManager.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/OperatingSystemPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/OperatingSystemPythonInterface.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedBreakpointPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedFrameProviderPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedFramePythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedFramePythonInterface.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedHookPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPlatformPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedProcessPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPlanPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPythonInterface.h
M lldb/test/Shell/Commands/command-scripting-extension-list.test
Log Message:
-----------
[lldb] Expand ScriptedExtension coverage across scripted Python interfaces (NFC) (#209307)
Commit: 795a5a9a19bb2b356d82a46426d95f245d1d0049
https://github.com/llvm/llvm-project/commit/795a5a9a19bb2b356d82a46426d95f245d1d0049
Author: Vijay Kandiah <vkandiah at nvidia.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Lower/CUDA/cuda-implicit-managed-alloc.cuf
Log Message:
-----------
[flang][cuda] Implicitly attribute allocatables/pointers under -gpu=unified (#209292)
When `-gpu=unified` is in effect, allocatables and pointers with no
explicit CUDA data attribute were left with no data attribute, and were allocated
as ordinary host memory. Under unified memory, such objects must be
reachable from the device; leaving them as plain host allocations makes device kernels
fault on systems that do not provide transparent host-memory access.
The existing code here already assigned `Managed` implicitly under
`-gpu=managed` (when CUDA Fortran is enabled). This extends that handling to
`-gpu=unified`: prefer the `Unified` attribute where it is legal (host subprogram, main
program, or derived-type component) so generic resolution still selects the unified
specific, and fall back to `Managed` elsewhere (module scope, device
subprograms). Both attributes route allocation through the same managed
allocator, so this keeps the allocation device-accessible while avoiding
spurious `ATTRIBUTES(UNIFIED)` legality errors.
The attribution stays gated on CUDA Fortran being enabled, preserving
the existing behavior for non-CUDA-Fortran translation units.
Commit: b15f9326d21cbd05463fcb34d989bae95982cc9b
https://github.com/llvm/llvm-project/commit/b15f9326d21cbd05463fcb34d989bae95982cc9b
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
A flang/test/Evaluate/fold-kind-logical.f90
A flang/test/Evaluate/fold-kind-substring.f90
A flang/test/Evaluate/fold-kind-zero-size.f90
M flang/test/Evaluate/logical-args.f90
A flang/test/Lower/HLFIR/array-ctor-character-kind.f90
A flang/test/Semantics/modfile84.F90
A flang/test/Semantics/substring-literal-kind.f90
Log Message:
-----------
[flang] Add kind-preservation regression tests (#208760)
These tests pin currently-correct behaviors where the KIND type
parameter of a result must be preserved by constant folding, semantics,
and lowering. They all pass at head; their purpose is to guard against
silent kind loss during future refactoring of the Evaluate library's
type-parameterized machinery (see the discussion on PR #206907, where an
experimental rewrite passed check-flang while dropping kinds in several
places).
Folded LOGICAL operations: `.NOT./.AND./.OR./.EQV./.NEQV.` keep their
operand kind; ANY/ALL/PARITY and logical DOT_PRODUCT results have the
MASK/argument kind (F2023 16.9.14/16.9.16/16.9.148), including for empty
masks where there is no element value to take a kind from; MERGE and
TRANSFER keep the TSOURCE/MOLD kind; STORAGE_SIZE of folded
non-default-kind logicals folds to the right value; the default BOUNDARY
fill element of a folded EOSHIFT has the array's kind; relational
results are default logical regardless of operand kinds; and generic
resolution over LOGICAL kinds is unchanged by folding
(flang/test/Evaluate/fold-kind-logical.f90 and an extension of
flang/test/Evaluate/logical-args.f90).
Empty typed array constructors and zero-size PACK/SPREAD/RESHAPE/UNPACK
results keep the kind (and character length) of their type-spec (F2023
7.8), including across a module file into a separately compiled
consumer, and empty non-default-kind character array constructors lower
with the correct `!fir.char` element type
(flang/test/Evaluate/fold-kind-zero-size.f90,
flang/test/Semantics/modfile84.F90,
flang/test/Lower/HLFIR/array-ctor-character-kind.f90).
A substring of a character literal has the kind of the literal (F2023
9.4.1): KIND() and LEN() fold correctly, and concatenation with a
same-kind literal is accepted
(flang/test/Evaluate/fold-kind-substring.f90,
flang/test/Semantics/substring-literal-kind.f90).
Assisted-by: AI
Commit: b959f7886f0fdbf8f683c11e945cca3f1afca36a
https://github.com/llvm/llvm-project/commit/b959f7886f0fdbf8f683c11e945cca3f1afca36a
Author: Sean Perry <perry at ca.ibm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/lit/lit/builtin_commands/cat.py
Log Message:
-----------
Add text file support for z/OS back in (#209259)
Support for auto conversion of text files was added to cat.py in
https://github.com/llvm/llvm-project/pull/90128. That was accidently
removed in https://github.com/llvm/llvm-project/pull/204711 while
removing some old win32 code. This adds the z/OS support back in.
Commit: 67f5b53995d3e8ce0b062ea73be1fbb9186d6b30
https://github.com/llvm/llvm-project/commit/67f5b53995d3e8ce0b062ea73be1fbb9186d6b30
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lld/test/ELF/retain-symbols-file.s
Log Message:
-----------
[ELF,test] Improve retain-symbols-file.s (#209366)
Commit: f18e59a195eb253573a26c118d3a09a83acb73ca
https://github.com/llvm/llvm-project/commit/f18e59a195eb253573a26c118d3a09a83acb73ca
Author: Thurston Dang <thurston at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_common_nolibc.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_dl.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_dl.h
M compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
M compiler-rt/lib/tsan/go/buildgo.sh
M compiler-rt/test/sanitizer_common/TestCases/Linux/dlopen_image_base.c
Log Message:
-----------
Revert "[compiler-rt] [sanitizer_common] Fix SIGSEGV in ForEachMappedRegion for DSOs with custom image base" (#209371)
Reverts llvm/llvm-project#206299 due to buildbot breakage
(https://github.com/llvm/llvm-project/pull/206299#issuecomment-4964804971)
Commit: c4edd8bde42cf6b1a25839601b75f3865bba6976
https://github.com/llvm/llvm-project/commit/c4edd8bde42cf6b1a25839601b75f3865bba6976
Author: ejose02 <ejose at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/Object/IRSymtab.h
A llvm/test/Object/X86/irsymtab-large-common.ll
M llvm/test/Object/X86/irsymtab.ll
Log Message:
-----------
[Object] Fix irsymtab CommonSize truncation past 4 GiB (#209085)
Fixes #208669
Issue :
With -flto, Fortran COMMON blocks larger than 4 GiB were silently
miscompiled. The linker reserved only the low 32 bits of the declared
size, so stores past that boundary could segfault with no diagnostic.
Root Cause :
storage::Uncommon::CommonSize in the LTO irsymtab was stored as 32-bit
(Word). Sizes above 2^32 bytes were truncated when the symtab was
written and read back at link time.
Fix :
Widen CommonSize to 64-bit and bump irsymtab format version to 4. Added
test to verify symtab records the full size.
Commit: a527c6f0bc9644cf8b13a9fb5a43e81257bedba6
https://github.com/llvm/llvm-project/commit/a527c6f0bc9644cf8b13a9fb5a43e81257bedba6
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M orc-rt/lib/executor/Logging.cpp
Log Message:
-----------
[orc-rt] Statically check logging category/level name array sizes. (#209372)
Add static_asserts to trigger compilation failure if the sizes of these
arrays don't match their respective enum/macro value ranges.
Commit: a70234b00d12aaa7723eb2ae5e8efe3348aeeb37
https://github.com/llvm/llvm-project/commit/a70234b00d12aaa7723eb2ae5e8efe3348aeeb37
Author: Sergey Shcherbinin <sscherbinin at nvidia.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIROpsSupport.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Lower/CallInterface.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/FunctionAttr.cpp
A flang/test/Driver/function-attr-readonly.f90
M flang/test/Lower/HLFIR/structure-constructor.f90
M flang/test/Lower/Intrinsics/dconjg.f90
M flang/test/Lower/Intrinsics/dimag.f90
M flang/test/Lower/Intrinsics/dreal.f90
M flang/test/Lower/OpenMP/optional-argument-map.f90
M flang/test/Lower/OpenMP/wsloop-unstructured.f90
M flang/test/Lower/achar.f90
M flang/test/Lower/arguments.f90
M flang/test/Lower/call-copy-in-out.f90
M flang/test/Lower/dispatch.f90
A flang/test/Lower/dummy-argument-readonly.f90
M flang/test/Lower/polymorphic-temp.f90
M flang/test/Lower/polymorphic.f90
M flang/test/Lower/select-type.f90
M flang/test/Lower/unsigned-ops.f90
M flang/test/Lower/volatile1.f90
A flang/test/Transforms/function-attrs-readonly.fir
Log Message:
-----------
[flang] Propagate INTENT(IN) dummy arguments as readonly (#207732)
Mark eligible `INTENT(IN)` dummy data objects with a `fir.read_only`
argument attribute during lowering, and teach `FunctionAttr` to
translate the marker to LLVM `readonly` for reference arguments when
optimizing for speed.
LLVM FunctionAttrs can infer `readonly` later in the pipeline, but this
happens too late for IPSCCP function specialization.
`FunctionSpecializer::promoteConstantStackValues` requires
`onlyReadsMemory()` before promoting constant by-reference scalar
arguments. Providing `readonly` satisfies this check and allows these
arguments to be promoted, enabling function specialization, including in
non-LTO builds.
For direct-data arguments, restrict propagation to by-reference
non-character intrinsic scalars. Ordinary arrays and derived-type
arguments are excluded because compiler-generated copy-out may write
back through a forwarded dummy argument. LLVM `readonly` does not permit
such writes, even when the stored value is unchanged.
`INTENT(IN)` `POINTER` and `ALLOCATABLE` dummies are supported with
shallow descriptor semantics: `readonly` protects the descriptor
storage, but does not imply that data addressed by the descriptor is
read-only. In particular, a `POINTER` target may still be modified.
Keep `readonly` handling independent from `noalias` and `nocapture`.
`TARGET` arguments may receive `readonly`, but must not receive
`noalias` or `nocapture`. Apply `readonly` to `BIND(C)` definitions
while leaving external C declarations unannotated. `VALUE`,
`ASYNCHRONOUS`, and `VOLATILE` dummy arguments remain excluded.
In our measurements, the enabled function specialization gives a 1.5x
speedup on 548.exchange2 on NVIDIA Neoverse V2 in a non-LTO
configuration.
Update existing lowering tests to account for the new `fir.read_only`
argument attribute, and add focused coverage:
* `dummy-argument-readonly.f90` checks marker emission for supported
scalar and descriptor arguments, excluded cases, and shallow pointer
semantics.
* `function-attrs-readonly.fir` checks translation from `fir.read_only`
to LLVM `readonly`, including `TARGET`, `BIND(C)`, and descriptor
references.
* `function-attr-readonly.f90` checks the optimization-level pipeline
gate and verifies that `readonly` reaches final LLVM IR.
* `call-copy-in-out.f90` checks that ordinary array copy-out cases
remain unmarked and that pointer-target copy-out is compatible with
shallow descriptor `readonly`.
Commit: 44a42e631e5b4e01855750c371dea87fb3927550
https://github.com/llvm/llvm-project/commit/44a42e631e5b4e01855750c371dea87fb3927550
Author: Peiqi Li <voyager.lpq at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang-tools-extra/clang-tidy/misc/RedundantExpressionCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/misc/redundant-expression.cpp
Log Message:
-----------
[clang-tidy] Fix false positive in misc-redundant-expression with type aliases (#198085)
The `misc-redundant-expression` check previously flagged expressions as
redundant if their underlying `DeclRefExpr` pointed to the same
declaration. This caused false positives when comparing identical values
accessed through distinct type aliases.
Following Clang's diagnostic `aka` logic, this patch uses the AST
Printer to stringify and compare the `NestedNameSpecifier` and
`TemplateArguments`. This safely preserves sugared types while natively
normalizing all whitespaces and newlines, ensuring robustness against
multiline formatting changes.
Fixes #145415
Commit: 6de51be4f636eda95e439db50f8463bdf8bde02e
https://github.com/llvm/llvm-project/commit/6de51be4f636eda95e439db50f8463bdf8bde02e
Author: David Green <david.green at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/bf16-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
Log Message:
-----------
[AArch64][GlobalISel] Legalization for bf16 fptosi/fptoui. (#209206)
Similar to other operations, this makes sure we can widen bf16
fptosi/fptoui correctly, promoting the value to a f32. The vector
variants have been proven by exhaustive checking.
Commit: 1bd46015ea4e842091109cd2a491c55c0b455330
https://github.com/llvm/llvm-project/commit/1bd46015ea4e842091109cd2a491c55c0b455330
Author: Erick Velez <erickvelez7 at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang-tools-extra/clang-doc/CMakeLists.txt
M clang-tools-extra/clang-doc/Generators.cpp
M clang-tools-extra/clang-doc/Generators.h
M clang-tools-extra/clang-doc/Representation.h
R clang-tools-extra/clang-doc/YAMLGenerator.cpp
M clang-tools-extra/clang-doc/tool/ClangDocMain.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
R clang-tools-extra/test/clang-doc/yaml/builtin_types.cpp
R clang-tools-extra/test/clang-doc/yaml/conversion_function.cpp
R clang-tools-extra/test/clang-doc/yaml/single-file-public.cpp
R clang-tools-extra/test/clang-doc/yaml/single-file.cpp
R clang-tools-extra/test/clang-doc/yaml/templates.cpp
M clang-tools-extra/unittests/clang-doc/CMakeLists.txt
R clang-tools-extra/unittests/clang-doc/YAMLGeneratorTest.cpp
Log Message:
-----------
[clang-doc] Remove the YAML generator (#209350)
The original intent of the YAML generator was to package the
documentation information in a structured and reusable way. It has been
superseded by the JSON generator.
Commit: 05b6b4f1af9f2eb5bebc2cfd10b2fff6bbfab55d
https://github.com/llvm/llvm-project/commit/05b6b4f1af9f2eb5bebc2cfd10b2fff6bbfab55d
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt-c/Logging.h
M orc-rt/lib/executor/Logging.cpp
M orc-rt/test/unit/LoggingTest.cpp
Log Message:
-----------
[orc-rt] Add new ControllerAccess logging category. (#209380)
The orc_rt_log_Category_ControllerAccess category should be used to log
messages from ControllerAccess implementations. E.g.
ORC_RT_LOG(Error, ControllerAccess, "connect() failed with <error>");
Commit: 4d5bc903c8a79fbadb62d8dd1e7cc93ad7a394fd
https://github.com/llvm/llvm-project/commit/4d5bc903c8a79fbadb62d8dd1e7cc93ad7a394fd
Author: Sean Clarke <sclarke at tenstorrent.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/test/CodeGen/AArch64/clmul.ll
M llvm/test/CodeGen/RISCV/clmul.ll
M llvm/test/CodeGen/X86/clmul.ll
Log Message:
-----------
[SelectionDAG] Improve `CLMUL` lowering for `Promote` types wider than register width (#209265)
For `ISD::CLMUL`, add a check to `PromoteIntRes_CLMUL` to take advantage
of the cross-product expansion in `ExpandIntRes_CLMUL` when possible for
`Promote` types which are wider than the register width (e.g. `i96` for
64-bit registers).
Commit: 8eb6e260047bd2f69d9d2c1f0967ae59f7ec5374
https://github.com/llvm/llvm-project/commit/8eb6e260047bd2f69d9d2c1f0967ae59f7ec5374
Author: Martin Storsjö <martin at martin.st>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M openmp/runtime/src/kmp_utility.cpp
Log Message:
-----------
[openmp] Apply a mingw/64 bit codepath to arm64ec too (#209297)
When targeting arm64ec, neither KMP_ARCH_X86_64 nor KMP_ARCH_AARCH64 is
defined.
This fixes a compilation warning when building openmp for mingw/arm64ec.
Commit: a436e36f5e57e8daabee71fd0cb649c1633e314f
https://github.com/llvm/llvm-project/commit/a436e36f5e57e8daabee71fd0cb649c1633e314f
Author: David Green <david.green at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/bf16-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
M llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll
M llvm/test/CodeGen/AArch64/round-fptoui-sat-scalar.ll
Log Message:
-----------
[AArch64][GlobalISel] Legalization for bf16 fptosi.sat/fptoui.sat (#209378)
This is the equivalent change to #209206 for fptoi.sat.
Commit: f60650c772485640b57520e91cec9779cc7f27dc
https://github.com/llvm/llvm-project/commit/f60650c772485640b57520e91cec9779cc7f27dc
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
Log Message:
-----------
[BitcodeReader] Lazily read and cache target triple (NFC) (#208175)
Lazily read and cache the target triple from the stream, currently meant
to be used only for upgrading AArch64 memory effects from old bitcode.
Co-authored-by: Caroline Concatto <caroline.concatto at arm.com>
Commit: 69ee6b114ac3d3c6652b39d0d57b292bcfa3a81c
https://github.com/llvm/llvm-project/commit/69ee6b114ac3d3c6652b39d0d57b292bcfa3a81c
Author: WMC <tnwilly at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/test/Dialect/LLVMIR/nvvm.mlir
M mlir/test/Target/LLVMIR/nvvmir.mlir
Log Message:
-----------
[NVVM] Add FP8 (e4m3/e5m2) support to dense mma.sync (#207307)
## Motivation
I'm adding NVIDIA FP8 mma.sync support in IREE for sm_89/sm_120, and
IREE's codegen lowers through `nvgpu.mma.sync` on this path, which in
turn lowers to `nvvm.mma.sync`. This MLIR-level gap is blocking that
work, so I'm upstreaming the fix here first. This is split into two PRs
per review feedback — this one covers `nvvm.mma.sync` only; a follow-up
PR will add the corresponding `nvgpu.mma.sync` support built on top of
this.
## Description:
`nvvm.mma.sync` (warp-level, dense) don't support FP8 (e4m3/e5m2)
operands, even though the underlying PTX/NVPTX intrinsics have supported
FP8 `mma.sync.m16n8k32` since sm_89. FP8 currently only exists on the
sparse mma path and on warpgroup-level `wgmma`; the warp-level dense
path was never updated.
This adds FP8 (e4m3/e5m2) support to `nvvm.mma.sync`, covering
`m16n8k16` and `m16n8k32`.
## Verification
`$ mlir-opt mlir/test/Dialect/LLVMIR/nvvm.mlir -split-input-file
-verify-diagnostics | FileCheck mlir/test/Dialect/LLVMIR/nvvm.mlir
`
```
%0 = nvvm.mma.sync A[...] B[...] C[...]
{multiplicandAPtxType = #nvvm.mma_type<e4m3>,
multiplicandBPtxType = #nvvm.mma_type<e4m3>,
shape = #nvvm.shape<m = 16, n = 8, k = 32>}
: (i32, i32, f32) -> !llvm.struct<(f32, f32, f32, f32)>
```
`$ mlir-translate -mlir-to-llvmir mlir/test/Target/LLVMIR/nvvmir.mlir
-split-input-file -verify-diagnostics | FileCheck
mlir/test/Target/LLVMIR/nvvmir.mlir
`
```
%8 = call { float, float, float, float } @llvm.nvvm.mma.m16n8k16.row.col.f32.e4m3.e4m3.f32(i32 %0, i32 %1, i32 %2, float %3, float %4, float %5, float %6)
%11 = call { float, float, float, float } @llvm.nvvm.mma.m16n8k32.row.col.f32.e4m3.e5m2.f32(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, float %6, float %7, float %8, float %9)
```
All existing tests in nvvm.mlir (including -verify-diagnostics error
cases) still pass — no regression.
Co-authored with Claude Sonnet 5
Signed-off-by: weimin023 <tnwilly at gmail.com>
Commit: 317efbe4496900a60de09812aa91b1f486b2e795
https://github.com/llvm/llvm-project/commit/317efbe4496900a60de09812aa91b1f486b2e795
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/branch-cond-split-fcmp.ll
M llvm/test/CodeGen/AArch64/sve2p1-while-pn-folds.ll
Log Message:
-----------
[AArch64] Fold CSET + BR_CC into a conditional branch (#207398)
Fold CSETs into conditional branches (rather than lowering to a CSET +
TB[N]Z). This is most useful for lowering loop conditions based on
predicate-as-counter whiles to:
```
whilelo pn8.s, x0, x1, vlx4
b.mi .Lloop
```
Commit: 70496276d0f441999b61e84ca22e59d61fa43582
https://github.com/llvm/llvm-project/commit/70496276d0f441999b61e84ca22e59d61fa43582
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/MarkLive.cpp
M lld/ELF/SymbolTable.cpp
M lld/ELF/Writer.cpp
M lld/docs/ReleaseNotes.rst
M lld/docs/ld.lld.1
M lld/test/ELF/retain-symbols-file.s
M lld/test/ELF/version-script-warn.s
Log Message:
-----------
[ELF] --retain-symbols-file: keep listed symbols in .symtab, not .dynsym (#209063)
Commit c0fc25307143dd06c12fb2f5ebdb1dade7290ccf (2017) implements
--retain-symbols-file with symbol version machinery
`{local: *; global: listed;}`, which removes unlisted symbols from
.dynsym and leaves .symtab untouched. GNU ld does the opposite: it keeps
only the listed symbols in .symtab and does not touch .dynsym.
Reuse the --discard-{locals,all} mechanism to reimplement the feature,
matching GNU ld.
Use --export-dynamic-symbol or a version script to control .dynsym.
Extend `markUsedSymbols` to mark referenced globals as well, so
--emit-relocs/-r keep a valid symbol index.
Fix #91055
Commit: e8e88dbde96a75ffe0e8bf10ea9481a053292421
https://github.com/llvm/llvm-project/commit/e8e88dbde96a75ffe0e8bf10ea9481a053292421
Author: Harlen Batagelo <hbatagelo at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaTemplateInstantiate.cpp
A clang/test/SemaTemplate/GH195988.cpp
Log Message:
-----------
[clang][sema] Fix crash on class template instantiation when a member variable partial specialization has an invalid primary template (#202006)
Fixes #195988.
For the root cause, consider this reproducer:
https://godbolt.org/z/6jTnvocs4
```cpp
template <typename> struct A {
template <typename U> static B x; // unknown type name 'B'
template <typename U> static int x<U*>;
};
A<int> a;
```
During the instantiation of `A<int>`, the variable template `x` is
skipped because it was marked as an invalid declaration due to the
unknown type `B`. When the partial specialization `x<U*>` is visited
next, the lookup for `x` finds nothing and triggers the assertion:
https://github.com/llvm/llvm-project/blob/2433b06e6dbe3ef015a226620d207a45f7b98c7c/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp#L2538
Fix by instantiating invalid variable templates using the `int` fallback
instead of skipping them.
Commit: aae01919171394ed4a4bf6b2fb82cc0d70561994
https://github.com/llvm/llvm-project/commit/aae01919171394ed4a4bf6b2fb82cc0d70561994
Author: Petr Hosek <phosek at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/src/include/overridable_function.h
Log Message:
-----------
[libcxx] Rename __libcpp_launder to __launder_function_pointer (#209320)
This addresses post-commit feedback raised in #208330.
Commit: 6c6ecb376a940d16e17dae2d40dc076466898860
https://github.com/llvm/llvm-project/commit/6c6ecb376a940d16e17dae2d40dc076466898860
Author: Petr Hosek <phosek at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/src/include/overridable_function.h
M libcxx/src/new.cpp
M libcxxabi/src/stdlib_new_delete.cpp
Log Message:
-----------
[libcxx][libcxxabi] Remove OVERRIDABLE_FUNCTION macro (#209323)
This is no longer needed, we can just use [[gnu::weak]] attribute.
Commit: 9a342c137d4ed8c6d4571ebc5a62f22aa9642278
https://github.com/llvm/llvm-project/commit/9a342c137d4ed8c6d4571ebc5a62f22aa9642278
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/early-exit-live-out.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-prune-vf.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-access-wide-stride.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
M llvm/test/Transforms/LoopVectorize/VPlan/RISCV/expand-scev.ll
Log Message:
-----------
[VPlan] Use VPSCEVExpander in convertToStridedAccesses (#208939)
Expand SCEVs to VPInstructions, falling back to expanding to IR
instructions. Expanding to VPInstructions has the advantage that the
expansion would be made visible to the VPlan optimization pipeline,
allowing existing simplifications to kick in.
Commit: 5514c1eff5fe52d0bcc2c017c0210bd31fd0bf32
https://github.com/llvm/llvm-project/commit/5514c1eff5fe52d0bcc2c017c0210bd31fd0bf32
Author: Baranov Victor <bar.victor.2002 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang-tools-extra/clang-tidy/modernize/UseScopedLockCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/modernize/use-scoped-lock.rst
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-scoped-lock-warn-on-single-locks-false.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-scoped-lock.cpp
Log Message:
-----------
[clang-tidy] Flag consecutive scoped_locks in use-scoped-lock (#209272)
Fixes https://github.com/llvm/llvm-project/issues/209112.
Commit: 94b7d2b4d8d7c8cfa2d09a6aa2bb1d7df81d047c
https://github.com/llvm/llvm-project/commit/94b7d2b4d8d7c8cfa2d09a6aa2bb1d7df81d047c
Author: gtrong <40399865+gtrong at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Parse/ParseDecl.cpp
M clang/test/Parser/cxx-default-args.cpp
Log Message:
-----------
[Clang] Fix error recovery for default arguments (#208868)
Fixes #205718
### Description
This PR fixes an issue where Clang incorrectly skips the creation of a
parameter when an error occurs in a default argument that involves a GNU
statement expression (`({ ... })`).
Previously, if the default expression evaluation failed within a
statement expression, the error recovery was not handled properly,
leading to the parameter being dropped. This fix ensures that the
parameter is correctly created and error recovery proceeds as expected.
### Testing
Added/Updated test cases in
`clang/test/SemaCXX/default-arg-error-recovery.cpp` to cover invalid
default arguments inside statement expressions.
Commit: 9144e3292c6caaeed2ad16b6ed2a2eba620c0257
https://github.com/llvm/llvm-project/commit/9144e3292c6caaeed2ad16b6ed2a2eba620c0257
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/include/clang/Basic/AArch64CodeGenUtils.h
M clang/include/clang/Basic/arm_neon.td
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
M clang/test/Sema/aarch64-neon-target.c
M clang/test/Sema/aarch64-neon-without-target-feature.cpp
Log Message:
-----------
[AArch64][llvm][clang] Rename 9.7 ACLE vmmlaq_f16_f16 to vmmlaq_f16 (#209242)
Rename Armv9.7 ACLE intrinsic `vmmlaq_f16_f16` to `vmmlaq_f16`
as it matches convention better.
See https://github.com/ARM-software/acle/pull/443 for the ACLE change.
Commit: 25ee70e271dd60978f8bfded54198dbe72009847
https://github.com/llvm/llvm-project/commit/25ee70e271dd60978f8bfded54198dbe72009847
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
M llvm/test/CodeGen/WebAssembly/simd-relaxed-fmax.ll
M llvm/test/CodeGen/WebAssembly/simd-relaxed-fmin.ll
Log Message:
-----------
[WebAssembly] Fix operands in relaxed_pmin/relaxed_pmax pattern (#209398)
After 56e62e539eb65ebe4ec9fc6de0328fea21ae86fd these should be
operands 0 and 1 instead of 1 and 2.
Also add an explicit SIMD128 check when marking these as legal.
It works fine without it (presumably because the types just aren't
legal), but this makes it more explicit when the operations are
available.
Commit: 95349af763cfc48858fdd40058bd46a11779deb2
https://github.com/llvm/llvm-project/commit/95349af763cfc48858fdd40058bd46a11779deb2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
A llvm/test/MC/AMDGPU/amdgcn-target-directive-conflict.s
M llvm/test/MC/AMDGPU/amdgcn-target-directive-subarch-cpu-field.s
M llvm/test/MC/AMDGPU/amdgcn-target-directive-triple-env.s
M llvm/test/MC/AMDGPU/hsa-diag-v4.s
M llvm/test/MC/AMDGPU/hsa-exp.s
M llvm/test/MC/AMDGPU/hsa-gfx12-v4.s
M llvm/test/MC/AMDGPU/hsa-gfx13-v4.s
M llvm/test/MC/AMDGPU/hsa-tg-split.s
M llvm/test/MC/AMDGPU/hsa-v4.s
M llvm/test/MC/AMDGPU/hsa-v5-uses-dynamic-stack.s
M llvm/test/MC/AMDGPU/isa-version-hsa.s
M llvm/test/MC/AMDGPU/isa-version-pal.s
M llvm/test/MC/AMDGPU/isa-version-unk.s
M llvm/test/MC/ELF/AMDGPU/cfi.s
Log Message:
-----------
AMDGPU: Defer validation of target assembler directives (#207812)
Stop immediately emitting the .amdgcn_target directive from the command
line's target, and wait until any target directives in the file are
encountered. This requires lazily emitting the target directive to before the
point anything is to be emitted. Weaken the validation that the xnack and
sramecc settings match the command line's state, and take the mode from the
target directive
(mutating the tracked target ID state). Liberalize the triple check so that after
#206480, old assembly files will not break on new assembler invocations.
For some reason we have 2 different assembler directives that indicate
the target, .amdgcn_target for amdhsa and .amd_amdgpu_isa for amdpal.
Previously, we would take the target from the command line and then error if the
directive did not exactly match. In order to move away from depending on the xnack
and sramecc subtarget features, start treating the directives as a change of
target, similar to ARM's .cpu and .arch directives.
Both .amdgcn_target and .amd_amdgpu_isa encode full triples, but unlike
.amdgcn_target, the PAL directive does not include xnack or sramecc.
Ideally we would introduce new independent directives for these.
Co-Authored-By: Claude Opus 4.6 <noreply at anthropic.com>
Commit: 2d401082440f16d36a42e5b55c2992f8bab4cb5f
https://github.com/llvm/llvm-project/commit/2d401082440f16d36a42e5b55c2992f8bab4cb5f
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M .github/workflows/containers/github-action-ci/Dockerfile
Log Message:
-----------
[GitHub] Install libedit, libxml2 and liblzma to be used in Linux LLDB builds (#209129)
In #188049 we missed some test failures because GitHub CI does not have
libxml2 installed. I checked the logs and found a couple of other things
missing.
In this change I'm adding to the Linux container:
* libedit
* libxml2
* liblzma
I am not adding ncurses because this would enable text user interface
tests that are often unstable. They do run post-commit, and don't change
that often anyway.
I am not adding Lua or TreeSitter because they are more obscure and are
tested somewhere post-commit (in Green Dragon I think).
Commit: f195f4d45dc253192270a4be3f806f2913a071d1
https://github.com/llvm/llvm-project/commit/f195f4d45dc253192270a4be3f806f2913a071d1
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/bindings/interface/SBTargetDocstrings.i
M lldb/docs/use/tutorial.md
M lldb/source/Breakpoint/Watchpoint.cpp
M lldb/test/Shell/Register/x86-db-read.test
Log Message:
-----------
[lldb] Add comma separator in watchpoint description (#209176)
I find it easier to read this way, especially the last "state = enabled type = m" which looks like "enabled type = m" at a glance:
Watchpoint 1: addr = 0xaaaaaaab1018 size = 20 state = enabled type = m
With commas:
Watchpoint 1: addr = 0xaaaaaaab1018, size = 20, state = enabled, type = m
Code breakpoints include commas already:
1: name = 'main', locations = 1, resolved = 1, hit count = 1
1.1: where = test.o`main at test.c:13:15, address = 0x0000aaaaaaaa0714, resolved, hit count = 1
Used the regex "Watchpoint [0-9]+:" to find tests and docs that needed
updating.
Commit: dad3e30521b596cade7e3c516909657c44ed2840
https://github.com/llvm/llvm-project/commit/dad3e30521b596cade7e3c516909657c44ed2840
Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/Rematerializer.h
M llvm/lib/CodeGen/Rematerializer.cpp
M llvm/unittests/CodeGen/RematerializerTest.cpp
Log Message:
-----------
[CodeGen] Fix incorrect rematerialization rollback order (#197576)
This fixes an issue in the rematerializer's rollbacker wherein adjacent
MIs that were deleted through rematerializations would
sometimes---depending on the exact order in which they were
deleted---not be re-created in their original pre-rematerialization
order. While this does not impact correctness (i.e., use-def relations
are always honored), this goes against the rollbacker's intent to
re-create the MIR exactly as it was pre-rematerializations (up to slot
index changes).
Commit: 5566c87df36cacb1f006535476108dc5e4c8c18f
https://github.com/llvm/llvm-project/commit/5566c87df36cacb1f006535476108dc5e4c8c18f
Author: Victor Campos <victor.campos at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/test/CodeGen/builtins.c
Log Message:
-----------
[Clang] Fix boolean vector bit counting on big-endian targets (#209146)
`__builtin_ctzg` and `__builtin_clzg` (count leading/trailing zeroes)
can accept boolean vectors as arguments. In this case, they operate in
logical vector lane order. However, `EmitBitCountExpr`, used to generate
the argument to those builtins, bitcasts boolean vectors directly to
integer bitfields, whose bit order is reversed on big-endian targets.
This caused libc's SIMD `find_first_set` and `find_last_set` helpers to
count lanes from the wrong end in big-endian mode. But the issue was
general and could affect any user.
This patch normalizes the integer representation with `llvm.bitreverse`
on big-endian targets before emitting bit-count intrinsics. On top of
that, the codegen test has been refactored to run on more targets and to
cover big-endian mode as well.
As a side effect of this change, and because of the way the code is
structured, the bit reverse operation also happens for
`__builtin_popcountg`. For this intrinsic, the integer bitfield's bit
order doesn't matter because it simply counts set bits. However, to make
this change only affect the count leading/trailing intrinsics would be
too intrusive, and in any case, with optimizations enabled, the
pointless bit reversing operation on popcount is optimized away. This
behaviour is covered in the test.
Assisted-by: codex. It was used for the test, not the implementation.
Commit: afac9463c13d6e44f287ee693309497cb79e1e10
https://github.com/llvm/llvm-project/commit/afac9463c13d6e44f287ee693309497cb79e1e10
Author: Mateusz Chudyk <mateusz.chudyk at intel.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir
Log Message:
-----------
[GlobalISel] Fix crash in matchCombineInsertVecElts with INLINEASM-de… (#208225)
…fined base
matchCombineInsertVecElts walks the G_INSERT_VECTOR_ELT chain by
following operand 0 of the source-defining instruction. When the base
vector is defined by INLINEASM, operand 0 is the asm string (not a
register), so calling getReg() triggers an assertion:
Assertion `isReg() && "This is not a register operand!"' failed.
Fix by using the mi_match overload that takes a MachineInstr instead of
a Register, which checks the instruction opcode before accessing any
operands.
Commit: 7401694a38d9126bc910d3edf7e04331a66befa4
https://github.com/llvm/llvm-project/commit/7401694a38d9126bc910d3edf7e04331a66befa4
Author: YaFan Tao <765370813 at qq.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
A llvm/test/CodeGen/AMDGPU/atomic_optimizations_dpp_lds_expected_active_lanes.ll
A llvm/test/Verifier/amdgpu-expected-active-lanes.ll
Log Message:
-----------
[AMDGPU] Add threshold for DPP atomic optimizer on LDS atomics (#186762)
Add amdgpu.expected.active.lane metadata which can be applied to operations by a
compiler front-end. Do not apply the DPP atomic optimizer to LDS atomics where
less than five active lanes are expected.
This is an empirically derived threshold based on GFX11 and GFX12 testing.
---------
Co-authored-by: YaFan <YaFan.Tao at amd.com>
Commit: c9610acc5b1d4f49d197a4c8816fb688736963ae
https://github.com/llvm/llvm-project/commit/c9610acc5b1d4f49d197a4c8816fb688736963ae
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYTargetStreamer.h
Log Message:
-----------
[CSKY] Fix build without PCH (#209405)
Commit: 00bf3d6cf36d1c9a910d470814a76a4be1ab1634
https://github.com/llvm/llvm-project/commit/00bf3d6cf36d1c9a910d470814a76a4be1ab1634
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/clang-tools-extra/clang-doc/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 1bd4601 (#209377)
This fixes 1bd46015ea4e842091109cd2a491c55c0b455330.
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=1bd46015ea4e842091109cd2a491c55c0b455330
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 7c151447bc8abceefa3be9e5f1b27b83803d77af
https://github.com/llvm/llvm-project/commit/7c151447bc8abceefa3be9e5f1b27b83803d77af
Author: Folkert de Vries <folkert at folkertdev.nl>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
R llvm/test/CodeGen/X86/pr142937.ll
A llvm/test/CodeGen/X86/type-tests-must-be-lowered.ll
Log Message:
-----------
[SDAG] emit error when `llvm.type.checked.load` is not lowered (#208058)
Fixes https://github.com/llvm/llvm-project/issues/164663
In rust we can enable devirtualization and LTO on a build that actually
builds a library and hence LTO does not really run. That means typed
loads are emitted, but they are not lowered (or cleaned up), which made
us hit an ICE. Giving a slightly better error message, analogous to the
existing one for `Intrinsic::type_test`, seems nice.
I'm putting this together based on
https://github.com/llvm/llvm-project/pull/179249 and
https://github.com/llvm/llvm-project/issues/164663#issuecomment-3433581033.
Commit: a31c941fa7fd9eaea855cff3bb40347c0d22243d
https://github.com/llvm/llvm-project/commit/a31c941fa7fd9eaea855cff3bb40347c0d22243d
Author: David Stuttard <david.stuttard at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
A llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr-hsa.ll
A llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr-rel32.mir
A llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr.ll
Log Message:
-----------
[AMDGPU] Support global address in V/S_MOV_B64 lowering (#203527)
Hit an issue where V_MOV_B64_PSEUDO had a global, which wasn't
previously handled.
Added support for this, and also for the S_MOV_B64_IMM_PSEUDO to make it
symmetrical.
Claude has been used for this commit, primarily assisting creating a
test.
Commit: d21d602d65bc5f6494da679d004b764e47347b49
https://github.com/llvm/llvm-project/commit/d21d602d65bc5f6494da679d004b764e47347b49
Author: Vikram Hegde <Vikram.Hegde at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/Analysis/ModuleSummaryAnalysis.h
M llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
M llvm/lib/Analysis/StackSafetyAnalysis.cpp
M llvm/lib/Passes/PassRegistry.def
Log Message:
-----------
[NPM] Port ImmutableModuleSummaryAnalysis to NPM (#203510)
Required in LTO pipelines
Commit: d4568c9fd15235bd4545a5c57f23bfcb42673f39
https://github.com/llvm/llvm-project/commit/d4568c9fd15235bd4545a5c57f23bfcb42673f39
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
Log Message:
-----------
[mlir][SPIR-V] Collapse TanPattern/TanhPattern into DirectConversionPattern (#203830)
Commit: 6a1f23ab1333ced760666282c23a7afd2db2719e
https://github.com/llvm/llvm-project/commit/6a1f23ab1333ced760666282c23a7afd2db2719e
Author: Vikram Hegde <Vikram.Hegde at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/MachineBlockPlacement.h
M llvm/include/llvm/CodeGen/RegisterCoalescerPass.h
M llvm/include/llvm/CodeGen/RenameIndependentSubregs.h
M llvm/include/llvm/CodeGen/TwoAddressInstructionPass.h
M llvm/include/llvm/CodeGen/UnreachableBlockElim.h
M llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h
M llvm/include/llvm/Transforms/Utils/UnifyLoopExits.h
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h
M llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.h
M llvm/lib/Target/AMDGPU/GCNNSAReassign.h
M llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h
M llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h
M llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h
M llvm/lib/Target/AMDGPU/SILowerControlFlow.h
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h
M llvm/lib/Target/AMDGPU/SILowerWWMCopies.h
M llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.h
Log Message:
-----------
[NPM] Make few more passes required (#203511)
essentially a port of https://github.com/llvm/llvm-project/pull/148115.
matches legacy behaviour. MachineBlockPlacement is made optional since
it is optional in legacy as well. not sure if there was any reason to
make it required in NPM.
Commit: 37d488f15991d8c65666834a7aed14000d1393fa
https://github.com/llvm/llvm-project/commit/37d488f15991d8c65666834a7aed14000d1393fa
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/induction-condition-in-loop-exit.ll
M llvm/test/Transforms/ConstraintElimination/loops-header-tested-pointer-cmps.ll
Log Message:
-----------
[ConstraintElim] Look through post-increment in header EQ/NE compare. (#209199)
Extend the header-controlled induction handling to look through a
post-increment `PN + C` (constant C) on the compared value
For now, the new path is limited to deriving unsigned facts.
Alive2 Proof: https://alive2.llvm.org/ce/z/DCNeSr
PR: https://github.com/llvm/llvm-project/pull/209199
Commit: 922b1a9da0a16e9df23c1a91203cf37c24d5c26d
https://github.com/llvm/llvm-project/commit/922b1a9da0a16e9df23c1a91203cf37c24d5c26d
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/cmake/modules/FindDIASDK.cmake
Log Message:
-----------
Revert "[cmake] Fix VSINSTALLDIR check in FindDIASDK module (#208524)" (#209137)
This reverts commit 4c5e15667fe384e434961fe44cf5950dc309fdf1.
https://github.com/llvm/llvm-project/pull/208524 fixed a flag which
enabled testing with the DIA SDK. This broke all Windows build bots,
because the SDK is not available in the PATH.
Commit: add1925e5ee942794d7d6e8b4d65b32c959d472a
https://github.com/llvm/llvm-project/commit/add1925e5ee942794d7d6e8b4d65b32c959d472a
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
[AArch64] NFCI: Simplify LowerVectorFP_TO_INT_SAT (part 2) (#207199)
This simplifies the logic a bit more, such that the flow of the lowering
is as follows:
* Try to promote if necessary (fp16/bf16 types or src < dst)
* Try to handle natively (satwidth == srcwidth == dstwidth)
* Otherwise use min/max + truncate.
Commit: dbbd4e0de70b62c2e05d8a650ddcdff954ef8d0f
https://github.com/llvm/llvm-project/commit/dbbd4e0de70b62c2e05d8a650ddcdff954ef8d0f
Author: Ralf Jung <post at ralfj.de>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/docs/LangRef.md
Log Message:
-----------
[LangRef] select: describe behavior for undef and poison (#208724)
The poison semantics is based on
https://llvm.org/docs/UndefinedBehavior.html#propagation-of-poison-through-select.
IMO this definitely should appear in the "semantics" section of the
`select` instruction. If this isn't part of the `select` semantics I
don't know what is.
The undef semantics are based on what Alive does.
Commit: 8c75e8018d52ead8f97648b7b279671b89c59fa0
https://github.com/llvm/llvm-project/commit/8c75e8018d52ead8f97648b7b279671b89c59fa0
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/test/CodeGen/AArch64/neon/fullfp16.c
M clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
Log Message:
-----------
[CIR][AArc64] Add lowering for fp16 intrinsics (multiply extended) (#209222)
This PR adds lowering for the following intrinsic groups:
* https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#multiply-extended-1
It also moves the corresponding tests from:
* clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
to:
* clang/test/CodeGen/AArch64/neon/fullfp16.c
The lowering follows the existing implementation in
CodeGen/TargetBuiltins/ARM.cpp.
Commit: 19401e09c063367a3503ae6cc1a47babfa95f243
https://github.com/llvm/llvm-project/commit/19401e09c063367a3503ae6cc1a47babfa95f243
Author: Andrew Ng <andrew.ng at sony.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/Format/CMakeLists.txt
Log Message:
-----------
[clang-format] Fix `check-format-depends` CMake for Windows (#209205)
Add `find_program` for `touch`. Convert found program paths to native
form and use these paths in the command invocation.
Commit: aa5960600ac38fcd923e69777bad1293f56658d7
https://github.com/llvm/llvm-project/commit/aa5960600ac38fcd923e69777bad1293f56658d7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper.c
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/lib/Object/OffloadBinary.cpp
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
Revert "clang-linker-wrapper: Use AMDGPU::TargetID for device-image compatibility" (#209407)
Reverts llvm/llvm-project#209135
This shouldn't be doing logical linking compatibility
Commit: f6393d657271b632de22cdfeaff35cfb3d45bf92
https://github.com/llvm/llvm-project/commit/f6393d657271b632de22cdfeaff35cfb3d45bf92
Author: Manuel Carrasco <Manuel.Carrasco at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/docs/CommandGuide/lit.rst
M llvm/utils/lit/lit/cl_arguments.py
M llvm/utils/lit/lit/main.py
M llvm/utils/lit/lit/util.py
A llvm/utils/lit/tests/Inputs/time-tests/b.txt
A llvm/utils/lit/tests/Inputs/time-tests/c.txt
M llvm/utils/lit/tests/time-tests.py
Log Message:
-----------
[lit] Add configurable slowest-test limit to --time-tests (#208444)
The PR parameterizes `--time-tests`, which was hardcoded to 20 tests. We
now allow `--time-tests=N` or `--time-tests=all`.
The changes still honor the original behavior of `--time-tests`. The
parsing logic could be slightly simpler if `--time-tests` would always
require an explicit number of tests (like `-j`), but that would be a CLI
breaking change.
Commit: 1a8e5b6f594926adaaa0417543773108b7fd737d
https://github.com/llvm/llvm-project/commit/1a8e5b6f594926adaaa0417543773108b7fd737d
Author: Xiaomeng Zhang <zhangxiaomeng at hygon.cn>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86.td
M llvm/test/CodeGen/X86/slow-unaligned-mem.ll
M llvm/test/CodeGen/X86/x86-prefer-no-gather-no-scatter.ll
A llvm/test/Transforms/LoopVectorize/X86/x86-prefer-no-gather.ll
A llvm/test/Transforms/LoopVectorize/X86/x86-prefer-no-scatter.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-abs.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-add-saddo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-add-ssat.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-add-uaddo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-add-usat.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-add.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-div.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fix.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshl-rot.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshl.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshr-rot.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshr.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-mul-smulo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-mul-umulo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-mul.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-scmp.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-smax.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-smin.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-sub-ssat.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-sub-ssubo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-sub-usat.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-sub-usubo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-sub.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-ucmp.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-umax.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-umin.ll
M llvm/test/Transforms/SLPVectorizer/X86/fabs.ll
M llvm/test/Transforms/SLPVectorizer/X86/fcopysign.ll
M llvm/test/Transforms/SLPVectorizer/X86/fma.ll
M llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll
M llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll
M llvm/test/Transforms/SLPVectorizer/X86/fmuladd.ll
M llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
M llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
M llvm/test/Transforms/SLPVectorizer/X86/fround.ll
M llvm/test/Transforms/SLPVectorizer/X86/shift-ashr.ll
M llvm/test/Transforms/SLPVectorizer/X86/shift-lshr.ll
M llvm/test/Transforms/SLPVectorizer/X86/shift-shl.ll
M llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
M llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll
A llvm/test/Transforms/SLPVectorizer/X86/x86-prefer-no-gather.ll
Log Message:
-----------
[X86] Add tuning features for Hygon C86-4G-M7 (#205992)
Add TuningPreferNoGather. TuningPreferNoScatter and TuningPrefer256Bit to C864GM7Tuning.
This will improve the performance of the C86-4G-M7.
Commit: 79acf12724942b687b7c777e1dc46dd56ca4d287
https://github.com/llvm/llvm-project/commit/79acf12724942b687b7c777e1dc46dd56ca4d287
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/test/Driver/msvc-link.c
Log Message:
-----------
[clang] Use lld-link by default when -marm64x is specified (#209324)
ARM64X hybrid object files require lld-link, as it is currently the only
linker that supports them.
Commit: f2ada6d997fe4f4854f15f2c880dd740cd2ebb8a
https://github.com/llvm/llvm-project/commit/f2ada6d997fe4f4854f15f2c880dd740cd2ebb8a
Author: Luke Lau <luke at igalia.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
A llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-unroll.ll
Log Message:
-----------
[VPlan] Add test for convertToStridedAccess flag issue. NFC (#209425)
>From the comment in
https://github.com/llvm/llvm-project/pull/209168/changes#r3574524959
Commit: b3f5986138f2f6a65072b6822892afa5d8859cf7
https://github.com/llvm/llvm-project/commit/b3f5986138f2f6a65072b6822892afa5d8859cf7
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/test/CodeGen/AArch64/neon-fcvt-intrinsics.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
Log Message:
-----------
[clang][CIR][AArch64] Add lowering for conversion intrinsics (#209252)
This PR adds lowering for intrinsic from the following groups:
* https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#conversions
It continues the work started in #190961, #193273 and #199990. This PR
implements the remaining conversions truncating to zero:
* vcvtd_s32_f64
* vcvtd_s64_f64
* vcvtd_u32_f64
* vcvtd_u64_f64
The corresponding tests are moved from:
* clang/test/CodeGen/AArch64/
to:
* clang/test/CodeGen/AArch64/neon/
The lowering follows the existing implementation in
CodeGen/TargetBuiltins/ARM.cpp.
Commit: 95e647c8aa180f946c83d1e6f361989442206f52
https://github.com/llvm/llvm-project/commit/95e647c8aa180f946c83d1e6f361989442206f52
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/intrinsic-amdgcn-s-alloc-vgpr.ll
M llvm/test/CodeGen/AMDGPU/invalid-cast-load-i1.ll
M llvm/test/CodeGen/AMDGPU/invalid-hidden-kernarg-in-kernel-signature.ll
M llvm/test/CodeGen/AMDGPU/invariant-image-load.ll
M llvm/test/CodeGen/AMDGPU/ipra.ll
M llvm/test/CodeGen/AMDGPU/irtranslator-whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/isel-whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/issue121601-combine-concat-vectors-assumes-f16.ll
M llvm/test/CodeGen/AMDGPU/issue130120-eliminate-frame-index.ll
M llvm/test/CodeGen/AMDGPU/issue139317-bad-opsel-reg-sequence-fold.ll
M llvm/test/CodeGen/AMDGPU/issue153808-extract-subvector-legalize.ll
M llvm/test/CodeGen/AMDGPU/issue176966-extend-vector-inreg.ll
M llvm/test/CodeGen/AMDGPU/issue48473.mir
M llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
M llvm/test/CodeGen/AMDGPU/issue98474-assigned-physreg-interference.mir
M llvm/test/CodeGen/AMDGPU/issue98474-need-live-out-undef-subregister-def.ll
M llvm/test/CodeGen/AMDGPU/issue98474-virtregrewriter-live-out-undef-subregisters.mir
M llvm/test/CodeGen/AMDGPU/itofp.i128.bf.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
M llvm/test/CodeGen/AMDGPU/kernarg-size.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
M llvm/test/CodeGen/AMDGPU/kernel-mubuf-with-voffset.mir
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/kill-true-in-return-block.ll
M llvm/test/CodeGen/AMDGPU/known-never-nan.ll
M llvm/test/CodeGen/AMDGPU/known-never-snan.ll
M llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
M llvm/test/CodeGen/AMDGPU/large-alloca-graphics.ll
M llvm/test/CodeGen/AMDGPU/large-avgpr-assign-last.mir
M llvm/test/CodeGen/AMDGPU/large-constant-initializer.ll
M llvm/test/CodeGen/AMDGPU/large-phi-search.ll
M llvm/test/CodeGen/AMDGPU/large-work-group-promote-alloca.ll
M llvm/test/CodeGen/AMDGPU/lds-barrier-memoperand.ll
M llvm/test/CodeGen/AMDGPU/lds-bounds.ll
M llvm/test/CodeGen/AMDGPU/lds-branch-vmem-hazard.mir
M llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx11.mir
M llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx12.mir
M llvm/test/CodeGen/AMDGPU/lds-dma-hazards.mir
M llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir
M llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll
M llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-global-non-entry-func.ll
M llvm/test/CodeGen/AMDGPU/lds-initializer.ll
M llvm/test/CodeGen/AMDGPU/lds-limit-diagnostics-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/lds-limit-diagnostics.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-agpr.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-callgraph.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-named-barrier.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-typeid.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-named-barrier.ll
M llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
M llvm/test/CodeGen/AMDGPU/lds-mixed-absolute-addresses-unused.ll
M llvm/test/CodeGen/AMDGPU/lds-mixed-absolute-dynlds.ll
M llvm/test/CodeGen/AMDGPU/lds-no-realign-allocated-variables.ll
M llvm/test/CodeGen/AMDGPU/lds-reject-anonymous-kernels.ll
M llvm/test/CodeGen/AMDGPU/lds-reject-mixed-absolute-addresses.ll
M llvm/test/CodeGen/AMDGPU/lds-relocs.ll
M llvm/test/CodeGen/AMDGPU/lds-run-twice-absolute-md.ll
M llvm/test/CodeGen/AMDGPU/lds-run-twice.ll
M llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx950.ll
M llvm/test/CodeGen/AMDGPU/lds-size-pal-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/lds-size-pal-gfx950.ll
M llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll
M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/ldsdmacnt_sched.mir
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.dead.mir
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-fp-load-invariant.ll
M llvm/test/CodeGen/AMDGPU/legalize-soffset-mbuf.ll
M llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
M llvm/test/CodeGen/AMDGPU/licm-valu.mir
M llvm/test/CodeGen/AMDGPU/licm-wwm.mir
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (17) (#209120)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: db8ea12c3918fe10912298b7acfd21269d03cab2
https://github.com/llvm/llvm-project/commit/db8ea12c3918fe10912298b7acfd21269d03cab2
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt-c/Logging.h
M orc-rt/test/regression/logging/os_log/delivery.test
M orc-rt/test/tools/orc-rt-log-check.cpp
M orc-rt/test/unit/LoggingTest.cpp
Log Message:
-----------
[orc-rt] Add ORC_RT_LOG_PUB_S for logging runtime strings. (#209401)
ORC_RT_LOG requires its format to be a string literal, so the specifier
for a runtime C string cannot be written at the call site by hand -- and
it differs by backend: os_log redacts a plain "%s" argument to <private>
unless it carries a "%{public}s" annotation, which libc's printf does
not understand.
Add ORC_RT_LOG_PUB_S, which expands to "%{public}s" on the os_log
backend and plain "%s" everywhere else. Call sites compose it into the
format by literal adjacency, so the format stays a single literal on
every backend:
ORC_RT_LOG(Info, General, "resolved " ORC_RT_LOG_PUB_S, SymbolName);
LoggingTest covers the compile/format-check path (including os_log
builds); the orc-rt-log-check delivery test confirms os_log publishes
the string rather than redacting it to <private>.
Commit: e793eee71340131b7dcbfd5fce2edde84ab4ad5a
https://github.com/llvm/llvm-project/commit/e793eee71340131b7dcbfd5fce2edde84ab4ad5a
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
Log Message:
-----------
[ORC] Add LLLazyJIT destructor with call to endSession. (#209399)
Add an LLLazyJIT destructor with a call to ExecutionSession::endSession.
This ensures that the ExecutionSession's TaskDispatcher is shut down
(and in-flight tasks completed) before LLLazyJIT class members are
destroyed. Failure to do this could lead to use-after-free errors when
using thread-based task dispatch. This was likely the cause of flakiness
in test/ExecutionEngine/OrcLazy/multiple-compile-threads-basic.ll.
rdar://181982834
Commit: 2a6cc991cc691f2cc666483c417f01675321ce2c
https://github.com/llvm/llvm-project/commit/2a6cc991cc691f2cc666483c417f01675321ce2c
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
M llvm/lib/Target/SystemZ/SystemZInstrVector.td
M llvm/test/CodeGen/SystemZ/vec-max-05.ll
M llvm/test/CodeGen/SystemZ/vec-max-min-zerosplat.ll
M llvm/test/CodeGen/SystemZ/vec-min-05.ll
Log Message:
-----------
[SystemZ] Support pseudo fmin/fmax (#209178)
s390x supports the pseudo fmin/fmax operations (x < y ? x : y and x > y
? x : y) as mode 2 in vfmin/vfmax. As such, we should lower
PSEUDO_FMIN/FMAX to those. Also disable formation of minnum/maxnum in
SDAGBuilder, as it's not useful if we have native support for this
operation.
Commit: a9d295d615a81574eabb3645ed5d2eb5a5f4efd9
https://github.com/llvm/llvm-project/commit/a9d295d615a81574eabb3645ed5d2eb5a5f4efd9
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolutionDivision.cpp
Log Message:
-----------
[SCEVDivision] Add assertion to check operand types match (NFCI) (#204146)
In ScalarEvolutionDivision.h, the `SCEVDivision::divide` operation is
defined as follows:
```
/// Computes the Quotient and Remainder of the division of Numerator by
/// Denominator. We are not actually performing the division here. Instead, we
/// are trying to find SCEV expressions Quotient and Remainder that satisfy:
///
/// Numerator = Denominator * Quotient + Remainder
```
Therefore, I believe it makes sense to enforce that the types of
`Numerator` and `Denominator` are the same.
This patch adds an assertion to verify that restriction.
Commit: 96dcb03caa310852329c4e7ad1d678c024c6ed94
https://github.com/llvm/llvm-project/commit/96dcb03caa310852329c4e7ad1d678c024c6ed94
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
Log Message:
-----------
[NFC][LLVM][CodeGen][SVE] Strengthen the isel definition of AArch64setcc_z. (#209170)
Making all operand types derive from the compare's LHS reduces the
number of types an isel rule must specify, which improves readability.
Commit: 16094a86a6cfe79fa50dcca39b539ab6465b8ac0
https://github.com/llvm/llvm-project/commit/16094a86a6cfe79fa50dcca39b539ab6465b8ac0
Author: Srinivasa Ravi <srinivasar at nvidia.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Dialect/NVGPU/IR/NVGPUOps.td
M mlir/lib/Conversion/NVGPUToNVVM/CMakeLists.txt
M mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp
M mlir/lib/Dialect/NVGPU/IR/NVGPUDialect.cpp
A mlir/test/Conversion/NVGPUToNVVM/nvgpu-extf-large.mlir
A mlir/test/Conversion/NVGPUToNVVM/nvgpu-extf.mlir
A mlir/test/Conversion/NVGPUToNVVM/nvgpu-truncf-large.mlir
A mlir/test/Conversion/NVGPUToNVVM/nvgpu-truncf.mlir
A mlir/test/Dialect/NVGPU/nvgpu-extf-invalid.mlir
A mlir/test/Dialect/NVGPU/nvgpu-truncf-invalid.mlir
Log Message:
-----------
[MLIR][NVGPU] Add truncf and extf Ops (#199700)
This change adds the `extf` and `truncf` ops to the NVGPU dialect to
support floating-point conversion operations.
These ops support scalar and vector inputs and lower to the corresponding
NVVM ops after padding and chunking the input into `i32` registers.
Commit: c311e7b3d68cb88487c4dbc4029d101e4c19c908
https://github.com/llvm/llvm-project/commit/c311e7b3d68cb88487c4dbc4029d101e4c19c908
Author: Iurii Khosoi <aadaa_fgtaa at pm.me>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/test/CodeGen/X86/bitcnt-false-dep.ll
A llvm/test/CodeGen/X86/bls-false-dep.ll
A llvm/test/CodeGen/X86/compress-false-deps.ll
A llvm/test/CodeGen/X86/expand-false-deps.ll
Log Message:
-----------
[X86] Break false dependencies on Zen 4 and 5 (#206849) (#207079)
Some variants of Zen 5 microarchitectures have a false dependency on the
output register of tzcnt, blsr, blsi and blsmsk instructions. This PR
splits existing tuning feature for the false dependency of tzcnt/lzcnt
and adds a new tuning feature for bls*. The tzcnt and bls* tunings are
enabled by default for Zen 5.
Furthermore, at least some variants of Zen 4 and 5 microarchitectures
appear to have a false dependency on the output register of zero-masked
compress and expand instructions. Tested on Ryzen 9 9950X, Ryzen 9 7950X
and Ryzen AI 7 350, also apparent in uops.info data from Ryzen 5 7600X
and Ryzen 7 9700X (see #206849). This PR adds a new tuning feature for
the false dependency of compress/expand. The tuning is enabled for Zen 4
and Zen 5.
Fixes #206849
Commit: 7de5af16e0e72d6325d3dd63ee619a1cb3bce783
https://github.com/llvm/llvm-project/commit/7de5af16e0e72d6325d3dd63ee619a1cb3bce783
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/test/API/tools/lldb-dap/stackTrace/TestDAP_stackTrace.py
M lldb/test/API/tools/lldb-dap/stackTraceCompilerGeneratedCode/TestDAP_stackTraceCompilerGeneratedCode.py
M lldb/test/API/tools/lldb-dap/stackTraceDisassemblyDisplay/TestDAP_stackTraceDisassemblyDisplay.py
M lldb/test/API/tools/lldb-dap/stackTraceMissingFunctionName/TestDAP_stackTraceMissingFunctionName.py
M lldb/test/API/tools/lldb-dap/stackTraceMissingModule/TestDAP_stackTraceMissingModule.py
Log Message:
-----------
[lldb-dap] Migrate lldb-dap stackTrace tests (#209236)
Migrate
- TestDAP_stackTrace
- TestDAP_stackTraceDisassemblyDisplay
- TestDAP_stackTraceDisassemblyDisplay
- TestDAP_stackTraceMissingFunctionName
- TestDAP_stackTraceMissingModule
Commit: c1ae9eabc8b55aa4e2a06efacca6003ccecf6249
https://github.com/llvm/llvm-project/commit/c1ae9eabc8b55aa4e2a06efacca6003ccecf6249
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
[AArch64] Fixup possibly unused variable warning after #207199 (#209418)
Using [[maybe_unused]] as the variable is only used in asserts which
results in a diagnostic for no-assert builds.
Commit: 64de40e5cbfba35eb4118254326889dabb04bb6c
https://github.com/llvm/llvm-project/commit/64de40e5cbfba35eb4118254326889dabb04bb6c
Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/Rematerializer.h
M llvm/lib/CodeGen/Rematerializer.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/unittests/CodeGen/RematerializerTest.cpp
Log Message:
-----------
[CodeGen][AMDGPU] Prepare rematerializer for multi-def remat support (NFC) (#197579)
This makes some NFCs to the rematerializer before adding initial support
for rematerializing registers with multiple defs. The main change is
that, in the representation of (un)rematerializable register
dependencies, we drop references to machine operand indices which lose
meaning in the multi-def case.
Other minor changes listed below.
- Removal of `DefRegion` argument to `Rematerializer::recreateReg`.
Registers are always re-created in their original region so there is no
need to set their region again.
- Removal of `InsertPos` unused argument to
`Rematerializer::postRematerialization`.
- Refactor of how AMDGPU's scheduler checks whether a given register is
rematerializable.
Commit: 9582f71a3b5f71e871bee0062e641f3587e0ae23
https://github.com/llvm/llvm-project/commit/9582f71a3b5f71e871bee0062e641f3587e0ae23
Author: Mikołaj Piróg <mikolaj.maciej.pirog at intel.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86WinEHUnwindV3.cpp
M llvm/test/CodeGen/X86/win64-eh-unwindv3-split-large.ll
Log Message:
-----------
[UnwinderV3] Include padding in spliting calculations (#208458)
As in title. This is achieved by making the pass count split points in
bytes and making the average instruction size a variable.
PR done with usage of Claude Code
Commit: 24c3eaa9ccaffca94e4d82a312fcc4ed13e62476
https://github.com/llvm/llvm-project/commit/24c3eaa9ccaffca94e4d82a312fcc4ed13e62476
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/limit-soft-clause-reg-pressure.mir
M llvm/test/CodeGen/AMDGPU/literal-constant-like-operand-instruction-size.ll
M llvm/test/CodeGen/AMDGPU/literal64.ll
M llvm/test/CodeGen/AMDGPU/live-interval-bug-in-rename-independent-subregs.mir
M llvm/test/CodeGen/AMDGPU/liveout-implicit-def-subreg-redef-blender-verifier-error.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.add.min.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.addrspacecast.nonnull.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.wave32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitreplicate.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load-last-use.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.dwordx3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.lds.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.dwordx3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.flat.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-agent.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-basic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-singlethread.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-system.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-wavefront.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-workgroup.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubeid.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubema.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubesc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubetc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f32.fp8.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.e5m3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.off.f32.i4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.pk.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dot4.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.add.gs.reg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.append.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.atomic.async.barrier.arrive.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.atomic.barrier.arrive.rtn.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.fi.b32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.push.pop.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.consume.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-bundle.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.br.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.p.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.v.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add-errors.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add-unsupported.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx10.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.permute.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.read.tr.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.sub.gs.reg.rtn.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (18) (#209121)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping
the redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 23a32bcedb91f27ffdac5d6e6bc65a3b19b3b36c
https://github.com/llvm/llvm-project/commit/23a32bcedb91f27ffdac5d6e6bc65a3b19b3b36c
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolutionDivision.cpp
Log Message:
-----------
[SCEVDivision] Remove unnecessary integer casts (NFCI) (#208155)
Since #204146 requires callers of SCEVDivision to pass the numerator and
the denominator with the same type, the bitwidth check in
`visitConstant` no longer makes sense.
Commit: b1c29d83c938183a4fbd706818aa09de7e9eafec
https://github.com/llvm/llvm-project/commit/b1c29d83c938183a4fbd706818aa09de7e9eafec
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/docs/resources/lldbgdbremote.md
Log Message:
-----------
[lldb][docs] Fix some formatting in the packets doc (#209440)
Commit: 03b4714611ab0aab34c7267e0946fb79bf40babe
https://github.com/llvm/llvm-project/commit/03b4714611ab0aab34c7267e0946fb79bf40babe
Author: Sergey Shcherbinin <sscherbinin at nvidia.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M flang/test/Driver/function-attr-readonly.f90
Log Message:
-----------
[flang][NFC] Fix function-attr-readonly test on PowerPC (#209431)
Follow-up fix for the newly added test, which was not exercised on all
targets. PowerPC adds llvm.target_features between the function argument
list and the body. Stop requiring the opening brace to immediately
follow the argument list so that the checks remain target-independent.
Commit: 48636d19ab5e3bf82cbff593a82573e8094abed1
https://github.com/llvm/llvm-project/commit/48636d19ab5e3bf82cbff593a82573e8094abed1
Author: Joel Walker <theagingboy05 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/knownbits-avg.mir
M llvm/test/CodeGen/AArch64/aarch64-known-bits-hadd.ll
Log Message:
-----------
[GlobalISel] Add G_UAVGFLOOR/G_UAVGCEIL/G_SAVGFLOOR/G_SAVGCEIL to computeKnownBits (#209171)
Add known-bits handling for the averaging (halving add) opcodes G_UAVGFLOOR,
G_UAVGCEIL, G_SAVGFLOOR and G_SAVGCEIL in GISelValueTracking, using the
existing `KnownBits::avg{Floor,Ceil}{S,U}` helpers. This matches
SelectionDAG's handling of the corresponding ISD::AVGFLOOR*/AVGCEIL*
nodes.
This lets GlobalISel drop the redundant masking around hadd/rhadd of
zero-extended operands on AArch64 (see aarch64-known-bits-hadd.ll, where the
GlobalISel output now matches SelectionDAG). The sign-extended cases are
unaffected, since the masking is not redundant there.
Part of #150515.
---
Assisted by Claude (Anthropic).
Commit: cba0124e3c4f0bb5eebf551b049f8e463879642b
https://github.com/llvm/llvm-project/commit/cba0124e3c4f0bb5eebf551b049f8e463879642b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.compr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.prim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.flat.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fract.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fract.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.mant.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.mant.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.store.async.from.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticsize.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.AFLCustomIRMutator.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.large.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.simple.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.small.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.single.2b.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.single.2c.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.flt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.pk.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.d16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.d16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.o.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.getlod.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.x.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.nsa.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.cd.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.cd.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.cd.g16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.cd.g16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.o.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.wave32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.direct.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.param.load.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (19) (#209122)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: da99ce2fe0f4a185ceb02c9a650ba5efdb208612
https://github.com/llvm/llvm-project/commit/da99ce2fe0f4a185ceb02c9a650ba5efdb208612
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libc/include/llvm-libc-macros/linux/signal-macros.h
M libc/test/src/signal/sigaction_test.cpp
Log Message:
-----------
[libc] Implement SA_NODEFER and SA_RESETHAND signal flags (#209429)
Defined SA_NODEFER and SA_RESETHAND in Linux signal-macros.h.
Added unit tests in sigaction_test.cpp to verify the behavior of the new
flags. Also added a test case for SA_SIGINFO.
Assisted-by: Automated tooling, human reviewed.
Commit: b4b19c8f0cc28c20d98fe2ebcd2e869d0835c8eb
https://github.com/llvm/llvm-project/commit/b4b19c8f0cc28c20d98fe2ebcd2e869d0835c8eb
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lerp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.tr.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.clamp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mbcnt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.form.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.i8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.gfx1251.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.u32.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.msad.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mulhi.i24.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mulhi.u24.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.bcast.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.down.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.idx.gen.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.up.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.xor.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane32.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.prng.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.buffer.atomic.fadd_rtn_errors.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.queue.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.xfail.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.bf16.xfail.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.nxv2i32.fail.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.legacy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.m0.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (20) (#209211)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping
the redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 5d5dd83a547ea555a8eada2dfd50413c44a3cfe9
https://github.com/llvm/llvm-project/commit/5d5dd83a547ea555a8eada2dfd50413c44a3cfe9
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M flang/lib/Optimizer/Passes/Pipelines.cpp
M llvm/include/llvm/Passes/OptimizationLevel.h
M llvm/include/llvm/Transforms/IPO/ExpandVariadics.h
M llvm/lib/Passes/CMakeLists.txt
R llvm/lib/Passes/OptimizationLevel.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
M polly/lib/Support/RegisterPasses.cpp
Log Message:
-----------
[Passes] Replace OptimizationLevel with an enum (#209424)
Now that OptimizationLevel no longer has a size dimension, replace it
with a simple enum class.
Commit: 367d196e5cf964a1d89d596e13c89868da8c4d8c
https://github.com/llvm/llvm-project/commit/367d196e5cf964a1d89d596e13c89868da8c4d8c
Author: Anonmiraj <ezzibrahimx at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/Lex/Preprocessor.cpp
Log Message:
-----------
[clang][Diagnostics] Fix check-point recording under default colors (#209355)
`getShowColors() != ShowColorsKind::Off` is also true for the default
Auto, so ordinary non-TTY compiles where colors are never actually
emitted kept recording check points, leaving the original 718aac9f cost
in place.
Commit: ad3c1ef174f9cac5bd0332747226740ce1b16159
https://github.com/llvm/llvm-project/commit/ad3c1ef174f9cac5bd0332747226740ce1b16159
Author: Gábor Horváth <xazax.hun at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/Analysis/LiveVariables.cpp
Log Message:
-----------
[clang][Analysis] Speed up LiveVariables set merge (#209430)
LiveVariables' mergeSets built the union by unconditionally inserting
every element of B into A. Apply the two cheap tricks the
lifetime-safety analysis uses in its dataflow join:
* Return early when both operands are the same tree (an O(1) pointer
comparison), skipping the merge entirely. Merged liveness values are
canonicalized, so two predecessors with identical liveness share the
same tree -- common at confluence points.
* Insert the smaller set into the larger one, so the number of O(log n)
insertions is min(|A|, |B|) rather than always |B|.
The result is unchanged: set union is commutative and order-independent.
On a pathological function (1000 simultaneously-live locals across 5000
control-flow merges of identical sets) the liveness computation is ~18%
faster, essentially all from the identical-set short circuit. On real
translation units the merge is a small fraction of the analysis, so the
effect is within noise (measured neutral on DAGCombiner.cpp and
X86ISelLowering.cpp); this mainly avoids redundant work at unchanged
confluence points and brings the two dataflow analyses' merges into
line.
Assisted by: Claude Opus 4.8
Co-authored-by: Gabor Horvath <gaborh at apple.com>
Commit: edd94b8fbfae72059cbe31c78ac4580056b6bb9a
https://github.com/llvm/llvm-project/commit/edd94b8fbfae72059cbe31c78ac4580056b6bb9a
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/include/lldb/Utility/Log.h
M lldb/source/Commands/CommandObjectLog.cpp
M lldb/source/Utility/Log.cpp
M lldb/unittests/Utility/LogTest.cpp
Log Message:
-----------
[lldb] Return llvm::Error from DisableLogChannel (#207004)
Follow up to #206479.
llvm:Error better describes the success exor error message states that
we were previously doing with a boolean plus an error stream.
Commit: 42d52dfb9ceae5cb261b6032e50fba512479c7ce
https://github.com/llvm/llvm-project/commit/42d52dfb9ceae5cb261b6032e50fba512479c7ce
Author: Ömer Sinan Ağacan <omeragacan at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
Log Message:
-----------
[SelectionDAG] Update MemOp to distinguish memmove from memcpy (#206005)
Commit: 0c36950dd422b118b29621c4fc3e0c91cfcfd346
https://github.com/llvm/llvm-project/commit/0c36950dd422b118b29621c4fc3e0c91cfcfd346
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 16094a8 (#209435)
This fixes 16094a86a6cfe79fa50dcca39b539ab6465b8ac0.
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=16094a86a6cfe79fa50dcca39b539ab6465b8ac0
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 269820947e948a4e4bd0b3e352b6c2bd77525e83
https://github.com/llvm/llvm-project/commit/269820947e948a4e4bd0b3e352b6c2bd77525e83
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.clamp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.decperflevel.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.get.waveid.in.workgroup.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.incperflevel.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memrealtime.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memtime.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.monitor.sleep.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.nop.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.inst.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sethalt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.inc.wg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.ttracedata.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt_gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.hi.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.iterative.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.chain.arg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sffbh.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.softwqm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.load.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (21) (#209212)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping
the redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: f5a55b576add124ef5350d81089eccda7103cb93
https://github.com/llvm/llvm-project/commit/f5a55b576add124ef5350d81089eccda7103cb93
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/include/mlir/TableGen/Format.h
Log Message:
-----------
[MLIR][NFC] Fix tgfmt compilation with MSVC (#209446)
Apparently older MSVC has problems with inferring template argument
types. Provide them explicitly.
Fixes https://github.com/llvm/llvm-project/issues/209303.
Commit: cd75ff08c6baf74114933a927308e8ce581efc70
https://github.com/llvm/llvm-project/commit/cd75ff08c6baf74114933a927308e8ce581efc70
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Log Message:
-----------
[VPlan] Type VP(Recipe|Block)Ty SubclassID (NFC) (#209132)
With the advantage that switching over the SubclassID would give better
compile-time diagnostics.
Co-authored-by: Luke Lau <luke at igalia.com>
Commit: 4b32060e213376bf1d014ffc3a462c959d8adc0a
https://github.com/llvm/llvm-project/commit/4b32060e213376bf1d014ffc3a462c959d8adc0a
Author: disservin <disservin.social at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/bitreverse.ll
Log Message:
-----------
[X86] Use BMM for bitreverse without GFNI (#209223)
For the scalar path bitreverse currently doesn't lower to vbitrevb on
AVX512-BMM unless GFNI is specified as well. However, GFNI isn't
required at all for this and only BMM needs to be present.
See https://godbolt.org/z/xr61xYzYr
Commit: 5ae6537bbaf577889fb81f5f8397463b0d0499c3
https://github.com/llvm/llvm-project/commit/5ae6537bbaf577889fb81f5f8397463b0d0499c3
Author: ioana ghiban <ioana.ghiban at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/lib/Conversion/EmitCCommon/TypeConverter.cpp
M mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitC.cpp
M mlir/test/Conversion/FuncToEmitC/func-to-emitc-failed.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-alloc-dealloc.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-alloc-load-store.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-copy.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-failed.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc.mlir
Log Message:
-----------
[mlir][EmitC] Add rank-0 MemRef conversion (#205774)
Add rank-0 memref support to MemRefToEmitC and the EmitC TypeConverter,
needed for lowering the models generated by:
- `llvm/lib/Analysis/models/gen-inline-oz-test-model.py`
- `llvm/lib/Analysis/models/gen-regalloc-eviction-test-model.py`
Rank-0 memrefs are no longer rejected by `isMemRefTypeLegalForEmitC`.
The EmitC type converter maps `memref<T>` to `!emitc.ptr<T>`, giving
rank-0 memrefs addressable scalar storage.
`memref.alloc` now allocates one element for rank-0 memrefs.
`memref.dealloc` frees the pointer-backed value. `memref.load` and
`memref.store` lower rank-0 accesses through `emitc.subscript %ptr[0]`,
followed by `emitc.load` or `emitc.assign`. `memref.copy` lowers rank-0
copies as scalar load plus assign.
`memref.alloca` still rejects rank-0 memrefs because this patch only
supports pointer-backed rank-0 lowering.
The pointer recovery helper now accepts both direct `emitc.ptr<T>`
values and pointer values behind `builtin.unrealized_conversion_cast`,
which is needed by dealloc, copy, load, and store depending on where the
value comes from in conversion.
Tests cover rank-0 alloc/dealloc, load/store, alloc-backed load/store,
and copy. Removed cases this patch adds support for (rank-0) from
`func-to-emitc-failed`.
Assisted-by: Codex (refine implementation + tests). I reviewed all code
and tests before submission.
Commit: 2d1bc4fc5d00d6c96307d5375d7259011509faf3
https://github.com/llvm/llvm-project/commit/2d1bc4fc5d00d6c96307d5375d7259011509faf3
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/src/atomic.cpp
Log Message:
-----------
[libc++] Fix usage of constructive interference when we meant destructive (#208804)
We maintain a contention table to implement atomic wait/notify inside
atomic.cpp. Entries in that table are padded to avoid false sharing,
since they are expected to be accessed from multiple threads
concurrently.
However, we used std::hardware_constructive_interference_size for that,
when in reality std::hardware_destructive_interference_size is the one
we need. The semantics of constructive interference are to promote true
sharing for data that should stay colocated, while destructive
interference is to prevent false sharing.
Note that on platforms such as macOS arm64, destructive interference
size is larger than constructive interference size, which means that
this patch may regress the size of the dylib on some platforms. However,
that is required for performance purposes.
Fixes #208305
Commit: bf086335b25387ed7496577eb027531ea287f524
https://github.com/llvm/llvm-project/commit/bf086335b25387ed7496577eb027531ea287f524
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sudot4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sudot8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.dwordx3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.dwordx3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waitcnt.out.order.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.shuffle.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wavefrontsize.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.fmt-error.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.index.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma_32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma_64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id-unsupported-calling-convention.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.demote.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.vote.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.ll
M llvm/test/CodeGen/AMDGPU/llvm.deoptimize.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.memcpy.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.modf.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.pow-gfx9.ll
M llvm/test/CodeGen/AMDGPU/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.ll
M llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/lo16-hi16-illegal-copy.mir
M llvm/test/CodeGen/AMDGPU/lo16-hi16-physreg-copy.mir
M llvm/test/CodeGen/AMDGPU/lo16-lo16-physreg-copy-agpr.mir
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (22) (#209213)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping
the redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 6e515cd0982dbf8db7ab3850b23994396efb40bf
https://github.com/llvm/llvm-project/commit/6e515cd0982dbf8db7ab3850b23994396efb40bf
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
[lldb][Windows] add release notes for lldb-server (#209415)
As of https://github.com/llvm/llvm-project/pull/209258,
`lldb-server.exe` is now the default plugin if libxml2 is available at
build time.
This patch adds a release note for this change.
Commit: 98c4ea46bd474bff97c99be0800bd7b310185a29
https://github.com/llvm/llvm-project/commit/98c4ea46bd474bff97c99be0800bd7b310185a29
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/cmake/Modules/HandleLibCXXABI.cmake
Log Message:
-----------
[libc++] Improve diagnostic for libcxxabi missing from the runtimes (#208274)
When libc++ is configured to use libc++abi as an ABI library but
libcxxabi is not part of the runtimes, we'd end up with a confusing
build error about a missing <cxxabi.h> header. Instead, diagnose at
CMake configuration time.
Closes #136480
Commit: 23b3f21fd0fff64644cf60065b971686aab9c1b3
https://github.com/llvm/llvm-project/commit/23b3f21fd0fff64644cf60065b971686aab9c1b3
Author: inquisitivecrystal <open-source at inquisitivecrystal.addy.io>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/docs/Status/Cxx20Papers.csv
M libcxx/docs/Status/Cxx23Issues.csv
Log Message:
-----------
[libc++] Mark LWG3403 as complete (#208866)
LWG3403 specifies that `ranges::ssize` should work on non-range objects
for which `ranges::size` is valid. This has been true in libc++ since
6f1b10d, which first implemented `ranges::ssize` for libc++13. The tests
introduced by that commit are sufficient to verify compliance since they
test calling `ranges::ssize` with various non-range arguments.
In addition to marking LWG3403 as complete, this also updates the status
page entry for P1970R2, the paper that added `ranges::ssize`. P1970R2 was
previously marked complete in libc++15 as an approximation; however, it was
actually complete in libc++13.
Resolves #104280
Commit: cf9a244fb2216fb55b77e1df785f6535b44b3e7f
https://github.com/llvm/llvm-project/commit/cf9a244fb2216fb55b77e1df785f6535b44b3e7f
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libc/include/llvm-libc-macros/gpu/signal-macros.h
M libc/include/llvm-libc-macros/linux/signal-macros.h
M libc/include/llvm-libc-macros/netinet-in-macros.h
M libc/include/llvm-libc-types/__futex_word.h
M libc/include/sys/prctl.h.def
Log Message:
-----------
[libc] Fix non-relative includes of __llvm-libc-common.h (#209412)
This seems to work, but I ran into this problem when trying to expand
hermetic tests.
The hdrgen-generated headers already use relative includes of this file.
Commit: cd943207f38d36528a36009e55f80501da98bcef
https://github.com/llvm/llvm-project/commit/cd943207f38d36528a36009e55f80501da98bcef
Author: Mark Zhuang <mark.zhuang at spacemit.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M flang-rt/CMakeLists.txt
Log Message:
-----------
[flang-rt] Disable tests by default when cross-compiling (#208926)
Cross-compiled tests can't run on the build host and pull in host
dependencies (e.g. LLVMSupport's ZLIB::ZLIB) that break the build.
Fixes #208924
Commit: d64972c91369c6372e23e728881d9c645edeb37d
https://github.com/llvm/llvm-project/commit/d64972c91369c6372e23e728881d9c645edeb37d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper.c
Log Message:
-----------
clang-linker-wrapper: Add additional amdgpu device merging tests (#209428)
Commit: 12ce00a865b09cb72a3ea9a84f9308236a4f6038
https://github.com/llvm/llvm-project/commit/12ce00a865b09cb72a3ea9a84f9308236a4f6038
Author: Ben Dunbobbin <Ben.Dunbobbin at sony.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
A cross-project-tests/dtlto/cache-extraction.test
R cross-project-tests/dtlto/cache-serialization.test
M lld/test/ELF/dtlto/timetrace.test
M llvm/include/llvm/DTLTO/DTLTO.h
M llvm/include/llvm/LTO/LTO.h
M llvm/lib/DTLTO/DTLTO.cpp
M llvm/lib/DTLTO/DTLTOInputFiles.cpp
Log Message:
-----------
[DTLTO] terminology - use extract rather than serialize (#208468)
Change the terminology used for DTLTO from "serialization" to
"extraction" for improved clarity.
Update the DTLTO time-trace scope and tests to match the new wording,
and rename/update related LLD and cross-project DTLTO cache tests.
I have also improved some unrelated wording in the comments and removed
a redundant comment block from the DTLTO class comment.
This terminology improvement was agreed in
https://github.com/llvm/llvm-project/pull/204104. Note that the
documentation already uses this terminology, see:
https://llvm.org/docs/DTLTO.html.
Commit: 226acaf7aeeda64a6e4e55d21f586ffe97a72fc8
https://github.com/llvm/llvm-project/commit/226acaf7aeeda64a6e4e55d21f586ffe97a72fc8
Author: Osama Abdelkader <osama.abdelkader at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/Sema/DeclSpec.cpp
M clang/test/SemaCXX/auto-cxx0x.cpp
Log Message:
-----------
Fix auto type-specifier conflict crash (#209308)
Clear owned type state when an invalid C++ auto/type-specifier conflict
is converted to an error so invalid declarations cannot trip DeclSpec
invariants.
Fixes https://github.com/llvm/llvm-project/issues/209000
Commit: 40152b8767769873a8f0d99b857f07c874cccf4a
https://github.com/llvm/llvm-project/commit/40152b8767769873a8f0d99b857f07c874cccf4a
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/include/__functional/function.h
Log Message:
-----------
[libc++][NFC] Inline std::function members into the class body (#209461)
The `std::function` members are incredibly simple to the point where
they are just wrappers around internal functions. We can inline them
into the body to simplify the implementation a bit.
Commit: 8748e5e3ac5d06663c3f2057a71ef19065baebaf
https://github.com/llvm/llvm-project/commit/8748e5e3ac5d06663c3f2057a71ef19065baebaf
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt/Compiler.h
M orc-rt/test/unit/CMakeLists.txt
A orc-rt/test/unit/CompilerTest.cpp
Log Message:
-----------
[orc-rt] Add ORC_RT_UNREACHABLE / ORC_RT_BUILTIN_UNREACHABLE (#209466)
ORC_RT_BUILTIN_UNREACHABLE is an optimizer hint that a location is
unreachable, wrapping __builtin_unreachable / __assume(false). Executing
it is undefined behavior.
ORC_RT_UNREACHABLE(MSG) marks a point the program must never reach. It
aborts with MSG in +Asserts builds; otherwise it lowers to
ORC_RT_BUILTIN_UNREACHABLE.
Adds a CompilerTest unit test covering both the returning-function
compile path and, in +Asserts builds only, the abort behavior via a
death test.
Commit: 2e86804e612fc6d1bace4e08b8404d0ea383d368
https://github.com/llvm/llvm-project/commit/2e86804e612fc6d1bace4e08b8404d0ea383d368
Author: Scott Manley <rscottmanley at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsCG.h
M mlir/lib/Dialect/OpenACC/Transforms/ACCRecipeMaterialization.cpp
M mlir/test/Dialect/OpenACC/acc-recipe-materialization-reduction.mlir
Log Message:
-----------
[OpenACC] apply seq par dims to reduction variables (#209261)
When the acc.parallel op is "effectively sequential" apply the correct
par dims during recipe materialization of reduction variables
Commit: fba1a4b1292af3e7d08e9678e967ce12795d67d4
https://github.com/llvm/llvm-project/commit/fba1a4b1292af3e7d08e9678e967ce12795d67d4
Author: Hrólf Kraki <janmejayapanda400 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/Sema/SemaOverload.cpp
M clang/test/SemaCXX/recovery-expr-type.cpp
Log Message:
-----------
[clang] Prevent nested RecoveryExpr in BuildConvertedConstantExpression (#207072)
when BuildConvertedConstantExpression receives an expression that is
already a RecoveryExpr, return it directly instead of wrapping it in
another RecoveryExpr
Fixes #186656
Fixes #202117
Commit: 8518c74b5ef8950b9b604df588f29d9037fe1380
https://github.com/llvm/llvm-project/commit/8518c74b5ef8950b9b604df588f29d9037fe1380
Author: 1sgtpepper <cynejarviszarceno at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Target/LLVMIR/Import/function-attributes.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[mlir][llvm] Preserve function entry count metadata (#204707)
Fixes #202374.
Preserve LLVM function `!prof` metadata for:
- `synthetic_function_entry_count`
- `function_entry_count` with import GUID operands
The importer represents the entry count, count kind, and trailing import
GUID operands in a single `#llvm.function_entry_count` attribute,
validates malformed operands before mutating the operation, and exports
the metadata through `llvm::Function::setEntryCount`.
Tests cover import, export, malformed metadata operands, synthetic
counts, synthetic counts with trailing operands, import GUID
round-tripping, and raw i64 bit-pattern preservation.
Checks:
- `git diff --check`
- `git clang-format --diff origin/main -- ...`
- `llvm-as -disable-output` smoke check
Codex was used in making this PR.
Commit: 571a27629c1bdf0b63e65a884ffa35c5c3ede767
https://github.com/llvm/llvm-project/commit/571a27629c1bdf0b63e65a884ffa35c5c3ede767
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M orc-rt/test/unit/CMakeLists.txt
Log Message:
-----------
[orc-rt] Sort unit test sources in CMakeLists.txt. NFC. (#209470)
Commit: b26c417dd887aec06f4a09cd23a979b705c59fa2
https://github.com/llvm/llvm-project/commit/b26c417dd887aec06f4a09cd23a979b705c59fa2
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Analysis/InlineCost.cpp
M llvm/test/Transforms/Inline/byval.ll
Log Message:
-----------
[InlineCost] Drop Requirements around ByVal Arguments
The underlying behavior was fixed in
e47359a925b88cd081ea85d10b55b0625d17b212, but given that the example
was marked alwaysinline, it bypassed any legality checks it would have
otherwise hit.
See
https://github.com/llvm/llvm-project/pull/97306#discussion_r1679306183
for discussion around which address space we should be using/legality.
This is necessary to preserve the behavior in
byval-with-non-alloca-addrspace.ll after we enable function attribute
compatibility checks in always-inline.
Reviewers: aeubanks, nikic, arsenm
Pull Request: https://github.com/llvm/llvm-project/pull/209344
Commit: 37b8e765ce4837a7577e6f762bcdffe4b232759c
https://github.com/llvm/llvm-project/commit/37b8e765ce4837a7577e6f762bcdffe4b232759c
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/IPO/AlwaysInliner.cpp
A llvm/test/Transforms/Inline/X86/always-inline-incompatible-target-features.ll
M llvm/test/Transforms/Inline/always-inline-phase-ordering.ll
Log Message:
-----------
[AlwaysInliner] Do not inline on attribute mismatches
7bdca287b102ee935e982613dba2264cbc7a32ad made it so that the inliner
will not inline functions with mismatched target attributes regardless
of the presence of alwaysinline. However, always-inline never actually
called into this function so would still do the illegal thing. I believe
the motivation for not putting it here originally/recently was that
clang does some rudimentary target feature checks, but we should not be
crashing on valid IR, and we do generate IR that caused crashes in ISel
due to this (e.g., ICP in ThinLTO backend actions).
Reviewers: nikic, aeubanks
Pull Request: https://github.com/llvm/llvm-project/pull/209345
Commit: c43967ca744ae2479987c1859df36fbb2fcf0866
https://github.com/llvm/llvm-project/commit/c43967ca744ae2479987c1859df36fbb2fcf0866
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/unittests/StaticAnalyzer/FalsePositiveRefutationBRVisitorTest.cpp
Log Message:
-----------
[analyzer] Uplift UnSatAtErrorNodeDueToRefinedConstraint test after smarter range inference (#209443)
Commit db28e48d67e3b0c44d88be9ea2d28eca2d239a9a taught
`SymbolicRangeInferrer` to derive the range of
`BO_Add`/`BO_Sub`/`BO_Mul` symbols from their operands via
`inferFromCorners`. This broke
`FalsePositiveRefutationBRVisitorTestBase.UnSatAtErrorNodeDueToRefinedConstraintNoReport`.
The test relied on the analyzer not being able to bound `int y = x + n;`
(with `x:[0,2]`, `n:[1,2]`), so that `reportIfCanBeTrue(y == 5)` created
a false state that only the Z3 crosscheck could refute. Now the analyzer
natively bounds y to `[1,4]`, proves `y == 5` infeasible, and never
emits `CAN_BE_TRUE`, so the non-Z3 assertion lost its second line.
Addition can never produce a gap (the sum of two intervals is a full
interval), so the test's premise is no longer achievable with '+'.
Switch to multiplication: for `x:[0,2]`, `n:[1,2]` the reachable
products are `{0,1,2,4}`, but `inferFromCorners` over-approximates `x*n`
to the contiguous range `[0,4]`. So `y == 3` is inside the inferred
range (native manager returns `UNKNOWN -> CAN_BE_TRUE` emitted without
Z3) yet is genuinely unreachable (Z3 refutes `x*n == 3` -> report
invalidated with crosscheck). This restores the exact refutation-visitor
mechanism the test exercises.
Fixes up #209048.
This issue would have been caught if we had a CI running Z3, like
proposed in #184695.
Assisted-by: Claude Opus 4.8
Commit: fb423ba07c3ff51fda3caa41d8bbb78d50f61906
https://github.com/llvm/llvm-project/commit/fb423ba07c3ff51fda3caa41d8bbb78d50f61906
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
A llvm/test/Assembler/thinlto-bad-summary-5.ll
Log Message:
-----------
[ThinLTO] Error on missing ValueInfo for function definition
We assume that these are available inside of BitcodeWriter
https://github.com/llvm/llvm-project/blob/09796808802f99c30a23bc0f2cd68243764e84ab/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp#L4927,
but do not currently validate this in input IR. This means that when
doing reductions with automated tooling in a non-asserts build, it is
pretty easy to end up with invalid IR that is not caught as invalid.
Reviewers: teresajohnson, mtrofin
Pull Request: https://github.com/llvm/llvm-project/pull/208948
Commit: 6af0a79d7a4e8558e89290df56491521c6730acd
https://github.com/llvm/llvm-project/commit/6af0a79d7a4e8558e89290df56491521c6730acd
Author: Douglas Yung <douglas.yung at sony.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang-tools-extra/docs/ReleaseNotes.rst
M clang/docs/ReleaseNotes.md
M cmake/Modules/LLVMVersion.cmake
M flang/docs/ReleaseNotes.md
M libcxx/include/__config
M lld/docs/ReleaseNotes.rst
M llvm/docs/ReleaseNotes.md
M llvm/utils/gn/secondary/llvm/version.gni
M llvm/utils/lit/lit/__init__.py
M llvm/utils/mlgo-utils/mlgo/__init__.py
Log Message:
-----------
Bump version to 24.0.0git (#209473)
Commit: aefba88f46a6e55645c848f58f6ba56944d5ae62
https://github.com/llvm/llvm-project/commit/aefba88f46a6e55645c848f58f6ba56944d5ae62
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/test/CodeGen/AArch64/sve-cmp-folds.ll
Log Message:
-----------
[LLVM][CodeGen][SVE] Add isel for zext(setcc(x,0,ne)) -> umin(x,1). (#209452)
Commit: c5022b53e409f68de0a21039f536d0119bb666c9
https://github.com/llvm/llvm-project/commit/c5022b53e409f68de0a21039f536d0119bb666c9
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZInstrVector.td
A llvm/test/CodeGen/SystemZ/vec-strict-pseudo-max.ll
A llvm/test/CodeGen/SystemZ/vec-strict-pseudo-min.ll
Log Message:
-----------
[SystemZ] Add support for strict_pseudo_fmin/fmax (#209434)
Mode 2 of vfmin/vfmax is also compatible with strict semantics
(producing invalid operation exception for both qNaN and sNaN and
returning RHS if masked.)
Commit: 6d12cf1389fa3ef57f880b8c0b25e66f0caa2f32
https://github.com/llvm/llvm-project/commit/6d12cf1389fa3ef57f880b8c0b25e66f0caa2f32
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/Analysis/CGSCCPassManager.h
M llvm/include/llvm/CodeGen/MachinePassManager.h
M llvm/include/llvm/IR/PassManager.h
M llvm/include/llvm/IR/PassManagerInternal.h
M llvm/include/llvm/Transforms/Scalar/LoopPassManager.h
Log Message:
-----------
Reapply "[IR][NFC] Drop vtable from PassConcept/PassModel" (#208168) (#209414)
The PassConcept/PassModel vtable has a size of 64 bytes (offset to top,
RTTI pointer, complete object destructor, deleting destructor, run,
printPipeline, name, isRequired), which add up to 53kiB (all
targets)/44 kiB (single-target). As more back-end passes get ported to
the new pass manager, this size will increase.
Remove the vtables by replacing the virtual dispatch with explicit
function pointers, initialized when adding the pass to the pass manager.
While this very slightly increases the cost of adding a pass, there's
also a very slight win from avoiding the vtable indirection when
running/destructing the pass.
Use a unique_ptr with a custom deleter to store PassConcept instances.
This avoids new/delete size mismatches.
This reverts commit 6ae5965f26e53d7338a779a73725a597a4d136e5.
Commit: b1a6a90dff53b60d66f49516938ef47344a45699
https://github.com/llvm/llvm-project/commit/b1a6a90dff53b60d66f49516938ef47344a45699
Author: Vachan <vachanvy05 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/test/CodeGen/X86/bitcnt-load-with-cmov.ll
A llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt-i64.ll
A llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt.ll
A llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt-i64.ll
A llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt.ll
Log Message:
-----------
[X86] Remove redundant `cmp` before `adc` after `lzcnt` or `tzcnt` (#208392)
fixes #193178
Commit: 3205689645eea30c9d7fde2474bdeff52629210d
https://github.com/llvm/llvm-project/commit/3205689645eea30c9d7fde2474bdeff52629210d
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M orc-rt/test/unit/ErrorTest.cpp
Log Message:
-----------
[orc-rt] Move ErrorTest death tests to an ErrorDeathTest suite. (#209476)
GoogleTest recommends putting death tests in a suite whose name ends in
"DeathTest": it runs those suites before all others, which avoids the
fork-after-threads hazard that can make death tests flaky.
Move the nine EXPECT_DEATH tests in ErrorTest.cpp from the ErrorTest
suite to a new ErrorDeathTest suite. Only the suite name changes; the
test bodies are untouched.
Commit: 1b10cd91d12d783fe8754c100a3afaacfee3bf9f
https://github.com/llvm/llvm-project/commit/1b10cd91d12d783fe8754c100a3afaacfee3bf9f
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/non-power-of-2-with-adjusted-gathers.ll
M llvm/test/Transforms/SLPVectorizer/X86/control-deps-schedule-data-recalculate.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-root-multiuse-same-opcode.ll
Log Message:
-----------
[SLP]Do not blacklist ordered-reduction operands on failed root attempt
An ordered reduction pulls its leaf operands into ReductionOps via the
fallback in matchAssociativeReduction. When such a reduction fails to
vectorize, marking every reduction op as analyzed also blocks those leaves,
which may still be valid reduction roots on their own.
Fixes https://github.com/llvm/llvm-project/pull/185320#issuecomment-4925949343
Reviewers: hiraditya, bababuck, RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/208511
Commit: db63c56a4f985426a0c44de4da215eb06cd5a278
https://github.com/llvm/llvm-project/commit/db63c56a4f985426a0c44de4da215eb06cd5a278
Author: Midhunesh <midhunesh.p at ibm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M compiler-rt/lib/asan/AIX/asan.link_with_main_exec.txt
M compiler-rt/lib/asan/asan_malloc_linux.cpp
M compiler-rt/test/asan/TestCases/AIX/vec_malloc_calloc.cpp
Log Message:
-----------
[ASan][AIX] Intercept __linux_vec_malloc/__linux_vec_calloc/__linux_realloc (#209359)
On AIX PASE, when `__VEC__` and `_ALL_SOURCE` are defined, the XL
compiler frontend lowers calls to vec_malloc/vec_calloc/realloc to
internal symbols named `__linux_vec_malloc`, `__linux_vec_calloc`, and
`__linux_realloc` instead of the standard
`vec_malloc`/`vec_calloc`/`realloc` names. These symbols were not
intercepted, so allocations made through them bypassed ASan entirely, no
redzone poisoning, no use-after-free or overflow detection.
This adds interceptors for `__linux_vec_malloc`, `__linux_vec_calloc`,
and `__linux_realloc`, following the same pattern as the existing
`vec_malloc`/`vec_calloc` interceptors (#175584): `__linux_vec_malloc`
and `__linux_vec_calloc` route through
`asan_vec_malloc`/`asan_vec_calloc` (16-byte aligned), and
`__linux_realloc` routes through the existing `asan_realloc`.
---------
Co-authored-by: Midhunesh <midhuensh.p at ibm.com>
Commit: e731908c4f84e04a5bfbe2784231f072aac90fe6
https://github.com/llvm/llvm-project/commit/e731908c4f84e04a5bfbe2784231f072aac90fe6
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaConcept.cpp
M clang/test/SemaCXX/concepts-subsumption.cpp
Log Message:
-----------
[Clang] Adjust NTTP depths in IsAtLeastAsConstrained (#209445)
The default transform for NTTP, which is no-op, doesn't help if we need
to adjust their depths when comparing constraints.
Fixes https://github.com/llvm/llvm-project/issues/182671
Commit: 53da348e107f8e6a52625ceab355c6d200a9709a
https://github.com/llvm/llvm-project/commit/53da348e107f8e6a52625ceab355c6d200a9709a
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags.ll
Log Message:
-----------
[LV] Add test showing incorrect trip count materialization (NFC) (#209460)
Add test case showing mis-compile for
https://github.com/llvm/llvm-project/issues/209159.
Commit: 0a5793ba557fb31ea1f847aa353397bb9b88cb18
https://github.com/llvm/llvm-project/commit/0a5793ba557fb31ea1f847aa353397bb9b88cb18
Author: ayrai-gb <ayrai at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
A llvm/test/Transforms/InstCombine/shuffle-cmp-cast-preserve-flags.ll
Log Message:
-----------
[InstCombine] Preserve IR flags when reordering icmp/fcmp/cast through a shuffle (#208627)
InstCombine's `evaluateInDifferentElementOrder` pushes a lane-reordering
`shufflevector` *through* the instruction that produced its input,
rebuilding that instruction on the reordered operands via the `buildNew`
helper — a `switch` with one case per opcode. The binary-operator case
carefully re-applies the original's poison-generating flags
(`nuw`/`nsw`, `exact`, FMF), and the `GetElementPtr` case passes through
its `getNoWrapFlags()`.
The `ICmp`, `FCmp`, and cast cases are the odd ones out. Each is a terse
`return Builder.CreateICmp/CreateFCmp/CreateCast(...)` that copies only
the predicate/opcode, returning the rebuilt instruction with default
flags. As a result a reordered `icmp samesign`, `fcmp nnan ninf`, `zext
nneg`, or `trunc nuw`/`nsw` silently loses its flag, even though the
flag held on the original.
Route each rebuilt instruction through `copyIRFlags(I)`, bringing these
cases in line with the binary-op and GEP cases. `copyIRFlags` transfers
only the flags the source instruction actually carried, so this can
never introduce an unsound promise. This is a missed-optimization fix,
not a miscompile — dropping these flags only makes later passes more
conservative.
Added
`llvm/test/Transforms/InstCombine/shuffle-cmp-cast-preserve-flags.ll`
(`icmp_samesign`, `fcmp_fmf`, `zext_nneg`), which feed the compare/cast
from `insertelement` chains so that `canEvaluateShuffled` permits the
reorder and `buildNew` actually runs, and check that the flag survives
on the rebuilt instruction after the reversing shuffle.
Found via jlebar's X86 LLVM bug-hunt / FuzzX effort:
https://github.com/SemiAnalysisAI/FuzzX/tree/master/x86/bugs/241-instcombine-buildNew-shuffle-reorder-drops-cmp-cast-flags
---------
Co-authored-by: Ayush Rai <ayrai at amd.com>
Commit: 2a1200e08cd1cb0e6744e38a7ec4611d983fb44f
https://github.com/llvm/llvm-project/commit/2a1200e08cd1cb0e6744e38a7ec4611d983fb44f
Author: Akash Banerjee <akash.banerjee at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M flang/lib/Optimizer/OpenMP/AutomapToTargetData.cpp
A flang/test/Lower/OpenMP/declare-target-automap.f90
M flang/test/Transforms/omp-automap-to-target-data.fir
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/omptarget-declare-target-llvm-host.mlir
M offload/test/offloading/fortran/declare-target-automap.f90
Log Message:
-----------
[Flang][OpenMP] Fix Fortran automap handling (#162501)
This fixes Fortran `declare target enter(automap:...)` handling for
allocatable
descriptors.
- Replace the previous `has_device_addr` target-region rewrite with
explicit
target data operations around allocation/deallocation.
- On allocation, emit:
- descriptor `map(always,to)` to keep the Fortran descriptor present
- storage `map(storage)` for the allocated array data
- `map(attach)` to update the device descriptor base address to the
device data
- On deallocation, delete both the mapped storage and descriptor.
- Add a weak visible offload-entry alias for local/hidden `declare
target to/enter`
globals so libomptarget can associate the host descriptor with the real
device
global without changing the original symbol linkage.
This fixes `offload/test/offloading/fortran/declare-target-automap.f90`
reported broken in #161265.
Co-authored-by: Codex <codex at openai.com>
Commit: e1d7480aabee9ea5b06be8f7902ff2ab23f50647
https://github.com/llvm/llvm-project/commit/e1d7480aabee9ea5b06be8f7902ff2ab23f50647
Author: Benedek Kaibas <82393336+benedekaibas at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt
M clang/lib/StaticAnalyzer/Checkers/LifetimeModeling.cpp
M clang/lib/StaticAnalyzer/Checkers/LifetimeModeling.h
A clang/lib/StaticAnalyzer/Checkers/ReportDanglingPtrDeref.cpp
A clang/test/Analysis/dangling-ptr-deref.cpp
Log Message:
-----------
[analyzer] Implemented the DanglingPtrDeref checker to detect use-after-scope lifetime errors (#209278)
Commit: 8b7b61f099616a3fbeca563b7a1da34279142797
https://github.com/llvm/llvm-project/commit/8b7b61f099616a3fbeca563b7a1da34279142797
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
A llvm/test/tools/llvm-reduce/reduce-instructions-x86-amx.ll
A llvm/test/tools/llvm-reduce/reduce-operands-x86-amx.ll
M llvm/tools/llvm-reduce/deltas/ReduceInstructions.cpp
M llvm/tools/llvm-reduce/deltas/ReduceOperands.cpp
Log Message:
-----------
[llvm-reduce] Avoid invalid replacements with x86_amx type (#209506)
It's not possible to create zero constants of this type, and even
poison constants result in a verifier error when used as an intrinsic
argument.
Commit: d6349588f34bc2f087ba6440049473ecd97853e0
https://github.com/llvm/llvm-project/commit/d6349588f34bc2f087ba6440049473ecd97853e0
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
[lldb][Windows] add release notes for the Python private API removal (#209456)
The official lldb releases set `LLDB_EMBED_PYTHON_HOME` to `OFF`
https://github.com/llvm/llvm-project/blob/9582f71a3b5f71e871bee0062e641f3587e0ae23/llvm/utils/release/build_llvm_release.bat#L213
meaning that lldb on Windows does not use the private Python API by
default. Users are free to use any Python version they want. Add a
release note for this.
Commit: de4bb53abe61dec8482f91b39ce3dac6ab0d5cd9
https://github.com/llvm/llvm-project/commit/de4bb53abe61dec8482f91b39ce3dac6ab0d5cd9
Author: lntue <lntue at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libc/test/src/sys/mman/linux/posix_madvise_test.cpp
Log Message:
-----------
[libc] Fix posix_madvise_test for riscv32 bot. (#209504)
Commit: e217dcb8de5dd83b307fe8b95b43de11a7d894ab
https://github.com/llvm/llvm-project/commit/e217dcb8de5dd83b307fe8b95b43de11a7d894ab
Author: George Burgess IV <george.burgess.iv at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp
Log Message:
-----------
[mlir] fix builders by moving var into assert (#209494)
non-asserts builders are failing since `vecTy` is unused aside from this
one assertion: https://lab.llvm.org/buildbot/#/builders/228/builds/4754
Since side-effects here are uninteresting, move the entire expr into the
assert, per CodingStandards.md
Fix-forward for #199700
Commit: 05aba69f4d8ee34179b0658c57280064a724f039
https://github.com/llvm/llvm-project/commit/05aba69f4d8ee34179b0658c57280064a724f039
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
A llvm/test/tools/llvm-reduce/reduce-operands-to-args-x86-amx.ll
M llvm/tools/llvm-reduce/deltas/ReduceOperandsToArgs.cpp
Log Message:
-----------
[llvm-reduce] Avoid another invalid x86_amx replacement (#209509)
Commit: 7cd1a8361376525a6094b0b365d5e726f014cde6
https://github.com/llvm/llvm-project/commit/7cd1a8361376525a6094b0b365d5e726f014cde6
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/tools/lldb-dap/DAPSessionManager.cpp
Log Message:
-----------
[lldb-dap] Simplify DAPSessionManager GetInstance (#209264)
We don't need the `std::call_once` as this guaranteed to be [thread safe
and initialised
once](https://en.cppreference.com/cpp/language/storage_duration#Static_block_variables)
since c++11.
Commit: 2ff357b2e1b9aed337a50478af2469fd9fd7442d
https://github.com/llvm/llvm-project/commit/2ff357b2e1b9aed337a50478af2469fd9fd7442d
Author: Joel Walker <theagingboy05 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Support/KnownBits.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sdiv.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-udiv.mir
M llvm/test/CodeGen/X86/udiv_fix.ll
M llvm/test/CodeGen/X86/udiv_fix_sat.ll
M llvm/test/Transforms/InstCombine/known-bits.ll
Log Message:
-----------
[KnownBits] Use min non-zero divisor and quotient lower bound in udiv (#209360)
`KnownBits::udiv` was discarding information in two cases. This tightens
both:
- A zero divisor is UB, so when the divisor's known bits permit zero,
use the smallest non-zero value as the minimum divisor instead of
bailing out.
- Compute a lower bound on the quotient (`MinNum / MaxDenom`) and keep
the leading bits it shares with the upper bound, the same way
`ConstantRange::toKnownBits` does.
Both follow from the quotient being monotonic in each operand, with all
four operand bounds attainable.
`KnownBitsTest.BinaryExhaustive` passes with no unsound results, and an
exhaustive width-4 check drops suboptimal outputs from 1790 to 864.
Regenerated the affected MIR and InstCombine tests; two X86 fixed-point
tests lose now-redundant instructions.
Assisted by Claude (Anthropic).
Commit: 132ba0d21e9f53671906af6b0a8343245b4c5021
https://github.com/llvm/llvm-project/commit/132ba0d21e9f53671906af6b0a8343245b4c5021
Author: lianjinfeng2003 <101249452+mygitljf at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
Log Message:
-----------
[CIR][NFC] Update fpclass mask checks (#208975)
I updated the CIR checks to match the formatted `llvm.is.fpclass` masks
introduced by #207653. This fixes the three CIR test failures that
became visible after #208919 restored the CIR build.
Commit: 0530817558e92a99ad3a37372dc42eb165f5f69e
https://github.com/llvm/llvm-project/commit/0530817558e92a99ad3a37372dc42eb165f5f69e
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/__init__.py
R lldb/packages/Python/lldbsuite/test/tools/lldb_dap/dap_types.py
R lldb/packages/Python/lldbsuite/test/tools/lldb_dap/lldb_dap_testcase.py
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/session.py
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/session_helpers.py
A lldb/packages/Python/lldbsuite/test/tools/lldb_dap/testcase.py
A lldb/packages/Python/lldbsuite/test/tools/lldb_dap/types.py
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/utils.py
M lldb/test/API/tools/lldb-dap/exception/TestDAP_exception.py
M lldb/test/API/tools/lldb-dap/exception/asan/TestDAP_asan.py
M lldb/test/API/tools/lldb-dap/exception/cpp/TestDAP_exception_cpp.py
M lldb/test/API/tools/lldb-dap/exception/objc/TestDAP_exception_objc.py
M lldb/test/API/tools/lldb-dap/exception/ubsan/TestDAP_ubsan.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_args.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_basic.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_cwd.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_debuggerRoot.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_disableSTDIO.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_environment_with_array.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_environment_with_object.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_extra_launch_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_failing_console.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_failing_launch_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_invalid_launch_commands_and_console.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_invalid_program.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_no_lldbinit_flag.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_shellExpandArguments_disabled.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_shellExpandArguments_enabled.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_sourcePath.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stdio_redirection.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stdio_redirection_and_console.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stopOnEntry.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_terminate_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_termination.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_version.py
M lldb/test/API/tools/lldb-dap/module-event/TestDAP_module_event.py
M lldb/test/API/tools/lldb-dap/module/TestDAP_module.py
M lldb/test/API/tools/lldb-dap/moduleSymbols/TestDAP_moduleSymbols.py
M lldb/test/API/tools/lldb-dap/stackTrace/TestDAP_stackTrace.py
M lldb/test/API/tools/lldb-dap/stackTraceCompilerGeneratedCode/TestDAP_stackTraceCompilerGeneratedCode.py
M lldb/test/API/tools/lldb-dap/stackTraceDisassemblyDisplay/TestDAP_stackTraceDisassemblyDisplay.py
M lldb/test/API/tools/lldb-dap/stackTraceMissingFunctionName/TestDAP_stackTraceMissingFunctionName.py
M lldb/test/API/tools/lldb-dap/stackTraceMissingModule/TestDAP_stackTraceMissingModule.py
M lldb/test/API/tools/lldb-dap/utils/TestDAPUtils_DAPConnection.py
M lldb/test/API/tools/lldb-dap/utils/TestDAPUtils_EventHistory.py
M lldb/test/API/tools/lldb-dap/utils/TestDAPUtils_Types.py
M lldb/test/API/tools/lldb-dap/variables/TestDAP_variables.py
M lldb/test/API/tools/lldb-dap/variables/children/TestDAP_variables_children.py
Log Message:
-----------
[NFC][lldb-dap] Simplify DAP imports. (#209442)
Expose commonly used classes in the lldb_dap package and avoid repeating
the lldb_dap namespace.
Commit: 921361839666196d5b60fc6e57836570ec86665a
https://github.com/llvm/llvm-project/commit/921361839666196d5b60fc6e57836570ec86665a
Author: Nerixyz <nerixdev at outlook.de>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/source/Plugins/SymbolLocator/SymStore/CMakeLists.txt
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
[lldb] Add release note for SymStore and generate settings docs (#209469)
We didn't have a release note for the symstore symbol locator and the
settings weren't included on https://lldb.llvm.org/use/settings.html.
The second part is probably because both were landing at the same time,
so I missed the JSON output there.
Commit: ce72145fd034cdb8abe5d14c5f9e73b8b47a8e6b
https://github.com/llvm/llvm-project/commit/ce72145fd034cdb8abe5d14c5f9e73b8b47a8e6b
Author: Usman Nadeem <mnadeem at qti.qualcomm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/AArch64/fold-sext-in-reg-predicate-fixed-length.ll
M llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
Log Message:
-----------
[SelectionDAG] Add GET_ACTIVE_LANE_MASK to ComputeNumSignBits (#208977)
`GET_ACTIVE_LANE_MASK ` acts like `icmp ult` so code is similar to
`SETCC`.
Commit: fdc884f5a5f0921a191bfec3bdf2ac9aae21687a
https://github.com/llvm/llvm-project/commit/fdc884f5a5f0921a191bfec3bdf2ac9aae21687a
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M .github/workflows/containers/github-action-ci-windows/Dockerfile
Log Message:
-----------
[docker][Windows] install libxml2 using vcpkg (#209422)
Since https://github.com/llvm/llvm-project/pull/209258, lldb uses
`lldb-server.exe` by default if libxml2 is available at build time. This
means that lldb-server requires installing libxml2 in the CI
environments to test it.
This patch adds a step to install libxml2 in the docker container used
for lldb pre-merge testing on Windows.
Commit: 7b54498f07642eb8f243664079211528d6a3b0a6
https://github.com/llvm/llvm-project/commit/7b54498f07642eb8f243664079211528d6a3b0a6
Author: Nicolas Miller <nicolas.pierre.miller at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
M llvm/lib/Target/Hexagon/HexagonPatterns.td
M llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
M llvm/test/CodeGen/Hexagon/fminmax-v67.ll
M llvm/test/CodeGen/Hexagon/fminmax.ll
Log Message:
-----------
[Hexagon] Add lowering for `{max,min}num` (#202938)
Since the floating point requirements for `{max,min}num` are less strict
than the ones for `{max,min}imumnum`, it is fine to lower them to the
same instructions that already meet the requirements for the latter.
This is similar to what the RISC-V backend does for example.
This is also a lot better than generating a standard library call.
Commit: 48c259847d186c4d773407c63393e28d0170666b
https://github.com/llvm/llvm-project/commit/48c259847d186c4d773407c63393e28d0170666b
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags.ll
Log Message:
-----------
[VPlan] Use VPlan::hasTailFolded in materializeConstantVectorTC. (#209502)
The current checks in materializeConstantVectorTripCount miss
tail-folded cases when vectorizing loops with fmax without fast-math
flags. Use recently added hasTailFolded helper to ensure we always bail
out on tail-folded loops.
Fixes https://github.com/llvm/llvm-project/issues/209159.
Commit: a80e98e15a6188f2eed31a70a8834264a2319f81
https://github.com/llvm/llvm-project/commit/a80e98e15a6188f2eed31a70a8834264a2319f81
Author: Mircea Trofin <mtrofin at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/CodeGen/CGCUDANV.cpp
M clang/test/CodeGenCUDA/device-stub.cu
Log Message:
-----------
[clang][cuda] Use the source filename for module ID (#209239)
Prior to
[#184065](vscode-file://vscode-app/Applications/Visual%20Studio%20Code.app/Contents/Resources/app/out/vs/code/electron-browser/workbench/workbench.html
"https://github.com/llvm/llvm-project/issues/184065") (relanded in
[#201849](vscode-file://vscode-app/Applications/Visual%20Studio%20Code.app/Contents/Resources/app/out/vs/code/electron-browser/workbench/workbench.html
"https://github.com/llvm/llvm-project/issues/201849")), the code
introduced in https://reviews.llvm.org/D42922 was using the GUID of an
internal linkage GlobalValue to create a module id, which would then be
used in a few cuda-specific places (including creating a symbol name
suffix).
[#184065](vscode-file://vscode-app/Applications/Visual%20Studio%20Code.app/Contents/Resources/app/out/vs/code/electron-browser/workbench/workbench.html
"https://github.com/llvm/llvm-project/issues/184065") assumed the
linkage of that symbol is external - which it isn't - and, thus, all
module IDs computed for this would be identical.
The fix is to not rely on GlobalValue GUIDs in the first place. What is
needed here is a hash that's specific to this module. So we're creating
that and explicitly decoupling that calculation from GlobalValue's
notion of GUIDs.
The change should be safe wrt uniqueness / hash collisions: the old
behavior was computing a hash where the only distinguishing component
was the module's `getSourceFileName`.
FWIW, there's a stronger module ID we could compute, with
`llvm::getUniqueModuleId` (or with a trivial refactoring of it, because
it prepends a ".").
Commit: 97f76580cdb0893d0b4edc7adf703162a23c0a67
https://github.com/llvm/llvm-project/commit/97f76580cdb0893d0b4edc7adf703162a23c0a67
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
M clang/test/CodeGen/memcpy-inline-builtin.c
M clang/test/CodeGen/pr9614.c
Log Message:
-----------
[Clang] Require x86 target for some tests (#209532)
These tests assert behavior about the always-inliner which now requires
a target to be present to check function attribute compatibility for
inlining.
Fix forward for 37b8e765ce4837a7577e6f762bcdffe4b232759c.
Commit: 7d511e4c9dfeed9884bc3e0b76f720e6cc1ad437
https://github.com/llvm/llvm-project/commit/7d511e4c9dfeed9884bc3e0b76f720e6cc1ad437
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clang-doc/BUILD.gn
R llvm/utils/gn/secondary/clang-tools-extra/clang-doc/markdown/BUILD.gn
M llvm/utils/gn/secondary/clang-tools-extra/unittests/clang-doc/BUILD.gn
Log Message:
-----------
[gn] port 7633d1e7a0f336 (no more clangDocMarkdown) (#209546)
Commit: 1f066996b7cc3715300ee9841e4000cd546d6135
https://github.com/llvm/llvm-project/commit/1f066996b7cc3715300ee9841e4000cd546d6135
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clang-doc/BUILD.gn
M llvm/utils/gn/secondary/clang-tools-extra/unittests/clang-doc/BUILD.gn
Log Message:
-----------
[gn build] Port 1bd46015ea4e (#209543)
Commit: 6f2cffb15640809fb86e27c807b366c08e790c54
https://github.com/llvm/llvm-project/commit/6f2cffb15640809fb86e27c807b366c08e790c54
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Passes/BUILD.gn
Log Message:
-----------
[gn build] Port 5d5dd83a547e (#209544)
Commit: 2eac996946092e7dc11ef4027c9202734b7e600e
https://github.com/llvm/llvm-project/commit/2eac996946092e7dc11ef4027c9202734b7e600e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/lo16-lo16-physreg-copy-sgpr.mir
M llvm/test/CodeGen/AMDGPU/load-atomic-flat.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-global.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-local.ll
M llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
M llvm/test/CodeGen/AMDGPU/load-global-f64.ll
M llvm/test/CodeGen/AMDGPU/load-global-i1.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i64.ll
M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-invariant.ll
M llvm/test/CodeGen/AMDGPU/load-hi16.ll
M llvm/test/CodeGen/AMDGPU/load-lo16.ll
M llvm/test/CodeGen/AMDGPU/load-local-f32-no-ds128.ll
M llvm/test/CodeGen/AMDGPU/load-local-f32.ll
M llvm/test/CodeGen/AMDGPU/load-local-f64.ll
M llvm/test/CodeGen/AMDGPU/load-local-i1.ll
M llvm/test/CodeGen/AMDGPU/load-local-i16.ll
M llvm/test/CodeGen/AMDGPU/load-local-i32.ll
M llvm/test/CodeGen/AMDGPU/load-local-i64.ll
M llvm/test/CodeGen/AMDGPU/load-local-i8.ll
M llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll
M llvm/test/CodeGen/AMDGPU/load-local.128.ll
M llvm/test/CodeGen/AMDGPU/load-local.96.ll
M llvm/test/CodeGen/AMDGPU/load-range-metadata-assert.ll
M llvm/test/CodeGen/AMDGPU/load-range-metadata-sign-bits.ll
M llvm/test/CodeGen/AMDGPU/load-saddr-offset-imm.ll
M llvm/test/CodeGen/AMDGPU/load-select-ptr.ll
M llvm/test/CodeGen/AMDGPU/load-store-cnt.ll
M llvm/test/CodeGen/AMDGPU/load-store-opt-addc0.mir
M llvm/test/CodeGen/AMDGPU/load-store-opt-dlc.mir
M llvm/test/CodeGen/AMDGPU/load-store-opt-ds-regclass-constrain.mir
M llvm/test/CodeGen/AMDGPU/load-store-opt-scale-offset.mir
M llvm/test/CodeGen/AMDGPU/load-store-opt-scc.mir
M llvm/test/CodeGen/AMDGPU/load-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/local-64.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/local-atomics.ll
M llvm/test/CodeGen/AMDGPU/local-atomics64.ll
M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/local-memory.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-sort-framerefs.mir
M llvm/test/CodeGen/AMDGPU/local-stack-slot-offset.ll
M llvm/test/CodeGen/AMDGPU/loop-header-align-gfx950.mir
M llvm/test/CodeGen/AMDGPU/loop-idiom.ll
M llvm/test/CodeGen/AMDGPU/loop-live-out-copy-undef-subrange.ll
M llvm/test/CodeGen/AMDGPU/loop-on-function-argument.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll
M llvm/test/CodeGen/AMDGPU/loop_header_nopred.mir
M llvm/test/CodeGen/AMDGPU/lower-brcond-with-xor.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-dead-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-lastuse-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-intervals.mir
M llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir
M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-declaration.ll
M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-existing.ll
M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor.ll
M llvm/test/CodeGen/AMDGPU/lower-empty-ctor-dtor.ll
M llvm/test/CodeGen/AMDGPU/lower-i1-copies-clear-kills.mir
M llvm/test/CodeGen/AMDGPU/lower-i1-copies-implicit-def-unstructured-loop.mir
M llvm/test/CodeGen/AMDGPU/lower-indirect-lds-references.ll
M llvm/test/CodeGen/AMDGPU/lower-intrinsics-noalias-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-kernel-and-module-lds.ll
M llvm/test/CodeGen/AMDGPU/lower-kernel-arguments-noalias-call-no-ptr-args.ll
M llvm/test/CodeGen/AMDGPU/lower-kernel-lds-constexpr.ll
M llvm/test/CodeGen/AMDGPU/lower-kernel-lds-super-align.ll
M llvm/test/CodeGen/AMDGPU/lower-kernel-lds.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-merge.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-with-alias-scope.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-with-noalias.ll
M llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics-threshold.ll
M llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (23) (#209214)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: c8c3c30d5b986450618e77ed1069232a2063a0ae
https://github.com/llvm/llvm-project/commit/c8c3c30d5b986450618e77ed1069232a2063a0ae
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/ScalableStaticAnalysis/Analyses/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/ScalableStaticAnalysis/BUILD.gn
Log Message:
-----------
[gn build] Port 612e7ca85c53 (#209545)
Commit: c8e2abb23d252da15fc16fcd6f43f9ab7543e02d
https://github.com/llvm/llvm-project/commit/c8e2abb23d252da15fc16fcd6f43f9ab7543e02d
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn
Log Message:
-----------
[gn build] Port a718d2ad092b (#209547)
Commit: 61853bac070678debbd80acf891dd681ceb0c1eb
https://github.com/llvm/llvm-project/commit/61853bac070678debbd80acf891dd681ceb0c1eb
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clang-doc/BUILD.gn
M llvm/utils/gn/secondary/clang-tools-extra/unittests/clang-doc/BUILD.gn
Log Message:
-----------
[gn build] Port c6ebd7a2ced7 (#209548)
Commit: 26e2b0980e10001174405d4412abd0d86f2e0ff5
https://github.com/llvm/llvm-project/commit/26e2b0980e10001174405d4412abd0d86f2e0ff5
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Checkers/BUILD.gn
Log Message:
-----------
[gn build] Port e1d7480aabee (#209549)
Commit: 77ff300cdfdbafc1abf60a79c32da497616afc1a
https://github.com/llvm/llvm-project/commit/77ff300cdfdbafc1abf60a79c32da497616afc1a
Author: lntue <lntue at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libc/test/src/sys/mman/linux/posix_madvise_test.cpp
Log Message:
-----------
[libc] Fix a typo in posix_madvise_test. (#209523)
Commit: cb83c6a8ba2f17cfb8d01d10722b9c1aa9743328
https://github.com/llvm/llvm-project/commit/cb83c6a8ba2f17cfb8d01d10722b9c1aa9743328
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/test/benchmarks/algorithms/min.bench.cpp
M libcxx/test/benchmarks/algorithms/minmax.bench.cpp
M libcxx/test/benchmarks/algorithms/nonmodifying/search_n.bench.cpp
Log Message:
-----------
[libc++][NFC] Remove unused <cassert> from algorithm benchmarks (#209492)
A few benchmark files were including <cassert> but didn't use it.
Commit: 1a072b5f008321f22e61f744b7474fe52f0ee48c
https://github.com/llvm/llvm-project/commit/1a072b5f008321f22e61f744b7474fe52f0ee48c
Author: Douglas Yung <douglas.yung at sony.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/SystemZ/zos-ppa2.ll
Log Message:
-----------
Fix test that had a check embedded which depended on the current LLVM version number. (#209530)
When the test was refactored, it embedded the current LLVM version
number in one of the check strings so that when I bumped the LLVM
version to 24, the test failed since it was expecting 23 but the
compiler was now generating 23.
Fix this issue by changing the check to a regex so it doesn't need
updating after every LLVM version change.
Commit: 83dc9c6c9a56bc90faa810512e0577e59dc46033
https://github.com/llvm/llvm-project/commit/83dc9c6c9a56bc90faa810512e0577e59dc46033
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M flang/lib/Optimizer/Support/CMakeLists.txt
M flang/lib/Optimizer/Support/InitFIR.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
M mlir/include/mlir/Target/LLVMIR/Dialect/All.h
R mlir/include/mlir/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.h
M mlir/lib/Target/LLVMIR/CMakeLists.txt
M mlir/lib/Target/LLVMIR/Dialect/CMakeLists.txt
R mlir/lib/Target/LLVMIR/Dialect/OpenACC/CMakeLists.txt
R mlir/lib/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.cpp
R mlir/test/Target/LLVMIR/openacc-llvm.mlir
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/Support/BUILD.bazel
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/Transforms/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][openacc] Remove OpenACCToLLVMIRTranslation (#209295)
OpenACCToLLVMIRTranslation was designed more than 5 years ago and does
not align with the current upstreaming effort. OpenACC will be converted
to LLVM IR dialect before the translation to LLVM IR so this translation
is obsolete. Remove it to avoid confusion.
Commit: 4697832bae3f891c474fba3c58e852585bd1ff5f
https://github.com/llvm/llvm-project/commit/4697832bae3f891c474fba3c58e852585bd1ff5f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/lower-module-lds-all-indirect-accesses.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-constantexpr-phi.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-constantexpr.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-inactive.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-indirect-extern-uses-max-reachable-alignment.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-link-time-classify.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-link-time-global-scope.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-link-time-internal-func.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-link-time-internal-multi-user.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-offsets.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-precise-allocate-to-module-struct.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-single-var-ambiguous.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-single-var-unambiguous.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-used-list.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-zero-size-arr.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds.ll
M llvm/test/CodeGen/AMDGPU/lower-multiple-ctor-dtor.ll
M llvm/test/CodeGen/AMDGPU/lower-noalias-kernargs.ll
M llvm/test/CodeGen/AMDGPU/lower-term-opcodes.mir
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-opt.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/lrint.ll
M llvm/test/CodeGen/AMDGPU/lro-coerce-v4i8-phi-loop.ll
M llvm/test/CodeGen/AMDGPU/lro-phi-samebb-nonlookthrough-store.ll
M llvm/test/CodeGen/AMDGPU/lround.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/lsr-cost-model-vector-iv.ll
M llvm/test/CodeGen/AMDGPU/lto-lower-module-lds.ll
M llvm/test/CodeGen/AMDGPU/machine-cp-propagation.mir
M llvm/test/CodeGen/AMDGPU/machine-cse-commute-target-flags.mir
M llvm/test/CodeGen/AMDGPU/machine-cse-ssa.mir
M llvm/test/CodeGen/AMDGPU/machine-function-info-cwsr.ll
M llvm/test/CodeGen/AMDGPU/machine-scheduler-rematerialization-scoring.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-revert-slot-monotonicity.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-cycle.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-fence.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-ignorable-exec-use.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-lane-mask.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.mir
M llvm/test/CodeGen/AMDGPU/machinelicm-undef-use.mir
M llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
M llvm/test/CodeGen/AMDGPU/mad-combine.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/mad_int24.ll
M llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll
M llvm/test/CodeGen/AMDGPU/mad_uint24.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx90a.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards-mfma-scale.gfx950.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards.mir
M llvm/test/CodeGen/AMDGPU/mai-inline.ll
M llvm/test/CodeGen/AMDGPU/make-buffer-rsrc-lds-fails.ll
M llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/max.i16.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/max3.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/mcexpr-knownbits-assign-crash-gh-issue-110930.ll
M llvm/test/CodeGen/AMDGPU/mcp-aligned-vgprs.mir
M llvm/test/CodeGen/AMDGPU/mcp-implicit-clobber.mir
M llvm/test/CodeGen/AMDGPU/mcp-overlap-after-propagation.mir
M llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
M llvm/test/CodeGen/AMDGPU/med3-knownbits.ll
M llvm/test/CodeGen/AMDGPU/med3-no-simplify.ll
M llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
M llvm/test/CodeGen/AMDGPU/memcpy-fixed-align.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memcpy-param-combinations.ll
M llvm/test/CodeGen/AMDGPU/memcpy-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memcpy-scoped-aa.ll
M llvm/test/CodeGen/AMDGPU/memcpy_const_compare.ll
M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
M llvm/test/CodeGen/AMDGPU/memmove-param-combinations.ll
M llvm/test/CodeGen/AMDGPU/memmove-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memmove-var-size.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (24) (#209485)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: e255003ae9a942d0d62c5c8405dc45de97f31ca4
https://github.com/llvm/llvm-project/commit/e255003ae9a942d0d62c5c8405dc45de97f31ca4
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/memory-legalizer-av-none.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-av-unknown.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-barriers-mmra.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-barriers.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-global.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-local.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-invalid-addrspace.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-invalid-syncscope.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-lds-dma-volatile-and-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-non-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-region.mir
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.mir
M llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
M llvm/test/CodeGen/AMDGPU/memset-pattern.ll
M llvm/test/CodeGen/AMDGPU/merge-buffer-gfx12.mir
M llvm/test/CodeGen/AMDGPU/merge-buffer.mir
M llvm/test/CodeGen/AMDGPU/merge-consecutive-wait-alus.mir
M llvm/test/CodeGen/AMDGPU/merge-flat-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-flat-saddr-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-image-load-gfx10.mir
M llvm/test/CodeGen/AMDGPU/merge-image-load-gfx11.mir
M llvm/test/CodeGen/AMDGPU/merge-image-load-gfx12.mir
M llvm/test/CodeGen/AMDGPU/merge-image-load.mir
M llvm/test/CodeGen/AMDGPU/merge-image-sample-gfx10.mir
M llvm/test/CodeGen/AMDGPU/merge-image-sample-gfx11.mir
M llvm/test/CodeGen/AMDGPU/merge-image-sample-gfx12.mir
M llvm/test/CodeGen/AMDGPU/merge-image-sample.mir
M llvm/test/CodeGen/AMDGPU/merge-load-store-agpr.mir
M llvm/test/CodeGen/AMDGPU/merge-load-store-vreg.mir
M llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll
M llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.mir
M llvm/test/CodeGen/AMDGPU/merge-s-load.mir
M llvm/test/CodeGen/AMDGPU/merge-sbuffer-load.mir
M llvm/test/CodeGen/AMDGPU/merge-store-crash.ll
M llvm/test/CodeGen/AMDGPU/merge-store-usedef.ll
M llvm/test/CodeGen/AMDGPU/merge-stores.ll
M llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx10.mir
M llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx11.mir
M llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx12.mir
M llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx9.mir
M llvm/test/CodeGen/AMDGPU/merged-bfx-opt.ll
M llvm/test/CodeGen/AMDGPU/mesa3d.ll
M llvm/test/CodeGen/AMDGPU/mfma-bf16-vgpr-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-convergent.mir
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select-gfx942.ll
M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select.ll
M llvm/test/CodeGen/AMDGPU/min-waves-per-eu-not-respected.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/min3.ll
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (25) (#209486)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 4a2cfd73fdb55b32c3f341b0db589cf1f22c3a70
https://github.com/llvm/llvm-project/commit/4a2cfd73fdb55b32c3f341b0db589cf1f22c3a70
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/aggressive-interleaving.ll
M llvm/test/Transforms/LoopVectorize/AArch64/alias-mask-uniforms.ll
M llvm/test/Transforms/LoopVectorize/AArch64/alias-mask.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-constant-ops.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-incomplete-chains.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs-apple.ll
M llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-derived-ivs.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/pr41179.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing-alias-mask.ll
M llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-alias-mask.ll
M llvm/test/Transforms/LoopVectorize/WebAssembly/induction-branch-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/fold-tail-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-opaque-pointers.ll
M llvm/test/Transforms/LoopVectorize/X86/optsize.ll
M llvm/test/Transforms/LoopVectorize/X86/pr48340.ll
M llvm/test/Transforms/LoopVectorize/X86/pr72969.ll
M llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/alias-mask-data-tail-folding-style.ll
M llvm/test/Transforms/LoopVectorize/alias-mask-needs-freeze.ll
M llvm/test/Transforms/LoopVectorize/alias-mask-small-index.ll
M llvm/test/Transforms/LoopVectorize/alias-mask.ll
M llvm/test/Transforms/LoopVectorize/hoist-and-sink-mem-ops-with-invariant-pointers.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-different-insert-position.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-metadata.ll
M llvm/test/Transforms/LoopVectorize/metadata.ll
M llvm/test/Transforms/LoopVectorize/opaque-ptr.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/pr45259.ll
M llvm/test/Transforms/LoopVectorize/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/preserve-dbg-loc-and-loop-metadata.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-known-true.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-needed-but-empty.ll
M llvm/test/Transforms/LoopVectorize/scev-predicate-reasoning.ll
Log Message:
-----------
[VPlan] Expand SCEV ptrtoint/ptrtoaddr casts in VPSCEVExpander. (#209172)
Extend the cast handling in VPSCEVExpander::tryToExpand to also expand
scPtrToInt and scPtrToAddr SCEV expressions to PtrToInt/PtrToAddr
VPInstructions.
This allows pointer-distance expressions (e.g. the runtime-check
difference between two pointers, which contains ptrtoint of each
pointer) to be expanded directly to VPInstructions instead of falling
back to a VPExpandSCEVRecipe.
PR: https://github.com/llvm/llvm-project/pull/209172
Commit: 194f7a360c475fd7da253248a6aade878b52318c
https://github.com/llvm/llvm-project/commit/194f7a360c475fd7da253248a6aade878b52318c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-014bb.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-cfg-with-self-loop.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-phi-merge-distances.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-acyclic-cfg-with-4-self-loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-11blocks.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-15blocks.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop-a.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/if_else_with_loops_nested_in_2_outer_loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/inner_cfg_in_2_nested_loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/loop_nested_in_3_outer_loops_complex_cfg.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/nested-loops-with-side-exits-a.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/sequence_2_loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/simple-loop-3blocks.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_basic_case.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_do_not_spill_restore_inside_loop.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_common_dominator.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader1.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader2.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader3.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader4.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_keep_spilled_reg_live.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_nested_loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_in_common_dominator_and_optimize_restores.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_loop_livethrough_reg.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_loop_value_in_exit_block.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/three-tier-ranking-nested-loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/triple-nested-loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/two-sequential-loops.mir
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll
M llvm/test/CodeGen/AMDGPU/mir-dynamic-vgpr-block-size-roundtrip.mir
M llvm/test/CodeGen/AMDGPU/misaligned-vgpr-regsequence.mir
M llvm/test/CodeGen/AMDGPU/misched-into-wmma-hazard-shadow.mir
M llvm/test/CodeGen/AMDGPU/misched-killflags.mir
M llvm/test/CodeGen/AMDGPU/missing-store.ll
M llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
M llvm/test/CodeGen/AMDGPU/mixed-wave32-wave64.ll
M llvm/test/CodeGen/AMDGPU/mixed_wave32_wave64.ll
M llvm/test/CodeGen/AMDGPU/mmo-target-flags-folding.ll
M llvm/test/CodeGen/AMDGPU/mmra.ll
M llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll
M llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus-fake16.mir
M llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus.mir
M llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/mode-register.mir
M llvm/test/CodeGen/AMDGPU/modf-constant-fold.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll
M llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu-flat.mir
M llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu.mir
M llvm/test/CodeGen/AMDGPU/move-to-valu-absdiff.mir
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-lshl_add.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-lshlrev.mir
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-fake16.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-worklist.ll
M llvm/test/CodeGen/AMDGPU/movreld-bug.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
M llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll
M llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll
M llvm/test/CodeGen/AMDGPU/mubuf.ll
M llvm/test/CodeGen/AMDGPU/mul.i16.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multi-call-resource-usage-mcexpr.ll
M llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
M llvm/test/CodeGen/AMDGPU/multi-dword-vgpr-spill.ll
M llvm/test/CodeGen/AMDGPU/multi-use-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/naked-fn-with-frame-pointer.ll
M llvm/test/CodeGen/AMDGPU/nand.ll
M llvm/test/CodeGen/AMDGPU/narrow_math_for_and.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/neg_ashr64_reduce.ll
M llvm/test/CodeGen/AMDGPU/neighboring-mfma-padding.mir
M llvm/test/CodeGen/AMDGPU/nested-calls.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/no-bundle-asm.ll
M llvm/test/CodeGen/AMDGPU/no-corresponding-integer-type.ll
M llvm/test/CodeGen/AMDGPU/no-dup-inst-prefetch.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (26) (#209487)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 27dce1908288eb57ce90b7c42fb7046260f39731
https://github.com/llvm/llvm-project/commit/27dce1908288eb57ce90b7c42fb7046260f39731
Author: Caroline Newcombe <caroline.newcombe at hpe.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
A flang/test/Analysis/AliasAnalysis/alias-analysis-omp-private-boxed-wsloop.mlir
A flang/test/Analysis/AliasAnalysis/alias-analysis-omp-private-unboxed-wsloop.mlir
Log Message:
-----------
[flang][OpenMP] Resolve private array source from block-arg owner in alias analysis (#208227)
Part of #208086. `fir::AliasAnalysis::getSource` fails to recognize an
OpenMP private array as an `Allocate` source when its `hlfir.declare` is
nested inside an omp.loop_nest, and conservatively returns `MayAlias`.
This changes `getSource` to resolve the clause-carrying OpenMP op from
the private block argument's owner region, so the private is correctly
classified and does not spuriously alias other objects. Assisted-by: Copilot
Commit: 9c7d1d2fe0d607b0cd5cfca1b8bb9ea6eee374ec
https://github.com/llvm/llvm-project/commit/9c7d1d2fe0d607b0cd5cfca1b8bb9ea6eee374ec
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/test/std/ranges/range.utility/view.interface/view.interface.pass.cpp
Log Message:
-----------
[libc++][ranges][NFC] Format `view.interface.pass.cpp` (#209391)
A prerequisite to #205012
Commit: 4264f9154c9ee153392cce6c90827fa4544bff7e
https://github.com/llvm/llvm-project/commit/4264f9154c9ee153392cce6c90827fa4544bff7e
Author: void_17 <61356189+void2012 at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Support/Windows/DynamicLibrary.inc
Log Message:
-----------
[NFC] Rename misleading `msvcrt` comment in `Windows/DynamicLibrary.inc` (#208884)
The comment in function `DynamicLibrary::HandleSet::DLSym` referred to
the mysterious `msvc.dll` windows standard dynamic library which simply
doesn't exist and `msvcrt.dll` was likely meant, so fix the comments.
Commit: 7618426138aae95561da676a1d1e10ee0392bf78
https://github.com/llvm/llvm-project/commit/7618426138aae95561da676a1d1e10ee0392bf78
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/include/__functional/function.h
Log Message:
-----------
Revert "[libc++][NFC] Inline std::function members into the class body" (#209555)
Reverts llvm/llvm-project#209461
This is breaking LLDB testing bots and it also failed pre-merge CI.
Commit: d454522b4140d7baa9d1be5d0ce2da327104c0d1
https://github.com/llvm/llvm-project/commit/d454522b4140d7baa9d1be5d0ce2da327104c0d1
Author: Usman Nadeem <mnadeem at qti.qualcomm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
M llvm/test/CodeGen/AArch64/active_lane_mask.ll
M llvm/test/CodeGen/AArch64/sve-mask-partition.ll
Log Message:
-----------
[AArch64] Tighten conditions for expanding GET_ACTIVE_LANE_MASK (#208962)
Lower to whilelo in more cases.
For fixed-width even if the operands are <32 bits, expanding is going to
be more expensive compared to promoting the operands from a smaller
type.
For SVE I also added lowering for nxv1i1 type as: `nxv2i1 -> extract
nxv1i1.`
Commit: 84199dde7198eabc924e93750063a20ceef26ef2
https://github.com/llvm/llvm-project/commit/84199dde7198eabc924e93750063a20ceef26ef2
Author: Hubert Tong <hubert.reinterpretcast at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
A libunwind/test/.clang-format
Log Message:
-----------
[libunwind][test] Add .clang-format (#209364)
Borrow from `libcxx/test/.clang-format` to avoid `clang-format`
suggestions that are incompatible with `FileCheck`.
Commit: a56f9cefd75cd12802e37a66425b1a57d761a0af
https://github.com/llvm/llvm-project/commit/a56f9cefd75cd12802e37a66425b1a57d761a0af
Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/vgpr-set-msb-coissue.mir
Log Message:
-----------
[AMDGPU][CodeGen] Pre-commit test for gfx1250 Setreg hazard violation (#209524)
Co-issue optimizations during placement of `S_SET_VGPR_MSB` instructions
can create a situation where a `S_SET_VGPR_MSB` appears directly after a
`S_SETREG_IMM32_B32(MODE)`, silently dropping the former and causing a
hazard violation on gfx1250.
Commit: 79d1db7e00932407c4aa1028632f2c188d14cac8
https://github.com/llvm/llvm-project/commit/79d1db7e00932407c4aa1028632f2c188d14cac8
Author: Garvit Gupta <garvgupt at qti.qualcomm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVInstrPredicates.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
A llvm/test/CodeGen/RISCV/xqcilo-xqcilia-frame-index.ll
Log Message:
-----------
[RISCV] Fold 26-bit frame-index offsets into Xqcilo/Xqcilia load/store/addi (#209315)
Extend frame-index addressing such that the sp-relative offset resolved for a stack access that fits within 26-bit and not 12-bits; folds directly into the wide Xqcilo/Xqcilia instructions. This is achieved by adding the support for the following:
- Adding support for stack accesses to complex pattern `SelectAddrRegImm26` for 26-bit loads and stores
- Adding support for frame index operand to qc.e.addi instruction
- Allowing 26-bit offsets to fold into the loads and store instructions from qcilo/qcilia extension
Commit: 8410006af686f3fb5e8af2705c8aab28c374c13a
https://github.com/llvm/llvm-project/commit/8410006af686f3fb5e8af2705c8aab28c374c13a
Author: Alex Kuleshov <0xAX at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/tools/llvm-mc/Disassembler.cpp
M llvm/tools/llvm-mc/Disassembler.h
M llvm/tools/llvm-mc/llvm-mc.cpp
Log Message:
-----------
[llvm-mc] Remove unused MCRegisterInfo/MCAsmInfo in Disassembler (NFC) (#208483)
Disassembler::disassemble() creates MCRegisterInfo and MCAsmInfo
instances that are no longer used.
Initially, they were introduced in a1bc0f5 to construct MCContext after
MCDisassembler began requiring one, but became dead in 2cb2707.
llvm-mc's main() already creates both objects and passes them into the
MCContext that disassemble() receives, so the error paths here are
unreachable.
Removing these objects also makes the MCTargetOptions parameter unused,
so drop it as well.
Commit: c7a0afe5049a3d4789f34a8d746c6a45d73557b4
https://github.com/llvm/llvm-project/commit/c7a0afe5049a3d4789f34a8d746c6a45d73557b4
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/source/Utility/Policy.cpp
Log Message:
-----------
[lldb] Gate `PolicyStack::Current()` log behind verbose (#209527)
`Process::GetState()` calls `PolicyStack::Get().Current()` on every
prompt redraw, so the previous unconditional LLDB_LOG at the read site
fired on every keypress once `log enable lldb process` was on, drowning
out any other process log output. Keep the dump for when it's actually
wanted, but only fire it if the log is set to verbose.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: 4471a0be22e8784a7487e1ce01e9083b50c47116
https://github.com/llvm/llvm-project/commit/4471a0be22e8784a7487e1ce01e9083b50c47116
Author: David Young <davidayoung at meta.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
Log Message:
-----------
[lldb][bazel] Generate SafeAutoloadPaths.inc in the Bazel overlay (#209454)
The auto-load-paths mechanism added in #187031 generates
SafeAutoloadPaths.inc via a CMake configure_file() of
SafeAutoloadPaths.inc.in (lldb/source/Core/CMakeLists.txt), gated by the
LLDB_SAFE_AUTO_LOAD_PATHS cache variable which defaults to empty.
Debugger.cpp #includes SafeAutoloadPaths.inc, but the Bazel overlay
never modeled the configure_file(), so the header is missing from the
Bazel build of lldb Core.
Reproduce the generation with expand_template (substituting
@SAFE_PATH_ENTRIES@ with "" to match the empty default). Emit the header
under include/ and expose it via includes = ["include"] so the bare
#include resolves, matching how Config.h and Version.inc are handled in
this overlay.
assisted with: claude
I ensured this is valid bazel that Meta can translate into valid BUCK
and build lldb with internally via buck2. This appears to match a few
other template/library pairs.
Commit: 666b87dd01d31cc80f356315c1c2d03974759138
https://github.com/llvm/llvm-project/commit/666b87dd01d31cc80f356315c1c2d03974759138
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll
M llvm/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll
M llvm/test/CodeGen/AMDGPU/no-remat-indirect-mov.mir
M llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
M llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll
M llvm/test/CodeGen/AMDGPU/nofpclass-call.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/noop-shader-O0.ll
M llvm/test/CodeGen/AMDGPU/nop-data.ll
M llvm/test/CodeGen/AMDGPU/nor-divergent-lanemask.ll
M llvm/test/CodeGen/AMDGPU/nor.ll
M llvm/test/CodeGen/AMDGPU/nsa-reassign.ll
M llvm/test/CodeGen/AMDGPU/nsa-reassign.mir
M llvm/test/CodeGen/AMDGPU/nsa-vmem-hazard.mir
M llvm/test/CodeGen/AMDGPU/object-linking-local-resources.ll
M llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf-and-hostcall.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf-pipeline.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf-unsupported.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf.ll
M llvm/test/CodeGen/AMDGPU/operand-folding.ll
M llvm/test/CodeGen/AMDGPU/operand-spacing.ll
M llvm/test/CodeGen/AMDGPU/opt-exec-masking-pre-ra-update-liveness-wave32.mir
M llvm/test/CodeGen/AMDGPU/opt-exec-masking-pre-ra-update-liveness.mir
M llvm/test/CodeGen/AMDGPU/opt-vgpr-live-range-verifier-error.mir
M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.mir
M llvm/test/CodeGen/AMDGPU/optimize-ds-bvh-stack-pre-ra.ll
M llvm/test/CodeGen/AMDGPU/optimize-exec-copies-extra-insts-after-copy.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-alloc-failure.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-loop-phi.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-no-fold-exec-copy.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-non-empty-but-used-interval.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-masking-strip-terminator-bits.mir
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/or3.ll
M llvm/test/CodeGen/AMDGPU/overlapping-tuple-copy-implicit-op-failure.ll
M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
M llvm/test/CodeGen/AMDGPU/packed-dependencies.mir
M llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-bf16.ll
M llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-fp16.ll
M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
M llvm/test/CodeGen/AMDGPU/packed-op-sel.ll
M llvm/test/CodeGen/AMDGPU/packed-u64.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable-dvgpr.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-dvgpr.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx950.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.6-dvgpr.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.6.ll
M llvm/test/CodeGen/AMDGPU/pal-simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/pal-userdata-regs.ll
M llvm/test/CodeGen/AMDGPU/partial-forwarding-hazards.mir
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
M llvm/test/CodeGen/AMDGPU/peephole-fold-imm-multi-use.mir
M llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir
M llvm/test/CodeGen/AMDGPU/peephole-opt-fold-reg-sequence-subreg.mir
M llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir
M llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir
M llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
M llvm/test/CodeGen/AMDGPU/pei-build-spill-offset-overflow-gfx950.mir
M llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir
M llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir
M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir
M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir
M llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
M llvm/test/CodeGen/AMDGPU/perfhint.ll
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permlane16_opsel.ll
M llvm/test/CodeGen/AMDGPU/permlane16_var-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permute.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/phi-av-pressure.ll
M llvm/test/CodeGen/AMDGPU/phi-elim-mli-available.mir
M llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir
M llvm/test/CodeGen/AMDGPU/phys-partial-liveness.mir
M llvm/test/CodeGen/AMDGPU/pk-lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/pk_max_f16_literal.ll
M llvm/test/CodeGen/AMDGPU/post-ra-sched-kill-bundle-use-inst.mir
M llvm/test/CodeGen/AMDGPU/post-ra-sched-reset.mir
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/postra-bundle-memops.mir
M llvm/test/CodeGen/AMDGPU/postra-bundle-vimage-vsample-gfx12.mir
M llvm/test/CodeGen/AMDGPU/postra-machine-sink-livein-subrange.mir
M llvm/test/CodeGen/AMDGPU/postra-machine-sink.mir
M llvm/test/CodeGen/AMDGPU/postra-norename.mir
M llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll
M llvm/test/CodeGen/AMDGPU/postra-sink-update-dependency.mir
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (27) (#209488)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 4473e5fb88c3f222e6042d0c181a113a2d92b8a0
https://github.com/llvm/llvm-project/commit/4473e5fb88c3f222e6042d0c181a113a2d92b8a0
Author: Jianhui Li <jian.hui.li at intel.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir
M mlir/test/Dialect/XeGPU/propagate-layout.mlir
M mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_quantizeA_F4.mlir
Log Message:
-----------
[MLIR][XeGPU] Prefer the nearer consumer's layout in LayoutInfo::meet (#208365)
**Summary**
During backward layout propagation a value can be demanded by multiple
consumers with conflicting
layouts. Previously LayoutInfo::meet kept whichever demand was assigned
first, so the winner depended on
the dataflow worklist's visitation order — nondeterministic and often
not what we want.
This changes meet to prefer the layout demanded by the consumer nearer
to the producer in program order.
This tends to preserve a consumer's layout as far up the def chain as
possible, reducing layout
conversions. It is a heuristic hint, not a proven optimum.
- Each op gets a program-order index from a pre-order walk (matching
printed-IR order), so a use inside
an scf.for body is nearer than a use after the loop.
- LayoutInfo carries the demanding op's index in a new programOrder
field. visitOperation sets a
file-scoped currentProgramOrder, and the single-arg LayoutInfo
constructor stamps it automatically.
- meet keeps the smaller programOrder; ties keep lhs.
- Removes a dead LayoutInfo::transpose declaration.
- Adds truncf_prefers_nearer_user in propagate-layout-inst-data.mlir.
- Updates the multiple-use tests in propagate-layout.mlir
(scatter_ops_preserve_load_perm_layout,
binary_op_multiple_uses, if_multiple_uses) to reflect that the nearer
consumer's layout now wins.
- a minor layout fix for simple_mxfp_gemm_quantizeA_F4.mlir
---------
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Commit: 681cc1b9f87b355c8c5f95ee35d6521e62531ceb
https://github.com/llvm/llvm-project/commit/681cc1b9f87b355c8c5f95ee35d6521e62531ceb
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/power-sched-no-instr-sunit.mir
M llvm/test/CodeGen/AMDGPU/pr51516.mir
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-IR-lowering.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs-IR-lowering.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preserve-hi16.ll
M llvm/test/CodeGen/AMDGPU/preserve-only-inactive-lane.mir
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/print-pipeline-passes.ll
M llvm/test/CodeGen/AMDGPU/printf-defined.ll
M llvm/test/CodeGen/AMDGPU/printf-existing-format-strings.ll
M llvm/test/CodeGen/AMDGPU/private-access-no-objects.ll
M llvm/test/CodeGen/AMDGPU/private-function.ll
M llvm/test/CodeGen/AMDGPU/prologue-epilogue-markers.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-array-aggregate.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-array-allocation.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-bitcast-function.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-cfg.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-globals.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-invariant-markers.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-lifetime.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-loadstores.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-max-regs.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-mem-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-memset.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-multidim.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-negative-index.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-non-byte-sizes.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-non-constant-index.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-padding-size-estimate.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-placeholder-replacement.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-pointer-array.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-proper-value-replacement.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-scoring.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-strip-abi-opt-attributes.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-subvecs.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-constantexpr-use.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-icmp.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-phi.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-unhandled-intrinsic.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-use-after-erase.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-user-mult.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts-llc.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep-of-gep.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-to-vector.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vgpr-ratio.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-volatile.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx10.mir
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx90a.mir
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir
M llvm/test/CodeGen/AMDGPU/promote-vect3-load.ll
M llvm/test/CodeGen/AMDGPU/propagate-attributes-bitcast-function.ll
M llvm/test/CodeGen/AMDGPU/propagate-flat-work-group-size.ll
M llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
M llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll
M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag-mubuf.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag-undef-poison.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll
M llvm/test/CodeGen/AMDGPU/ptrmask.ll
M llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll
M llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
M llvm/test/CodeGen/AMDGPU/rcp-pattern.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-register.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll
M llvm/test/CodeGen/AMDGPU/read-write-register-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/read_register.ll
M llvm/test/CodeGen/AMDGPU/readcyclecounter.ll
M llvm/test/CodeGen/AMDGPU/readlane_exec0.mir
M llvm/test/CodeGen/AMDGPU/readsteadycounter.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll
M llvm/test/CodeGen/AMDGPU/recursion.ll
M llvm/test/CodeGen/AMDGPU/recursive-resource-usage-mcexpr.ll
M llvm/test/CodeGen/AMDGPU/recursive_global_initializer.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (28) (#209489)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: b14bf6e583da3e35054bac26c5eef74ff4e717d2
https://github.com/llvm/llvm-project/commit/b14bf6e583da3e35054bac26c5eef74ff4e717d2
Author: AZero13 <gfunni234 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
A llvm/test/Transforms/InstCombine/udiv-isknownnegative.ll
Log Message:
-----------
[InstCombine] Generalize udiv by negative constant fold to handle non-constant values (#209322)
Use isKnownNegative() to catch non constant divisors.
Commit: 6e80f6733abb83ddc0a5447829a050b0497e0fb5
https://github.com/llvm/llvm-project/commit/6e80f6733abb83ddc0a5447829a050b0497e0fb5
Author: Usman Nadeem <mnadeem at qti.qualcomm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/fold-sext-in-reg-predicate-fixed-length.ll
M llvm/test/CodeGen/AArch64/get-active-lane-mask-extract.ll
Log Message:
-----------
[DAGCombiner] Fold extract_vector(get_active_lane_mask(),0) to get_active_lane_mask (#208978)
If we are extracting from the start of the vector, then we can just
rewrite to `get_active_lane_mask` with a new type and the same operands.
Depends on https://github.com/llvm/llvm-project/pull/208962 and
https://github.com/llvm/llvm-project/pull/208977
Commit: 3d7535a03c1a036204a5347a79e9f66eb96ce4bc
https://github.com/llvm/llvm-project/commit/3d7535a03c1a036204a5347a79e9f66eb96ce4bc
Author: Gábor Horváth <xazax.hun at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LiveOrigins.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LoanPropagation.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/MovedLoans.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/Utils.h
M clang/include/clang/Analysis/Analyses/LiveVariables.h
M clang/lib/Analysis/LiveVariables.cpp
M llvm/benchmarks/ImmutableSetBuildBM.cpp
M llvm/benchmarks/ImmutableSetIteratorBM.cpp
M llvm/include/llvm/ADT/ImmutableMap.h
M llvm/include/llvm/ADT/ImmutableSet.h
M llvm/unittests/ADT/ImmutableSetTest.cpp
Log Message:
-----------
[ADT] Make canonicalization a compile-time parameter of ImmutableSet/Map (#209300)
ImmutableSet and ImmutableMap always carried the machinery needed for
tree canonicalization -- a per-node `prev`/`next` cache chain and cached
`digest`, plus the factory-side cache and a runtime `canonicalize` flag
-- even for the many clients that disable it (the Clang dataflow
analyses, e.g. lifetime safety and LiveVariables, for which
canonicalization is a large performance loss). Those clients paid for
state and code paths they never used.
Add a `bool Canonicalize` template parameter (defaulting to true, so
existing users are unaffected) that moves the decision to compile time:
* When disabled, the `prev`/`next` links (empty base) and `digest`
(LLVM_NO_UNIQUE_ADDRESS member) vanish, shrinking a set node from 56 to
40 bytes and a map node from 64 to 40 on 64-bit; `getCanonicalTree`, the
factory cache, and the `destroy()` unlink branch are `if constexpr`-ed
away. Node fields are ordered so the traversal-hot members come first.
* When enabled, the node layout is unchanged, and `operator==`/`!=`
become O(1) pointer comparisons (equal canonical trees share a root, as
with ImmutableList) instead of a structural walk.
The runtime `canonicalize` factory argument is now redundant and
removed; the in-tree non-canonicalizing users are switched to the
template argument.
Node microbenchmark (ImmutableSetBuildBM, non-canonicalizing, -O2):
| Benchmark | Before | After | Speedup |
|--------------------|---------:|---------:|:-------:|
| Build/256 | 20.3 us | 18.3 us | 1.11x |
| Build/4096 | 790 us | 731 us | 1.08x |
| Build/65536 | 18.8 ms | 18.4 ms | 1.02x |
| BuildRemove/256 | 40.7 us | 35.0 us | 1.16x |
| BuildRemove/4096 | 1.46 ms | 1.39 ms | 1.05x |
| BuildRemove/65536 | 34.6 ms | 33.8 ms | 1.02x |
End to end, the smaller node cuts the lifetime-safety analysis peak RSS
by up to ~23% on allocation-dense inputs with neutral-to-positive run
time, and the O(1) equality speeds up a Clang static analyzer run on
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp by ~1.3% (95.1s -> 93.9s).
Assisted by: Claude Opus 4.8
---------
Co-authored-by: Gabor Horvath <gaborh at apple.com>
Commit: 266c25684b32bd43d846f8de1c3a9f358066ffc4
https://github.com/llvm/llvm-project/commit/266c25684b32bd43d846f8de1c3a9f358066ffc4
Author: Mikhail Gudim <mgudim at qti.qualcomm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetFrameLowering.h
M llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
Log Message:
-----------
[CodeGen] Split determineCalleeSaves into smaller functions. (#203981)
The function `getMustPreserveRegisters` - returns the list of registers
that must be preserved by the function.
The function `determineUncondPrologCalleeSaves` - determines which of
the registers reported by `getMustPreserveRegisters` must be saved in
prolog and reloaded in epilog regardless of whether or not they were
modified by the function.
Commit: 3e706075dc1857e88a293b8104c81b31a08f4cd5
https://github.com/llvm/llvm-project/commit/3e706075dc1857e88a293b8104c81b31a08f4cd5
Author: Liza Burakova <liza at chromium.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/include/__pstl/backends/libdispatch.h
Log Message:
-----------
[libc++][pstl] Add missing #pragma GCC system_header to libdispatch.h (#209579)
This adds `#pragma GCC system_header` to libdispatch.h, as removing the
`[system]` attributes in the modulemap surfaced this gap.
Commit: e4a959ffebe24abae49fc93a4f84c58625dabbea
https://github.com/llvm/llvm-project/commit/e4a959ffebe24abae49fc93a4f84c58625dabbea
Author: Florian Mayer <fmayer at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/utils/generate-test-checks.py
Log Message:
-----------
[NFC] [MLIR] fix typo in argument desc (#209587)
Commit: 995b7229bc4a9614669fb57b76c2cddc9fb4db52
https://github.com/llvm/llvm-project/commit/995b7229bc4a9614669fb57b76c2cddc9fb4db52
Author: Scott Linder <scott.linder at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
Log Message:
-----------
[AMDGPU] Fix type for DWARF register number in SIFrameLowering (#209535)
It so happened that using MCRegister here happened to work, but
the encoded dwarf number is definitely not an MCRegister.
Commit: b43a0072fa011ec50c29b683da057730b2682ae2
https://github.com/llvm/llvm-project/commit/b43a0072fa011ec50c29b683da057730b2682ae2
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
Log Message:
-----------
[VPlan] Introduce VPIRFlags::getNWFlagsOrNone (NFC) (#207176)
Similar to getFMFOrNone. Also introduce a default WrapFlagsTy
constructor to go along with it.
Commit: 527396dd7c7370b1649ade49ceb48e48f6f26de1
https://github.com/llvm/llvm-project/commit/527396dd7c7370b1649ade49ceb48e48f6f26de1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/reduce-build-vec-ext-to-ext-build-vec.ll
M llvm/test/CodeGen/AMDGPU/reduce-load-width-alignment.ll
M llvm/test/CodeGen/AMDGPU/reduction.ll
M llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll
M llvm/test/CodeGen/AMDGPU/reg-coalescer-subreg-liveness.mir
M llvm/test/CodeGen/AMDGPU/reg-sequence-like-v-pk-mov-b32.mir
M llvm/test/CodeGen/AMDGPU/regalloc-fail-unsatisfiable-overlapping-tuple-hints.mir
M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
M llvm/test/CodeGen/AMDGPU/regalloc-fast-dont-drop-subreg-index-issue61134.mir
M llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.mir
M llvm/test/CodeGen/AMDGPU/regalloc-illegal-eviction-assert.ll
M llvm/test/CodeGen/AMDGPU/regalloc-introduces-copy-sgpr-to-agpr.mir
M llvm/test/CodeGen/AMDGPU/regalloc-sgpr128-partial-def.mir
M llvm/test/CodeGen/AMDGPU/regalloc-spill-wmma-scale.ll
M llvm/test/CodeGen/AMDGPU/regalloc-undef-copy-fold.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-64-bit-only-regs.mir
M llvm/test/CodeGen/AMDGPU/regcoalescing-remove-partial-redundancy-assert.mir
M llvm/test/CodeGen/AMDGPU/register-coalescer--set-undef-full-reg-use-implicit-def-erase-issue109249.mir
M llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir
M llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure1.ll
M llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
M llvm/test/CodeGen/AMDGPU/reject-agpr-usage-before-gfx908.ll
M llvm/test/CodeGen/AMDGPU/rel32.ll
M llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir
M llvm/test/CodeGen/AMDGPU/release-vgprs-gfx12-dvgpr.mir
M llvm/test/CodeGen/AMDGPU/release-vgprs-gfx12.mir
M llvm/test/CodeGen/AMDGPU/release-vgprs-spill.ll
M llvm/test/CodeGen/AMDGPU/release-vgprs.mir
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.ll
M llvm/test/CodeGen/AMDGPU/remat-fp64-constants.ll
M llvm/test/CodeGen/AMDGPU/remat-physreg-copy-subreg-extract-already-live-at-def-issue120970.mir
M llvm/test/CodeGen/AMDGPU/remat-smrd.mir
M llvm/test/CodeGen/AMDGPU/remat-sop.mir
M llvm/test/CodeGen/AMDGPU/remat-through-copy.mir
M llvm/test/CodeGen/AMDGPU/remat-vop.mir
M llvm/test/CodeGen/AMDGPU/remove-incompatible-extended-image-insts.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-functions.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-gws.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-s-time.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-wave32-feature.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-wave64-feature.ll
M llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll
M llvm/test/CodeGen/AMDGPU/remove-not-short-exec-branch-on-unconditional-jump.mir
M llvm/test/CodeGen/AMDGPU/remove-register-flags.mir
M llvm/test/CodeGen/AMDGPU/remove-short-exec-branches-gpr-idx-mode.mir
M llvm/test/CodeGen/AMDGPU/remove-short-exec-branches-special-instructions.mir
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs-unused-lanes.ll
M llvm/test/CodeGen/AMDGPU/reorder-stores.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/replace-store-of-insert-load.ll
M llvm/test/CodeGen/AMDGPU/reqd-work-group-size.ll
M llvm/test/CodeGen/AMDGPU/required-export-priority.ll
M llvm/test/CodeGen/AMDGPU/required-export-priority.mir
M llvm/test/CodeGen/AMDGPU/reserved-reg-in-clause.mir
M llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll
M llvm/test/CodeGen/AMDGPU/resource-usage-crash-unhandled-reg.mir
M llvm/test/CodeGen/AMDGPU/resource-usage-dead-function.ll
M llvm/test/CodeGen/AMDGPU/resource-usage-pal.ll
M llvm/test/CodeGen/AMDGPU/ret.ll
M llvm/test/CodeGen/AMDGPU/ret_jump.ll
M llvm/test/CodeGen/AMDGPU/return-with-successors.mir
M llvm/test/CodeGen/AMDGPU/returnaddress.ll
M llvm/test/CodeGen/AMDGPU/rewrite-mfma-form-spill-cost-reset.ll
M llvm/test/CodeGen/AMDGPU/rewrite-out-arguments-address-space.ll
M llvm/test/CodeGen/AMDGPU/rewrite-out-arguments.ll
M llvm/test/CodeGen/AMDGPU/rewrite-undef-for-phi.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-scale-to-agpr.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-multi-store-mir.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-multi-store.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
M llvm/test/CodeGen/AMDGPU/rotate-add.ll
M llvm/test/CodeGen/AMDGPU/rotl.i64.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.i64.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32-safe.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
M llvm/test/CodeGen/AMDGPU/rsq.f64.ll
M llvm/test/CodeGen/AMDGPU/s-barrier-id-allocation.ll
M llvm/test/CodeGen/AMDGPU/s-barrier-lowering.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s-buffer-load-mmo-offsets.ll
M llvm/test/CodeGen/AMDGPU/s-cluster-barrier.ll
M llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
M llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
M llvm/test/CodeGen/AMDGPU/s_add_co_pseudo_lowering.mir
M llvm/test/CodeGen/AMDGPU/s_addk_i32.ll
M llvm/test/CodeGen/AMDGPU/s_cmp_0.ll
M llvm/test/CodeGen/AMDGPU/s_code_end.ll
M llvm/test/CodeGen/AMDGPU/s_movk_i32.ll
M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
M llvm/test/CodeGen/AMDGPU/s_or_b32_transformation.ll
M llvm/test/CodeGen/AMDGPU/s_or_saveexec_xor_combine.mir
M llvm/test/CodeGen/AMDGPU/s_uaddo_usubo_pseudo.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/saddsat.ll
M llvm/test/CodeGen/AMDGPU/salu-to-valu.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (29) (#209558)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: ea56bc30bdabf00e401422f49e9588f1b5ff5e73
https://github.com/llvm/llvm-project/commit/ea56bc30bdabf00e401422f49e9588f1b5ff5e73
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/same-lds-variable-multiple-use-in-one-phi-node.ll
M llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir
M llvm/test/CodeGen/AMDGPU/save-fp.ll
M llvm/test/CodeGen/AMDGPU/scalar-branch-missing-and-exec.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
M llvm/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector_v2x16.ll
M llvm/test/CodeGen/AMDGPU/scalarize-insert-subvector.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-global.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-scratch.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-smem.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-post-RA.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-pre-RA.mir
M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pipeline-solver.mir
M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pre-RA.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-dead-def-join.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
M llvm/test/CodeGen/AMDGPU/sched-image-sample-post-RA.mir
M llvm/test/CodeGen/AMDGPU/sched-ldsdma-mask.mir
M llvm/test/CodeGen/AMDGPU/sched-no-schedmodel.mir
M llvm/test/CodeGen/AMDGPU/sched-prefer-non-mfma.mir
M llvm/test/CodeGen/AMDGPU/sched-setprio.ll
M llvm/test/CodeGen/AMDGPU/sched.group.classification.mir
M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir
M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_cost.mir
M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_diff_types.mir
M llvm/test/CodeGen/AMDGPU/schedmodel-dummywrite.mir
M llvm/test/CodeGen/AMDGPU/schedule-addrspaces.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg-crash.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/schedule-avoid-spills.ll
M llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier-latency.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
M llvm/test/CodeGen/AMDGPU/schedule-ilp-liveness-tracking.mir
M llvm/test/CodeGen/AMDGPU/schedule-ilp.ll
M llvm/test/CodeGen/AMDGPU/schedule-ilp.mir
M llvm/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll
M llvm/test/CodeGen/AMDGPU/schedule-pending-queue.mir
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-ilp-metric-spills.mir
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-lds.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit-clustering.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit2.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit3.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-misched-max-waves.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-no-unclustered-regions.mir
M llvm/test/CodeGen/AMDGPU/schedule-relaxed-occupancy.ll
M llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll
M llvm/test/CodeGen/AMDGPU/schedule-xdl-resource.ll
M llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir
M llvm/test/CodeGen/AMDGPU/scheduler-rp-calc-one-successor-two-predecessors-bug.ll
M llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll
M llvm/test/CodeGen/AMDGPU/scratch-buffer.ll
M llvm/test/CodeGen/AMDGPU/scratch-pointer-sink.ll
M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
M llvm/test/CodeGen/AMDGPU/sdag-print-divergence.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdivrem24.ll
M llvm/test/CodeGen/AMDGPU/sdwa-commute.ll
M llvm/test/CodeGen/AMDGPU/sdwa-cse.mir
M llvm/test/CodeGen/AMDGPU/sdwa-gfx9.mir
M llvm/test/CodeGen/AMDGPU/sdwa-op64-test.ll
M llvm/test/CodeGen/AMDGPU/sdwa-ops.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-fail.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-sext.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-wave32.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-wave64.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel-dst.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel-src.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-gfx10.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/sdwa-preserve.mir
M llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir
M llvm/test/CodeGen/AMDGPU/sdwa-stack.mir
M llvm/test/CodeGen/AMDGPU/sdwa-vop2-64bit.mir
M llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-fp.ll
M llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-int.ll
M llvm/test/CodeGen/AMDGPU/select-constant-xor.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract-legacy.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.f16.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.legal.f16.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (30) (#209559)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 9035d06155596c1214f302bef2e60b631d38e73a
https://github.com/llvm/llvm-project/commit/9035d06155596c1214f302bef2e60b631d38e73a
Author: Vijay Kandiah <vkandiah at nvidia.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
A flang/test/Fir/CUDA/cuda-managed-descriptor-component.fir
Log Message:
-----------
[flang][cuda] Size managed globals with descriptor components via LLVM Type (#209577)
When we do `-cuda -gpu=unified` (or `managed`) on a derived type with an
allocatable/pointer component, recent change
https://github.com/llvm/llvm-project/pull/209292 implicitly
attributed the component making lowering place the enclosing
derived-type global
in CUF managed memory. `CUFAddConstructor` then sizes that global via
`getTypeSizeAndAlignmentOrCrash`, which has no case for the descriptor
component
(`!fir.box<...>`) and aborts.
With this change, instead of aborting, we fall back to converting the
global to its LLVM type which
inlines the fixed-size descriptors, and query the data layout.
Commit: e3227da7cdb8173c2df465e443a1dc73c71f017b
https://github.com/llvm/llvm-project/commit/e3227da7cdb8173c2df465e443a1dc73c71f017b
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/crash_scatter_load_reorder.ll
Log Message:
-----------
[SLP] Fix ScatterVectorize reorder desyncing scalars from operands
Record the reorder in ReorderIndices instead of permuting the scatter node's
Scalars, keeping them aligned with the per-lane operand list the scheduler
reads.
Fixes #209444
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209594
Commit: 42b67e529c59b77c6dfac9cc5d2b263e752851f6
https://github.com/llvm/llvm-project/commit/42b67e529c59b77c6dfac9cc5d2b263e752851f6
Author: David Young <davidayoung at meta.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/lit/lit/LitConfig.py
A llvm/utils/lit/tests/unit/LitConfig.py
Log Message:
-----------
[lit] Don't crash in _write_message when getsourcefile() returns None (#206957)
LitConfig._write_message currently derives the file to report a
note()/warning()/ error() against with:
file = os.path.abspath(inspect.getsourcefile(f))
inspect.getsourcefile(f) returns None when the calling frame's source is
not on disk and not in linecache -- for example when lit is packaged
into a zip archive, or when a config is exec'd from a synthetic
filename. In that case os.path.abspath(None) raises TypeError: expected
str, bytes or os.PathLike object, not NoneType, which turns an
informational diagnostic into a fatal config-parse crash.
Fall back to inspect.getfile(f), which returns the frame's co_filename
and is always a str, so the diagnostic is emitted (tagged with
co_filename) instead of crashing. Since all tests normally pass
currently on build bots, this new code should never trigger and only
works as a backup in the case I'm running into on a different test infra
running lit tests.
Add a lit unit test covering the None case.
Assisted with- claude
Commit: e0b4701f2621d2542405830008797e3cf319a3f0
https://github.com/llvm/llvm-project/commit/e0b4701f2621d2542405830008797e3cf319a3f0
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/select-i1.ll
M llvm/test/CodeGen/AMDGPU/select-load-to-load-select-ptr-combine.ll
M llvm/test/CodeGen/AMDGPU/select-nsz-known-values-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/select-phi-s16-fp.ll
M llvm/test/CodeGen/AMDGPU/select-undef.ll
M llvm/test/CodeGen/AMDGPU/select-vectors.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/select64.ll
M llvm/test/CodeGen/AMDGPU/selectcc-opt.ll
M llvm/test/CodeGen/AMDGPU/selectcc.ll
M llvm/test/CodeGen/AMDGPU/sema-v-unsched-bundle.ll
M llvm/test/CodeGen/AMDGPU/sendmsg-m0-hazard.mir
M llvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir
M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
M llvm/test/CodeGen/AMDGPU/set_kill_i1_for_floation_point_comparison.ll
M llvm/test/CodeGen/AMDGPU/setcc-f64-hi32mask.ll
M llvm/test/CodeGen/AMDGPU/setcc-fneg-constant.ll
M llvm/test/CodeGen/AMDGPU/setcc-limit-load-shrink.ll
M llvm/test/CodeGen/AMDGPU/setcc-multiple-use.ll
M llvm/test/CodeGen/AMDGPU/setcc-opt.ll
M llvm/test/CodeGen/AMDGPU/setcc64.ll
M llvm/test/CodeGen/AMDGPU/seto.ll
M llvm/test/CodeGen/AMDGPU/setuo.ll
M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll
M llvm/test/CodeGen/AMDGPU/sext-in-reg.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-duplicate-operand.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/sgpr-count-graphics.ll
M llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
M llvm/test/CodeGen/AMDGPU/sgpr-scavenge-fi-stack-id.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-incorrect-fi-bookkeeping-bug.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-unhandled.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spills-empty-prolog-block.mir
M llvm/test/CodeGen/AMDGPU/sgpr-to-vreg1-copy.ll
M llvm/test/CodeGen/AMDGPU/shader-addr64-nonuniform.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shift-i64-opts.ll
M llvm/test/CodeGen/AMDGPU/shift-select.ll
M llvm/test/CodeGen/AMDGPU/shl-add-to-add-shl.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shl64_reduce.ll
M llvm/test/CodeGen/AMDGPU/shl64_reduce_flags.ll
M llvm/test/CodeGen/AMDGPU/shlN_add.ll
M llvm/test/CodeGen/AMDGPU/shl_add.ll
M llvm/test/CodeGen/AMDGPU/shl_add_constant.ll
M llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll
M llvm/test/CodeGen/AMDGPU/shl_add_ptr_csub.ll
M llvm/test/CodeGen/AMDGPU/shl_add_ptr_global.ll
M llvm/test/CodeGen/AMDGPU/shl_or.ll
M llvm/test/CodeGen/AMDGPU/should-not-hoist-set-inactive.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/shrink-carry.mir
M llvm/test/CodeGen/AMDGPU/shrink-fma-f64.mir
M llvm/test/CodeGen/AMDGPU/shrink-i32-kimm.mir
M llvm/test/CodeGen/AMDGPU/shrink-instructions-flags.mir
M llvm/test/CodeGen/AMDGPU/shrink-instructions-illegal-fold.mir
M llvm/test/CodeGen/AMDGPU/shrink-instructions-implicit-vcclo.mir
M llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir
M llvm/test/CodeGen/AMDGPU/shrink-mad-fma-fake16.mir
M llvm/test/CodeGen/AMDGPU/shrink-mad-fma-gfx10.mir
M llvm/test/CodeGen/AMDGPU/shrink-mad-fma.mir
M llvm/test/CodeGen/AMDGPU/shrink-true16.mir
M llvm/test/CodeGen/AMDGPU/shrink-v-cmp-wave32-dead-vcc-lo.mir
M llvm/test/CodeGen/AMDGPU/shufflevector-physreg-copy.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v3bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v4bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v2f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v3f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v4f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v2f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v3f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v3i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v4i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v2i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v3i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v4i32.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (31) (#209560)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: d0775bdb7f483b8aa4700b97a65718d5f3c9cfa8
https://github.com/llvm/llvm-project/commit/d0775bdb7f483b8aa4700b97a65718d5f3c9cfa8
Author: lntue <lntue at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libc/src/__support/threads/linux/futex_utils.h
Log Message:
-----------
[libc] Fix potential timespec type mismatch for arm32 targets in futex_utils.h. (#209556)
This causes the arm32 build bots to hang.
Assisted-by: Gemini 3.5 Flash.
Commit: 226b0b59bfca58ef831bd668dcf219a79f11f957
https://github.com/llvm/llvm-project/commit/226b0b59bfca58ef831bd668dcf219a79f11f957
Author: Muhammad Bassiouni <60100307+bassiounix at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/docs/LanguageExtensions.md
M clang/docs/ReleaseNotes.md
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Parse/Parser.h
M clang/lib/Parse/ParseExprCXX.cpp
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Parse/ParseStmt.cpp
A clang/test/C/C2y/n3267.c
M clang/www/c_status.html
Log Message:
-----------
[Clang][C2y] Add support for if declarations (N3356 paper) (#198244)
Add support for _if declarations_ in `C2y` mode by exploiting existing
C++ code.
The only new changes to the code is narrowing the code path to `C` mode
and introduce new errors and warnings for some pitfalls with the syntax
and what is expected from the standard and old language modes.
It should be noted that the first clause in the standard paper can only
be declaration. This means we can't allow expression statement in the
first clause of the condition, and that's the goal of the new
warnings/errors. Also this is different from C++ grammar.
Commit: 21bc62e6688a5dcaf79ebd992e5e4676b287a674
https://github.com/llvm/llvm-project/commit/21bc62e6688a5dcaf79ebd992e5e4676b287a674
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v3i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v2p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v3p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v2p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v3p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v4p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v3bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v4bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v2f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v3f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v4f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v2f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v3f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v3i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v4i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v2i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v3i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v4i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v3i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v2p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v3p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v2p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v3p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v4p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v3bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v4bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v2f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v3f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v4f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v2f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v3f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v3i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v4i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v2i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v3i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v4i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v3i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v2p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v3p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v2p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v3p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v4p3.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf-kill.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf-unreachable.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-nested-control-flows.ll
M llvm/test/CodeGen/AMDGPU/si-annotatecfg-multiple-backedges.ll
M llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies-av-constrain.mir
M llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies-copy-to-sgpr.mir
M llvm/test/CodeGen/AMDGPU/si-fold-aligned-agprs.mir
M llvm/test/CodeGen/AMDGPU/si-fold-aligned-vgprs.mir
M llvm/test/CodeGen/AMDGPU/si-fold-copy-kills.mir
M llvm/test/CodeGen/AMDGPU/si-fold-kimm.mir
M llvm/test/CodeGen/AMDGPU/si-fold-operands-agpr-copy-reg-sequence.mir
M llvm/test/CodeGen/AMDGPU/si-fold-operands-bundle.mir
M llvm/test/CodeGen/AMDGPU/si-fold-operands-commute-same-operands-assert.mir
M llvm/test/CodeGen/AMDGPU/si-fold-operands-gfx11.mir
M llvm/test/CodeGen/AMDGPU/si-fold-operands-requires-ssa.mir
M llvm/test/CodeGen/AMDGPU/si-fold-operands-subreg-imm.gfx942.mir
M llvm/test/CodeGen/AMDGPU/si-fold-operands-subreg-imm.mir
M llvm/test/CodeGen/AMDGPU/si-fold-reg-sequence.mir
M llvm/test/CodeGen/AMDGPU/si-fold-scalar-add-sub-imm.mir
M llvm/test/CodeGen/AMDGPU/si-fold-scalar-clamp.mir
M llvm/test/CodeGen/AMDGPU/si-init-whole-wave.mir
M llvm/test/CodeGen/AMDGPU/si-insert-hard-clauses-no-nesting.mir
M llvm/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll
M llvm/test/CodeGen/AMDGPU/si-instr-info-vopc-exec.mir
M llvm/test/CodeGen/AMDGPU/si-late-branch-lowering-preserve-loop-info.mir
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-preserve-dom-tree.mir
M llvm/test/CodeGen/AMDGPU/si-lower-i1-copies-order-of-phi-incomings.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-cycle-header.ll
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir
M llvm/test/CodeGen/AMDGPU/si-lower-wwm-copies.mir
M llvm/test/CodeGen/AMDGPU/si-opt-vgpr-liverange-bug-deadlanes.mir
M llvm/test/CodeGen/AMDGPU/si-optimize-vgpr-live-range-dbg-instr.ll
M llvm/test/CodeGen/AMDGPU/si-optimize-vgpr-live-range-dbg-instr.mir
M llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
M llvm/test/CodeGen/AMDGPU/si-pre-emit-peephole-preserve-loop-info.mir
M llvm/test/CodeGen/AMDGPU/si-scheduler-exports.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (32) (#209561)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: fc0b032ba8b56f02e834847ec3e2a6375011017f
https://github.com/llvm/llvm-project/commit/fc0b032ba8b56f02e834847ec3e2a6375011017f
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
R llvm/test/Transforms/SampleProfile/icp_target_feature.ll
Log Message:
-----------
Revert "[PGO][ICP] Prevent indirect call promotion to functions with incompatible target features" (#209572)
Reverts llvm/llvm-project#208774
The failure that caused the revert last time should be fixed by
37b8e765ce4837a7577e6f762bcdffe4b232759c.
Commit: 5245afc014c4d34705bf8734fc835bcbfe9b6f39
https://github.com/llvm/llvm-project/commit/5245afc014c4d34705bf8734fc835bcbfe9b6f39
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/SPIRV/vk-pushconstant-layout.ll
Log Message:
-----------
[NFC][SPIR-V] Remove stale XFAIL in vk-pushconstant-layout.ll (#209447)
Commit: f69342fa200100560c689e0ccdbbc5c3249aee4b
https://github.com/llvm/llvm-project/commit/f69342fa200100560c689e0ccdbbc5c3249aee4b
Author: Mike Kruskal <mkruskal at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_common_nolibc.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_dl.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_dl.h
M compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
M compiler-rt/lib/tsan/go/buildgo.sh
M compiler-rt/test/sanitizer_common/TestCases/Linux/dlopen_image_base.c
Log Message:
-----------
Reland "[compiler-rt] [sanitizer_common] Fix SIGSEGV in ForEachMappedRegion for DSOs with custom image base" (#209576)
Attempt 2 at #206299, fixing a linkage issue with gotsan on older
versions of glibc. Rather than forcing linkage of libdl (which may not
be safe with go), this just disables the dladdr usage under go builds.
This bug only affected MSAN and DFSAN anyway, and the code should be
unused by TSAN.
`ForEachMappedRegion` processes dynamic linker map entries to track
loaded segments. However, it assumes map->l_addr is the address of the
ELF header. For DSOs linked with a custom preferred image base offset
(e.g. -Wl,--image-base=0x4000000), `map->l_addr` contains the relocation
bias: `map->l_addr = actual_load_address - preferred_base`
In this case, map->l_addr points below the first loaded segment in
unmapped or PROT_NONE memory. Doing a read dereference at this address
triggers a SIGSEGV. Add a call to dladdr() on the dynamic section
pointer map->l_ld to obtain the true ELF header base address.
Likely fixes https://github.com/llvm/llvm-project/issues/84482 - which
looks like the exact same stacktrace I was debugging that led me to this
fix
Also looks it may have shown up in
https://github.com/llvm/llvm-project/issues/21068 - my case was also
flaky, and it only shows up if you build the so with custom base address
Assisted-by: Gemini
Commit: 0fae10b74b93723b4a2a53804331696c1b37fe14
https://github.com/llvm/llvm-project/commit/0fae10b74b93723b4a2a53804331696c1b37fe14
Author: Scott Linder <scott.linder at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/misaligned-vgpr-regsequence.mir
Log Message:
-----------
[AMDGPU] Add stackPtrOffsetReg to llvm/test/CodeGen/AMDGPU/misaligned-vgpr-regsequence.mir (#209533)
Prepare for this being observable to the CFA generation code.
Commit: d218bc40aba65687ddc2fb616a154b2799631f0f
https://github.com/llvm/llvm-project/commit/d218bc40aba65687ddc2fb616a154b2799631f0f
Author: Kyungtak Woo <kevinwkt at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/Assembler/thinlto-bad-summary-5.ll
Log Message:
-----------
[ThinLTO] Fix thinlto-bad-summary-5.ll in read-only environments (#209513)
The test thinlto-bad-summary-5.ll was failing in read-only environments
(such as sandboxed test runners) because it attempted to write the
output bitcode file to the same directory as the input file, resulting
in a "Permission denied" error.
Fix this by redirecting the output to /dev/null using `-o /dev/null`.
We cannot use `-disable-output` here because the error we want to
test is triggered inside the BitcodeWriter, which is bypassed when
output is disabled.
assisted by gemini
Commit: fbba327208d7f6994f9a28a51dca3e913e3b444a
https://github.com/llvm/llvm-project/commit/fbba327208d7f6994f9a28a51dca3e913e3b444a
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/cmake/modules/HandleLLVMOptions.cmake
Log Message:
-----------
[CMake] Add -Wl,-z,pack-relative-relocs if supported (#208217)
We should aim to provide a good experience by default. Enable RELR for
PIC builds (which is on by default, even in non-dylib builds) if
supported by the linker (feature-tested) and the libc (currently
hardcoded as glibc 2.36+; musl has no easy way to determine support).
RELR substantially reduces the size of the dynamic relocations in PIE
executables and shared libraries and therefore also lowers max-rss and
startup time due to fewer page faults.
Commit: fc298ccbc52a9199a2181d30fa6e7189c374c091
https://github.com/llvm/llvm-project/commit/fc298ccbc52a9199a2181d30fa6e7189c374c091
Author: firmiana <firmiana402 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/source/Expression/DWARFExpression.cpp
M lldb/unittests/Expression/DWARFExpressionTest.cpp
Log Message:
-----------
[lldb] Reject mixed typed DWARF binary operands (#201288)
## Summary
LLDB currently accepts and evaluates some ill-typed DWARF typed binary
operations whose two operands have different base types.
DWARF v5 typed-expression rules require arithmetic/logical and
relational binary operators to operate on operands of the same type,
either the same base type or the generic type. (see [DWARF v5
doc](https://dwarfstd.org/doc/DWARF5.pdf) Section 2.5.1.4)
This patch adds an explicit compatibility check before evaluating the
affected binary operators.
## Example
A DWARF expression illustrating the issue is:
```text
DW_OP_constu 0xff
DW_OP_convert <unsigned char>
DW_OP_constu 0x1
DW_OP_convert <short unsigned int>
DW_OP_plus
DW_OP_stack_value
```
The left operand is typed as unsigned char, while the right operand is
typed as short unsigned int. These are different DWARF base types, so
`DW_OP_plus` should reject the expression instead of evaluating it.
In differential testing, GDB rejects this kind of expression with:
```text
Incompatible types on DWARF stack
```
Before this patch, LLDB continued evaluating the expression and produced
a concrete result through the existing `Scalar` arithmetic path.
## Affected operations
The issue is not specific to DW_OP_plus. The same acceptance pattern was
observed for mixed-base-type typed operands across these binary
operations:
- Arithmetic: `DW_OP_plus`, `DW_OP_minus`, `DW_OP_div`, `DW_OP_mod`
- Bitwise: `DW_OP_and`, `DW_OP_or`, `DW_OP_xor`
- Shifts: `DW_OP_shl`, `DW_OP_shr`, `DW_OP_shra`
- Relations: `DW_OP_lt`, `DW_OP_le`, `DW_OP_gt`, `DW_OP_ge`, `DW_OP_eq`,
`DW_OP_ne`
## Implementation notes
LLDB's DWARF expression stack currently stores `Value` objects, whose
scalar payload is represented by `Scalar`. `Scalar` does not preserve
the original DWARF base type DIE, but it does carry the pieces of
base-type information used by the evaluator:
- scalar kind
- byte size
- integer signedness
This patch therefore checks those `Scalar` properties before dispatching
each affected binary operation to the existing arithmetic/comparison
logic. If the two operands do not match, evaluation now stops with an
error.
This **PR Text** was prepared with assistance from Codex. I reviewed the
PR Text and take responsibility for the contribution.
Commit: 3ba1b70dc2f4920d727ec1e678a79b744ce72b99
https://github.com/llvm/llvm-project/commit/3ba1b70dc2f4920d727ec1e678a79b744ce72b99
Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
M llvm/test/CodeGen/AMDGPU/vgpr-set-msb-coissue.mir
Log Message:
-----------
[AMDGPU][CodeGen] Fix `S_NOP` insertion during `S_SET_VGPR_MSB` placement (#209525)
The issue arises when co-issue optimizations move the initial insertion
position for `S_SET_VGPR_MSB` to an earlier spot, creating a mismatch
with the position used to determine whether a `S_NOP` is needed.
Commit: 0b908e100f3d88232aa3b0190e23e41ca327edf1
https://github.com/llvm/llvm-project/commit/0b908e100f3d88232aa3b0190e23e41ca327edf1
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/test/Driver/msvc-link.c
Log Message:
-----------
[clang][test] Avoid relying on `-fuse-ld=ld` default value for marm64x test (#209597)
Test case added in #209324
Commit: 2c31050a6cf609285b0561b9a7c262fa4cf790c8
https://github.com/llvm/llvm-project/commit/2c31050a6cf609285b0561b9a7c262fa4cf790c8
Author: lntue <lntue at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M .github/workflows/libc-overlay-tests.yml
Log Message:
-----------
[libc][ci] Add qemu armhf overlay tests to precommit CI. (#203369)
Commit: eecd874fba6cef85071f8e02afc81c81e9d352e5
https://github.com/llvm/llvm-project/commit/eecd874fba6cef85071f8e02afc81c81e9d352e5
Author: Hansang Bae <hansang.bae at intel.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M offload/plugins-nextgen/common/src/RecordReplay.cpp
Log Message:
-----------
[Offload] Remove unnecessary assert (#209518)
`uint32_t` is always greater than or equal to zero.
Commit: 04aa50715cafa5f205b44bc88a6f721d296ec91c
https://github.com/llvm/llvm-project/commit/04aa50715cafa5f205b44bc88a6f721d296ec91c
Author: Hans Wennborg <hans at hanshq.net>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/AST/DeclCXX.cpp
M clang/test/CXX/drs/cwg15xx.cpp
M clang/test/CodeGenCXX/devirtualize-virtual-function-calls.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
Revert "[Clang] Allow devirtualization involving array subscripts with constant indices when the pointee type is known [CWG1504] (#207540) (#209596)
It caused miscompiles, see discussion on the PR.
This reverts commit ee24ac00d874ce82eaf36431f9aeb2ad744bc3b8.
Commit: 73615e792dc3116d5c66cb8175039dd6d4840f31
https://github.com/llvm/llvm-project/commit/73615e792dc3116d5c66cb8175039dd6d4840f31
Author: Pawan Nirpal <pnirpal at qti.qualcomm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
A llvm/test/CodeGen/ARM/thumb1-copy-physreg-dbg-value-crash.ll
Log Message:
-----------
[ARM] - Fix Thumb1InstrInfo::copyPhysReg crash on debug instructions during liveness walk. (#209478)
clang asserts when compiling with -mthumb -mcpu=arm926ej-s -O0 -g
(pre-v6 Thumb1, debug info enabled). The crash occurs in
LiveRegUnits::stepBackward which unconditionally asserts that it must
never be called on a debug instruction, but Thumb1InstrInfo::copyPhysReg
walks the basic block backward without skipping DBG_VALUE instructions.
Fixes: https://github.com/llvm/llvm-project/issues/209475
Commit: d089325bad0e85c1be958d54cfbf9d44bf02fcf1
https://github.com/llvm/llvm-project/commit/d089325bad0e85c1be958d54cfbf9d44bf02fcf1
Author: Scott Linder <scott.linder at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-scc-clobber.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir
M llvm/test/CodeGen/AMDGPU/pei-build-spill-offset-overflow-gfx950.mir
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir
M llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir
M llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir
M llvm/test/CodeGen/AMDGPU/spillv16.mir
M llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir
Log Message:
-----------
[AMDGPU] Fix CFI emission when scratch instructions are used to spill (#209534)
4b1cfc5d7c606e "[NFCI][AMDGPU] Final touch before moving to
`GET_SUBTARGETINFO_MACRO` (#177401)" (or more generally the move to
hasFlatScratchEnabled over just enableFlatScratch) was missed during the
CFI upstreaming for AMDGPU, and so we currently define the CFA
incorrectly for the architected flat scratch case.
This incorrect CFI is generated for e.g. gfx942. For such architecture,
the stack pointer (s32) holds a swizzled address (per-lane offset) but
the CFA needs to be an unswizzled address (per-wave).
In the incorrect program, we have a prologue looking like:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_mov_b32 s0, s33
s_mov_b32 s33, s32
[...]
s_add_i32 s32, s32, 16
[...]
(16 is a per-lane offset) but CFA ends up being defined as
DW_CFA_LLVM_def_aspace_cfa: SGPR32 +0 in addrspace6
with addrspace6 being DW_ASPACE_AMDGPU_private_wave. The correct CFA
should instead be:
DW_CFA_def_cfa_expression: DW_OP_regx SGPR32, DW_OP_deref_size 0x4,
DW_OP_lit6, DW_OP_shl, DW_OP_lit6, DW_OP_LLVM_user
DW_OP_LLVM_form_aspace_address
which converts from swizzled to unswizzled.
Deciding which form to use is done in SIFrameLowering::emitDefCFA which
still uses the old ST.enableFlatScratch() instead of
ST.hasFlatScratchEnabled(). This patch fixes this as well as the other
user of enableFlatScratch in createScaledCFAInPrivateWave.
The naming for the "enable-flat-scratch" feature seems unfortunate in
retrospect, although I'm not sure we can change it easily at this point?
CFI generation tested for gfx942 and gfx1031 with ROCgdb's testsuite.
Commit: db9efd93912b71e5ec200549b17391696dcae18f
https://github.com/llvm/llvm-project/commit/db9efd93912b71e5ec200549b17391696dcae18f
Author: Xi Ruoyao <xry111 at xry111.site>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsFastISel.cpp
M llvm/test/CodeGen/Mips/divrem.ll
Log Message:
-----------
[Mips] Do not emit teq if NoZeroDivCheck in FastISel (#204386)
Fix the issue: -mno-check-zero-division is not respected at -O0 for some
test cases.
Co-authored-by: Folkert de Vries <folkert at folkertdev.nl>
Commit: 1e4b05a1bb87a8fe3a75eb2960e11afc46c72ebb
https://github.com/llvm/llvm-project/commit/1e4b05a1bb87a8fe3a75eb2960e11afc46c72ebb
Author: firmiana <firmiana402 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
M lldb/unittests/Expression/DWARFExpressionTest.cpp
Log Message:
-----------
[lldb] Prefer DW_AT_bit_size for DW_OP_convert type width (#208478)
This PR fixes a DW_OP_convert issue where LLDB derives the conversion
width from DW_AT_byte_size * 8 before considering DW_AT_bit_size,
#208203
For base types that carry both DW_AT_byte_size and DW_AT_bit_size, such
as C _BitInt(31), DW_AT_bit_size describes the actual value width. LLDB
should therefore prefer DW_AT_bit_size when it is present, and only fall
back to DW_AT_byte_size otherwise.
## Tests
Extended DWARFExpression.DW_OP_convert coverage with a base type that
has both DW_AT_byte_size and DW_AT_bit_size, and verifies that the
conversion uses the DW_AT_bit_size width.
Commit: 05b9aa46fdb72495bb596dea621fda1f9df22880
https://github.com/llvm/llvm-project/commit/05b9aa46fdb72495bb596dea621fda1f9df22880
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
A llvm/test/Transforms/ConstraintElimination/induction-condition-in-loop-exit-latch-counted.ll
A llvm/test/Transforms/ConstraintElimination/induction-condition-in-loop-exit-postinc.ll
M llvm/test/Transforms/ConstraintElimination/induction-condition-in-loop-exit.ll
A llvm/test/Transforms/ConstraintElimination/induction-nowrap-from-scev-not-ir.ll
M llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-signed.ll
A llvm/test/Transforms/ConstraintElimination/or-non-negative.ll
M llvm/test/Transforms/ConstraintElimination/transfer-signed-facts-to-unsigned.ll
A llvm/test/Transforms/PhaseOrdering/constraint-eliminiation-interactions.ll
Log Message:
-----------
[ConstraintEim] Add tests for postinc IVs, signed reasoning. (#209612)
Extend test coverage for postinc IVs (both in header and latch), as well
as signed reasoning and transfers for upcoming patche.
Commit: 147bf7102fdcd4d016c6d214ff9924c9fa3ee215
https://github.com/llvm/llvm-project/commit/147bf7102fdcd4d016c6d214ff9924c9fa3ee215
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/test/API/tools/lldb-dap/stackTrace/TestDAP_stackTrace.py
Log Message:
-----------
[lldb-dap][test] Fix stackTrace test in symlink environment (#209595)
This test (edited in #209236) fails when run in an environment where
source files are symlinks. Using `realpath` breaks that, as we use the
path in assertions later. The var is already constructed as `source_file
= self.getSourcePath("main.c")` which should be sufficient for
`_RecurseSource()` to work.
Commit: ef118b5b3a617237729b010b944237c146e8d300
https://github.com/llvm/llvm-project/commit/ef118b5b3a617237729b010b944237c146e8d300
Author: Jan Korous <jkorous at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
A clang/include/clang/ScalableStaticAnalysis/Analyses/SharedLexicalRepresentation/SharedLexicalRepresentation.h
M clang/include/clang/ScalableStaticAnalysis/BuiltinAnchorSources.def
M clang/lib/ScalableStaticAnalysis/Analyses/CMakeLists.txt
A clang/lib/ScalableStaticAnalysis/Analyses/SharedLexicalRepresentation/SharedLexicalRepresentationFormat.cpp
M clang/unittests/ScalableStaticAnalysis/CMakeLists.txt
A clang/unittests/ScalableStaticAnalysis/Serialization/JSONFormatTest/SharedLexicalRepresentationFormatTest.cpp
Log Message:
-----------
[SSAF] Add EntitySourceLocationsSummary and JSON format (#208841)
Adds a per-entity TU-level summary recording the canonical (file, line,
column) of each declaration registered against an entity. The data feeds
a follow-on whole-program analysis that groups entities sharing a
declaration source-location into equivalence classes.
Assisted-By: Claude Opus 4.7
Commit: d9f6dbca81714fd5ee1c5aaf656fed6b0b5a4c01
https://github.com/llvm/llvm-project/commit/d9f6dbca81714fd5ee1c5aaf656fed6b0b5a4c01
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/utils/compare-benchmarks
M libcxx/utils/requirements.txt
Log Message:
-----------
[libc++] Compute a confidence interval in compare-benchmarks (#208090)
When comparing benchmark results with more than one sample per
benchmark, compute a confidence interval and flag rows that are
statistically significant. This should make the A/B comparison PR job
more robust to noise and easier to rely on. After this change, output
for a multi-sample run looks like:
```
Benchmark Baseline Candidate Difference % Difference Significant? 95% C.I. of %diff
------------------------------ ---------- ----------- ------------ -------------- -------------- -------------------
std::any_of(list<int>)/32 39.92 39.22 -0.70 -1.75% [-6.5%, +1.6%]
std::any_of(list<int>)/32768 54071.34 65395.51 11324.17 20.94% [-2.8%, +34.5%]
std::any_of(list<int>)/50 67.39 69.08 1.69 2.51% x [+0.2%, +4.7%]
std::any_of(list<int>)/8 7.21 6.46 -0.75 -10.40% x [-25.0%, -0.7%]
std::any_of(list<int>)/8192 21745.58 22299.32 553.74 2.55% [-20.3%, +38.4%]
std::any_of(vector<int>)/32 24.21 14.61 -9.60 -39.65% x [-41.2%, -38.4%]
std::any_of(vector<int>)/32768 24365.14 12498.21 -11866.93 -48.70% x [-48.9%, -48.6%]
Geomean 324.15 247.83 -76.32 -23.54%
```
The confidence interval is computed based on the mean of the N samples,
but we still present the median of N in the results. Because of that,
the result is not centered within the confidence interval, and we must
report it as [low, high] instead of a single number. The general idea is
that if 0% falls within the confidence interval, we can't really be
certain that the result changed at all. Similarly, if significant
negative and positive % diffs are in the confidence interval, we can't
be confident that we are introducing an optimization, regression, or any
change at all.
I think this approach is reasonable given the small number of samples
(usually around 3), which severely limits the statistical methods
available to us.
Assisted by Claude
Commit: 3eb929be5e17d66900020bd1caa7d2510d4f9601
https://github.com/llvm/llvm-project/commit/3eb929be5e17d66900020bd1caa7d2510d4f9601
Author: Eli Friedman <efriedma at qti.qualcomm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/src/ios.cpp
Log Message:
-----------
Make ios_base::xalloc non-atomic with LIBCXX_ENABLE_THREADS=OFF. (#208356)
762b77a moved the definition of "xindex" out of the header, and in the
process dropped the _LIBCPP_HAS_THREADS check. Re-add the check to
maintain the status quo.
The discussion on https://github.com/llvm/llvm-project/pull/198994
indicates it's not clear whether LIBCXX_ENABLE_THREADS=OFF is actually
supposed to mean single-threaded. But it clearly does in practice:
atomic_support.h uses non-atomic ops when threads are disabled, and a
few other APIs have explicit non-atomic fallback paths.
My team ran into this trying to run libc++ tests for a RISC-V core
without the "a" extension.
Commit: 3ae8e355a288a8306bae6cd3ce635ce3de4a1359
https://github.com/llvm/llvm-project/commit/3ae8e355a288a8306bae6cd3ce635ce3de4a1359
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M orc-rt/test/unit/CommonTestUtils.h
Log Message:
-----------
[orc-rt] Make noDispatch test helper fail in -Asserts builds. (#209493)
noDispatch guards Sessions that must never dispatch a wrapper call, but
it did so with assert(false), which compiles out under NDEBUG.
Replace the assert with ADD_FAILURE(), which records a failure in every
build mode, and then complete the call via its Return continuation with
an out-of-band error. Completing the call means a caller awaiting the
result unblocks and fails too, rather than hanging, even when the
dispatch arrives on a non-test thread where ADD_FAILURE() alone may not
be observed.
Commit: 5fc69663ad4a99b8ad0f7cc11e8ba2d626cc2acc
https://github.com/llvm/llvm-project/commit/5fc69663ad4a99b8ad0f7cc11e8ba2d626cc2acc
Author: Carlos Seo <carlos.seo at linaro.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
M flang/test/Semantics/OpenMP/declare-simd-empty.f90
A flang/test/Semantics/OpenMP/declare-simd-scope.f90
M flang/test/Semantics/OpenMP/declare-simd.f90
Log Message:
-----------
[flang][OpenMP] Check the context of the declare_simd directive (#209318)
OpenMP 6.0, 9.8 "declare_simd Directive", restricts the placement of the
directive:
Any declare_simd directive must appear in the specification part of a
subroutine subprogram, function subprogram, or interface body to which
it applies.
Flang did not enforce this, and accepted the directive in the
specification part of a module, submodule, main program or block data.
Note: the restriction requiring the argument to name the procedure to
which the directive applies is not implemented here.
Fixes #205478
Commit: 71db296bc0f847220e41bd913b6cce4031a23492
https://github.com/llvm/llvm-project/commit/71db296bc0f847220e41bd913b6cce4031a23492
Author: qyingwu <46992476+qyingwu at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/lib/Dialect/SparseTensor/Transforms/SparseIterationToScf.cpp
M mlir/test/Dialect/SparseTensor/sparse_iteration_to_scf.mlir
Log Message:
-----------
[mlir][sparse] Handle dense iterators in sparse iteration lowering (#208963)
Fixes #205980.
`lower-sparse-iteration-to-scf` always called `linkNewScope()` when
lowering
iterators handled by `scf.for`. Dense levels are random-access
iterators, and
`linkNewScope()` asserts for random-access iterators because those
should be
traversed by coordinate.
Use `locate()` for random-access iterators and keep `linkNewScope()` for
non-random-access iterators.
Verification:
- `cmake --build /tmp/mlir-208198 --target mlir-opt`
- `/tmp/mlir-208198/bin/mlir-opt -lower-sparse-iteration-to-scf
/tmp/issue-
205980.mlir`
- `/tmp/mlir-208198/bin/llvm-lit -sv mlir/test/Dialect/SparseTensor/
sparse_iteration_to_scf.mlir mlir/test/Dialect/SparseTensor/
sparse_kernels_to_iterator.mlir mlir/test/Dialect/SparseTensor/
sparse_space_collapse.mlir`
Commit: 2e38be8333fcd9c17eb7be1b2553b85e0cd9ab15
https://github.com/llvm/llvm-project/commit/2e38be8333fcd9c17eb7be1b2553b85e0cd9ab15
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/source/Expression/DWARFExpression.cpp
M lldb/source/Target/RegisterContextUnwind.cpp
Log Message:
-----------
[lldb] Allow generic operands in DWARF binary type check (#209641)
fc298ccbc52a's CheckScalarOperandsHaveSameType also rejects legitimate
generic-typed operands, breaking breakpad STACK WIN / raSearch unwinding
on 32-bit targets. For `DW_OP_breg7 +0, DW_OP_consts +80, DW_OP_plus`,
DW_OP_breg yields a register-sized (8-byte) scalar while DW_OP_const*
yields an address-sized (4-byte) generic one. The strict size gate ran
before the genericness escape, and the escape only checked the left
operand, so the CFA expression was rejected and the unwind failed.
Reorder so two integers that are each at least as wide as the generic
type are accepted before the size/signedness gate. The commit's own
type-check unit tests still pass.
Also fix a latent crash the failure exposed: ReadFrameAddress and
GetReturnAddressHint only consumed the error inside an UNWIND_LOG
argument, which is skipped when the log is off, so the errored Expected
was destroyed unchecked and aborted. Consume it via LLDB_LOG_ERROR /
LLDB_LOG_ERRORV instead.
Commit: 4d0a3021c01e15c473e6a515dc8498fb190e3709
https://github.com/llvm/llvm-project/commit/4d0a3021c01e15c473e6a515dc8498fb190e3709
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/NVPTX/CMakeLists.txt
M llvm/lib/Target/NVPTX/NVPTX.h
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXPassRegistry.def
A llvm/lib/Target/NVPTX/NVPTXPromoteParamAlign.cpp
R llvm/lib/Target/NVPTX/NVPTXSetByValParamAlign.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
A llvm/test/CodeGen/NVPTX/promote-param-align.ll
R llvm/test/CodeGen/NVPTX/set-byval-param-align.ll
M llvm/utils/gn/secondary/llvm/lib/Target/NVPTX/BUILD.gn
Log Message:
-----------
[NVPTX] Promote internal function alignments in IR pass (#208040)
During lowering NVPTX will update the alignment of parameters and return
values if the function is internal and has only compatible direct calls.
Previously this happened within the alignment helper functions during
ISel and assembly printing making it opaque and unreliable. This change
moves that logic to an IR pass so that it can be inspected and disabled
more easily.
Commit: 68f74b7c1f648f7272f46af5d3d6e314e85601fc
https://github.com/llvm/llvm-project/commit/68f74b7c1f648f7272f46af5d3d6e314e85601fc
Author: Florian Mayer <fmayer at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
Log Message:
-----------
[NFC] [TableGen] mention `srcvalue` in unused input error (#209633)
Commit: e2fe51e408e097237a214f82385adf97090b3dee
https://github.com/llvm/llvm-project/commit/e2fe51e408e097237a214f82385adf97090b3dee
Author: David Young <davidayoung at meta.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/plugin_config.bzl
Log Message:
-----------
[lldb][bazel] Add ScriptedFrameProvider plugin to the Bazel overlay (#209634)
Adds the PluginScriptedFrameProvider cc_library for the new
SyntheticFrameProvider/ScriptedFrameProvider category and registers it
in DEFAULT_PLUGINS. Deps mirror the plugin's CMakeLists.txt (lldbCore,
lldbInterpreter, lldbTarget, lldbUtility, Support) plus the
:PluginScriptedProcess plugin dep it uses.
The ScriptedFrameProvider plugin was added upstream in PR #161870
("[lldb] Introduce ScriptedFrameProvider for real threads"), relanded as
PR #170236; this wires it into the Bazel overlay build.
bazel rule creation assisted with: claude
Can confirm this rule translates into a valid buck2 rule for Meta to
build internally, but no bazel build locally; will await CI testing.
Commit: 75fd1ca48059b26360dc961651ec9a23dccff53c
https://github.com/llvm/llvm-project/commit/75fd1ca48059b26360dc961651ec9a23dccff53c
Author: Marco Elver <elver at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/Analysis/ThreadSafety.cpp
M clang/test/SemaCXX/warn-thread-safety-analysis.cpp
Log Message:
-----------
Thread Safety Analysis: Handle statement expressions in try-lock conditions (#209330)
Previously, statement expressions (`({ bool b = mu.TryLock(); b; })`)
used as try-lock conditions were not supported. Handle StmtExpr in
getTrylockCallExpr() by recursively analyzing the last statement of the
statement expression.
Commit: 514b75bbc54f751abdcd32f118f620c3dd2ce4ae
https://github.com/llvm/llvm-project/commit/514b75bbc54f751abdcd32f118f620c3dd2ce4ae
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/include/lldb/Core/PluginManager.h
M lldb/include/lldb/Interpreter/CommandCompletions.h
M lldb/include/lldb/Interpreter/CommandOptionArgumentTable.h
M lldb/include/lldb/Interpreter/Interfaces/ScriptedInterfaceUsages.h
M lldb/include/lldb/Interpreter/ScriptInterpreter.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/source/Commands/CommandCompletions.cpp
M lldb/source/Commands/CommandObjectScripting.cpp
M lldb/source/Commands/Options.td
M lldb/source/Core/PluginManager.cpp
M lldb/source/Interpreter/Interfaces/ScriptedInterfaceUsages.cpp
M lldb/source/Interpreter/ScriptInterpreter.cpp
A lldb/test/API/commands/scripting/extension/TestScriptingExtensionListJSON.py
M lldb/test/Shell/Commands/command-scripting-extension-list.test
Log Message:
-----------
[lldb/script] Improve `scripting extension list` output and filtering (#209400)
This patch improves `scripting extension list` in three ways.
First, it groups the output by `ScriptedExtension`: instead of one row
per registered plugin instance, one entry per extension is printed with
a combined `Language` field.
Second, it colorizes and visually separates the output. Each entry is
preceded by a dimmed dashed separator; field labels are printed in bold
green, the extension name value in bold cyan as a mini-heading, and
`None` usage values are dimmed, all via the same
`ansi::FormatAnsiTerminalCodes(..., use_color)` idiom
`Breakpoint::GetDescription` uses elsewhere, gracefully no-op when color
is disabled or unsupported. `ScriptedInterfaceUsages::Dump` takes an
optional `use_color` parameter so its own `API Usages:` / `Command
Interpreter Usages:` labels can match.
Third, it adds `-j`/`--json` to emit a JSON array of `{name,
description, languages, api_usages, command_interpreter_usages}` per
extension, mirroring `plugin list`'s existing `-j`. `DoExecute` now
computes the extension grouping once and branches into
`OutputJsonFormat` or `OutputTextFormat`, sharing a
`GetLanguagesForExtension` helper. It also accepts optional positional
`<extension-name>` arguments to filter the listing to specific
extensions (matched via the same case-insensitive
`ScriptInterpreter::StringToExtension` used by `scripting extension
generate`), with completion wired up via `eScriptedExtensionCompletion`.
Also fix a latent lifetime bug in the shared language-collection helper
so it owns its `std::string` values instead of holding `StringRef`s to
temporaries; the JSON path made it observable.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: ef81c51cddcb7395a94da0240ec48e367a60f18c
https://github.com/llvm/llvm-project/commit/ef81c51cddcb7395a94da0240ec48e367a60f18c
Author: Endre Fülöp <endre.fulop at sigmatechnology.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/docs/analyzer/checkers.rst
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/StaticAnalyzer/Checkers/PthreadLockChecker.cpp
M clang/test/Analysis/analyzer-config.c
M clang/test/Analysis/c11lock.c
M clang/test/Analysis/fuchsia_lock.c
M clang/test/Analysis/pthreadlock-notes.c
M clang/test/Analysis/pthreadlock.c
Log Message:
-----------
[analyzer] Disable lock order reversal check by default in PthreadLoc… (#202452)
…kChecker
Lock order reversal is a real source of deadlocks, but the current
single-path intraprocedural analysis is a single-path analysis, and it
cannot reason about potentially overlapping executions.This makes this
part of the checker too imprecise for default-on.
Add a WarnOnLockOrderReversal option (default: false) for the previous
behavior.
Commit: 4a223ced16f7aec0389b4b6257a8aecfe5cf57bf
https://github.com/llvm/llvm-project/commit/4a223ced16f7aec0389b4b6257a8aecfe5cf57bf
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/source/Expression/DWARFExpression.cpp
Log Message:
-----------
[lldb] Distinguish DWARF binary type-check error messages (#209644)
CheckScalarOperandsHaveSameType reported every operand-check failure
with the same "requires operands to have the same type" message, even
though it rejects operands for three different reasons: mismatched type
kind, mismatched size, and mismatched signedness. That made a failed
check hard to diagnose from the error alone.
Parameterize the message so each check names what actually differs
(type, size, or signedness).
Follow-up to Augusto's review of #209641.
Commit: 23040e8b2f9256cf4fba5af30a10593cb691f39d
https://github.com/llvm/llvm-project/commit/23040e8b2f9256cf4fba5af30a10593cb691f39d
Author: Thurston Dang <thurston at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
A llvm/test/Instrumentation/MemorySanitizer/X86/avx512dq-intrinsics.ll
Log Message:
-----------
[msan][NFCI] Add AVX512 DQ tests (#207059)
This adds tests for AVX512 DQ ("Doubleword and Quadword Instructions",
not to be mistaken with Dairy Queen), forked from
llvm/test/CodeGen/X86/avx512dq-intrinsics.ll.
Commit: d7e6268cf237308ff84fc1afbb5638862d5cac3f
https://github.com/llvm/llvm-project/commit/d7e6268cf237308ff84fc1afbb5638862d5cac3f
Author: Thurston Dang <thurston at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
Log Message:
-----------
[msan][NFCI] Add forceIntegerIntrinsic option to handleIntrinsicByApplyingToShadow() (#207053)
Currently, if handleIntrinsicByApplyingToShadow() is given an
IntrinsicInst with floating-point arguments, it will cast the shadows to
floating-point, apply the intrinsic, and then cast the result back to
integer/shadow. This is inefficient, and, depending on the intrinsic,
may also result in floating-point exceptions.
The user can explicitly supply an integer variant of the intrinsic to be
applied to the shadow (shadowIntrinsicID), but this does not work if the
integer and floating-point variants are overloaded forms of the same
intrinsic ID.
This patch adds an option, 'forceIntegerIntrinsic', which will pass the
shadows as integers to the intrinsic, thus avoiding unnecessary casts.
(This is not enabled by default since some intrinsics do not support
integer arguments.)
As an example, future work can use 'forceIntegerIntrinsic' to handle
`<16 x float> @llvm.x86.avx512.mask.compress (<16 x float>, <16 x
float>, <16 x i1> %mask)`
with
`<16 x i32> @llvm.x86.avx512.mask.compress (<16 x i32>, <16 x i32>, <16
x i1> %mask)`
Commit: 3f58d3dfe808a5605c72fa812776ed6495188a6b
https://github.com/llvm/llvm-project/commit/3f58d3dfe808a5605c72fa812776ed6495188a6b
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/test/API/functionalities/statusline/TestStatusline.py
M lldb/test/API/functionalities/statusline/statusline_flood.py
Log Message:
-----------
[lldb][test] Deflake the statusline scripted-command output test (#209643)
test_scripted_command_output_not_eaten failed intermittently in CI on
its assertIn(b"\x1b7", data) guard because the captured window held no
statusline escape at all, only the command output and the next prompt.
The cause is a thread-scheduling race, not a bug. The statusline is
redrawn on the event thread once per progress event, but on a loaded
machine the event thread need not run until the flood command has
already returned, so it drains the queued progress events after (lldb)
was matched and the capture stopped, leaving no redraw to inspect.
Widen the flood (the line count is now an argument) so the event thread
has a larger window to redraw in, and retry until at least one complete
cursor save/restore pair is observed before checking that no output was
spliced into it. If a redraw is never seen, skip rather than fail.
I deliberately avoided a per-line sleep as it would let each redraw
finish between prints and hide the very interleaving the test looks for.
Fixes #209605
Commit: 5be3fdbc59fd78d0b86236ebc44c10c41571ce4c
https://github.com/llvm/llvm-project/commit/5be3fdbc59fd78d0b86236ebc44c10c41571ce4c
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/include/lldb/Host/Editline.h
M lldb/source/Host/common/Editline.cpp
Log Message:
-----------
[lldb] Use std::atomic<bool> for Editline's pending-resize flag (#209619)
TerminalSizeChanged() used a volatile std::sig_atomic_t to record that a
resize is pending. That type was chosen because the SIGWINCH handler ran
in async-signal context and could only touch an sig_atomic_t. Signals
are now handled on a dedicated thread, so the flag is written from a
normal thread and std::atomic<bool> is sufficient to handle that.
el_resize() still runs on the thread that owns libedit, in its read
loop. I discovered that it is not safe to run elsewhere, because it
resets libedit's display model without redrawing. Applying it off that
thread seems to throw it off and makes it duplicate the prompt.
Commit: 6dc5473fa6846830134f3ffe2257113382200391
https://github.com/llvm/llvm-project/commit/6dc5473fa6846830134f3ffe2257113382200391
Author: Rafael Auler <rafaelauler at meta.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M bolt/include/bolt/Core/BinaryContext.h
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Core/BinaryEmitter.cpp
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/X86/dwarf-inline-range-plt-shift.s
Log Message:
-----------
[BOLT] Fix shifted DWARF inline-scope ranges; track scope boundaries (#207291)
Summary:
BOLT updated DWARF lexical-scope ranges (DW_TAG_inlined_subroutine /
lexical_block low_pc/high_pc and DW_AT_ranges) via
translateInputToOutputRange(), which mapped a boundary using its input
offset relative to the start of the containing basic block:
OutAddr = BB.getOutputAddressRange().first + (InputOffset -
BB.getOffset())
This assumes intra-block byte offsets are preserved input->output. Any
pass that changes instruction sizes within a block ahead of a scope
boundary breaks that assumption. With --plt=all, each `call foo at PLT` (5
bytes, e8+rel32) is rewritten to `call *foo at GOT(%rip)` (6 bytes, ff
15+rel32); N such calls before a boundary shift its emitted low_pc/
high_pc N bytes too early, onto the preceding instruction. The range
stays within the parent so `llvm-dwarfdump --verify` does not catch it;
symbolizers then attribute samples on those instructions to the wrong
inlined frames.
Fix is to resolve scope-range boundaries through the precise
per-instruction input-to-output AddressMap (the same map BAT already
uses) instead of input-relative block offsets. Boundary instructions are
arbitrary (not just calls/branches), so they are normally absent from
that map; to make them resolvable, disassembly now keeps an offset for
the boundary instructions (only the boundaries, to keep the AddressMap
small) and those offsets are emitted as AddressMap entries whenever an
address map is required (requiresAddressMap(), which includes
--update-debug-sections via requiresPreciseAddressMap()), not only under
BAT.
Boundary collection (BinaryContext::collectDebugScopeBoundaries) runs in
readDebugInfo() after preprocessDebugInfo(). It streams the DIEs of the
CUs that will be updated directly from the already-loaded DWARFContext
with DWARFDebugInfoEntry::extractFast, decoding one DIE at a time into a
single reusable entry, so no DIE forest is materialized and no second
DWARF context is created. For split DWARF the .dwo DIEs are already
extracted by preprocessDWODebugInfo(), so the cached array is reused
instead. Boundaries are stored per function in a sorted, deduplicated
vector (BinaryFunction::DebugScopeBoundaryOffsets), queried during
disassembly with a monotonic cursor, and freed once the function is
disassembled, so the feature adds no global state.
The behavior is on by default and can be disabled with
--accurate-debug-ranges=0, which falls back to the old block-relative
mapping.
Test on big binaries with split dwarf, -lite=0:
wall Max RSS
-accurate-debug-ranges=0 1070.1s 94.91
-accurate-debug-ranges=1 1173.0s 100.07
delta +102.9s +5.16 (+4.6% CPU,
+5.4% RSS)
Test on big binaries with split dwarf, lite=1:
-accurate-debug-ranges=0 433.9s 83.23
-accurate-debug-ranges=1 434.7s 83.79 (+0.7% RSS)
--time-rewrite shows the boundary-collection phase itself is cheap:
"read debug ranges" is 5.8s of 4960s total user time on one binary
(0.1%) and 18.8s of 6307s on another binary; the feature's
cost is dominated by emitting/translating the extra AddressMap entries,
not by collection.
Commit: e2ead479f043a10e9b6d74f633346b96f37d9b2b
https://github.com/llvm/llvm-project/commit/e2ead479f043a10e9b6d74f633346b96f37d9b2b
Author: Sam Elliott <aelliott at qti.qualcomm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/MC/RISCV/xqcia-invalid.s
M llvm/test/MC/RISCV/xqciac-invalid.s
M llvm/test/MC/RISCV/xqcibi-invalid.s
M llvm/test/MC/RISCV/xqcibm-invalid.s
M llvm/test/MC/RISCV/xqcicli-invalid.s
M llvm/test/MC/RISCV/xqcicm-invalid.s
M llvm/test/MC/RISCV/xqcics-invalid.s
M llvm/test/MC/RISCV/xqcicsr-invalid.s
M llvm/test/MC/RISCV/xqciint-invalid.s
M llvm/test/MC/RISCV/xqcilb-invalid.s
M llvm/test/MC/RISCV/xqcili-invalid.s
M llvm/test/MC/RISCV/xqcilia-invalid.s
M llvm/test/MC/RISCV/xqcilo-invalid.s
M llvm/test/MC/RISCV/xqcilsm-invalid.s
M llvm/test/MC/RISCV/xqcisim-invalid.s
M llvm/test/MC/RISCV/xqcisls-invalid.s
M llvm/test/MC/RISCV/xqcisync-invalid.s
Log Message:
-----------
[RISCV][MC][NFC] Cleanup Xqci Tests (#209646)
Commit: a6d35f4715f1b6aaf1339bfa63e92685c0f46ed2
https://github.com/llvm/llvm-project/commit/a6d35f4715f1b6aaf1339bfa63e92685c0f46ed2
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/source/Plugins/Protocol/MCP/ProtocolServerMCP.cpp
M lldb/source/Plugins/Protocol/MCP/ProtocolServerMCP.h
M lldb/source/Plugins/Protocol/MCP/Tool.cpp
M lldb/source/Plugins/Protocol/MCP/Tool.h
M lldb/unittests/Protocol/MCPPluginTest.cpp
Log Message:
-----------
[lldb] Add MCP tools to create and destroy debugger instances (#209288)
Add debugger_create and debugger_delete tools to the MCP server so a
client can manage debugger instances, not just command the ones that
already exist. debugger_create detaches the new debugger's stdio from
the host process (redirecting input/output/error to the null device) so
its prompt and asynchronous output cannot corrupt an MCP stream that
shares the host's stdout. Command results flow through
CommandReturnObject and are unaffected.
Factor the tool and resource registration out of
ProtocolServerMCP::Extend into a shared PopulateServer() so an embedded
in-process server (e.g. in lldb-mcp) can install the same set.
Assisted-by: Claude
rdar://181722721
Commit: f7491eae219f3f5fb5d6ebd187977fb3f9eaa89a
https://github.com/llvm/llvm-project/commit/f7491eae219f3f5fb5d6ebd187977fb3f9eaa89a
Author: Thurston Dang <thurston at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Utils/MetaRenamer.cpp
M llvm/test/Transforms/MetaRenamer/metarenamer.ll
M llvm/test/Transforms/MetaRenamer/opcodes.ll
Log Message:
-----------
[MetaRenamer] Change basic block naming from 'bb' to 'bbl' (#205393)
Currently, `update_test_checks.py` warns when run on MetaRenamer output
e.g., `WARNING: Change IR value name 'bb3' or use
--prefix-filecheck-ir-name to prevent possible conflict with scripted
FileCheck name.`
Avoid this conflict by changing MetaRenamer to use 'bbl' for basic
blocks.
This is similar in spirit to
https://github.com/llvm/llvm-project/commit/86a63b2ae147e5a3edc39643783acfd39b059c92,
which renamed instructions from 'tmp' to 'inst' to avoid a conflict with
automatically-generated checks.
Commit: f89a59461103fdf71bd6c69dd68476b0e568fa52
https://github.com/llvm/llvm-project/commit/f89a59461103fdf71bd6c69dd68476b0e568fa52
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/test/CIR/CodeGenBuiltins/X86/avx10_2_512bf16-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/avx10_2bf16-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/keylocker.c
Log Message:
-----------
[CIR] Fix x86 builtin tests after tighter inlining (#209653)
The behavior of the AlwaysInliner was tightened in a recent change
(https://github.com/llvm/llvm-project/pull/209345) to avoid inling
functions with mismatched target attributes even when the alwaysinline
attribute was present. This exposed a few failures in CIR where we were
either running with stale target features or missing target features
that were needed for the builtins we were testing.
This change updates the run lines to use the correct feature sets.
Commit: 6ce9488de626f6e791f1d6cdce2562842f665944
https://github.com/llvm/llvm-project/commit/6ce9488de626f6e791f1d6cdce2562842f665944
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/lit/tests/Inputs/per-test-coverage-by-lit-cfg/lit.cfg
M llvm/utils/lit/tests/Inputs/per-test-coverage/lit.cfg
R llvm/utils/lit/tests/Inputs/shtest-external-shell-kill/lit.cfg
R llvm/utils/lit/tests/Inputs/shtest-external-shell-kill/test.txt
M llvm/utils/lit/tests/Inputs/shtest-readfile/lit.cfg
A llvm/utils/lit/tests/Inputs/shtest-run-at-line/basic.txt
A llvm/utils/lit/tests/Inputs/shtest-run-at-line/empty-run-line.txt
R llvm/utils/lit/tests/Inputs/shtest-run-at-line/external-shell/basic.txt
R llvm/utils/lit/tests/Inputs/shtest-run-at-line/external-shell/empty-run-line.txt
R llvm/utils/lit/tests/Inputs/shtest-run-at-line/external-shell/line-continuation.txt
R llvm/utils/lit/tests/Inputs/shtest-run-at-line/external-shell/lit.local.cfg
R llvm/utils/lit/tests/Inputs/shtest-run-at-line/external-shell/run-line-with-newline.txt
R llvm/utils/lit/tests/Inputs/shtest-run-at-line/internal-shell/basic.txt
R llvm/utils/lit/tests/Inputs/shtest-run-at-line/internal-shell/empty-run-line.txt
R llvm/utils/lit/tests/Inputs/shtest-run-at-line/internal-shell/line-continuation.txt
R llvm/utils/lit/tests/Inputs/shtest-run-at-line/internal-shell/lit.local.cfg
R llvm/utils/lit/tests/Inputs/shtest-run-at-line/internal-shell/run-line-with-newline.txt
A llvm/utils/lit/tests/Inputs/shtest-run-at-line/line-continuation.txt
M llvm/utils/lit/tests/Inputs/shtest-run-at-line/lit.cfg
A llvm/utils/lit/tests/Inputs/shtest-run-at-line/run-line-with-newline.txt
M llvm/utils/lit/tests/Inputs/shtest-timeout/lit.cfg
M llvm/utils/lit/tests/per-test-coverage-by-lit-cfg.py
M llvm/utils/lit/tests/per-test-coverage.py
R llvm/utils/lit/tests/shtest-external-shell-kill.py
R llvm/utils/lit/tests/shtest-readfile-external.py
M llvm/utils/lit/tests/shtest-run-at-line.py
M llvm/utils/lit/tests/shtest-timeout.py
Log Message:
-----------
[lit] Remove most external shell test coverage
Now that LLVM 23 has branched, we can look at removing the external
shell.
https://discourse.llvm.org/t/rfc-removal-of-the-lit-external-shell/90951
This patch removes most test coverage that was explicitly for the
external shell as it was entirely duplicated with the internal shell.
This patch leaves out removing test coverage in shtest-format as not all
the coverage there is duplicated and it seems like there is some missing
from the internal shell and I want to give it more careful
consideration.
Reviewers: hnrklssn, ilovepi, jh7370, arichardson
Pull Request: https://github.com/llvm/llvm-project/pull/209500
Commit: e824f1ab372f09e4e9dbae9a19cd9245772b381c
https://github.com/llvm/llvm-project/commit/e824f1ab372f09e4e9dbae9a19cd9245772b381c
Author: Jim Lin <jim at andestech.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedAndes45.td
Log Message:
-----------
[RISCV] Rename VLSU_MEM_LATENCY to Andes45VLSU_MEM_LATENCY in RISCVSchedAndes45.td (#209388)
Prefix the defvar with the Andes45 scheduler name to match the other
Andes45-local defvars (e.g. Andes45DLEN) and avoid a bare, generic name
in the shared RISC-V TableGen namespace.
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Commit: b208160cd01b220d3482f0159607d3e3855faf57
https://github.com/llvm/llvm-project/commit/b208160cd01b220d3482f0159607d3e3855faf57
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/test/Analysis/exploded-graph-rewriter/lit.local.cfg
M clang/test/Analysis/lit.local.cfg
M clang/test/Analysis/scan-build/lit.local.cfg
M clang/test/lit.cfg.py
M clang/test/utils/update_cc_test_checks/Inputs/lit.cfg.example
M clang/test/utils/update_cc_test_checks/lit.local.cfg
M clang/utils/perf-training/bolt.lit.cfg
M clang/utils/perf-training/lit.cfg
M clang/utils/perf-training/order-files.lit.cfg
Log Message:
-----------
[Clang] Drop ability to use the external shell
The external shell in lit is getting deleted soon and it will soon no
longer be possible to force enable it.
Reviewers: compnerd, petrhosek, ilovepi
Pull Request: https://github.com/llvm/llvm-project/pull/209564
Commit: 4376c0b7565895f6b936ce1fac610b92099deba7
https://github.com/llvm/llvm-project/commit/4376c0b7565895f6b936ce1fac610b92099deba7
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/test/lit.cfg.py
Log Message:
-----------
[MLIR] Remove ability to use external shell
The external shell is getting removed soon, so clean up the logic here
to enable it.
Reviewers: petrhosek, jpienaar, ilovepi, joker-eph
Pull Request: https://github.com/llvm/llvm-project/pull/209565
Commit: 6e6272088e69834fde6e30f0033f36ee63806d00
https://github.com/llvm/llvm-project/commit/6e6272088e69834fde6e30f0033f36ee63806d00
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M polly/test/UnitIsl/lit.cfg
M polly/test/lit.cfg
Log Message:
-----------
[Polly] Remove ability to use external shell
The external shell is getting removed soon, so remove the ability to
force enable it for polly tests.
Reviewers: ilovepi, Meinersbur, petrhosek
Pull Request: https://github.com/llvm/llvm-project/pull/209566
Commit: b1a35022e0d7abee1b3baffa8907feca19a7daa8
https://github.com/llvm/llvm-project/commit/b1a35022e0d7abee1b3baffa8907feca19a7daa8
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M bolt/test/lit.cfg.py
Log Message:
-----------
[BOLT] Remove ability to use external shell
The external shell is getting removed soon, so remove the ability to
force the use of it within BOLT.
Reviewers:
aaupov, petrhosek, maksfb, yozhu, paschalis-mpeis, yavtuk, ilovepi, rafaelauler, ayermolo
Pull Request: https://github.com/llvm/llvm-project/pull/209567
Commit: 3f6af3be1f3283aef568d1943318f90e4adae5e2
https://github.com/llvm/llvm-project/commit/3f6af3be1f3283aef568d1943318f90e4adae5e2
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/ADT/GenericCycleImpl.h
M llvm/include/llvm/ADT/GenericCycleInfo.h
M llvm/test/Analysis/CycleInfo/basic.ll
M llvm/test/Analysis/CycleInfo/unreachable-predecessor.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/branch-outside.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/diverged-entry-headers-nested.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/diverged-entry-headers.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/exit-divergence.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/reducible-headers.ll
M llvm/test/CodeGen/X86/cycle-info.mir
M llvm/test/Transforms/FixIrreducible/callbr.ll
Log Message:
-----------
[CycleInfo] Store blocks using Euler tour representation (#208614)
Each GenericCycle owned a `SetVector<BlockT*>` of its blocks (its own
plus every nested cycle's), so a block nested D cycles deep is stored D
times.
Instead, store every cycle's blocks in one GenericCycleInfo::BlockLayout
array laid out as an Euler tour of the cycle forest: each cycle owns a
contiguous range [IdxBegin, IdxEnd) nested inside its parent's.
run() builds the cycle tree and the block-to-innermost-cycle map as
before, then lays the array out in `layoutBlocks`. Its DFS also moves
from a single worklist that eagerly pushed every successor (so the stack
grew with the fan-out along the current path) to a stack of (block,
successor cursor) frames bounded by the DFS depth, with each block
pushed once; successors are still visited in the same order (hence the
weird `std::reverse_iterator`), so the cycles found are unchanged.
Block iteration order within a cycle changes, so cycle-print order in
some
CycleInfo/UniformityAnalysis/FixIrreducible tests shifts (block sets are
unchanged).
Aided by Claude Opus 4.8
Commit: f6a359fe20904afe5cc899d3c2fda258322f1f71
https://github.com/llvm/llvm-project/commit/f6a359fe20904afe5cc899d3c2fda258322f1f71
Author: Kito Cheng <kito.cheng at sifive.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/ReplaceWithVeclib.cpp
A llvm/test/CodeGen/X86/sincos-fpmath.ll
M llvm/test/CodeGen/X86/veclib-llvm.sincos.ll
Log Message:
-----------
[CodeGen] Teach ReplaceWithVeclib split vector llvm.sincos when only sin/cos veclib mappings exist (#194639)
Some vector math libraries provide vector sin and vector cos but no
vector sincos or no sincos with an ABI that LLVM can emit.
The one of the common case is glibc libmvec on x86: it exposes
`_ZGV{b,c,d,e}N{2,4,8,16}vvv_sincos{,f}` symbols, but those use a
vectors-of-pointers output ABI that expandMultipleResultFPLibCall does
not currently support. As a result, sincos will falls back to scalar
sincos calls even when the target has a fully working vector sin and
vector cos.
So we trying to split it into separate sin and cos calls, which will
then be replaced with vector calls if the target supports it, it
generally better than scalarized sincos calls.
Commit: 2033c4569af6ae3665a731dd276ea9795d531256
https://github.com/llvm/llvm-project/commit/2033c4569af6ae3665a731dd276ea9795d531256
Author: Kazu Hirata <kazu at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/ProfileData/SampleProfReader.h
M llvm/lib/ProfileData/SampleProfReader.cpp
Log Message:
-----------
[SampleProfile] Remove ProfileHasAttribute parameter from readFuncMetadata (NFC) (#208604)
This patch removes the ProfileHasAttribute parameter from
readFuncMetadata overloads.
Because ProfileHasAttribute is set once in readImpl during section
header parsing and never modified afterward, readFuncMetadata observes
the exact same immutable value regardless of whether it is passed as a
function parameter or read from the class member variable.
Assisted-by: Antigravity
Commit: 4148172fb742eaca83b427e43b0ff5691fe28d72
https://github.com/llvm/llvm-project/commit/4148172fb742eaca83b427e43b0ff5691fe28d72
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lld/test/lit.cfg.py
Log Message:
-----------
[lld] Remove ability to use the external shell
The external shell is going to get removed soon, so remove the ability
to force the use of it for lld tests.
Reviewers: ilovepi, MaskRay, petrhosek
Pull Request: https://github.com/llvm/llvm-project/pull/209568
Commit: 3f46a5e91cdf2ade1d8ca350f4a57af8221407ea
https://github.com/llvm/llvm-project/commit/3f46a5e91cdf2ade1d8ca350f4a57af8221407ea
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/FileCheck/lit.local.cfg
M llvm/test/lit.cfg.py
M llvm/test/tools/UpdateTestChecks/lit.local.cfg
M llvm/utils/mlgo-utils/tests/lit.cfg
Log Message:
-----------
[LLVM] Drop ability to use external shell
The external shell is getting removed soon, so drop the ability to force
the use of it for running LLVM tests.
Reviewers: ilovepi, petrhosek, arichardson
Pull Request: https://github.com/llvm/llvm-project/pull/209569
Commit: bf8924c7e10d4b0571c73f0b55274fb585a65c23
https://github.com/llvm/llvm-project/commit/bf8924c7e10d4b0571c73f0b55274fb585a65c23
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/lit/tests/Inputs/shtest-define/lit.cfg
M llvm/utils/lit/tests/Inputs/shtest-output-printing/lit.cfg
M llvm/utils/lit/tests/Inputs/shtest-pushd-popd/lit.cfg
M llvm/utils/lit/tests/Inputs/shtest-run-at-line/lit.cfg
M llvm/utils/lit/tests/Inputs/shtest-ulimit-nondarwin/lit.cfg
M llvm/utils/lit/tests/Inputs/shtest-ulimit/lit.cfg
M llvm/utils/lit/tests/Inputs/shtest-umask/lit.cfg
M llvm/utils/lit/tests/lit.cfg
M llvm/utils/lit/tests/per-test-coverage-by-lit-cfg.py
Log Message:
-----------
[lit] Drop explicitly setting execute_external=False
That parameter will be going away soon.
Reviewers: jh7370, arichardson, hnrklssn, ilovepi
Pull Request: https://github.com/llvm/llvm-project/pull/209570
Commit: a2fac66e0678ecb0ffe90cbd40afbc97eb84cf70
https://github.com/llvm/llvm-project/commit/a2fac66e0678ecb0ffe90cbd40afbc97eb84cf70
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M flang-rt/test/lit.cfg.py
M flang/test/lit.cfg.py
Log Message:
-----------
[Flang] Drop option to use external shell for testing
The external shell will be deleted soon, so drop the option to enable
the use of it for testing flang/flang-rt.
Reviewers: petrhosek, clementval, ilovepi
Pull Request: https://github.com/llvm/llvm-project/pull/209624
Commit: dcbf2a9eee64a100d22d4194293e828864cbbdbc
https://github.com/llvm/llvm-project/commit/dcbf2a9eee64a100d22d4194293e828864cbbdbc
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang-tools-extra/clangd/test/lit.cfg.py
M clang-tools-extra/include-cleaner/test/lit.cfg.py
M clang-tools-extra/test/lit.cfg.py
Log Message:
-----------
[clang-tools-extra] Drop option to use external shell
The external shell is going to be removed from lit soon, so drop the
option to enable using it.
Reviewers: petrhosek, compnerd, ilovepi
Pull Request: https://github.com/llvm/llvm-project/pull/209625
Commit: 00112b0ac171c360ae60d2f7ffabb7f22d62cdd0
https://github.com/llvm/llvm-project/commit/00112b0ac171c360ae60d2f7ffabb7f22d62cdd0
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M compiler-rt/test/builtins/Unit/lit.cfg.py
M compiler-rt/test/lit.common.cfg.py
Log Message:
-----------
[compiler-rt] Drop support for using the external shell
The lit external shell is going to be removed soon, so drop support for
using it to run the compiler-rt tests.
Reviewers: petrhosek, ilovepi, thurstond
Pull Request: https://github.com/llvm/llvm-project/pull/209626
Commit: 7c7f62c8880c0a4d94ea9607ea038ad6690264db
https://github.com/llvm/llvm-project/commit/7c7f62c8880c0a4d94ea9607ea038ad6690264db
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
R llvm/utils/lit/tests/Inputs/shtest-format/external_shell/fail.txt
R llvm/utils/lit/tests/Inputs/shtest-format/external_shell/fail_with_bad_encoding.txt
R llvm/utils/lit/tests/Inputs/shtest-format/external_shell/fail_with_control_chars.txt
R llvm/utils/lit/tests/Inputs/shtest-format/external_shell/lit.local.cfg
R llvm/utils/lit/tests/Inputs/shtest-format/external_shell/pass.txt
R llvm/utils/lit/tests/Inputs/shtest-format/external_shell/utf8_command.txt
R llvm/utils/lit/tests/Inputs/shtest-format/external_shell/write-bad-encoding.py
R llvm/utils/lit/tests/Inputs/shtest-format/external_shell/write-control-chars.py
A llvm/utils/lit/tests/Inputs/shtest-format/fail_with_bad_encoding.txt
A llvm/utils/lit/tests/Inputs/shtest-format/fail_with_control_chars.txt
A llvm/utils/lit/tests/Inputs/shtest-format/utf8_command.txt
A llvm/utils/lit/tests/Inputs/shtest-format/write-bad-encoding.py
A llvm/utils/lit/tests/Inputs/shtest-format/write-control-chars.py
M llvm/utils/lit/tests/shtest-format.py
Log Message:
-----------
[lit] Remove external shell tests for shtest-format
fail.txt was redundant with an internal shell test.
Move the other tests into the internal shell directory as they are not
redundant.
Reviewers: arichardson, jh7370, hnrklssn, ilovepi
Pull Request: https://github.com/llvm/llvm-project/pull/209552
Commit: bd1983e7ec9fef429787997684b48644dee583c4
https://github.com/llvm/llvm-project/commit/bd1983e7ec9fef429787997684b48644dee583c4
Author: AZero13 <gfunni234 at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/TableGen/TGParser.cpp
Log Message:
-----------
[TableGen] V is always a TypedInit, so use cast (#209208)
No need to dyn_cast. It is functionally impossible for V to not be a
TypedInit at this point.
Commit: 848d409e60845352cfce85c2a23d1d262a0c68f3
https://github.com/llvm/llvm-project/commit/848d409e60845352cfce85c2a23d1d262a0c68f3
Author: Sairudra More <sairudra60 at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
A flang/test/Integration/OpenMP/target-inreduction-llvmir.f90
A flang/test/Lower/OpenMP/Todo/target-inreduction-common.f90
A flang/test/Lower/OpenMP/Todo/target-inreduction-equivalence.f90
A flang/test/Lower/OpenMP/Todo/target-inreduction-firstprivate.f90
R flang/test/Lower/OpenMP/Todo/target-inreduction.f90
A flang/test/Lower/OpenMP/target-inreduction-unused.f90
A flang/test/Lower/OpenMP/target-inreduction.f90
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Dialect/OpenMP/host-op-filtering.mlir
M mlir/test/Dialect/OpenMP/invalid.mlir
A mlir/test/Target/LLVMIR/openmp-target-in-reduction-device.mlir
A mlir/test/Target/LLVMIR/openmp-target-in-reduction-multi.mlir
A mlir/test/Target/LLVMIR/openmp-target-in-reduction.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[flang][OpenMP] Lower target in_reduction (#199967)
This patch carries `in_reduction` through `omp.target` for host
execution.
The lowering looks up the task-reduction private storage with
`__kmpc_task_reduction_get_th_data` and binds the target region argument
to that private pointer. This makes uses inside the target region refer
to the task-private reduction storage instead of continuing to use the
original variable.
This also fixes the `omp::TargetOp::build(TargetOperands)` path so
`in_reduction` operands are preserved instead of being dropped.
On the Flang side, `target in_reduction` list items are added to the
target map entries when needed, giving the translation a matching mapped
value to rewrite.
### Stack / review order
This PR is related to the OpenMP task-reduction translation stack:
1. #199565 — `omp.taskgroup task_reduction` translation
2. #199670 — `omp.taskloop` `reduction` / `in_reduction` translation
3. #202611 — explicit `omp.task in_reduction` translation
This PR is a target-specific sibling follow-up:
* #199967 — `omp.target in_reduction` host lowering
The intended main review order for the task/taskloop stack is:
#199565 → #199670 → #202611
This PR should be reviewed as the `omp.target in_reduction` host-side
lowering work built on the same task-reduction runtime model, not as a
dependency of #202611.
Addresses #199904.
Assisted-by: Claude Opus 4.8 and ChatGPT 5.5
Commit: f859de88413c729166b08c00af5fcfe4f4b15b2d
https://github.com/llvm/llvm-project/commit/f859de88413c729166b08c00af5fcfe4f4b15b2d
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/lit.cfg.py
Log Message:
-----------
[LLVM] Use kwargs for ShTest constructor (#209676)
Since extra_substitutions is not the first argument (although it will be
soon).
Fixes https://lab.llvm.org/buildbot/#/builders/223/builds/7170.
This was broken by 3f46a5e91cdf2ade1d8ca350f4a57af8221407ea.
Commit: f8d8dc1f864fa887f949418a2ebb58e1a0d239b8
https://github.com/llvm/llvm-project/commit/f8d8dc1f864fa887f949418a2ebb58e1a0d239b8
Author: Wenju He <wenju.he at intel.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Support/raw_ostream.cpp
M llvm/unittests/Support/raw_ostream_test.cpp
Log Message:
-----------
[Support] Treat Windows "NUL" as the null device in writeToOutput (#208179)
llvm-objcopy (via writeToOutput) only special-cased "/dev/null", so on
Windows an output path of "NUL" fell through to TempFile::create() +
rename. Windows reserves "NUL" as a device name, so the rename fails
with "permission denied". This broke clang-offload-bundler's SYCL fat
object step when the driver is invoked with `-o nul` in downstream test
https://github.com/intel/llvm/blob/sycl/sycl/test/include_deps/header_reach.cpp
Assisted by: Claude
Commit: 11ebc0e6645c8c53c75bca93e9fddf0053507cc1
https://github.com/llvm/llvm-project/commit/11ebc0e6645c8c53c75bca93e9fddf0053507cc1
Author: Keshav Vinayak Jha <31160700+keshavvinayak01 at users.noreply.github.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
A llvm/test/CodeGen/AMDGPU/GlobalISel/merge-values-s16-true16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/select-merge-values-build-vector-s16.mir
Log Message:
-----------
[AMDGPU][GlobalISel] Select s16 G_MERGE_VALUES into wider scalars (#207999)
With real-true16 (default on `gfx11`/`gfx12`), a scalar `s16` is a
register type, so the `G_MERGE_VALUES` legality rule started accepting
scalar merges built from `s16` pieces, e.g. `s64 = G_MERGE_VALUES(4 x
s16)`. The instruction selector has no pattern for that shape. So this
aborts with `cannot select` on something like:
```mlir
define amdgpu_kernel void @k(ptr %p) {
store i136 0, ptr %p, align 8
ret void
}
```
Make it selectable rather than restricting legalization: Pack pairs of
`s16` with `S_PACK_LL_B32_B16` then `REG_SEQUENCE`.
Assisted-by: Claude
Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
Commit: 454a66a65c66012004b2e1e711247f5ebf729957
https://github.com/llvm/llvm-project/commit/454a66a65c66012004b2e1e711247f5ebf729957
Author: Vikram Hegde <Vikram.Hegde at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Target/TargetMachine.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
Log Message:
-----------
[CodeGen][NPM] Disable Machine verifier at the end of default pipelines (#208357)
keeping discussions in https://github.com/llvm/llvm-project/pull/176693.
Adds target option to disable machine verifier at the end of default
pilelines (O0,O1..). Also ref.
https://github.com/llvm/llvm-project/pull/201004 for discussions
regarding why this is required (temporarily atleast) so that NPM
migration is unblocked. should be removed once we have fixed all the
latent verifier issues.
Commit: 424421a80936e1d3cb824eecce51344acbc80253
https://github.com/llvm/llvm-project/commit/424421a80936e1d3cb824eecce51344acbc80253
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M orc-rt/include/CMakeLists.txt
M orc-rt/lib/executor/CMakeLists.txt
Log Message:
-----------
[orc-rt] Sort header and source lists in CMakeLists. NFC. (#209685)
Commit: 74822b4ee01f168f2d9a808594abb0c8936f5bbf
https://github.com/llvm/llvm-project/commit/74822b4ee01f168f2d9a808594abb0c8936f5bbf
Author: Weibo He <NewSigma at 163.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaType.cpp
M clang/test/SemaCXX/cxx2b-deducing-this.cpp
Log Message:
-----------
[clang][Sema] Fix rejected-valid for explicit object parameters in dependent nested classes context (#209107)
In #89078, we banned explicit object parameters from several invalid
contexts. This patch proposes we relax the restriction and allow
entering contexts so that nested classes can be visited correctly.
Close #136472
Commit: c4830afdbbc7b16a52a05d6a5b56e6c3fc14fb98
https://github.com/llvm/llvm-project/commit/c4830afdbbc7b16a52a05d6a5b56e6c3fc14fb98
Author: David Zbarsky <dzbarsky at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang-tools-extra/clangd/ConfigYAML.cpp
Log Message:
-----------
[clangd] Use unique_function for config handlers (#203008)
`ConfigYAML.cpp`'s `DictParser` owns its callbacks for one parse and
never copies them, so this replaces `std::function` with move-only
`llvm::unique_function` and removes the unused copy machinery for each
lambda.
In a matched Release AArch64 build, `ConfigYAML.cpp.o` shrank by 94,560
bytes, stripped clangd shrank by 16,848 bytes, unstripped clangd shrank
by 82,512 bytes, and dyld fixups fell by 336.
Validated with the 16 `ParseYAML` unit tests and `clangd --check`; 12
paired runs of 100,000 parses improved mean user CPU time by 3.46% (95%
CI: 1.31% to 5.61%).
Work towards #202616
AI tool disclosure: Co-authored with OpenAI Codex.
Commit: b570a7754d9b84af8ceffd8834194d559077cda5
https://github.com/llvm/llvm-project/commit/b570a7754d9b84af8ceffd8834194d559077cda5
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/socket/BUILD.bazel
Log Message:
-----------
[libc][bazel] Add recently added sys/socket functions and syscall wrappers (#209457)
This patch adds the missing functions to BUILD.bazel:
- recvmmsg
- sendmmsg
- setsockopt
- shutdown
I also add the corresponding syscall wrapper libraries that these
functions depend on, along with a couple of additional type libraries.
I'm leaving the remaining sys/socket functions and test suites out for
now since some of them require additional infrastructure or type
definitions.
Assisted by Gemini.
Commit: 36c6568b04aff4e1cf00a60570ab4a4344692920
https://github.com/llvm/llvm-project/commit/36c6568b04aff4e1cf00a60570ab4a4344692920
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M libc/src/__support/StringUtil/CMakeLists.txt
M libc/src/__support/StringUtil/signal_to_string.cpp
M libc/src/__support/StringUtil/tables/CMakeLists.txt
M libc/src/__support/StringUtil/tables/linux_extension_signals.h
M libc/src/__support/StringUtil/tables/posix_signals.h
M libc/src/__support/StringUtil/tables/stdc_signals.h
M libc/src/signal/kill.h
M libc/src/signal/linux/CMakeLists.txt
M libc/src/signal/linux/kill.cpp
M libc/src/signal/linux/sigemptyset.cpp
M libc/src/signal/raise.h
M libc/src/spawn/linux/CMakeLists.txt
M libc/src/spawn/linux/posix_spawn.cpp
M libc/src/sys/wait/linux/CMakeLists.txt
M libc/src/sys/wait/wait4Impl.h
M libc/src/unistd/linux/CMakeLists.txt
M libc/src/unistd/linux/fork.cpp
M libc/test/src/fenv/enabled_exceptions_test.cpp
M libc/test/src/signal/kill_test.cpp
M libc/test/src/signal/pthread_sigmask_test.cpp
M libc/test/src/signal/raise_test.cpp
M libc/test/src/signal/sigaddset_test.cpp
M libc/test/src/signal/sigdelset_test.cpp
M libc/test/src/signal/sigfillset_test.cpp
M libc/test/src/signal/signal_test.cpp
M libc/test/src/signal/sigprocmask_test.cpp
M libc/test/src/stdlib/abort_test.cpp
M libc/test/src/string/strsignal_test.cpp
M libc/test/src/sys/mman/linux/mprotect_test.cpp
Log Message:
-----------
[libc] Remove #include <signal.h> (#209433)
Replace it with granular includes of the appropriate type/macro proxy
headers.
Assisted by Gemini.
Commit: 7881a375884c3793d2fa7c31ab97781a43547f31
https://github.com/llvm/llvm-project/commit/7881a375884c3793d2fa7c31ab97781a43547f31
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/PackAndUnpackPatterns.cpp
M mlir/test/Dialect/Linalg/simplify-pack-unpack.mlir
Log Message:
-----------
[mlir][linalg] Refine pack/unpack simplification checks (NFC) (#209522)
Update `isPackOn1D`, which is used by both
`SimplifyPackToExpandShape` and `SimplifyUnPackToCollapseShape`:
* Rename it to `isPackOnEffectively1D` to better reflect its
functionality: the underlying pack can be multi-dimensional.
* Add checks to ensure that the unique non-unit inner tile is used to
tile the unique non-unit unpacked dimension (that was previously
left as an unchecked assumption).
* Add comments to the test file for these patterns, grouping the tests
according to the functionality/cases being tested.
Commit: 89fa7352a2cfd5ec498ba442de77d257475954f2
https://github.com/llvm/llvm-project/commit/89fa7352a2cfd5ec498ba442de77d257475954f2
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/arpa/inet.yaml
M libc/src/arpa/inet/CMakeLists.txt
A libc/src/arpa/inet/inet_ntoa.cpp
A libc/src/arpa/inet/inet_ntoa.h
M libc/test/src/arpa/inet/CMakeLists.txt
A libc/test/src/arpa/inet/inet_ntoa_test.cpp
Log Message:
-----------
[libc] Implement inet_ntoa (#208702)
Implement inet_ntoa, reusing the internal net::ipv4_to_str helper that
backs inet_ntop.
The result is stored in a *thread-local* static buffer. A thread-local
buffer is not required for POSIX conformance, but there is some
precedent for that, both in llvm libc (e.g. `strsignal`) and in glibc
(whose `inet_ntoa` uses it). I'm doing the same for maximum
compatiblity.
Assisted by Gemini.
Commit: 69e0994c93bc56f96e5f0ef83fdd0121a829c9d0
https://github.com/llvm/llvm-project/commit/69e0994c93bc56f96e5f0ef83fdd0121a829c9d0
Author: Wendi <uwendi at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/docs/QualGroup.rst
Log Message:
-----------
[Docs] Document Qualification WG artifacts and meeting archive (#209382)
# Summary
Update the LLVM Qualification Working Group page to point readers to the
group's directory in the `llvm-wgs` repository.
The new **Working Group artifacts** section explains that the directory
is the central location for the group's public technical outputs and
working materials, including qualification guidance, templates,
analyses, and proposals.
The **Meeting Materials** section is also updated to reflect the
migration of meeting materials, agendas, and minutes to the `llvm-wgs`
repository. The repository is presented as the long-term archive, while
the existing Discourse thread remains the location where upcoming
agendas and newly published minutes are shared.
# Changes
- Add a link to the Qualification Working Group's `fusa-qual-wg`
directory.
- Explain the purpose and maturity of the artifacts stored there.
- Link directly to the meeting materials and meeting minutes
directories.
- Add a link to the repository-based meeting archive.
- Retain the Discourse thread as the communication channel for agendas
and minutes.
# Related repository
https://github.com/llvm/llvm-wgs/tree/main/fusa-qual-wg
Commit: bff9c544bd87087d1e13a7b1c6298aa9e21a313c
https://github.com/llvm/llvm-project/commit/bff9c544bd87087d1e13a7b1c6298aa9e21a313c
Author: Sam Elliott <aelliott at qti.qualcomm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
M llvm/test/MC/RISCV/corev/XCValu-invalid.s
M llvm/test/MC/RISCV/corev/XCVbi-invalid.s
M llvm/test/MC/RISCV/corev/XCVbitmanip-invalid.s
M llvm/test/MC/RISCV/corev/XCVelw-invalid.s
M llvm/test/MC/RISCV/corev/XCVmac-invalid.s
M llvm/test/MC/RISCV/corev/XCVmem-invalid.s
M llvm/test/MC/RISCV/corev/XCVsimd-invalid.s
M llvm/test/MC/RISCV/function-call-invalid.s
M llvm/test/MC/RISCV/priv-invalid.s
M llvm/test/MC/RISCV/rv32d-invalid.s
M llvm/test/MC/RISCV/rv32f-invalid.s
M llvm/test/MC/RISCV/rv32i-aliases-invalid.s
M llvm/test/MC/RISCV/rv32i-invalid.s
M llvm/test/MC/RISCV/rv32q-invalid.s
M llvm/test/MC/RISCV/rv32xqccmp-invalid.s
M llvm/test/MC/RISCV/rv32zcmp-invalid.s
M llvm/test/MC/RISCV/rv32zdinx-invalid.s
M llvm/test/MC/RISCV/rv32zfh-invalid.s
M llvm/test/MC/RISCV/rv32zhinx-invalid.s
M llvm/test/MC/RISCV/rv64d-invalid.s
M llvm/test/MC/RISCV/rv64f-invalid.s
M llvm/test/MC/RISCV/rv64i-aliases-invalid.s
M llvm/test/MC/RISCV/rv64q-invalid.s
M llvm/test/MC/RISCV/rv64xqccmp-invalid.s
M llvm/test/MC/RISCV/rv64xtheadfmemidx-invalid.s
M llvm/test/MC/RISCV/rv64xtheadmemidx-invalid.s
M llvm/test/MC/RISCV/rv64zcmp-invalid.s
M llvm/test/MC/RISCV/rv64zdinx-invalid.s
M llvm/test/MC/RISCV/rv64zfh-invalid.s
M llvm/test/MC/RISCV/rv64zfinx-invalid.s
M llvm/test/MC/RISCV/rv64zhinx-invalid.s
M llvm/test/MC/RISCV/rve-invalid.s
M llvm/test/MC/RISCV/rvzfbfmin-invalid.s
M llvm/test/MC/RISCV/rvzfhmin-invalid.s
M llvm/test/MC/RISCV/rvzicond-invalid.s
M llvm/test/MC/RISCV/tlsdesc.s
M llvm/test/MC/RISCV/xmips-invalid.s
M llvm/test/MC/RISCV/xqcibm-invalid.s
M llvm/test/MC/RISCV/xqcili-invalid.s
M llvm/test/MC/RISCV/xqcilo-invalid.s
M llvm/test/MC/RISCV/xqcisim-invalid.s
M llvm/test/MC/RISCV/xqcisls-invalid.s
M llvm/test/MC/RISCV/xtheadcondmov-invalid.s
M llvm/test/MC/RISCV/xtheadmac-invalid.s
Log Message:
-----------
[RISCV][MC] Improve GPR Error Messages (#209669)
- For the usual GPR RegClass
- For the GPRX0 RegClass as used by the `PseudoC_ADDI_NOP` instruction.
- For the SR07 regclass used by Zcmp and Xqccmp instructions.
Commit: 2d6692d577cfee5af4d96a0759a14b55ee58b6e1
https://github.com/llvm/llvm-project/commit/2d6692d577cfee5af4d96a0759a14b55ee58b6e1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/si-scheduler.ll
M llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll
M llvm/test/CodeGen/AMDGPU/si-spill-cf.ll
M llvm/test/CodeGen/AMDGPU/si-split-load-store-alias-info.ll
M llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
M llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
M llvm/test/CodeGen/AMDGPU/si-unify-exit-return-unreachable.ll
M llvm/test/CodeGen/AMDGPU/si-vector-hang.ll
M llvm/test/CodeGen/AMDGPU/sibling-call.ll
M llvm/test/CodeGen/AMDGPU/sign_extend.ll
M llvm/test/CodeGen/AMDGPU/siloadstoreopt-misaligned-regsequence.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call-2.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/simplify-libcall-nobuiltin-def.ll
M llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll
M llvm/test/CodeGen/AMDGPU/simplify-libcalls2.ll
M llvm/test/CodeGen/AMDGPU/simulated-trap-pseudo-expand.ll
M llvm/test/CodeGen/AMDGPU/sink-addr-memory-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/sink-after-control-flow-postra.mir
M llvm/test/CodeGen/AMDGPU/sink-after-control-flow.mir
M llvm/test/CodeGen/AMDGPU/sink-image-sample.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/skip-fold-regsequence.mir
M llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
M llvm/test/CodeGen/AMDGPU/skip-promote-alloca-vector-users.ll
M llvm/test/CodeGen/AMDGPU/smed3.ll
M llvm/test/CodeGen/AMDGPU/smem-no-clause-coalesced.mir
M llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir
M llvm/test/CodeGen/AMDGPU/smfmac_alloc_failure_no_agpr_O0.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/sminmax.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/smrd-fold-offset.mir
M llvm/test/CodeGen/AMDGPU/smrd-gfx10.ll
M llvm/test/CodeGen/AMDGPU/smrd-vccz-bug.ll
M llvm/test/CodeGen/AMDGPU/smrd.ll
M llvm/test/CodeGen/AMDGPU/smrd_vmem_war.ll
M llvm/test/CodeGen/AMDGPU/snippet-copy-bundle-regression.mir
M llvm/test/CodeGen/AMDGPU/soft-clause-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/soft-clause-exceeds-register-budget.ll
M llvm/test/CodeGen/AMDGPU/sopk-compares.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/speculative-execution-freecasts.ll
M llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
M llvm/test/CodeGen/AMDGPU/spill-agpr.ll
M llvm/test/CodeGen/AMDGPU/spill-agpr.mir
M llvm/test/CodeGen/AMDGPU/spill-alloc-sgpr-init-bug.ll
M llvm/test/CodeGen/AMDGPU/spill-cfg-position.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
M llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
M llvm/test/CodeGen/AMDGPU/spill-regpressure-less.mir
M llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/spill-sgpr-stack-no-sgpr.ll
M llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir
M llvm/test/CodeGen/AMDGPU/spill-sgpr-used-for-exec-copy.mir
M llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
M llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr-update-regscavenger.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr.ll
M llvm/test/CodeGen/AMDGPU/spill-wait.mir
M llvm/test/CodeGen/AMDGPU/spill-wide-sgpr.ll
M llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
M llvm/test/CodeGen/AMDGPU/spill192.mir
M llvm/test/CodeGen/AMDGPU/spill224.mir
M llvm/test/CodeGen/AMDGPU/spill288.mir
M llvm/test/CodeGen/AMDGPU/spill320.mir
M llvm/test/CodeGen/AMDGPU/spill352.mir
M llvm/test/CodeGen/AMDGPU/spill384.mir
M llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir
M llvm/test/CodeGen/AMDGPU/spillv16.ll
M llvm/test/CodeGen/AMDGPU/spillv16.mir
M llvm/test/CodeGen/AMDGPU/spillv16Kernel.ll
M llvm/test/CodeGen/AMDGPU/spillv16Kernel.mir
M llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll
M llvm/test/CodeGen/AMDGPU/split-liverange-overlapping-copies.mir
M llvm/test/CodeGen/AMDGPU/split-mbb-lis-subrange.mir
M llvm/test/CodeGen/AMDGPU/split-smrd.ll
M llvm/test/CodeGen/AMDGPU/split-vector-memoperand-offsets.ll
M llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
M llvm/test/CodeGen/AMDGPU/splitkit-do-not-undo-subclass-split-with-remat.mir
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
M llvm/test/CodeGen/AMDGPU/splitkit.mir
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/sram-ecc-default.ll
M llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-any.ll
M llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-disabled.ll
M llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-enabled.ll
M llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/srl-bitcast-bv.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (33) (#209562)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 162a2767d624684869d710f25096b882a32109bc
https://github.com/llvm/llvm-project/commit/162a2767d624684869d710f25096b882a32109bc
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper.c
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M llvm/include/llvm/Object/OffloadBinary.h
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/lib/Object/OffloadBinary.cpp
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
clang-linker-wrapper: Use AMDGPU::TargetID for image compatibilty (2) (#209563)
This reverts commit aa5960600ac38fcd923e69777bad1293f56658d7.
Before the first attempt, clang-linker-wrapper inconsistently
applied linker reasoning to the target ID feature modifiers, but
not the base processor. e.g., gfx90a was considered mergable
with gfx90a:xnack+.
The first attempt at this changed introduced and used
TargetID::isCompatibleWith, which applied full linking
compatibility logic. This broke tests which combined
generic and covered non-generic targets in the build (e.g.,
gfx9-generic and gfx900). The archives would both be treated
as compatible, resulting in multiple definition errors.
Split the TargetID compatibility checks into 2 different kinds:
1 for exact target match used for archives, and 1 for logical
compatibility usable for objects. For archive purposes, this stops
treating xnack-any as the same target with an xnack specifier which
is a behavior change. It just so happens that clang would error if you
tried to compile xnack-any and xnack+/- in the same invocation, so this
behavior was only observable when directly using the binary tools.
Co-authored-by: Claude (Opus 4.8)
Commit: b790c5cd267974456806773f01dfb8936b22e4f2
https://github.com/llvm/llvm-project/commit/b790c5cd267974456806773f01dfb8936b22e4f2
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M libc/src/__support/File/linux/CMakeLists.txt
M libc/src/__support/File/linux/file.cpp
M libc/src/pthread/CMakeLists.txt
M libc/src/pthread/pthread_condattr_getclock.cpp
M libc/src/pthread/pthread_condattr_getclock.h
M libc/src/pthread/pthread_condattr_setclock.cpp
M libc/src/pthread/pthread_condattr_setclock.h
M libc/src/sys/prctl/linux/CMakeLists.txt
M libc/src/sys/prctl/prctl.h
M libc/src/sys/random/getrandom.h
M libc/src/sys/random/linux/CMakeLists.txt
M libc/src/sys/resource/getrlimit.h
M libc/src/sys/resource/linux/CMakeLists.txt
M libc/src/sys/resource/setrlimit.h
M libc/src/sys/sendfile/linux/CMakeLists.txt
M libc/src/sys/sendfile/linux/sendfile.cpp
M libc/src/sys/sendfile/sendfile.h
M libc/src/sys/socket/linux/CMakeLists.txt
M libc/src/sys/socket/recv.h
M libc/src/sys/socket/send.h
M libc/src/sys/wait/linux/CMakeLists.txt
M libc/src/sys/wait/wait.h
M libc/src/sys/wait/waitpid.h
M libc/src/unistd/linux/CMakeLists.txt
M libc/src/unistd/linux/isatty.cpp
M libc/startup/linux/CMakeLists.txt
M libc/startup/linux/do_start.cpp
M libc/test/integration/src/sys/ptrace/linux/ptrace_test.cpp
M libc/test/src/fcntl/CMakeLists.txt
M libc/test/src/fcntl/creat_test.cpp
M libc/test/src/fcntl/fcntl_test.cpp
M libc/test/src/stdio/CMakeLists.txt
M libc/test/src/stdio/fdopen_test.cpp
M libc/test/src/string/memory_utils/protected_pages.h
M libc/test/src/sys/auxv/linux/CMakeLists.txt
M libc/test/src/sys/auxv/linux/getauxval_test.cpp
M libc/test/src/sys/mman/linux/CMakeLists.txt
M libc/test/src/sys/mman/linux/mlock_test.cpp
M libc/test/src/sys/mman/linux/mprotect_test.cpp
M libc/test/src/sys/mman/linux/posix_madvise_test.cpp
M libc/test/src/sys/mman/linux/remap_file_pages_test.cpp
M libc/test/src/sys/resource/CMakeLists.txt
M libc/test/src/sys/resource/getrlimit_setrlimit_test.cpp
M libc/test/src/sys/sendfile/CMakeLists.txt
M libc/test/src/sys/sendfile/sendfile_test.cpp
M libc/test/src/sys/socket/linux/CMakeLists.txt
M libc/test/src/sys/socket/linux/sendto_recvfrom_test.cpp
M libc/test/src/sys/socket/linux/socket_test.cpp
M libc/test/src/sys/socket/linux/socketopt_test.cpp
M libc/test/src/sys/socket/linux/socketpair_test.cpp
M libc/test/src/sys/stat/CMakeLists.txt
M libc/test/src/sys/stat/chmod_test.cpp
M libc/test/src/sys/stat/fchmod_test.cpp
M libc/test/src/sys/stat/fchmodat_test.cpp
M libc/test/src/sys/stat/fstat_test.cpp
M libc/test/src/sys/stat/lstat_test.cpp
M libc/test/src/sys/stat/stat_test.cpp
M libc/test/src/unistd/CMakeLists.txt
M libc/test/src/unistd/access_test.cpp
M libc/test/src/unistd/chown_test.cpp
M libc/test/src/unistd/dup2_test.cpp
M libc/test/src/unistd/dup3_test.cpp
M libc/test/src/unistd/dup_test.cpp
M libc/test/src/unistd/faccessat_test.cpp
M libc/test/src/unistd/fchown_test.cpp
M libc/test/src/unistd/ftruncate_test.cpp
M libc/test/src/unistd/isatty_test.cpp
M libc/test/src/unistd/link_test.cpp
M libc/test/src/unistd/linkat_test.cpp
M libc/test/src/unistd/pread_pwrite_test.cpp
M libc/test/src/unistd/read_write_test.cpp
M libc/test/src/unistd/symlink_test.cpp
M libc/test/src/unistd/symlinkat_test.cpp
M libc/test/src/unistd/syscall_test.cpp
M libc/test/src/unistd/truncate_test.cpp
M libc/test/src/unistd/unlink_test.cpp
M libc/test/src/unistd/unlinkat_test.cpp
Log Message:
-----------
[libc] Remove #include <sys/whatever.h> (#209449)
and replace with granular includes of type/macro proxy headers -- where
those headers exist. I'm leaving the creation of new proxy headers for
another patch.
Assisted by Gemini.
Commit: 15776b5cddd4bfd8ff06f2aac6e9eea09cf0112c
https://github.com/llvm/llvm-project/commit/15776b5cddd4bfd8ff06f2aac6e9eea09cf0112c
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/ADT/GenericCycleImpl.h
M llvm/include/llvm/ADT/GenericCycleInfo.h
Log Message:
-----------
[CycleInfo] Remove GenericCycle::TopLevelCycle. NFC (#209677)
moveTopLevelCycleToNewParent maintains TopLevelCycle eagerly, rewriting
the whole re-parented subtree with depth_first. When discovery nests k
cycles one by one this is quadratic, and the df_iterator walk plus its
visited set dominate construction on deep nests (~78% of time on a
1500-deep nest).
Walk ParentCycle links in getTopLevelParentCycle instead and delete the
member. The walk is valid during construction too: parent links are
always current, and discovery queries blocks whose innermost cycle sits
at the top of the forest being merged, so the walk is short.
Aided by Claude Fable 5
Commit: af84127cbfc571f86cf7c9ac344223e190bb9970
https://github.com/llvm/llvm-project/commit/af84127cbfc571f86cf7c9ac344223e190bb9970
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
Log Message:
-----------
[SPIR-V] Remove dead typed pointer check in getArgSPIRVType (#209515)
Arg->getType() can never be a TypedPointerType since opaque pointers are
now the only pointer representation in LLVM IR
Commit: b78a0acaa964804151dd3a25eaec360baacfd631
https://github.com/llvm/llvm-project/commit/b78a0acaa964804151dd3a25eaec360baacfd631
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
Log Message:
-----------
[SPIR-V] Unify duplicated named MDNode lookup helper (#209376)
Commit: 771d152cd10a05a10023beb0ff289ea1180b1751
https://github.com/llvm/llvm-project/commit/771d152cd10a05a10023beb0ff289ea1180b1751
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
M llvm/test/CodeGen/SPIRV/passes/SPIRVLegalizePointerCast.ll
Log Message:
-----------
[SPIR-V] Preserve offset alignment in pointer cast legalization (#209251)
Splitting a load/store into per-element accesses reused the original
alignment for every element, which could wrongly strengthen or discard
alignment
Compute each split access alignment via commonAlignment with its
DataLayout derived byte offset matching SPIRVLegalizerInfo.cpp
Commit: 046acff1018f034e2a5d714c7287b9055148d1c7
https://github.com/llvm/llvm-project/commit/046acff1018f034e2a5d714c7287b9055148d1c7
Author: SiHuaN <liyongtai at iscas.ac.cn>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsRISCV.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
Log Message:
-----------
[RISCV][P-ext] Add packed saturating rounding shift codegen (#208630)
Add codegen for `pssha`, `psshar`, `psshl`, and `psshlr` on RV32 and
RV64.
Commit: 396a2d700bba0f9d4ac97198921beb7413e5ce5c
https://github.com/llvm/llvm-project/commit/396a2d700bba0f9d4ac97198921beb7413e5ce5c
Author: SiHuaN <liyongtai at iscas.ac.cn>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/CodeGen/RISCV/rvp-insert-subvector.ll
Log Message:
-----------
[RISCV][P-ext] Fold packed insert-into-zero to zero-extend (#208006)
An insert_subvector of a 32-bit packed type (v4i8/v2i16) into a zero-filled
64-bit packed vector at index 0 is a zero-extend. Fold it so RV64 emits a
single zext.w instead of scalarizing into a byte-wise repack; RV32
concatenates with a zero half into the GPRPair.
Commit: bdd15ffec5f1e14962f86cbdb82a03016c2c5924
https://github.com/llvm/llvm-project/commit/bdd15ffec5f1e14962f86cbdb82a03016c2c5924
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/SRSRC-GIT-clobber-check.mir
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/srl64_reduce.ll
M llvm/test/CodeGen/AMDGPU/srl64_reduce_flags.ll
M llvm/test/CodeGen/AMDGPU/sroa-before-unroll.ll
M llvm/test/CodeGen/AMDGPU/sroa-phi-nodes.ll
M llvm/test/CodeGen/AMDGPU/ssubo.ll
M llvm/test/CodeGen/AMDGPU/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/stack-passed-subdword-arg-crash-issue157997.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll
M llvm/test/CodeGen/AMDGPU/stack-realign.ll
M llvm/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
M llvm/test/CodeGen/AMDGPU/stackguard.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.invalid.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/stale-livevar-in-twoaddr-pass.mir
M llvm/test/CodeGen/AMDGPU/statepoint-asm-printer.mir
M llvm/test/CodeGen/AMDGPU/statepoint-insert-waitcnts.mir
M llvm/test/CodeGen/AMDGPU/store-atomic-flat.ll
M llvm/test/CodeGen/AMDGPU/store-atomic-global.ll
M llvm/test/CodeGen/AMDGPU/store-atomic-local.ll
M llvm/test/CodeGen/AMDGPU/store-barrier.ll
M llvm/test/CodeGen/AMDGPU/store-clobbers-load.ll
M llvm/test/CodeGen/AMDGPU/store-global.ll
M llvm/test/CodeGen/AMDGPU/store-hi16.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/store-local.ll
M llvm/test/CodeGen/AMDGPU/store-private.ll
M llvm/test/CodeGen/AMDGPU/store-to-constant.ll
M llvm/test/CodeGen/AMDGPU/store-v3i64.ll
M llvm/test/CodeGen/AMDGPU/store-vector-ptrs.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/stress-calls.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fma.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fma.f64.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f64.ll
M llvm/test/CodeGen/AMDGPU/strict_fpext.ll
M llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f64.ll
M llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll
M llvm/test/CodeGen/AMDGPU/structurize-hoist.ll
M llvm/test/CodeGen/AMDGPU/sub-zext-cc-zext-cc.ll
M llvm/test/CodeGen/AMDGPU/sub.i16.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/sub64-low-32-bits-known-zero.ll
M llvm/test/CodeGen/AMDGPU/sub_i1.ll
M llvm/test/CodeGen/AMDGPU/sub_u64.ll
M llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
M llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
M llvm/test/CodeGen/AMDGPU/subreg-eliminate-dead.ll
M llvm/test/CodeGen/AMDGPU/subreg-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir
M llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
M llvm/test/CodeGen/AMDGPU/subvector-test.mir
M llvm/test/CodeGen/AMDGPU/swdev-549940.ll
M llvm/test/CodeGen/AMDGPU/swdev282079.ll
M llvm/test/CodeGen/AMDGPU/swdev282079.mir
M llvm/test/CodeGen/AMDGPU/swdev373493.ll
M llvm/test/CodeGen/AMDGPU/swdev380865.ll
M llvm/test/CodeGen/AMDGPU/swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir
M llvm/test/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll
M llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll
M llvm/test/CodeGen/AMDGPU/switch-default-block-unreachable.ll
M llvm/test/CodeGen/AMDGPU/switch-unreachable.ll
M llvm/test/CodeGen/AMDGPU/swizzle.bit.extract.ll
M llvm/test/CodeGen/AMDGPU/syncscopes.ll
M llvm/test/CodeGen/AMDGPU/tail-call-amdgpu-gfx.ll
M llvm/test/CodeGen/AMDGPU/tail-call-cgp.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.waterfall.ll
M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.ll
M llvm/test/CodeGen/AMDGPU/tail-duplication-convergent.ll
M llvm/test/CodeGen/AMDGPU/target-mem-intrinsic-metadata.ll
M llvm/test/CodeGen/AMDGPU/tgsplit.ll
M llvm/test/CodeGen/AMDGPU/threeaddr-wmma.mir
M llvm/test/CodeGen/AMDGPU/tid-kd-xnack-any.ll
M llvm/test/CodeGen/AMDGPU/tid-kd-xnack-off.ll
M llvm/test/CodeGen/AMDGPU/tid-kd-xnack-on.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (34) (#209598)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping
the redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 2af345af8dbffa975589b5f774ab006f372b4c00
https://github.com/llvm/llvm-project/commit/2af345af8dbffa975589b5f774ab006f372b4c00
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lldb/include/lldb/Target/MemoryRegionInfo.h
M lldb/source/Plugins/Process/Utility/LinuxProcMaps.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
M lldb/unittests/Process/Utility/LinuxProcMapsTest.cpp
Log Message:
-----------
[lldb-server] Add type info for qMemoryinfo reponse (#209235)
Use the name of the memory region to report the known cases where an
address points to stack/heap: "[stack]" or "[heap"].
According to [1], the "[stack]" name is the main thread's stack region:
```
[stack]
The initial process's (also known as the main
thread's) stack.
```
For other threads, we can't know their stack region because this field
got removed in newer kernels:
```
[stack:tid] (from Linux 3.4 to Linux 4.4)
A thread's stack (where the tid is a thread ID). It
corresponds to the /proc/pid/task/tid/ path. This
field was removed in Linux 4.5, since providing this
information for a process with large numbers of
threads is expensive.
```
So we can only set "isStack" to Yes in some cases, and to "No" when the
name is "[heap]". If there is no name, or the name is something else, we
keep the "don't know" answer.
[1]: https://man7.org/linux/man-pages/man5/proc_pid_maps.5.html
Commit: 06bf4bfff830207da473c06f2d90f93d777b51bb
https://github.com/llvm/llvm-project/commit/06bf4bfff830207da473c06f2d90f93d777b51bb
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll
Log Message:
-----------
[X86] combineINSERT_SUBVECTOR - enable shuffle combining of concat(extractsub(shuffle),extractsub(shuffle)) patterns (#209510)
Reuse the peekThroughBitcastsAndExtracts helper that we already use for insertsub(shuffle,extractsub(shuffle)) patterns
Commit: 13bdd50540a5365f5f25b0fff7410d5d69157a51
https://github.com/llvm/llvm-project/commit/13bdd50540a5365f5f25b0fff7410d5d69157a51
Author: Harry Ramsey <harry.ramsey at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/scalable_masked_interleaved_stores.ll
Log Message:
-----------
[AArch64][ISel] Enable masked interleaved stores for splat values (#207950)
Enable masked interleaved store combine to recognise splat values and
split them into SVE component vectors. This allows the existing stN
lowering path to handle masked stores where the stored value is a splat
rather than an explicit vector.interleave result.
Commit: 67dabeefa6271d638f548a68b20ffdc8d457e312
https://github.com/llvm/llvm-project/commit/67dabeefa6271d638f548a68b20ffdc8d457e312
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/cxx11.cpp
Log Message:
-----------
[clang][bytecode] Fix "declared here" location of ... (#209696)
... "read outside its lifetime" diagnostics.
We should be pointing to the first decl.
Commit: 0d33149259ab717d48d8e34b6cb6eae87c28e631
https://github.com/llvm/llvm-project/commit/0d33149259ab717d48d8e34b6cb6eae87c28e631
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/sroa-phi-nodes.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-invalid-any-off-on.ll
M llvm/test/CodeGen/AMDGPU/tied-op-for-wwm-scratch-reg-spill-restore.mir
M llvm/test/CodeGen/AMDGPU/token-factor-inline-limit-test.ll
M llvm/test/CodeGen/AMDGPU/track-spilled-vgpr-liveness.mir
M llvm/test/CodeGen/AMDGPU/trans-coexecution-hazard.mir
M llvm/test/CodeGen/AMDGPU/trans-forwarding-hazards.mir
M llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll
M llvm/test/CodeGen/AMDGPU/trap-abis.ll
M llvm/test/CodeGen/AMDGPU/triton_regression_no_waterfall.ll
M llvm/test/CodeGen/AMDGPU/triton_regression_no_waterfall.mir
M llvm/test/CodeGen/AMDGPU/triv-disjoint-mem-access-neg-offset.mir
M llvm/test/CodeGen/AMDGPU/true16-fold.mir
M llvm/test/CodeGen/AMDGPU/true16-imm-folded-to-0-regression.ll
M llvm/test/CodeGen/AMDGPU/true16-ra-pre-gfx11-regression-test.mir
M llvm/test/CodeGen/AMDGPU/true16-saveexec.mir
M llvm/test/CodeGen/AMDGPU/trunc-bitcast-vector.ll
M llvm/test/CodeGen/AMDGPU/trunc-cmp-constant.ll
M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-i1.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-i64.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-vec-i16-to-i8.ll
M llvm/test/CodeGen/AMDGPU/trunc-store.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/truncate-lshr-cast-build-vector-combine.ll
M llvm/test/CodeGen/AMDGPU/tti-unroll-prefs.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-bundle.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-fma-f64.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-fma.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-mad.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-wmma.mir
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/udivrem24.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/umed3.ll
M llvm/test/CodeGen/AMDGPU/umin-sub-to-usubo-select-combine.ll
M llvm/test/CodeGen/AMDGPU/unaligned-buffer.ll
M llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll
M llvm/test/CodeGen/AMDGPU/unallocatable-bundle-regression.mir
M llvm/test/CodeGen/AMDGPU/undef-build-vector.ll
M llvm/test/CodeGen/AMDGPU/undef-copy-propagation.mir
M llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll
M llvm/test/CodeGen/AMDGPU/undef-subreg-use-after-coalesce.mir
M llvm/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/unexpected-reg-unit-state.mir
M llvm/test/CodeGen/AMDGPU/unfold-masked-merge-scalar-variablemask.ll
M llvm/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll
M llvm/test/CodeGen/AMDGPU/uniform-alignbit.ll
M llvm/test/CodeGen/AMDGPU/uniform-branch-intrinsic-cond.ll
M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
M llvm/test/CodeGen/AMDGPU/uniform-crash.ll
M llvm/test/CodeGen/AMDGPU/uniform-intrin-combine-wqm-demote.ll
M llvm/test/CodeGen/AMDGPU/uniform-load-from-tid.ll
M llvm/test/CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll
M llvm/test/CodeGen/AMDGPU/uniform-phi-with-undef.ll
M llvm/test/CodeGen/AMDGPU/uniform-select.ll
M llvm/test/CodeGen/AMDGPU/uniform-vgpr-to-sgpr-return.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-attribute-missing.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-multistep.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-nested-function-calls.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-prevent-attribute-propagation.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-propagate-attribute.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-recursion-test.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-test.ll
M llvm/test/CodeGen/AMDGPU/uniform_branch_with_floating_point_cond.ll
M llvm/test/CodeGen/AMDGPU/unnamed-function-resource-info.ll
M llvm/test/CodeGen/AMDGPU/unpack-half.ll
M llvm/test/CodeGen/AMDGPU/unroll.ll
M llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/unsupported-atomics.ll
M llvm/test/CodeGen/AMDGPU/unsupported-av-load.ll
M llvm/test/CodeGen/AMDGPU/unsupported-av-store.ll
M llvm/test/CodeGen/AMDGPU/unsupported-calling-conv-call.ll
M llvm/test/CodeGen/AMDGPU/unsupported-calling-conv-func.ll
M llvm/test/CodeGen/AMDGPU/unsupported-code-object-version.ll
M llvm/test/CodeGen/AMDGPU/unsupported-cs-chain.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-a16.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-g16.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-sample.ll
M llvm/test/CodeGen/AMDGPU/update-lds-alignment.ll
M llvm/test/CodeGen/AMDGPU/update-phi.ll
M llvm/test/CodeGen/AMDGPU/urem.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/use_restore_frame_reg.mir
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (35) (#209599)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping
the redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: ba9f8e448ecd6f99664ed6b15c8d193650197845
https://github.com/llvm/llvm-project/commit/ba9f8e448ecd6f99664ed6b15c8d193650197845
Author: Balázs Kéri <balazs.keri at ericsson.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/UndefinedAssignmentChecker.cpp
M clang/test/Analysis/operator-calls.cpp
Log Message:
-----------
[clang][analyzer] Improved message in uninitialized.Assign at default assignment (#208173)
Commit: 1a0ddbdff9eef0257445778f36dd19b74f018487
https://github.com/llvm/llvm-project/commit/1a0ddbdff9eef0257445778f36dd19b74f018487
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/Combiner.h
M llvm/lib/CodeGen/GlobalISel/Combiner.cpp
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
M llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
Log Message:
-----------
[GlobalISel] Filter combiner worklists (#197693)
This follows on from #196017 which added an opcode predicate for GICombiner
matchers and used it to return from tryCombineAll before executing the match
table.
The better approach is to not add opcodes with no combines to the worklist in
the first place. This is a further -0.35% CTMark geomean improvement on
aarch64-O0-g, sqlite is -0.67%.
https://llvm-compile-time-tracker.com/compare.php?from=35f5d7ea802eae78b26a5fb2a46f072acd15f49d&to=c356bec46b68b59f37b26347f93676c9102d810c&stat=instructions%3Au
I also measured O3 locally and it's positive:
```
stage1-aarch64-O3 -fglobal-isel
instructions:u diff
old new
7zip 203863583445 203865335443 0.00%
Bullet 103920943623 103917036315 -0.00%
ClamAV 53008970261 52971646424 -0.07%
SPASS 41843361245 41815471487 -0.07%
consumer-typeset 31848080935 31816255572 -0.10%
kimwitu++ 39779892082 39733563964 -0.12%
lencod 67158153709 67134337444 -0.04%
mafft 36689364945 36675438948 -0.04%
sqlite3 33436727535 33410098701 -0.08%
tramp3d-v4 76553056559 76569825676 0.02%
geomean 57208304686 57180409869 -0.05%
```
I am a bit worried about the incurred overhead of this for other opt levels as
we add more combines, but right now at least the data is positive.
Assisted-by: codex
Commit: 3e4160fdc3d5bb0ed86480604bdfcd3130e7dd37
https://github.com/llvm/llvm-project/commit/3e4160fdc3d5bb0ed86480604bdfcd3130e7dd37
Author: Krisitan Erik Olsen <kristian.erik at outlook.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86LowerTileCopy.cpp
A llvm/test/CodeGen/X86/AMX/pr209512.ll
Log Message:
-----------
[X86] Skip debug instructions in tile copy lowering (#209640)
X86LowerTileCopy iterates over instructions in reverse to track live
registers, calling LiveRegUnits::stepBackward on every instruction
unconditionally. Since commit 16b2ef32 added an assertion that
stepBackward must not receive debug instructions, functions containing
debug info hit the assertion during tile copy lowering.
This patch skips debug instructions early in the loop, matching the
guard pattern used in RegisterScavenging.cpp and X86FixupBWInsts.cpp.
Fixes #209512
Commit: 0e877fd1a637ec2964883d324600211a6907b7bd
https://github.com/llvm/llvm-project/commit/0e877fd1a637ec2964883d324600211a6907b7bd
Author: Kito Cheng <kito.cheng at sifive.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/test/CodeGenOpenCL/builtins-f16.cl
M llvm/lib/Target/README.txt
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/test/Transforms/InstCombine/AMDGPU/tan.ll
M llvm/test/Transforms/InstCombine/fdiv-cos-sin.ll
M llvm/test/Transforms/InstCombine/fdiv-sin-cos.ll
M llvm/test/Transforms/InstCombine/may-alias-errno.ll
A llvm/test/Transforms/InstCombine/sincos-fpmath.ll
A llvm/test/Transforms/InstCombine/sincos.ll
Log Message:
-----------
Reland "[InstCombine] Combine llvm.sin/llvm.cos libcall pairs into llvm.sincos" (#194616)
This reland #184760
Fixed https://lab.llvm.org/buildbot/#/builders/123/builds/39337
The root cause is new created llvm.sincos is inserted into the right
after of the sin/cos's argument, however we didn't check if it's PHI, it
may cause it inserted into the middle of PHIs, and then fail the
verification.
Teach InstCombine to recognize pairs of `llvm.sin(x)` and `llvm.cos(x)`
intrinsic calls that share the same argument and replace them with a
single `llvm.sincos(x)` call, extracting the individual results.
The optimization works in two phases:
1. **SimplifyLibCalls**: Convert `sin`/`cos` C library calls (e.g.
`sinf`, `cosf`, `sin`, `cos`, `sinl`, `cosl`) into `llvm.sin` /
`llvm.cos` intrinsics when the call does not access memory (i.e. does
not set `errno`). This normalization step brings library calls into
the same form as compiler-generated intrinsics.
2. **InstCombineCalls**: When visiting an `llvm.sin` or `llvm.cos`
intrinsic, scan the users of the shared argument for a matching
counterpart. If found, emit a single `llvm.sincos` call placed right
after the argument definition, replace both original calls, and erase
the matched instruction.
Also remove the completed sincos TODO from Target/README.txt.
Commit: 4aa1590ad66a1bff9b3c74b4a2c7366473015b4c
https://github.com/llvm/llvm-project/commit/4aa1590ad66a1bff9b3c74b4a2c7366473015b4c
Author: Ella Ma <alansnape3058 at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/StaticAnalyzer/Checkers/DeadStoresChecker.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineC.cpp
A clang/test/Analysis/issue-173210-self-assign-init.c
Log Message:
-----------
[analyzer] Ignoring `T v=v;` idiom for uninitialized variable checker and dead store checker (#187530)
Closing #173210
The self-assignment initialization `Type var = var;` is an idiom in C
code. The analyzer is expected to suppress the uninitialized assignment
reports and dead store reports for this idiom. Variables that are really
uninitialized will be reported until they are actually used. Since GCC
will not generate assembly code for such usage, even if under -O0
optimization (but Clang will), this patch resolves this problem by
ignoring such self-assigned `DeclStmt`s in the `ExprEngine`, as well as
in the `DeadStoreObs` of the dead store checker.
This ignorance will be applied to C variables and non-reference C++
variables. For record types in C++, since the constructors will always
be invoked, they will not be affected by this change.
Commit: 94ef4fce34ca8bbf79729814959c0d70b4a9ba3b
https://github.com/llvm/llvm-project/commit/94ef4fce34ca8bbf79729814959c0d70b4a9ba3b
Author: Victor Campos <victor.campos at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M libc/test/UnitTest/CMakeLists.txt
A libc/test/UnitTest/ConstraintHandlerCheckingTest.h
Log Message:
-----------
[libc] Annex K: Add constraint handler unit test class (#197707)
This unit test class will be useful for the tests related to Annex K.
The functions in Annex K may call a constraint handler, so this new unit
test class will facilitate the checks that the constraint handling
mechanism is working as expected.
Commit: 4b455a91141d59ace3a29870c885f5f5e4ff0506
https://github.com/llvm/llvm-project/commit/4b455a91141d59ace3a29870c885f5f5e4ff0506
Author: Dan Liew <dan at su-root.co.uk>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaBoundsSafety.cpp
M clang/test/Sema/attr-sized-by-late-parsed-struct-ptrs.c
M clang/test/Sema/attr-sized-by-or-null-late-parsed-struct-ptrs.c
M clang/test/Sema/attr-sized-by-or-null-struct-ptrs.c
M clang/test/Sema/attr-sized-by-struct-ptrs.c
Log Message:
-----------
[BoundsSafety][Sema] Allow `sized_by`/`sized_by_or_null` on pointers to structs with a flexible array member (#209603)
`Sema::CheckCountedByAttrOnField()` in `SemaBoundsSafety.cpp` rejects
the `counted_by` family of attributes when the pointee is a struct that
contains a flexible array member (FAM). For example:
```
struct has_unannotated_fam {
int count;
int buffer[];
};
struct on_member_pointer_struct_with_fam {
int size;
struct has_unannotated_fam *objects __counted_by(size);
};
```
This restriction makes sense for `counted_by`/`counted_by_or_null`
because the size of a struct with a FAM is not statically known, so the
count of elements cannot be used to compute the size of the buffer.
However, the same check was incorrectly applied to `sized_by` and
`sized_by_or_null`. Unlike `counted_by`, these attributes describe the
size of the buffer in *bytes* rather than in *elements*, so the pointee
size is irrelevant and there is no ambiguity. Previously the following
would be rejected:
```
struct on_member_pointer_struct_with_fam {
int size;
struct has_unannotated_fam *objects __sized_by(size);
};
```
with the diagnostic:
```
error: 'sized_by' cannot be applied to a pointer with pointee of unknown
size because 'struct has_unannotated_fam' is a struct type with a
flexible array member
```
This patch guards the FAM check with `!CountInBytes` so that it only
applies to `counted_by`/`counted_by_or_null`. `sized_by` and
`sized_by_or_null` on such pointers are now correctly accepted.
The obsolete `expected-error` directives in the affected `sized_by` and
`sized_by_or_null` Sema tests are removed, turning those cases into
positive tests.
Assisted-by: Claude Code
rdar://182226884
Commit: 3485d8591992a967553493c53f17d9f3e8a0fc8e
https://github.com/llvm/llvm-project/commit/3485d8591992a967553493c53f17d9f3e8a0fc8e
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/test/SemaCXX/constexpr-late-instantiation.cpp
Log Message:
-----------
[Clang] Ensure correct template parameter depth for abbreviated templates (#209693)
This fixes another case of member functions where we overlooked template
depths when only abbreviated template parameters are involved.
This mirrors previous fix cfb25203c25f, but I don't intend to put it in
ParseTrailingRequiresClause because we might want the similar fix for
e.g. noexcept expressions, so let's keep it inline for future refactor.
The example comes from #205557.
Commit: a208080eff277fc4829f3519e1f918aa4eb6adeb
https://github.com/llvm/llvm-project/commit/a208080eff277fc4829f3519e1f918aa4eb6adeb
Author: Valery Pykhtin <valery.pykhtin at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
Log Message:
-----------
[NFC][AMDGPU] Use SIInstrFlags predicates in MC layer (#206766)
Replace raw TSFlags accesses with SIInstrFlags predicate calls in
AMDGPUInstPrinter and AMDGPUMCCodeEmitter.
Part of a series following the introduction of SIInstrFlags predicates.
Commit: f48b09bbe0654fcd7ddf6b8a8aec807d8552a816
https://github.com/llvm/llvm-project/commit/f48b09bbe0654fcd7ddf6b8a8aec807d8552a816
Author: Ilia Kuklin <ikuklin at accesssoftek.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/include/clang/Options/Options.td
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/dxc_debug.hlsl
M llvm/lib/Target/DirectX/DXContainerGlobals.cpp
M llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp
M llvm/lib/Target/DirectX/DXILWriter/DXILWriterPass.cpp
A llvm/test/CodeGen/DirectX/ContainerData/SourceInfo-Strip.ll
M llvm/test/CodeGen/DirectX/embed-ildb.ll
Log Message:
-----------
[Driver][DirectX] Add `/Qsource_in_debug_module` flag (#204415)
Adds a flag that embeds the source code info into `dx.source` nodes in
bitcode, for both main DXContainer and PDB file output. For the PDB
file, it also removes the `SRCI` part from the output.
Commit: 17406f7e49d45808cb828d6bc225b6f6656938b1
https://github.com/llvm/llvm-project/commit/17406f7e49d45808cb828d6bc225b6f6656938b1
Author: Kseniya Tikhomirova <kseniya.tikhomirova at intel.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M libsycl/docs/index.rst
R libsycl/include/sycl/__impl/detail/default_async_handler.hpp
M libsycl/include/sycl/__impl/event.hpp
M libsycl/include/sycl/__impl/exception.hpp
A libsycl/include/sycl/__impl/info/event.hpp
M libsycl/include/sycl/__impl/queue.hpp
M libsycl/src/detail/event_impl.cpp
M libsycl/src/detail/event_impl.hpp
M libsycl/src/detail/global_objects.cpp
M libsycl/src/detail/global_objects.hpp
M libsycl/src/detail/queue_impl.cpp
M libsycl/src/detail/queue_impl.hpp
A libsycl/src/detail/spinlock.hpp
M libsycl/src/event.cpp
M libsycl/src/exception_list.cpp
M libsycl/src/queue.cpp
M libsycl/unittests/CMakeLists.txt
M libsycl/unittests/common/device_images.hpp
A libsycl/unittests/common/scoped_binary_registration.hpp
M libsycl/unittests/common/unittests_helper.hpp
M libsycl/unittests/device_selector/get_device_preference.cpp
A libsycl/unittests/event/CMakeLists.txt
A libsycl/unittests/event/async_handler.cpp
A libsycl/unittests/event/event.cpp
M libsycl/unittests/mock/helpers.cpp
M libsycl/unittests/mock/helpers.hpp
M libsycl/unittests/mock/mock.cpp
M libsycl/unittests/program_manager/register_and_unregister.cpp
M libsycl/unittests/queue/sycl_kernel_launch.cpp
Log Message:
-----------
[libsycl] implement methods of synchronization in event and queue classes (#205860)
Extends libsycl’s sycl::event API by adding default-constructed event
semantics, wait-list exposure and async exceptions handling. Async
exceptions handling is generic for event and queue APIs and though added
to sycl::queue API as well.
Introduces async-exception aggregation/flush infrastructure (global
associative container).
Adds/adjusts unit tests and unifies test binary registration utilities
(Scoped*Registration, namespace cleanup).
This PR was assisted by GH Copilot.
Signed-off-by: Tikhomirova, Kseniya
[kseniya.tikhomirova at intel.com](mailto:kseniya.tikhomirova at intel.com)
Commit: ffcc00a1418e623176f348830ab16ad0ececba72
https://github.com/llvm/llvm-project/commit/ffcc00a1418e623176f348830ab16ad0ececba72
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lldb/source/Plugins/Platform/POSIX/PlatformPOSIX.cpp
M lldb/test/API/python_api/sbplatform/TestSBPlatform.py
Log Message:
-----------
[lldb][POSIX] Correctly report error copying from remote platform (#207365)
This fixes a bug I found where copying a file from a remote Linux
platform using the API would claim that it succeeded, but it had not.
The local file was read only so it was not updated. The host Linux
platform's copy did not have this bug.
There are two tests, one which will run if the testing platform is not
already a remote. This one spawns a "remote" platform, which is actually
still on the host, but it's enough to take the remote code path in the
POSIX platform implementation.
The second uses the testing platform. If that's a remote, use that, if
it's host then we use the host platform to check local copying
behaviour.
This test is not as specific as I'd like it to be, but I wanted
something that could run on many platforms. Even if the copy fails for a
reason other than permissions, at least we are checking that the failure
is propagated.
Commit: df1838f5d961f9587ca4f90d992bef81cc6155db
https://github.com/llvm/llvm-project/commit/df1838f5d961f9587ca4f90d992bef81cc6155db
Author: Karthika Devi C <kartc at qti.qualcomm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M polly/include/polly/CodeGen/LoopGenerators.h
M polly/lib/CodeGen/IslAst.cpp
M polly/lib/CodeGen/IslNodeBuilder.cpp
M polly/lib/CodeGen/LoopGenerators.cpp
M polly/test/CodeGen/Metadata/basic_vec_annotate.ll
A polly/test/CodeGen/Metadata/skip_vec_annotate_fp_dist1.ll
Log Message:
-----------
[Polly] Skip vectorize.enable for FP loops with dist=1 dependences (#205756)
When -polly-annotate-metadata-vectorize is active, Polly marks its
generated loops with llvm.loop.vectorize.enable=true. This is harmful
for loops with a loop-carried dependence of distance 1 that involve
floating-point operations: the Loop Vectorizer reorders FP operations
(e.g. scalar reduction like q = factor*q), producing results that differ
from the sequential scalar reference and causing correctness failures.
Two changes are made:
1. IslAst.cpp: add PollyVectorizeMetadata to the PerformParallelTest
gate so that dependence-distance computation is performed whenever
-polly-annotate-metadata-vectorize is passed, not only when
-polly-parallel or a vectorizer is active.
2. IslNodeBuilder.cpp / LoopGenerators.cpp: when a loop has a dist=1
dependence involving FP operations, omit the vectorize.enable annotation
entirely. This lets the Loop Vectorizer apply its own cost model and
legality checks decide.
Commit: f114107e67b967de450c0e5c0acf84e70d3d1208
https://github.com/llvm/llvm-project/commit/f114107e67b967de450c0e5c0acf84e70d3d1208
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lldb/include/lldb/Utility/Log.h
M lldb/source/Commands/CommandObjectLog.cpp
M lldb/source/Utility/Log.cpp
M lldb/unittests/Utility/LogTest.cpp
Log Message:
-----------
[lldb] Return llvm::Expected from ListChannelCategories (#209468)
Expected<string> is equivalent to bool+stream, but harder to misuse.
Commit: edbf9e3096c027b61d72df6397c2963be56b2b7b
https://github.com/llvm/llvm-project/commit/edbf9e3096c027b61d72df6397c2963be56b2b7b
Author: Dan Liew <dan at su-root.co.uk>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/Sema/SemaBoundsSafety.cpp
Log Message:
-----------
[NFC][BoundsSafety] Re-order some checks in `Sema::CheckCountedByAttrOnField` (#209713)
This is post-merge feedback for #209603
(4b455a91141d59ace3a29870c885f5f5e4ff0506).
Commit: d9b56d3e5e012a618f55318662e3e5c9ba2c4abf
https://github.com/llvm/llvm-project/commit/d9b56d3e5e012a618f55318662e3e5c9ba2c4abf
Author: Arendelle <Arendelle_ at outlook.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/AST/ExprConstant.cpp
M clang/test/AST/ByteCode/unions.cpp
M clang/test/SemaCXX/constant-expression-cxx2a.cpp
Log Message:
-----------
[clang][constexpr] Move anonymous-union check before getDestructor() in HandleDestructionImpl (#197416)
When HandleDestructionImpl destroys a class object during constant
evaluation, it attempts to look up the class's destructor via
getDestructor() before checking whether the record is an anonymous
union. Anonymous unions should not have their destructors invoked
directly during constant evaluation — their lifetime is managed by the
enclosing class's destructor. Move the anonymous-union short-circuit
before the getDestructor() call so anonymous unions are handled early,
regardless of whether getDestructor() returns null or not.
This fixes cases where an object with an implicitly-defined constexpr
destructor stored inside an anonymous union member was incorrectly
rejected during constant evaluation.
Commit: 083acc3c31fd4696bbc6d4b1c647c63ac976a7ec
https://github.com/llvm/llvm-project/commit/083acc3c31fd4696bbc6d4b1c647c63ac976a7ec
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/cxx2a.cpp
Log Message:
-----------
[clang][bytecode] Fix uninitialized diagnostics (#209702)
... if the pointer is also outside its lifetime. In that case, prefer to
diagnose it as outside its lifetime.
Commit: d0a85f53b9e6c3b7146736a6b19524d1e5f738ee
https://github.com/llvm/llvm-project/commit/d0a85f53b9e6c3b7146736a6b19524d1e5f738ee
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/use-after-free-after-cleanup-failed-vreg.ll
M llvm/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/usubsat.ll
M llvm/test/CodeGen/AMDGPU/v-cmp-cse-across-loop.mir
M llvm/test/CodeGen/AMDGPU/v1024.ll
M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_ashr_pk.ll
M llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_cvt_pk_u8_f32.ll
M llvm/test/CodeGen/AMDGPU/v_mac.ll
M llvm/test/CodeGen/AMDGPU/v_mac_f16-fpdp-rounding-mode.ll
M llvm/test/CodeGen/AMDGPU/v_mac_f16.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/v_mov_b64_expand_and_shrink.mir
M llvm/test/CodeGen/AMDGPU/v_mov_b64_expansion.mir
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard-true16.mir
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard-attrs.mir
M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard.mir
M llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx-set-kill.mir
M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx-wrong-kill-flags.mir
M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.ll
M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard-sdwa.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-permlane-vgpr-msb-gfx1250.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-permlane16var-hazard.mir
M llvm/test/CodeGen/AMDGPU/vector-alloca-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/vector-alloca-atomic.ll
M llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
M llvm/test/CodeGen/AMDGPU/vector-alloca-limits.ll
M llvm/test/CodeGen/AMDGPU/vector-alloca.ll
M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
M llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir
M llvm/test/CodeGen/AMDGPU/vector_range_metadata.ll
M llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vectorize-buffer-fat-pointer.ll
M llvm/test/CodeGen/AMDGPU/vectorize-global-local.ll
M llvm/test/CodeGen/AMDGPU/vectorize-loads.ll
M llvm/test/CodeGen/AMDGPU/vectorize-unroll-metadata.ll
M llvm/test/CodeGen/AMDGPU/verifier-sdwa-cvt.mir
M llvm/test/CodeGen/AMDGPU/verify-constant-bus-violations.mir
M llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
M llvm/test/CodeGen/AMDGPU/verify-duplicate-literal.mir
M llvm/test/CodeGen/AMDGPU/verify-gfx12-gds.mir
M llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir
M llvm/test/CodeGen/AMDGPU/verify-image-vaddr-align.mir
M llvm/test/CodeGen/AMDGPU/verify-image.mir
M llvm/test/CodeGen/AMDGPU/verify-scalar-store.mir
M llvm/test/CodeGen/AMDGPU/verify-vimage-vsample.mir
M llvm/test/CodeGen/AMDGPU/verify-vopd-gfx12.mir
M llvm/test/CodeGen/AMDGPU/verify-vopd.mir
M llvm/test/CodeGen/AMDGPU/vgpr-agpr-limit-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/vgpr-blocks-funcinfo.mir
M llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
M llvm/test/CodeGen/AMDGPU/vgpr-excess-threshold-percent-invalid.ll
M llvm/test/CodeGen/AMDGPU/vgpr-excess-threshold-percent.ll
M llvm/test/CodeGen/AMDGPU/vgpr-limit-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll
M llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250-t16.mir
M llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.mir
M llvm/test/CodeGen/AMDGPU/vgpr-remat-v_pk_mov_b32.mir
M llvm/test/CodeGen/AMDGPU/vgpr-remat.mir
M llvm/test/CodeGen/AMDGPU/vgpr-set-msb-coissue.mir
M llvm/test/CodeGen/AMDGPU/vgpr-setreg-mode-swar.mir
M llvm/test/CodeGen/AMDGPU/vgpr-spill-dead-frame-in-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
M llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (36) (#209600)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: c58ba1cf51d2886994da7e667a05c1bfe4f4396b
https://github.com/llvm/llvm-project/commit/c58ba1cf51d2886994da7e667a05c1bfe4f4396b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir
M llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
M llvm/test/CodeGen/AMDGPU/vi-removed-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/visit-physreg-vgpr-imm-folding-bug.ll
M llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
M llvm/test/CodeGen/AMDGPU/vmem-vcc-hazard.mir
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/vop-shrink.ll
M llvm/test/CodeGen/AMDGPU/vopc-remat.mir
M llvm/test/CodeGen/AMDGPU/vopc_dpp-true16.mir
M llvm/test/CodeGen/AMDGPU/vopc_dpp.ll
M llvm/test/CodeGen/AMDGPU/vopc_dpp.mir
M llvm/test/CodeGen/AMDGPU/vopd-combine-gfx1250.mir
M llvm/test/CodeGen/AMDGPU/vopd-combine.mir
M llvm/test/CodeGen/AMDGPU/vopd-gfx12-f64-relaxed.mir
M llvm/test/CodeGen/AMDGPU/vopd-src2acc-delay.mir
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.ll
M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.mir
M llvm/test/CodeGen/AMDGPU/wait-xcnt-atomic-rmw-optimization.ll
M llvm/test/CodeGen/AMDGPU/wait-xcnt-drain.mir
M llvm/test/CodeGen/AMDGPU/wait-xcnt.mir
M llvm/test/CodeGen/AMDGPU/wait.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-agpr.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-back-edge-loop.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-bvh.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-debug-output-crash.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-flat.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-func-global-inv.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-gfx1250.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-global-inv-wb.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-kmcnt-scc-different-block.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-flushed.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-flushed.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-pattern.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-store-barrier.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-irreducible.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-opt.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-single-basic-block.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-looptest.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-meta-instructions.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-multiple-funcs.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-overflow.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-permute.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-preexisting-vscnt.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-preexisting.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-sample-out-order.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-sample-waw.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-skip-meta.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-unscoped.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-vinterp.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-vmcnt-loop.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-vmem-waw.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-wbl2.ll
M llvm/test/CodeGen/AMDGPU/waitcnt.mir
M llvm/test/CodeGen/AMDGPU/waterfall-call-inreg-agpr.ll
M llvm/test/CodeGen/AMDGPU/waterfall-call-inreg-agpr.mir
M llvm/test/CodeGen/AMDGPU/waterfall-call-target-av-register-failure.ll
M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll
M llvm/test/CodeGen/AMDGPU/while-break.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-register-copy.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/widen_extending_scalar_loads.ll
M llvm/test/CodeGen/AMDGPU/wmma-coexecution-valu-hazards.mir
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-imm.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64.ll
M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx12-w32.mir
M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx12-w64.mir
M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1250-w32.mir
M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1251-w32.mir
M llvm/test/CodeGen/AMDGPU/wmma-hazards.mir
M llvm/test/CodeGen/AMDGPU/wmma-nop-hoisting.mir
M llvm/test/CodeGen/AMDGPU/wmma_modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma_multiple_32.ll
M llvm/test/CodeGen/AMDGPU/wmma_multiple_64.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/workitem-intrinsic-opts.ll
M llvm/test/CodeGen/AMDGPU/wqm-debug-instr-terminator.mir
M llvm/test/CodeGen/AMDGPU/wqm-gfx11.ll
M llvm/test/CodeGen/AMDGPU/wqm-propagate-for-execz-side-effect.mir
M llvm/test/CodeGen/AMDGPU/wqm-terminators.mir
M llvm/test/CodeGen/AMDGPU/wqm.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (37) (#209601)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 6b3b6a88905cfb7e098d3c4a790ae8a196cfeab2
https://github.com/llvm/llvm-project/commit/6b3b6a88905cfb7e098d3c4a790ae8a196cfeab2
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lldb/include/lldb/Target/StackID.h
M lldb/source/Target/StackFrameList.cpp
M lldb/source/Target/StackID.cpp
M lldb/source/Target/ThreadPlanStepInstruction.cpp
M lldb/source/Target/ThreadPlanStepOut.cpp
M lldb/source/Target/ThreadPlanStepRange.cpp
M lldb/source/Target/ThreadPlanStepUntil.cpp
Log Message:
-----------
[lldb][NFC] Create StackID::IsYounger (#209402)
Currently, StackIDs are compared with a custom operator <. There are
some issues with that:
1. It's not clear what "<" means in this context. It really is a test of
"frame A is on top of frame B or not comparable". But this notion is not
expressed through "<".
2. This is not a real operator "<" in the sense that if "!<" does not
imply ">=". In particular, frames may not always be comparable (i.e.
(they are not part of the same stack).
To address these issues, this commit replaces `<` with a custom function
"IsYounger", which makes explicit what is being tested.
Commit: 0f24969ade9df74b11ff70a2c0b1f49ff49e92fd
https://github.com/llvm/llvm-project/commit/0f24969ade9df74b11ff70a2c0b1f49ff49e92fd
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaAMDGPU.cpp
A clang/test/SemaOpenCL/builtins-amdgcn-cmp-deprecated.cl
Log Message:
-----------
[Clang][AMDGPU] Deprecate icmp/fcmp builtins in favor of ballot (#209416)
Deprecate these builtins with a warning recommending
__builtin_amdgcn_ballot_w32 or __builtin_amdgcn_ballot_w64 instead:
__builtin_amdgcn_uicmp
__builtin_amdgcn_uicmpl
__builtin_amdgcn_sicmp
__builtin_amdgcn_sicmpl
__builtin_amdgcn_fcmp
__builtin_amdgcn_fcmpf
Assisted-by: Claude Opus 4.8
Commit: f96628d9cab6c840ef836f3046d5d566dc620596
https://github.com/llvm/llvm-project/commit/f96628d9cab6c840ef836f3046d5d566dc620596
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/Driver/OffloadBundler.cpp
Log Message:
-----------
clang-offload-bundler: Reduce include of Cuda.h to OffloadArch.h (#209723)
This was only using OffloadArch, so use that header directly.
Commit: 11cc8d876e2bb696fef7079eed0a1ff574c0770f
https://github.com/llvm/llvm-project/commit/11cc8d876e2bb696fef7079eed0a1ff574c0770f
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/transfer-signed-facts-to-unsigned.ll
Log Message:
-----------
[ConstraintElim] Transfer SLE facts to unsigned (#209623)
Handle SLE analogous to SLT via getUnsignedPredicate.
Alive2 Proof: https://alive2.llvm.org/ce/z/yNjmL8
PR: https://github.com/llvm/llvm-project/pull/209623
Commit: ca71592c415c2c1e6fe8289d4bcff934279d8315
https://github.com/llvm/llvm-project/commit/ca71592c415c2c1e6fe8289d4bcff934279d8315
Author: Kaviya Rajendiran <67495422+kaviya2510 at users.noreply.github.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/Analysis/ArraySectionAnalyzer.h
M flang/include/flang/Optimizer/Builder/FIRBuilder.h
M flang/lib/Optimizer/Builder/FIRBuilder.cpp
M flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRAssign.cpp
A flang/test/HLFIR/inline-hlfir-assign-pointer-overlap.fir
A flang/test/HLFIR/inline-hlfir-assign-scalar-index.fir
A flang/test/HLFIR/inline-hlfir-assign-self-copy-runtime-stride.fir
A flang/test/HLFIR/inline-hlfir-assign-self-copy.fir
A flang/test/Lower/inline-hlfir-assign-forall-threadprivate.f90
A flang/test/Lower/inline-hlfir-assign-pointer-omp.f90
Log Message:
-----------
Reland "[Flang]Add support for inlining hlfir.assign operation where both LHS and RHS are slices of the same array #204532" (#208159)
Added support for inlining hlfir.assign when both LHS and RHS are slices
of the same array. When overlap between the slices cannot be determined,
the pass introduces a disjointness check:
- genIndexBasedDisjointnessCheck(..) is used when both sides are
sections of the same array.
- genAddressBasedDisjointnessCheck(..) used as a fallback for more
complex cases.
At runtime:
- If the slices are disjoint, a direct element-wise copy is performed
without allocating a temporary buffer.
- If overlap is possible, a temporary buffer is allocated, the RHS is
first copied into it and then the data is copied from the temporary
buffer to the LHS.
Fixes https://github.com/llvm/llvm-project/issues/203228
Commit: 1d4148821bf96bef23ea77952031e3e7bec26d3a
https://github.com/llvm/llvm-project/commit/1d4148821bf96bef23ea77952031e3e7bec26d3a
Author: Mel Chen <mel.chen at sifive.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-unroll.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
Log Message:
-----------
[VPlan] Fix nowrap flags for strided access pointers from SCEV (#209453)
This patch addresses two things. First, the offset calculation
(canonical IV * stride) should not reuse the NSW flag of the add
recurrence. The NSW property from SCEV for the original scalar
recurrence does not necessarily hold for the reconstructed
multiplication using the vector canonical IV. The NUW flag, however, can
still be safely propagated.
Second, because vputils::getGEPFlagsForPtr currently doesn't support
recipes other than VPInstruction, and to avoid relying on LLVM IR
function (like calling stripPointerCasts()), we change
VPVectorPointerRecipe's GEP flags to use the add recurrence's flags to
prevent propagating unprovable GEP flags like inbounds.
Commit: 54e36d6ba68c3c5f91bd36c1c9bf8d8af6f8940b
https://github.com/llvm/llvm-project/commit/54e36d6ba68c3c5f91bd36c1c9bf8d8af6f8940b
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/vk-ext-builtin-input.ll
Log Message:
-----------
[SPIR-V] Emit UniformId decoration as OpDecorateId with a Scope id operand (#207958)
Per spec, UniformId operand is a Scope `<id>`, not a literal
Previously it was printed via `printSymbolicOperand<ScopeOperand>`,
which asserts on a real id operand, and never emitted correctly
Commit: dadccf8e6ddb9d87f5b48431a0417dc7b39d9742
https://github.com/llvm/llvm-project/commit/dadccf8e6ddb9d87f5b48431a0417dc7b39d9742
Author: Utkarsh Saxena <usx at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
M clang/test/Sema/LifetimeSafety/dangling-field.cpp
Log Message:
-----------
[LifetimeSafety] Suppress false field-escape warnings in destructors (#209614)
Commit: 96a53b1c5356754b4708c0fee8517fd0d69cb1fd
https://github.com/llvm/llvm-project/commit/96a53b1c5356754b4708c0fee8517fd0d69cb1fd
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/loadi8.ll
M llvm/test/Transforms/SLPVectorizer/X86/runtime-alias-checks.ll
Log Message:
-----------
[SLP] Support memory runtime alias checks
Vectorize straight-line code blocked by runtime-checkable may-alias
dependencies by versioning the block. Drop the deps, and if the tree is
profitable, emit base-object address-range overlap checks branching to a
vector fast path or an original-order scalar fallback.
Fixes #201534
Original Pull Request: https://github.com/llvm/llvm-project/pull/203631
Recommit after revert in a9ba4d3fd27a05b31adfeaab5dcd42d8e43c1931,
related to late commit before the release and small after-commit change
request
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209305
Commit: 0dccfdc051a5865f4f0ef0e988084e70d317727e
https://github.com/llvm/llvm-project/commit/0dccfdc051a5865f4f0ef0e988084e70d317727e
Author: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/Driver/SanitizerArgs.cpp
Log Message:
-----------
[clang][Driver] Remove duplicate KernelAddress sanitizer kind. NFC. (#209079)
Remove the duplicate `SanitizerKind::KernelAddress` entry from the list
of sanitizers incompatible with `TypeSanitizer`.
Found using clang-tidy, with check `misc-redundant-expression`
Commit: d3f58ce0cc1c3533a3085671978ded2e0e867e16
https://github.com/llvm/llvm-project/commit/d3f58ce0cc1c3533a3085671978ded2e0e867e16
Author: jeanPerier <jperier at nvidia.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCTypeInterfaces.cpp
Log Message:
-----------
[flang][openacc][NFC] remove useAccReductionCombine cl switch (#208756)
Follow-up of https://github.com/llvm/llvm-project/pull/208473 to remove
the switch altogether to simplify the compiler code.
Commit: 8c9a6fd876677a69b3a08ce8d868f21730dd6915
https://github.com/llvm/llvm-project/commit/8c9a6fd876677a69b3a08ce8d868f21730dd6915
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDowngrade1p1To1p0.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
M mlir/lib/Dialect/Tosa/Utils/QuantUtils.cpp
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-downgrade-1-1-to-1-0.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
Log Message:
-----------
[mlir][tosa] Add support for block scaled types in matmul_t (#207851)
Builds on https://github.com/llvm/llvm-project/pull/203894 to enable
MXFP block scaled fotmats within matmul_t.
Commit: 5b3b76e77386b6e91c7627edb3beab64077e379f
https://github.com/llvm/llvm-project/commit/5b3b76e77386b6e91c7627edb3beab64077e379f
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M libcxx/docs/ReleaseNotes.rst
A libcxx/docs/ReleaseNotes/24.rst
Log Message:
-----------
[libc++] Create libc++ 24 release notes (#208814)
Now that the LLVM 23 branch has been created, this adds LLVM 24 release
notes. The release notes contain a few TODOs which will be easy to
address in separate PRs.
Commit: eb2163a5d116a2834844b035684a43c8ee765fc1
https://github.com/llvm/llvm-project/commit/eb2163a5d116a2834844b035684a43c8ee765fc1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/wqm.mir
M llvm/test/CodeGen/AMDGPU/write-register-invalid-register.ll
M llvm/test/CodeGen/AMDGPU/write-register-vgpr-into-sgpr.ll
M llvm/test/CodeGen/AMDGPU/write_register.ll
M llvm/test/CodeGen/AMDGPU/wwm-reg-shift-down-gfx11plus.mir
M llvm/test/CodeGen/AMDGPU/wwm-regalloc-error.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/wwm-spill-superclass-pseudo.mir
M llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-any.ll
M llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-disabled.ll
M llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-enabled.ll
M llvm/test/CodeGen/AMDGPU/xnor.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
M llvm/test/CodeGen/AMDGPU/xor3-i1-const.ll
M llvm/test/CodeGen/AMDGPU/xor3.ll
M llvm/test/CodeGen/AMDGPU/xor_add.ll
M llvm/test/CodeGen/AMDGPU/zero_extend.ll
M llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (38) (#209602)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: c8c0877e60c847ec81a4e469ec25a30fcf1aa46e
https://github.com/llvm/llvm-project/commit/c8c0877e60c847ec81a4e469ec25a30fcf1aa46e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add_shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-prelegalizer-combiner-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/and.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-asserts.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-concat-vectors.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-cse-leaves-dead-cast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_store_local.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-add-sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-and.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-or.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-xchg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-xor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_minmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/br-constant-invalid-sgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/bug_shuffle_vector_to_scalar.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-add-to-ptradd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-amdgpu-cvt-f32-ubyte.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ext-legalizer.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fdiv-sqrt-to-rsq.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-pre-legalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-foldable-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fpneg-one-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-s64-s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-trunc-sextinreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.postlegal.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.prelegal.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-urem-pow-2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-zext-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combiner-crash.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/compute-num-sign-bits-med3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
Log Message:
-----------
AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (39) (#209729)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping
the redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: f10eda428d5c4d21e57b5809805a5554922f851d
https://github.com/llvm/llvm-project/commit/f10eda428d5c4d21e57b5809805a5554922f851d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/test/Driver/clang-offload-bundler-multi-compress.c
M clang/test/OffloadTools/clang-offload-bundler/asserts-on.c
M clang/test/OffloadTools/clang-offload-bundler/basic.c
M clang/test/OffloadTools/clang-offload-bundler/fat-archive-unbundle-ext.c
M clang/test/OffloadTools/clang-offload-bundler/standardize.c
M clang/test/OffloadTools/clang-offload-bundler/zlib.c
M clang/test/OffloadTools/clang-offload-bundler/zstd.c
Log Message:
-----------
clang-offload-bundler: Fix host dependency of tests (#209720)
Use an explicit linux triple for the host target instead of using the
default/host target and marking most every other system as unsupported.
Fixes not running these tests on macos.
Co-authored-by: Claude (Opus 4.8)
Commit: e41f5aa4d656ed16b8f9890ee7f30fb1845d4a03
https://github.com/llvm/llvm-project/commit/e41f5aa4d656ed16b8f9890ee7f30fb1845d4a03
Author: Robert Imschweiler <robert.imschweiler at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/runtimes/CMakeLists.txt
Log Message:
-----------
[runtimes] Add explicit offload arch tool dependencies (#206076)
Needed for the offload unittests which detect the target arch at
configure time if not forced by OFFLOAD_TESTS_FORCE_AMDGPU_ARCH. Bug had
been masked by the dependency on flang, which we recently removed in
https://github.com/llvm/llvm-project/pull/198205.
Claude assisted with this patch.
Commit: 1980283edd2155bb058b58fbc97fb02d3e78c301
https://github.com/llvm/llvm-project/commit/1980283edd2155bb058b58fbc97fb02d3e78c301
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fcmp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.v2f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.gfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/floor.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmad.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmax_legacy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmin_legacy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx942.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.v2i65.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-value-addrspaces.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.illegal.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/hip.extern.shared.array.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/i1-copy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/icmp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.i16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.u16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.i16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.u16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ds.swizzle.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.compr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmad.ftz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.groupstaticsize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mbcnt.lo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mul.u24.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mulhi.i24.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mulhi.u24.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.legacy.mir
Log Message:
-----------
AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (40) (#209730)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: f48200029bf6277d4fe3915b480a5c87c8f172c9
https://github.com/llvm/llvm-project/commit/f48200029bf6277d4fe3915b480a5c87c8f172c9
Author: Lukacma <Marian.Lukac at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c
M clang/test/Driver/print-enabled-extensions/aarch64-ampere1c.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-a16.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-a17.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-m5.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.7-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.8-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.9-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.2-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.3-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.4-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.5-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
M clang/test/Driver/print-enabled-extensions/aarch64-c1-premium.c
M clang/test/Driver/print-enabled-extensions/aarch64-c1-pro.c
M clang/test/Driver/print-enabled-extensions/aarch64-c1-ultra.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a320.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520ae.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a720.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a720ae.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a725.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-x4.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-x925.c
M clang/test/Driver/print-enabled-extensions/aarch64-fujitsu-monaka.c
M clang/test/Driver/print-enabled-extensions/aarch64-gb10.c
M clang/test/Driver/print-enabled-extensions/aarch64-hip12.c
M clang/test/Driver/print-enabled-extensions/aarch64-neoverse-n3.c
M clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3.c
M clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3ae.c
M clang/test/Driver/print-enabled-extensions/aarch64-olympus.c
M clang/test/Driver/print-enabled-extensions/aarch64-rigel.c
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64Processors.td
M llvm/lib/Target/AArch64/AArch64SystemOperands.td
M llvm/test/MC/AArch64/armv8.7a-hcx.s
M llvm/test/MC/Disassembler/AArch64/armv8.7a-hcx.txt
Log Message:
-----------
[AArch64] Remove HCX feature flag from backend (#209477)
This patch removes +hcx option from the llvm and removes guarding of
HCRX_EL2 system register on it.
Commit: cceae35fc91ad84baaa046e65961bd49de89a6e6
https://github.com/llvm/llvm-project/commit/cceae35fc91ad84baaa046e65961bd49de89a6e6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.readfirstlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.reloc.constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.clamp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sffbh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-wave-address.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomic-cmpxchg-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomic-cmpxchg-region.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-region.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-region.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitreverse.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy-scc-vcc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy-scc-vcc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctlz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-cttz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.gfx11plus-fake16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.gfx11plus.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fconstant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmad.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-i1-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-old-legalization.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-saddr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.s96.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
Log Message:
-----------
AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (41) (#209731)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 52eb0512237be5b1a58a82cad84caaddab4e04aa
https://github.com/llvm/llvm-project/commit/52eb0512237be5b1a58a82cad84caaddab4e04aa
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
A clang/test/Driver/openmp-invalid-target-id.c
Log Message:
-----------
clang: Add OpenMP driver test for invalid target IDs (#209740)
Submit test that already exists in the rocm fork. This stresses
the error cases when using the legacy OpenMP -march target specifier,
which appears to be missing upstream.
Commit: 9744b475e28e180599fd1a42d956f74b0a1aaed8
https://github.com/llvm/llvm-project/commit/9744b475e28e180599fd1a42d956f74b0a1aaed8
Author: Ayokunle Amodu <ayokunle321 at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx1250.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-vi-f16.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
Log Message:
-----------
[CIR][AMDGPU] Add support for AMDGCN rsq and rsq_clamp builtins (#197349)
Adds codegen for the following AMDGCN reciprocal square root builtins:
- __builtin_amdgcn_rsq (double)
- __builtin_amdgcn_rsqf (float)
- __builtin_amdgcn_rsqh (half)
- __builtin_amdgcn_rsq_bf16 (bfloat16)
- __builtin_amdgcn_rsq_clamp (double)
- __builtin_amdgcn_rsq_clampf (float)
These are lowered to the corresponding `llvm.amdgcn.rsq` and
`llvm.amdgcn.rsq.clamp` intrinsic calls.
Commit: 567c6a7589fe9f29882d60ac2ddedc2f33bd80c1
https://github.com/llvm/llvm-project/commit/567c6a7589fe9f29882d60ac2ddedc2f33bd80c1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mad_64_32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-and-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pseudo-scalar-transcendental.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrmask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-returnaddress.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sbfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sopc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-packed.xfail.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sextload-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax-64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin-64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-stacksave-stackrestore.invalid.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-stacksave-stackrestore.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.s96.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.gfx10.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uaddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ubfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax-64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin-64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.gfx10.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zextload-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslate-bf16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-cs-chain.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fast-math-flags.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.v2i65.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-metadata.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces-vectors.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/known-bits-sbfe.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/known-fpclass-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-relocs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if-invalid.mir
Log Message:
-----------
AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (42) (#209732)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 2746fc6981516c9e26dbdaa7ba254279d391b534
https://github.com/llvm/llvm-project/commit/2746fc6981516c9e26dbdaa7ba254279d391b534
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if.xfail.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.rsq.clamp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.wavefrontsize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.workitem.id.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg-with-success.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-max.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-min.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-nand.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-block-addr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-splat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctls.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-divrem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp-s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fconstant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaximum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminimum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def-s1025.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2darraymsaa.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.3d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
Log Message:
-----------
AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (43) (#209733)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 42605e7b341ccbc6b2486e2ced82386f099c476a
https://github.com/llvm/llvm-project/commit/42605e7b341ccbc6b2486e2ced82386f099c476a
Author: ioana ghiban <ioana.ghiban at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M mlir/lib/Dialect/MemRef/Transforms/ElideReinterpretCast.cpp
M mlir/test/Dialect/MemRef/elide-reinterpret-cast.mlir
Log Message:
-----------
[mlir][memref] Support truncating copied dims to non-unit in reinterpret_cast elision (#209536)
Relax the `memref.copy`through `memref.reinterpret_cast` rewrite to
support same-dimension slices where strictly one non-unit source
dimension size is truncated to a smaller non-unit result dimension.
Previously, the rewrite only supported truncating to unit size:
```mlir
memref<1xMxNxf32>
to memref<1xMx1xf32, strided<[M*N, N, 1], offset: OFF>>
```
This change relaxes constraints to also support:
```mlir
memref<1xMxNxf32>
to memref<1xMxKxf32, strided<[M*N, N, 1], offset: OFF>>
```
where `K < N`.
The rewrite remains conservative:
* source must have identity layout,
* result strides must match the source identity strides,
* offset must be static for non-scalar results, and
* copied slice must be in bounds.
Assisted-by: Codex (refine PR description).
Commit: 0350a23a8bbc091e646406a2aaeafa35dc0216d3
https://github.com/llvm/llvm-project/commit/0350a23a8bbc091e646406a2aaeafa35dc0216d3
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt-c/WrapperFunction.h
M orc-rt/test/unit/WrapperFunctionBufferTest.cpp
Log Message:
-----------
[orc-rt] Fix WrapperFunctionBuffer empty range construction (#209751)
orc_rt_CreateWrapperFunctionBufferFromRange(const char *, size_t) left
the constructed buffer's data member uninitialized when the size
argument was zero. This could result in the returned buffer having a
non-null data field and a zero size field, which is a (malformed)
out-of-band error value, not an empty buffer.
Update orc_rt_CreateWrapperFunctionBufferFromRange to zero-initialize
the data field so that the size == 0 case yields a correctly formed
empty buffer.
Commit: 653c1dab3774d0cf02bb9fc8c469bbd356aff885
https://github.com/llvm/llvm-project/commit/653c1dab3774d0cf02bb9fc8c469bbd356aff885
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-4.ll
M llvm/test/CodeGen/X86/x86-interleaved-access.ll
Log Message:
-----------
[X86] combineINSERT_SUBVECTOR - enable shuffle combining of insertsub(extractsub(shuffle),extractsub(shuffle)) patterns (#209735)
Allows combineX86ShuffleChainWithExtract to more consistently fold
patterns from wider sources
Commit: 4b66bacd1fdf02803509b744034f3ab09945157c
https://github.com/llvm/llvm-project/commit/4b66bacd1fdf02803509b744034f3ab09945157c
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/AST/APValue.h
M clang/include/clang/AST/PropertiesBase.td
M clang/lib/AST/APValue.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Context.cpp
M clang/lib/AST/ByteCode/EvaluationResult.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Record.cpp
M clang/lib/AST/ByteCode/Record.h
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/CodeGen/CGExprConstant.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaType.cpp
A clang/test/AST/ByteCode/virtual-bases-codegen.cpp
A clang/test/AST/ByteCode/virtual-bases.cpp
M clang/test/CXX/drs/cwg16xx.cpp
M clang/test/CXX/drs/cwg18xx.cpp
M clang/test/CXX/drs/cwg6xx.cpp
M clang/www/cxx_status.html
Log Message:
-----------
[clang][ExprConst] Support virtual bases in C++26 (#204289)
Add support for virtual bases in constant expressions (P3533R2) to both the current constant interpreter as well as the bytecode interpreter.
Commit: 706db1e0959f45d6392edd2ad196a4ea38bb99d3
https://github.com/llvm/llvm-project/commit/706db1e0959f45d6392edd2ad196a4ea38bb99d3
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
Log Message:
-----------
[mlir][tosa] Add support for MXFP row_gather (#207933)
Adds profile compliance support for MXFP row_gather.
Commit: 4584a6489341b4fe7762991e65f98467ffe4c699
https://github.com/llvm/llvm-project/commit/4584a6489341b4fe7762991e65f98467ffe4c699
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.cpp
Log Message:
-----------
[lldb][AArch64][NFC] Make watchpoint adjustment more clear (#209483)
NativeRegisterContextDBReg_arm64::AdjustWatchpoint has a way of
adjusting the range of a watchpoint but it took me a while to figure out
how it worked. I've rewritten it in a way I think is easier to follow,
with more explanatory comments.
It turns out that this adjustment results in us only using a subset of
what the hardware allows.
* You don't have to select a continuous range of bytes (1, 2, 3). You
can select (1, 4) for example.
* The address can be 4 byte aligned, in which case only 4 bits of the
byte select apply (though you can set up an equivalent watch with 8 byte
alignment and a different 8 bit BAS value).
Commit: 2c978fa06d19095c0003508b8dac084689b12e78
https://github.com/llvm/llvm-project/commit/2c978fa06d19095c0003508b8dac084689b12e78
Author: Caroline Newcombe <caroline.newcombe at hpe.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang/lib/Lower/Support/Utils.cpp
M flang/test/Integration/OpenMP/copyprivate.f90
M flang/test/Integration/OpenMP/private-global.f90
M flang/test/Lower/OpenMP/DelayedPrivatization/target-teams-distribute-private-adjustable-array.f90
M flang/test/Lower/OpenMP/copyprivate.f90
M flang/test/Lower/OpenMP/delayed-privatization-array.f90
M flang/test/Lower/OpenMP/lastprivate-equivalence.f90
M flang/test/Lower/OpenMP/loop-directive.f90
M flang/test/Lower/OpenMP/parallel-private-clause.f90
A flang/test/Lower/OpenMP/private-array-boxing.f90
M flang/test/Lower/OpenMP/private-commonblock.f90
M flang/test/Lower/do_concurrent_local_assoc_entity.f90
Log Message:
-----------
[flang][OpenMP] Avoid boxing constant-size trivial private arrays (#208315)
Part of #208086. `privatizeSymbol` (used for both OpenMP privatization
and `do concurrent` locals) currently boxes every array as a workaround
for `fir.array` not being directly `alloca`-able in the OpenMP→LLVMIR
translation. This PR carves out the common case: a constant-shape array
of trivial intrinsic elements (e.g. `real(8) :: xx(3)`) is now
privatized unboxed, as a plain `fir.array`.
Commit: 2975dac23e684748ae1051e6c1112aa53d7aea2c
https://github.com/llvm/llvm-project/commit/2975dac23e684748ae1051e6c1112aa53d7aea2c
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lldb/test/Shell/helper/toolchain.py
M lldb/test/Shell/lit.cfg.py
Log Message:
-----------
[lldb] Drop support for using the external shell
The lit external shell is going to be removed soon, so drop support for
using it to run the LLDB tests.
Reviewers: DavidSpickett, JDevlieghere, petrhosek, ilovepi
Pull Request: https://github.com/llvm/llvm-project/pull/209627
Commit: a4d12bf0c2ab2acfd772a8fd6ad216e3a17e5c49
https://github.com/llvm/llvm-project/commit/a4d12bf0c2ab2acfd772a8fd6ad216e3a17e5c49
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lldb/cmake/modules/FindPythonAndSwig.cmake
Log Message:
-----------
[lldb][Windows] Enforce Python 3.11 (#209759)
https://github.com/llvm/llvm-project/pull/191159 recommended Python 3.11
or later. Now that llvm 23 has branched, we can enforce Python 3.11 as
the minimum requirement.
Commit: 25682c3470410534c59708d7d3e2c9248802485f
https://github.com/llvm/llvm-project/commit/25682c3470410534c59708d7d3e2c9248802485f
Author: Access <ShootingStarDragons at protonmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang-tools-extra/clangd/SemanticHighlighting.cpp
M clang-tools-extra/clangd/unittests/PrerequisiteModulesTest.cpp
Log Message:
-----------
[clangd] highlight import and export keywords for C++20 modules (#204511)
Add syntax highlighting for C++20 module `import` and `export` keywords.
Note: Highlighting of the `export` keyword in a module export statement is not possible, because such statements don't appear in the AST
Commit: 9a4deccf90ae914aa6d99acfff44b24bc5dfcb5c
https://github.com/llvm/llvm-project/commit/9a4deccf90ae914aa6d99acfff44b24bc5dfcb5c
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/CMakeLists.txt
A llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
A llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
Log Message:
-----------
[WebAssembly] Introduce CodeGenPassBuilder
This is the equivalent of TargetPassConfig for the NewPM. This currently
mirrors the existing TargetPassConfig as close as possible, but with
TODOs for passes that have not been ported to the NewPM.
Reviewers: aheejin, sbc100, dschuff
Pull Request: https://github.com/llvm/llvm-project/pull/208983
Commit: f4452848f0a5e827f5732ab390099d7d90084ca0
https://github.com/llvm/llvm-project/commit/f4452848f0a5e827f5732ab390099d7d90084ca0
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyAddMissingPrototypes.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/test/CodeGen/WebAssembly/add-prototypes.ll
Log Message:
-----------
[WebAssembly] Port WebAssemblyAddMissingPrototypesPass to NewPM
Standard pass porting.
Reviewers: dschuff, aheejin, sbc100
Pull Request: https://github.com/llvm/llvm-project/pull/208985
Commit: f69748cd80db74bcd81834b4bba8749fc508f99f
https://github.com/llvm/llvm-project/commit/f69748cd80db74bcd81834b4bba8749fc508f99f
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyFixFunctionBitcasts.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[WebAssembly] Port WebAssemblyFixFunctionBitcastsPass to NewPM
Standard pass porting.
Reviewers: aheejin, dschuff, sbc100
Pull Request: https://github.com/llvm/llvm-project/pull/208986
Commit: 80314ec06f15e7a0bb4b55380e50b2e529c5b0f7
https://github.com/llvm/llvm-project/commit/80314ec06f15e7a0bb4b55380e50b2e529c5b0f7
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/fenv/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/mman/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 36c6568 (#209689)
This fixes 36c6568b04aff4e1cf00a60570ab4a4344692920.
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=36c6568b04aff4e1cf00a60570ab4a4344692920
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 491539a8b801aad5706cc32fc54a319791d57a91
https://github.com/llvm/llvm-project/commit/491539a8b801aad5706cc32fc54a319791d57a91
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyOptimizeReturned.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[WebAssembly] Port WebAssemblyOptimizeReturnedPass
Standard pass porting for the NewPM.
Reviewers: sbc100, dschuff, aheejin
Pull Request: https://github.com/llvm/llvm-project/pull/209036
Commit: 0d93f2aec0b4847761bd8458b7847ce37b85cf03
https://github.com/llvm/llvm-project/commit/0d93f2aec0b4847761bd8458b7847ce37b85cf03
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/test/SemaCXX/enable_if.cpp
Log Message:
-----------
Fix references to complete types in attribute references (#209537)
This is a regression from #197215.
Attributes are not REALLY in the body of a function (though the name of
said function is... awkwardly inaccurate at best), but still need to pay
attention to the completeness of their references. As a result, we
weren't marking the expression as invalid, but were also trying to
evaluate it.
This patch fixes this in 2 ways. First, we re-add the
CXXThisTypeOverride check, but except constant substitution, since that
has some additional 'this' behavior from #197215. x
Secondly, we also make the constant evaluator give up on incomplete
types when handling an L value member. This stops us from trying to
evaluate the value if it is incomplete during template instantiation,
when the type is incomplete. We don't diagnose, since it is still
potentially a constant expression, but isn't currently one.
Fixes: #199527
Commit: 5fcfb4d168eae3e78da8d0f7649bf08a338eff42
https://github.com/llvm/llvm-project/commit/5fcfb4d168eae3e78da8d0f7649bf08a338eff42
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/test/CodeGen/WebAssembly/lower-em-exceptions-allowed.ll
Log Message:
-----------
[WebAssembly] Port WebAssemblyLowerEmscriptenEHSjLjImpl
Standard NewPM pass porting.
Reviewers: dschuff, sbc100, aheejin
Pull Request: https://github.com/llvm/llvm-project/pull/209040
Commit: c2da010159cc318b5fdba4a1fc7deef9438e749d
https://github.com/llvm/llvm-project/commit/c2da010159cc318b5fdba4a1fc7deef9438e749d
Author: David Young <davidayoung at meta.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/test/src/string/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/mman/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/resource/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/socket/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/unistd/BUILD.bazel
Log Message:
-----------
[libc][bazel] Add missing hdr/*_macros deps to test targets (#209761)
Commit b790c5cd2679 (#209449) switched several libc tests to include the
hdr/*_macros.h proxy headers and updated the CMake build accordingly,
but did not update the Bazel overlay. As a result, the Bazel libc test
targets include hdr/*_macros.h (and, via shared headers,
hdr/sys_mman_macros.h) without declaring the corresponding
//libc:hdr_*_macros dependencies, breaking the Bazel build with 'file
not found' / module layering errors.
Mirror the CMake dependency additions into the Bazel overlay so each
test target that includes an hdr macro header depends on the matching
//libc:hdr_*_macros (and //libc:types_struct_rlimit) target.
First found trying to land (#209747).
bazel changes assisted with: claude
cannot build with bazel locally so relying on CI to confirm green
Commit: 044f8a1f151f935d2e718faa5b1d7cb8e8f52bec
https://github.com/llvm/llvm-project/commit/044f8a1f151f935d2e718faa5b1d7cb8e8f52bec
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyReduceToAnyAllTrue.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[WebAssembly] Port WebAssemblyReduceToAnyAllTruePass
Standard NewPM pass porting. Made a little bit annoying by the module
caching that I'm not sure helps much, but I've left it in.
Reviewers: aheejin, dschuff, sbc100
Pull Request: https://github.com/llvm/llvm-project/pull/209043
Commit: 868e3b898dcf243f97885ce0d857a2827f4d1fa3
https://github.com/llvm/llvm-project/commit/868e3b898dcf243f97885ce0d857a2827f4d1fa3
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.chain.arg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
Log Message:
-----------
[AMDGPU] Fix set_inactive known bits to intersect both operands (#201817)
SimplifyDemandedBitsForTargetNode grouped amdgcn_set_inactive with the
single-source readfirstlane/readlane/wwm, taking known bits from operand
1 only
Handle the data from the operand 2 inactive lanes as well
Commit: 8396c758875a11a57a4b6a2b6b06b719c1b2ab1b
https://github.com/llvm/llvm-project/commit/8396c758875a11a57a4b6a2b6b06b719c1b2ab1b
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyRefTypeMem2Local.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[WebAssembly] Port WebAssemblyRefTypeMem2LocalPass
Standard NewPM pass porting.
Reviewers: sbc100, aheejin, dschuff
Pull Request: https://github.com/llvm/llvm-project/pull/209044
Commit: 7e80bca9c9130a49ded8ac500d19942928c3564b
https://github.com/llvm/llvm-project/commit/7e80bca9c9130a49ded8ac500d19942928c3564b
Author: Kseniya Tikhomirova <kseniya.tikhomirova at intel.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M libsycl/test/basic/parallel_for_indexers.cpp
Log Message:
-----------
[libsycl] Add missing include to test (#209722)
Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
Commit: 8a41c1f77732d18eae12409b572fc926df29062b
https://github.com/llvm/llvm-project/commit/8a41c1f77732d18eae12409b572fc926df29062b
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
Log Message:
-----------
[mlir][tosa] Add support for MXFP reshape (#207944)
Adds profile compliance support for MXFP reshape.
Commit: 2375505c7c19cf521b9ed5acaf7f359ddd9f216b
https://github.com/llvm/llvm-project/commit/2375505c7c19cf521b9ed5acaf7f359ddd9f216b
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/CMakeLists.txt
M llvm/lib/Target/WebAssembly/WebAssembly.h
A llvm/lib/Target/WebAssembly/WebAssemblyCoalesceFeaturesAndStripAtomics.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[NFC][WebAssembly] Move WebAssemblyCoalesceFeaturesAndStripAtomics
Move WebAssemblyCoalesceFeaturesAndStripAtomics to a separate file.
Having a pass implemented directly in the TargetMachine file is a bit
weird.
Reviewers: dschuff, sbc100, aheejin
Pull Request: https://github.com/llvm/llvm-project/pull/209046
Commit: a2b6a1bae7904be696d8283b9bb34331c39a54ef
https://github.com/llvm/llvm-project/commit/a2b6a1bae7904be696d8283b9bb34331c39a54ef
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyCoalesceFeaturesAndStripAtomics.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyPassRegistry.def
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
[WebAssembly] Port WebAssemblyCoalesceFeaturesAndStripAtomicsPass
Standard NewPM pass porting.
Reviewers: sbc100, aheejin, dschuff
Pull Request: https://github.com/llvm/llvm-project/pull/209054
Commit: d6627298f3047e87b1a663f3256f500c0179898f
https://github.com/llvm/llvm-project/commit/d6627298f3047e87b1a663f3256f500c0179898f
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M .github/workflows/containers/github-action-ci-windows/Dockerfile
M .github/workflows/containers/github-action-ci/Dockerfile
M .github/workflows/libc-overlay-tests.yml
A .github/workflows/libcxx-benchmark-commit.yml
M .github/workflows/libcxx-build-and-test.yaml
M .github/workflows/libcxx-pr-benchmark.yml
M .github/workflows/release-binaries-all.yml
M bolt/include/bolt/Core/BinaryContext.h
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Core/BinaryEmitter.cpp
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Rewrite/DWARFRewriter.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/X86/dwarf-inline-range-plt-shift.s
M bolt/test/X86/dwarf4-cross-cu-ranges.test
M bolt/test/X86/dwarf5-debug-names-cross-cu.s
M bolt/test/X86/match-blocks-with-pseudo-probes-inline.test
M bolt/test/X86/pseudoprobe-decoding-inline.test
M bolt/test/X86/pseudoprobe-decoding-noinline.test
M bolt/test/lit.cfg.py
M clang-tools-extra/clang-doc/CMakeLists.txt
M clang-tools-extra/clang-doc/Generators.cpp
M clang-tools-extra/clang-doc/Generators.h
M clang-tools-extra/clang-doc/JSONGenerator.cpp
M clang-tools-extra/clang-doc/MDGenerator.cpp
R clang-tools-extra/clang-doc/MDMustacheGenerator.cpp
M clang-tools-extra/clang-doc/Representation.h
R clang-tools-extra/clang-doc/YAMLGenerator.cpp
R clang-tools-extra/clang-doc/markdown/CMakeLists.txt
R clang-tools-extra/clang-doc/markdown/Markdown.cpp
R clang-tools-extra/clang-doc/markdown/Markdown.h
M clang-tools-extra/clang-doc/tool/ClangDocMain.cpp
M clang-tools-extra/clang-tidy/misc/RedundantExpressionCheck.cpp
M clang-tools-extra/clang-tidy/modernize/UseScopedLockCheck.cpp
M clang-tools-extra/clang-tidy/modernize/UseStringViewCheck.cpp
M clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp
M clang-tools-extra/clangd/ConfigYAML.cpp
M clang-tools-extra/clangd/SemanticHighlighting.cpp
M clang-tools-extra/clangd/test/lit.cfg.py
M clang-tools-extra/clangd/unittests/PrerequisiteModulesTest.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/modernize/use-scoped-lock.rst
M clang-tools-extra/include-cleaner/test/lit.cfg.py
M clang-tools-extra/test/clang-doc/basic-project.mustache.test
M clang-tools-extra/test/clang-doc/basic-project.test
M clang-tools-extra/test/clang-doc/md/array-type.cpp
M clang-tools-extra/test/clang-doc/md/builtin_types.cpp
M clang-tools-extra/test/clang-doc/md/class-partial-specialization.cpp
M clang-tools-extra/test/clang-doc/md/comments-in-macros.cpp
M clang-tools-extra/test/clang-doc/md/enum.cpp
M clang-tools-extra/test/clang-doc/md/function-pointer-type.cpp
M clang-tools-extra/test/clang-doc/md/member-function-pointer-type.cpp
M clang-tools-extra/test/clang-doc/md/namespace.cpp
M clang-tools-extra/test/clang-doc/md/nested-pointer-qualifiers.cpp
M clang-tools-extra/test/clang-doc/md/templates.cpp
R clang-tools-extra/test/clang-doc/yaml/builtin_types.cpp
R clang-tools-extra/test/clang-doc/yaml/conversion_function.cpp
R clang-tools-extra/test/clang-doc/yaml/single-file-public.cpp
R clang-tools-extra/test/clang-doc/yaml/single-file.cpp
R clang-tools-extra/test/clang-doc/yaml/templates.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/redundant-expression.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-scoped-lock-warn-on-single-locks-false.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-scoped-lock.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-string-view.cpp
A clang-tools-extra/test/clang-tidy/checkers/readability/Inputs/identifier-naming-macro-argument/.clang-tidy
A clang-tools-extra/test/clang-tidy/checkers/readability/Inputs/identifier-naming-macro-argument/include/macro.h
A clang-tools-extra/test/clang-tidy/checkers/readability/Inputs/identifier-naming-macro-argument/subdir/.clang-tidy
A clang-tools-extra/test/clang-tidy/checkers/readability/identifier-naming-macro-argument.cpp
M clang-tools-extra/test/lit.cfg.py
M clang-tools-extra/unittests/clang-doc/CMakeLists.txt
R clang-tools-extra/unittests/clang-doc/MDGeneratorTest.cpp
R clang-tools-extra/unittests/clang-doc/MarkdownParserTest.cpp
R clang-tools-extra/unittests/clang-doc/YAMLGeneratorTest.cpp
M clang/docs/LanguageExtensions.md
M clang/docs/ReleaseNotes.md
M clang/docs/analyzer/checkers.rst
M clang/include/clang/APINotes/APINotesReader.h
M clang/include/clang/AST/APValue.h
M clang/include/clang/AST/PropertiesBase.td
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LiveOrigins.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LoanPropagation.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/MovedLoans.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/Utils.h
M clang/include/clang/Analysis/Analyses/LiveVariables.h
M clang/include/clang/Basic/AArch64CodeGenUtils.h
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/IdentifierTable.h
M clang/include/clang/Basic/PointerAuthOptions.h
M clang/include/clang/Basic/TokenKinds.h
M clang/include/clang/Basic/arm_neon.td
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/Frontend/SSAFOptions.h
M clang/include/clang/Lex/Preprocessor.h
M clang/include/clang/Options/Options.td
M clang/include/clang/Parse/Parser.h
R clang/include/clang/ScalableStaticAnalysis/Analyses/OperatorNewDelete/OperatorNewDeletePointers.h
A clang/include/clang/ScalableStaticAnalysis/Analyses/SharedLexicalRepresentation/SharedLexicalRepresentation.h
A clang/include/clang/ScalableStaticAnalysis/Analyses/TypeConstrainedPointers/TypeConstrainedPointers.h
M clang/include/clang/ScalableStaticAnalysis/BuiltinAnchorSources.def
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/Template.h
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/BasicValueFactory.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/SMTConstraintManager.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/SMTConv.h
M clang/lib/APINotes/APINotesFormat.h
M clang/lib/APINotes/APINotesReader.cpp
M clang/lib/AST/APValue.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Context.cpp
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/EvalEmitter.h
M clang/lib/AST/ByteCode/EvaluationResult.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/ByteCode/Record.cpp
M clang/lib/AST/ByteCode/Record.h
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
M clang/lib/Analysis/LiveVariables.cpp
M clang/lib/Analysis/ThreadSafety.cpp
M clang/lib/Basic/Attributes.cpp
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGCUDANV.cpp
M clang/lib/CodeGen/CGExprCXX.cpp
M clang/lib/CodeGen/CGExprConstant.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/OffloadBundler.cpp
M clang/lib/Driver/SanitizerArgs.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Hexagon.cpp
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/lib/Format/CMakeLists.txt
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Headers/riscv_packed_simd.h
M clang/lib/Interpreter/IncrementalExecutor.cpp
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Lex/Lexer.cpp
M clang/lib/Lex/PPDirectives.cpp
M clang/lib/Lex/Preprocessor.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Parse/ParseExprCXX.cpp
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Parse/ParseStmt.cpp
M clang/lib/ScalableStaticAnalysis/Analyses/CMakeLists.txt
M clang/lib/ScalableStaticAnalysis/Analyses/CallGraph/CallGraphExtractor.cpp
R clang/lib/ScalableStaticAnalysis/Analyses/OperatorNewDelete/OperatorNewDeletePointers.cpp
M clang/lib/ScalableStaticAnalysis/Analyses/SSAFAnalysesCommon.cpp
M clang/lib/ScalableStaticAnalysis/Analyses/SSAFAnalysesCommon.h
A clang/lib/ScalableStaticAnalysis/Analyses/SharedLexicalRepresentation/SharedLexicalRepresentationFormat.cpp
A clang/lib/ScalableStaticAnalysis/Analyses/TypeConstrainedPointers/TypeConstrainedPointers.cpp
M clang/lib/Sema/DeclSpec.cpp
M clang/lib/Sema/SemaAMDGPU.cpp
M clang/lib/Sema/SemaAPINotes.cpp
M clang/lib/Sema/SemaBoundsSafety.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaFunctionEffects.cpp
M clang/lib/Sema/SemaLambda.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt
M clang/lib/StaticAnalyzer/Checkers/CStringChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/DeadStoresChecker.cpp
A clang/lib/StaticAnalyzer/Checkers/LifetimeModeling.cpp
A clang/lib/StaticAnalyzer/Checkers/LifetimeModeling.h
M clang/lib/StaticAnalyzer/Checkers/PthreadLockChecker.cpp
A clang/lib/StaticAnalyzer/Checkers/ReportDanglingPtrDeref.cpp
M clang/lib/StaticAnalyzer/Checkers/UndefinedAssignmentChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/UseAfterLifetimeEnd.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/DiagOutputUtils.h
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefCallArgsChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefLambdaCapturesChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefLocalVarsChecker.cpp
M clang/lib/StaticAnalyzer/Core/BasicValueFactory.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineC.cpp
M clang/lib/StaticAnalyzer/Core/RangeConstraintManager.cpp
M clang/lib/StaticAnalyzer/Core/Z3CrosscheckVisitor.cpp
A clang/test/APINotes/Inputs/Headers/WhereParametersSema.apinotes
A clang/test/APINotes/Inputs/Headers/WhereParametersSema.h
M clang/test/APINotes/Inputs/Headers/module.modulemap
A clang/test/APINotes/where-parameters-sema.cpp
M clang/test/AST/ByteCode/cxx11.cpp
M clang/test/AST/ByteCode/cxx2a.cpp
M clang/test/AST/ByteCode/invalid.cpp
M clang/test/AST/ByteCode/literals.cpp
M clang/test/AST/ByteCode/typeid.cpp
M clang/test/AST/ByteCode/unions.cpp
A clang/test/AST/ByteCode/virtual-bases-codegen.cpp
A clang/test/AST/ByteCode/virtual-bases.cpp
M clang/test/Analysis/ArrayBound/assumption-reporting.c
M clang/test/Analysis/Checkers/WebKit/local-vars-checked-const-member.cpp
M clang/test/Analysis/Checkers/WebKit/local-vars-counted-const-member.cpp
M clang/test/Analysis/Checkers/WebKit/member-function-pointer-crash.cpp
M clang/test/Analysis/Checkers/WebKit/unchecked-lambda-captures.cpp
M clang/test/Analysis/Checkers/WebKit/unchecked-local-vars.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures-decl-protects-this-crash.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-local-vars.cpp
M clang/test/Analysis/Checkers/WebKit/unretained-lambda-captures-arc.mm
M clang/test/Analysis/Checkers/WebKit/unretained-lambda-captures.mm
M clang/test/Analysis/Checkers/WebKit/unretained-local-vars-arc.mm
M clang/test/Analysis/Checkers/WebKit/unretained-local-vars.mm
R clang/test/Analysis/Scalable/OperatorNewDelete/Inputs/tu-summary-bad-id.json
R clang/test/Analysis/Scalable/OperatorNewDelete/Inputs/tu-summary-no-key.json
R clang/test/Analysis/Scalable/OperatorNewDelete/Inputs/tu-summary.json
R clang/test/Analysis/Scalable/OperatorNewDelete/Inputs/wpa-result-bad-id.json
R clang/test/Analysis/Scalable/OperatorNewDelete/Inputs/wpa-result-empty.json
R clang/test/Analysis/Scalable/OperatorNewDelete/Inputs/wpa-result-no-key.json
R clang/test/Analysis/Scalable/OperatorNewDelete/operator-new-delete.cpp
R clang/test/Analysis/Scalable/OperatorNewDelete/tu-summary-serialization.test
R clang/test/Analysis/Scalable/OperatorNewDelete/wpa-result-serialization.test
A clang/test/Analysis/Scalable/TypeConstrainedPointers/Inputs/tu-summary-bad-id.json
A clang/test/Analysis/Scalable/TypeConstrainedPointers/Inputs/tu-summary-no-key.json
A clang/test/Analysis/Scalable/TypeConstrainedPointers/Inputs/tu-summary.json
A clang/test/Analysis/Scalable/TypeConstrainedPointers/Inputs/wpa-result-bad-id.json
A clang/test/Analysis/Scalable/TypeConstrainedPointers/Inputs/wpa-result-empty.json
A clang/test/Analysis/Scalable/TypeConstrainedPointers/Inputs/wpa-result-no-key.json
A clang/test/Analysis/Scalable/TypeConstrainedPointers/tu-summary-serialization.test
A clang/test/Analysis/Scalable/TypeConstrainedPointers/type-constrained-pointers.cpp
A clang/test/Analysis/Scalable/TypeConstrainedPointers/wpa-result-serialization.test
A clang/test/Analysis/Scalable/call-graph-local-entities.cpp
M clang/test/Analysis/Scalable/command-line-interface.cpp
M clang/test/Analysis/Scalable/help.cpp
A clang/test/Analysis/Scalable/local-entities.cpp
M clang/test/Analysis/analyzer-config.c
M clang/test/Analysis/bitwise-shift-common.c
M clang/test/Analysis/c11lock.c
M clang/test/Analysis/constant-folding.c
A clang/test/Analysis/dangling-ptr-deref.cpp
M clang/test/Analysis/debug-lifetime-bound.cpp
M clang/test/Analysis/exploded-graph-rewriter/lit.local.cfg
M clang/test/Analysis/fuchsia_lock.c
A clang/test/Analysis/issue-173210-self-assign-init.c
M clang/test/Analysis/lifetime-bound.cpp
M clang/test/Analysis/lit.local.cfg
M clang/test/Analysis/malloc.c
M clang/test/Analysis/operator-calls.cpp
M clang/test/Analysis/pthreadlock-notes.c
M clang/test/Analysis/pthreadlock.c
M clang/test/Analysis/scan-build/lit.local.cfg
A clang/test/Analysis/string-search-modeling.c
M clang/test/Analysis/string.c
A clang/test/Analysis/z3/z3-logicalexpr-eval.c
M clang/test/Analysis/z3/z3-unarysymexpr.c
A clang/test/C/C2y/n3267.c
M clang/test/CIR/CodeGenBuiltins/X86/avx10_2_512bf16-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/avx10_2bf16-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/keylocker.c
M clang/test/CIR/CodeGenBuiltins/builtin-fpclassify.c
M clang/test/CIR/CodeGenBuiltins/builtin-isfpclass.c
M clang/test/CIR/CodeGenBuiltins/builtin-isinf-sign.c
A clang/test/CIR/CodeGenCXX/typeid-most-derived.cpp
A clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx1250.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-vi-f16.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
M clang/test/CXX/drs/cwg16xx.cpp
M clang/test/CXX/drs/cwg18xx.cpp
M clang/test/CXX/drs/cwg5xx.cpp
M clang/test/CXX/drs/cwg6xx.cpp
M clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c
M clang/test/CodeGen/AArch64/elf-pauthabi.c
M clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
M clang/test/CodeGen/AArch64/neon-2velem.c
M clang/test/CodeGen/AArch64/neon-extract.c
M clang/test/CodeGen/AArch64/neon-fcvt-intrinsics.c
M clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c
M clang/test/CodeGen/AArch64/neon-ldst-one.c
M clang/test/CodeGen/AArch64/neon-misc.c
M clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
M clang/test/CodeGen/AArch64/neon-vcmla.c
M clang/test/CodeGen/AArch64/neon/fullfp16.c
M clang/test/CodeGen/AArch64/neon/fused-multiply.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
M clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
M clang/test/CodeGen/AArch64/v8.5a-neon-frint3264-intrinsic.c
M clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M clang/test/CodeGen/SystemZ/zos-ppa1-name.c
M clang/test/CodeGen/arm-neon-vst.c
M clang/test/CodeGen/arm64_vdupq_n_f64.c
M clang/test/CodeGen/arm_neon_intrinsics.c
M clang/test/CodeGen/builtins.c
M clang/test/CodeGen/cx-complex-range-real.c
M clang/test/CodeGen/cx-complex-range.c
M clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
M clang/test/CodeGen/memcpy-inline-builtin.c
M clang/test/CodeGen/pr9614.c
M clang/test/CodeGen/ptrauth-init-fini.c
M clang/test/CodeGen/ptrauth-module-flags.c
M clang/test/CodeGenCUDA/device-stub.cu
M clang/test/CodeGenCXX/pfp-memcpy.cpp
M clang/test/CodeGenCXX/typeid-most-derived.cpp
M clang/test/CodeGenOpenCL/builtins-f16.cl
M clang/test/Driver/amdgpu-openmp-gpu-max-threads-per-block.c
M clang/test/Driver/clang-offload-bundler-multi-compress.c
M clang/test/Driver/dxc_debug.hlsl
M clang/test/Driver/hexagon-toolchain-linux.c
M clang/test/Driver/hexagon-toolchain-picolibc.c
M clang/test/Driver/msvc-link.c
A clang/test/Driver/openmp-invalid-target-id.c
M clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c
M clang/test/Driver/print-enabled-extensions/aarch64-ampere1c.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-a16.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-a17.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-m5.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.7-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.8-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.9-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.2-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.3-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.4-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.5-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
M clang/test/Driver/print-enabled-extensions/aarch64-c1-premium.c
M clang/test/Driver/print-enabled-extensions/aarch64-c1-pro.c
M clang/test/Driver/print-enabled-extensions/aarch64-c1-ultra.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a320.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520ae.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a720.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a720ae.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a725.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-x4.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-x925.c
M clang/test/Driver/print-enabled-extensions/aarch64-fujitsu-monaka.c
M clang/test/Driver/print-enabled-extensions/aarch64-gb10.c
M clang/test/Driver/print-enabled-extensions/aarch64-hip12.c
M clang/test/Driver/print-enabled-extensions/aarch64-neoverse-n3.c
M clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3.c
M clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3ae.c
M clang/test/Driver/print-enabled-extensions/aarch64-olympus.c
M clang/test/Driver/print-enabled-extensions/aarch64-rigel.c
M clang/test/Driver/print-enabled-extensions/riscv-spacemit-a100.c
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Driver/riscv-cpus.c
M clang/test/Interpreter/cxx20-modules.cppm
R clang/test/Interpreter/emulated-tls.cpp
M clang/test/Interpreter/execute-pch.cpp
A clang/test/Interpreter/pch-pic-mismatch.cpp
A clang/test/Interpreter/pcm-pic-mismatch.cpp
M clang/test/Misc/target-invalid-cpu-note/amdgcn.c
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper.c
M clang/test/OffloadTools/clang-offload-bundler/asserts-on.c
M clang/test/OffloadTools/clang-offload-bundler/basic.c
M clang/test/OffloadTools/clang-offload-bundler/fat-archive-unbundle-ext.c
M clang/test/OffloadTools/clang-offload-bundler/standardize.c
M clang/test/OffloadTools/clang-offload-bundler/zlib.c
M clang/test/OffloadTools/clang-offload-bundler/zstd.c
M clang/test/PCH/cxx20-template-args.cpp
M clang/test/Parser/cxx-default-args.cpp
A clang/test/Preprocessor/GH101342.c
M clang/test/Sema/LifetimeSafety/dangling-field.cpp
M clang/test/Sema/aarch64-neon-target.c
M clang/test/Sema/aarch64-neon-without-target-feature.cpp
M clang/test/Sema/attr-nonblocking-constraints.cpp
M clang/test/Sema/attr-sized-by-late-parsed-struct-ptrs.c
M clang/test/Sema/attr-sized-by-or-null-late-parsed-struct-ptrs.c
M clang/test/Sema/attr-sized-by-or-null-struct-ptrs.c
M clang/test/Sema/attr-sized-by-struct-ptrs.c
M clang/test/Sema/enum.c
A clang/test/SemaCXX/atomic-constexpr.cpp
M clang/test/SemaCXX/attr-sentinel.cpp
M clang/test/SemaCXX/auto-cxx0x.cpp
M clang/test/SemaCXX/concepts-subsumption.cpp
M clang/test/SemaCXX/constant-expression-cxx2a.cpp
M clang/test/SemaCXX/constexpr-late-instantiation.cpp
M clang/test/SemaCXX/cxx2b-deducing-this.cpp
M clang/test/SemaCXX/enable_if.cpp
M clang/test/SemaCXX/recovery-expr-type.cpp
M clang/test/SemaCXX/warn-thread-safety-analysis.cpp
A clang/test/SemaOpenCL/builtins-amdgcn-cmp-deprecated.cl
A clang/test/SemaTemplate/GH195988.cpp
M clang/test/SemaTemplate/concepts-lambda.cpp
M clang/test/SemaTemplate/concepts.cpp
M clang/test/lit.cfg.py
M clang/test/utils/update_cc_test_checks/Inputs/lit.cfg.example
M clang/test/utils/update_cc_test_checks/lit.local.cfg
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/unittests/AST/AttrTest.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Lex/PPMemoryAllocationsTest.cpp
R clang/unittests/ScalableStaticAnalysis/Analyses/OperatorNewDelete/OperatorNewDeletePointersExtractorTest.cpp
M clang/unittests/ScalableStaticAnalysis/Analyses/PointerFlow/PointerFlowTest.cpp
A clang/unittests/ScalableStaticAnalysis/Analyses/TypeConstrainedPointers/TypeConstrainedPointersExtractorTest.cpp
M clang/unittests/ScalableStaticAnalysis/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp
M clang/unittests/ScalableStaticAnalysis/CMakeLists.txt
A clang/unittests/ScalableStaticAnalysis/Serialization/JSONFormatTest/SharedLexicalRepresentationFormatTest.cpp
M clang/unittests/StaticAnalyzer/FalsePositiveRefutationBRVisitorTest.cpp
M clang/utils/TableGen/ClangOpcodesEmitter.cpp
M clang/utils/perf-training/bolt.lit.cfg
M clang/utils/perf-training/lit.cfg
M clang/utils/perf-training/order-files.lit.cfg
M clang/www/c_status.html
M clang/www/cxx_status.html
M cmake/Modules/LLVMVersion.cmake
M compiler-rt/lib/asan/AIX/asan.link_with_main_exec.txt
M compiler-rt/lib/asan/asan_malloc_linux.cpp
M compiler-rt/lib/gwp_asan/optional/backtrace_linux_libc.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_common_nolibc.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_dl.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_dl.h
M compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
M compiler-rt/lib/tsan/go/buildgo.sh
M compiler-rt/test/asan/TestCases/AIX/vec_malloc_calloc.cpp
M compiler-rt/test/builtins/Unit/lit.cfg.py
M compiler-rt/test/lit.common.cfg.py
M compiler-rt/test/sanitizer_common/TestCases/Linux/dlopen_image_base.c
A compiler-rt/test/ubsan/TestCases/Integer/Inputs/make_signed.h
A compiler-rt/test/ubsan/TestCases/Integer/Inputs/wrappers.h
A compiler-rt/test/ubsan/TestCases/Integer/suppressions-nested-calls.c
A cross-project-tests/dtlto/cache-extraction.test
R cross-project-tests/dtlto/cache-serialization.test
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M flang-rt/CMakeLists.txt
M flang-rt/test/lit.cfg.py
M flang/CMakeLists.txt
M flang/docs/FortranStandardsSupport.md
M flang/docs/ReleaseNotes.md
M flang/include/flang/Lower/MultiImageFortran.h
M flang/include/flang/Lower/OpenMP.h
M flang/include/flang/Optimizer/Analysis/ArraySectionAnalyzer.h
M flang/include/flang/Optimizer/Builder/FIRBuilder.h
M flang/include/flang/Optimizer/Builder/MIFCommon.h
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/include/flang/Optimizer/Dialect/FIROpsSupport.h
M flang/include/flang/Optimizer/Dialect/FIRTypes.td
M flang/include/flang/Optimizer/Dialect/MIF/MIFOps.td
M flang/include/flang/Optimizer/Transforms/Passes.td
A flang/include/flang/Semantics/omp-declare-variant.h
M flang/include/flang/Semantics/symbol.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/CMakeLists.txt
M flang/lib/Lower/CallInterface.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/MultiImageFortran.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/Support/Utils.cpp
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/lib/Optimizer/Builder/FIRBuilder.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/Builder/MIFCommon.cpp
M flang/lib/Optimizer/Builder/MutableBox.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Dialect/FIRType.cpp
M flang/lib/Optimizer/Dialect/MIF/MIFOps.cpp
M flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRAssign.cpp
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCTypeInterfaces.cpp
M flang/lib/Optimizer/OpenMP/AutomapToTargetData.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Support/CMakeLists.txt
M flang/lib/Optimizer/Support/InitFIR.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
M flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
A flang/lib/Optimizer/Transforms/EmitMIFGlobalCtors.cpp
M flang/lib/Optimizer/Transforms/FunctionAttr.cpp
M flang/lib/Optimizer/Transforms/MIFOpConversion.cpp
M flang/lib/Semantics/check-call.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-variant.cpp
M flang/lib/Semantics/mod-file.cpp
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Analysis/AliasAnalysis/alias-analysis-omp-private-boxed-wsloop.mlir
A flang/test/Analysis/AliasAnalysis/alias-analysis-omp-private-unboxed-wsloop.mlir
A flang/test/Driver/function-attr-readonly.f90
A flang/test/Evaluate/fold-kind-logical.f90
A flang/test/Evaluate/fold-kind-substring.f90
A flang/test/Evaluate/fold-kind-zero-size.f90
M flang/test/Evaluate/logical-args.f90
A flang/test/Fir/CUDA/cuda-managed-descriptor-component.fir
A flang/test/Fir/alloc-aligned-device.fir
A flang/test/Fir/alloc-aligned-omp.fir
A flang/test/Fir/alloc-aligned.fir
M flang/test/Fir/basic-program.fir
A flang/test/Fir/derived-type-aliases.fir
M flang/test/Fir/invalid.fir
A flang/test/HLFIR/inline-hlfir-assign-pointer-overlap.fir
A flang/test/HLFIR/inline-hlfir-assign-scalar-index.fir
A flang/test/HLFIR/inline-hlfir-assign-self-copy-runtime-stride.fir
A flang/test/HLFIR/inline-hlfir-assign-self-copy.fir
M flang/test/Integration/OpenMP/copyprivate.f90
M flang/test/Integration/OpenMP/private-global.f90
A flang/test/Integration/OpenMP/target-inreduction-llvmir.f90
M flang/test/Lower/CUDA/cuda-allocatable.cuf
A flang/test/Lower/CUDA/cuda-implicit-managed-alloc.cuf
M flang/test/Lower/HLFIR/allocatable-and-pointer-status-change.f90
A flang/test/Lower/HLFIR/array-ctor-character-kind.f90
M flang/test/Lower/HLFIR/custom-intrinsic.f90
M flang/test/Lower/HLFIR/intrinsic-dynamically-optional.f90
M flang/test/Lower/HLFIR/structure-constructor.f90
M flang/test/Lower/Intrinsics/dconjg.f90
M flang/test/Lower/Intrinsics/dimag.f90
M flang/test/Lower/Intrinsics/dreal.f90
M flang/test/Lower/Intrinsics/show_descriptor.f90
M flang/test/Lower/MIF/coarray_allocation4.f90
M flang/test/Lower/MIF/coarray_allocation5.f90
M flang/test/Lower/MIF/image_index.f90
M flang/test/Lower/OpenACC/acc-declare.f90
M flang/test/Lower/OpenMP/DelayedPrivatization/target-teams-distribute-private-adjustable-array.f90
A flang/test/Lower/OpenMP/Todo/declare-variant-structured-trait-property.f90
A flang/test/Lower/OpenMP/Todo/declare-variant-target-device.f90
R flang/test/Lower/OpenMP/Todo/declare-variant.f90
A flang/test/Lower/OpenMP/Todo/target-inreduction-common.f90
A flang/test/Lower/OpenMP/Todo/target-inreduction-equivalence.f90
A flang/test/Lower/OpenMP/Todo/target-inreduction-firstprivate.f90
R flang/test/Lower/OpenMP/Todo/target-inreduction.f90
M flang/test/Lower/OpenMP/allocatable-array-bounds.f90
M flang/test/Lower/OpenMP/copyprivate.f90
A flang/test/Lower/OpenMP/declare-mapper-hermetic.f90
A flang/test/Lower/OpenMP/declare-target-automap.f90
A flang/test/Lower/OpenMP/declare-variant-call.f90
A flang/test/Lower/OpenMP/declare-variant-construct.f90
A flang/test/Lower/OpenMP/declare-variant-device.f90
A flang/test/Lower/OpenMP/declare-variant-implementation.f90
A flang/test/Lower/OpenMP/declare-variant-module.f90
A flang/test/Lower/OpenMP/declare-variant-target-device.f90
M flang/test/Lower/OpenMP/delayed-privatization-array.f90
M flang/test/Lower/OpenMP/lastprivate-equivalence.f90
M flang/test/Lower/OpenMP/loop-directive.f90
M flang/test/Lower/OpenMP/optional-argument-map.f90
M flang/test/Lower/OpenMP/parallel-private-clause.f90
M flang/test/Lower/OpenMP/parallel-reduction-allocatable-array.f90
M flang/test/Lower/OpenMP/parallel-reduction-mixed.f90
A flang/test/Lower/OpenMP/private-array-boxing.f90
M flang/test/Lower/OpenMP/private-commonblock.f90
A flang/test/Lower/OpenMP/target-inreduction-unused.f90
A flang/test/Lower/OpenMP/target-inreduction.f90
A flang/test/Lower/OpenMP/unroll-partial01.f90
M flang/test/Lower/OpenMP/wsloop-reduction-allocatable-array-minmax.f90
M flang/test/Lower/OpenMP/wsloop-unstructured.f90
M flang/test/Lower/achar.f90
M flang/test/Lower/arguments.f90
M flang/test/Lower/call-copy-in-out.f90
M flang/test/Lower/dispatch.f90
M flang/test/Lower/do_concurrent_local_assoc_entity.f90
A flang/test/Lower/dummy-argument-readonly.f90
A flang/test/Lower/inline-hlfir-assign-forall-threadprivate.f90
A flang/test/Lower/inline-hlfir-assign-pointer-omp.f90
M flang/test/Lower/polymorphic-temp.f90
M flang/test/Lower/polymorphic.f90
M flang/test/Lower/select-type.f90
M flang/test/Lower/unsigned-ops.f90
M flang/test/Lower/volatile1.f90
A flang/test/Semantics/OpenMP/declare-reduction-operator-modfile-reexport.f90
M flang/test/Semantics/OpenMP/declare-simd-empty.f90
A flang/test/Semantics/OpenMP/declare-simd-scope.f90
M flang/test/Semantics/OpenMP/declare-simd.f90
M flang/test/Semantics/OpenMP/declare-variant.f90
A flang/test/Semantics/call48.f90
A flang/test/Semantics/modfile84.F90
A flang/test/Semantics/substring-literal-kind.f90
A flang/test/Transforms/function-attrs-readonly.fir
M flang/test/Transforms/omp-automap-to-target-data.fir
M flang/test/lit.cfg.py
M libc/cmake/modules/LLVMLibCArchitectures.cmake
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/riscv/headers.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/arpa/inet.yaml
M libc/include/limits.yaml
M libc/include/llvm-libc-macros/gpu/signal-macros.h
M libc/include/llvm-libc-macros/limits-macros.h
M libc/include/llvm-libc-macros/linux/signal-macros.h
M libc/include/llvm-libc-macros/netinet-in-macros.h
M libc/include/llvm-libc-types/__futex_word.h
M libc/include/sys/prctl.h.def
M libc/src/__support/CPP/expected.h
M libc/src/__support/File/linux/CMakeLists.txt
M libc/src/__support/File/linux/file.cpp
M libc/src/__support/StringUtil/CMakeLists.txt
M libc/src/__support/StringUtil/signal_to_string.cpp
M libc/src/__support/StringUtil/tables/CMakeLists.txt
M libc/src/__support/StringUtil/tables/linux_extension_signals.h
M libc/src/__support/StringUtil/tables/posix_signals.h
M libc/src/__support/StringUtil/tables/stdc_signals.h
M libc/src/__support/threads/linux/futex_utils.h
M libc/src/arpa/inet/CMakeLists.txt
A libc/src/arpa/inet/inet_ntoa.cpp
A libc/src/arpa/inet/inet_ntoa.h
M libc/src/pthread/CMakeLists.txt
M libc/src/pthread/pthread_condattr_getclock.cpp
M libc/src/pthread/pthread_condattr_getclock.h
M libc/src/pthread/pthread_condattr_setclock.cpp
M libc/src/pthread/pthread_condattr_setclock.h
M libc/src/signal/kill.h
M libc/src/signal/linux/CMakeLists.txt
M libc/src/signal/linux/kill.cpp
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M libcxx/src/filesystem/operations.cpp
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M llvm/include/llvm/CodeGen/UnreachableBlockElim.h
M llvm/include/llvm/DTLTO/DTLTO.h
M llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/include/llvm/IR/IntrinsicsRISCV.td
M llvm/include/llvm/IR/PassManager.h
M llvm/include/llvm/IR/PassManagerInternal.h
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/LTO/LTO.h
M llvm/include/llvm/MC/MCTargetOptions.h
M llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h
M llvm/include/llvm/Object/IRSymtab.h
M llvm/include/llvm/Object/OffloadBinary.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/OptimizationLevel.h
M llvm/include/llvm/ProfileData/SampleProfReader.h
M llvm/include/llvm/Target/TargetMachine.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/include/llvm/Transforms/IPO/ExpandVariadics.h
M llvm/include/llvm/Transforms/Scalar/GVN.h
M llvm/include/llvm/Transforms/Scalar/LoopPassManager.h
M llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h
M llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
M llvm/include/llvm/Transforms/Utils/UnifyLoopExits.h
M llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h
M llvm/lib/Analysis/InlineCost.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolutionDivision.cpp
M llvm/lib/Analysis/StackSafetyAnalysis.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/ExpandReductions.cpp
M llvm/lib/CodeGen/GlobalISel/Combiner.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/Rematerializer.cpp
M llvm/lib/CodeGen/ReplaceWithVeclib.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/DTLTO/DTLTO.cpp
M llvm/lib/DTLTO/DTLTOInputFiles.cpp
M llvm/lib/Debuginfod/BuildIDFetcher.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/ExecutionEngine/Orc/Layer.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/HTTP/HTTPClient.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/Constants.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/MC/MCObjectFileInfo.cpp
M llvm/lib/MC/MCTargetOptions.cpp
M llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
M llvm/lib/Object/ArchiveWriter.cpp
M llvm/lib/Object/OffloadBinary.cpp
M llvm/lib/Passes/CMakeLists.txt
R llvm/lib/Passes/OptimizationLevel.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/ProfileData/SampleProfReader.cpp
M llvm/lib/Support/APFloat.cpp
M llvm/lib/Support/KnownBits.cpp
M llvm/lib/Support/Windows/DynamicLibrary.inc
M llvm/lib/Support/raw_ostream.cpp
M llvm/lib/TableGen/TGParser.cpp
M llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
M llvm/lib/Target/AArch64/AArch64PointerAuth.h
M llvm/lib/Target/AArch64/AArch64Processors.td
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SystemOperands.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h
M llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
M llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.h
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/GCNNSAReassign.h
M llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h
M llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h
M llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SILowerControlFlow.h
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h
M llvm/lib/Target/AMDGPU/SILowerWWMCopies.h
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
M llvm/lib/Target/BPF/BPF.h
M llvm/lib/Target/BPF/BPFAsmPrinter.cpp
M llvm/lib/Target/BPF/BPFAsmPrinter.h
M llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp
A llvm/lib/Target/BPF/BPFCodeGenPassBuilder.cpp
M llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
M llvm/lib/Target/BPF/BPFMIChecking.cpp
M llvm/lib/Target/BPF/BPFMIPeephole.cpp
M llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp
M llvm/lib/Target/BPF/BPFPassRegistry.def
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
M llvm/lib/Target/BPF/BPFTargetMachine.h
M llvm/lib/Target/BPF/CMakeLists.txt
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYTargetStreamer.h
M llvm/lib/Target/DirectX/DXContainerGlobals.cpp
M llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp
M llvm/lib/Target/DirectX/DXILWriter/DXILWriterPass.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
M llvm/lib/Target/Hexagon/HexagonPatterns.td
M llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
M llvm/lib/Target/Mips/MipsFastISel.cpp
M llvm/lib/Target/NVPTX/CMakeLists.txt
M llvm/lib/Target/NVPTX/NVPTX.h
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXPassRegistry.def
A llvm/lib/Target/NVPTX/NVPTXPromoteParamAlign.cpp
R llvm/lib/Target/NVPTX/NVPTXSetByValParamAlign.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
M llvm/lib/Target/PowerPC/PPC.td
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/README.txt
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
M llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrFormats.td
M llvm/lib/Target/RISCV/RISCVInstrFormatsSpacemitV.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXSpacemiT.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVInstrPredicates.td
M llvm/lib/Target/RISCV/RISCVMacroFusion.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
M llvm/lib/Target/RISCV/RISCVSchedAndes45.td
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
M llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZTargetStreamer.cpp
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZTargetStreamer.h
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.h
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
M llvm/lib/Target/SystemZ/SystemZInstrVector.td
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86LowerTileCopy.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86WinEHUnwindV3.cpp
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/lib/Transforms/IPO/AlwaysInliner.cpp
M llvm/lib/Transforms/IPO/Attributor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
M llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
M llvm/lib/Transforms/Utils/FixIrreducible.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Utils/MetaRenamer.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/lib/Transforms/Utils/UnifyLoopExits.cpp
M llvm/lib/Transforms/Vectorize/CMakeLists.txt
M llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
M llvm/lib/Transforms/Vectorize/LoopIdiomVectorize.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.cpp
A llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.h
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/runtimes/CMakeLists.txt
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
M llvm/test/Analysis/CostModel/X86/div.ll
M llvm/test/Analysis/CostModel/X86/rem.ll
M llvm/test/Analysis/CycleInfo/basic.ll
M llvm/test/Analysis/CycleInfo/unreachable-predecessor.ll
A llvm/test/Analysis/LoopAccessAnalysis/wide-pointer-index-distance.ll
A llvm/test/Analysis/ScalarEvolution/ptrtoint-special-pointers.ll
M llvm/test/Analysis/ScalarEvolution/zext-add-nsw-fold.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/branch-outside.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/diverged-entry-headers-nested.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/diverged-entry-headers.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/exit-divergence.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/reducible-headers.ll
A llvm/test/Assembler/thinlto-bad-summary-5.ll
M llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir
A llvm/test/CodeGen/AArch64/GlobalISel/knownbits-avg.mir
A llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sat.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sdiv.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-udiv.mir
M llvm/test/CodeGen/AArch64/aarch64-known-bits-hadd.ll
M llvm/test/CodeGen/AArch64/active_lane_mask.ll
M llvm/test/CodeGen/AArch64/arm64-tls-dynamics.ll
M llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
M llvm/test/CodeGen/AArch64/arm64ec-hybrid-patchable.ll
M llvm/test/CodeGen/AArch64/basic-pic.ll
M llvm/test/CodeGen/AArch64/bf16-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
M llvm/test/CodeGen/AArch64/branch-cond-split-fcmp.ll
M llvm/test/CodeGen/AArch64/build-attributes-pauthabi.ll
M llvm/test/CodeGen/AArch64/clmul.ll
M llvm/test/CodeGen/AArch64/elf-globals-pic.ll
M llvm/test/CodeGen/AArch64/expand-vector-rot.ll
M llvm/test/CodeGen/AArch64/extern-weak.ll
M llvm/test/CodeGen/AArch64/fold-sext-in-reg-predicate-fixed-length.ll
M llvm/test/CodeGen/AArch64/fsh.ll
M llvm/test/CodeGen/AArch64/funnel-shift-rot.ll
M llvm/test/CodeGen/AArch64/get-active-lane-mask-extract.ll
M llvm/test/CodeGen/AArch64/got-abuse.ll
A llvm/test/CodeGen/AArch64/large-eh-encoding.ll
M llvm/test/CodeGen/AArch64/note-gnu-property-elf-pauthabi.ll
M llvm/test/CodeGen/AArch64/peephole-insert-subreg.mir
M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
M llvm/test/CodeGen/AArch64/ptrauth-elf-got-function-symbols.ll
A llvm/test/CodeGen/AArch64/ptrauth-init-fini-autoupgrade.ll
M llvm/test/CodeGen/AArch64/ptrauth-init-fini.ll
M llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll
M llvm/test/CodeGen/AArch64/round-fptoui-sat-scalar.ll
M llvm/test/CodeGen/AArch64/scalable_masked_interleaved_stores.ll
M llvm/test/CodeGen/AArch64/sve-cmp-folds.ll
A llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc-bf16.ll
M llvm/test/CodeGen/AArch64/sve-mask-partition.ll
M llvm/test/CodeGen/AArch64/sve2p1-while-pn-folds.ll
M llvm/test/CodeGen/AArch64/tagged-globals-pic.ll
M llvm/test/CodeGen/AArch64/tiny-model-pic.ll
M llvm/test/CodeGen/AArch64/tiny-model-static.ll
M llvm/test/CodeGen/AArch64/verify-imm.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add_shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-prelegalizer-combiner-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/and.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-asserts.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-concat-vectors.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-cse-leaves-dead-cast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_store_local.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-add-sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-and.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-or.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-xchg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-xor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_minmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/br-constant-invalid-sgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.ll
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M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sopc.mir
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M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir
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M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
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M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
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M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.v2i65.ll
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M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
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M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-sub.mir
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M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_common_dominator.mir
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M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader3.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader4.mir
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M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
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M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg-bfloat.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill.ll
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M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
M llvm/test/CodeGen/AMDGPU/call-return-types.ll
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M llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
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M llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
M llvm/test/CodeGen/AMDGPU/coalesce-identity-copies-undef-subregs.mir
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M llvm/test/CodeGen/AMDGPU/coalesce-liveout-undef-copy.mir
M llvm/test/CodeGen/AMDGPU/coalesce-vgpr-alignment.ll
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M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernel-argument-alignment.ll
M llvm/test/CodeGen/AMDGPU/implicitarg-offset-attributes.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si-gfx9.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-set-from-other-function.ll
M llvm/test/CodeGen/AMDGPU/indirect-private-64.ll
M llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.ll
M llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.mir
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M llvm/test/CodeGen/AMDGPU/infer-addrspace-flat-atomic.ll
M llvm/test/CodeGen/AMDGPU/infer-uniform-load-shader.ll
M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/inflate-av-remat-imm.mir
M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-agpr-negative-tests.mir
M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av.mir
M llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir
M llvm/test/CodeGen/AMDGPU/infloop-subrange-spill-inspect-subrange.mir
M llvm/test/CodeGen/AMDGPU/infloop-subrange-spill.mir
M llvm/test/CodeGen/AMDGPU/init-whole-wave-vgpr-count-large.ll
M llvm/test/CodeGen/AMDGPU/init-whole-wave-vgpr-count-leaf.ll
M llvm/test/CodeGen/AMDGPU/init-whole-wave-vgpr-count-use-inactive.ll
M llvm/test/CodeGen/AMDGPU/init-whole-wave-vgpr-count.ll
M llvm/test/CodeGen/AMDGPU/inline-asm-av-constraint-err.ll
M llvm/test/CodeGen/AMDGPU/inline-asm-av-constraint.ll
M llvm/test/CodeGen/AMDGPU/inline-asm-out-of-bounds-register.ll
M llvm/test/CodeGen/AMDGPU/inline-asm-reserved-regs.ll
M llvm/test/CodeGen/AMDGPU/inline-asm-vgpr-range-unsupported-width.ll
M llvm/test/CodeGen/AMDGPU/inline-asm-vgpr-sgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.ll
M llvm/test/CodeGen/AMDGPU/inline-attr.ll
M llvm/test/CodeGen/AMDGPU/inline-constraints.ll
M llvm/test/CodeGen/AMDGPU/inline-maxbb.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-16-fake16.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-16-true16.ll
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M llvm/test/CodeGen/AMDGPU/inlineasm-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-mismatched-size-error.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-packed.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-v16.ll
M llvm/test/CodeGen/AMDGPU/insert-branch-w32.mir
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-attr.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-literal.mir
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-parse.mir
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-wmma-xdl.mir
M llvm/test/CodeGen/AMDGPU/insert-delay-alu.mir
M llvm/test/CodeGen/AMDGPU/insert-handle-flat-vmem-ds.mir
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M llvm/test/CodeGen/AMDGPU/insert-waitcnts-callee.mir
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M llvm/test/CodeGen/AMDGPU/insert-waitcnts-fence-soft.mir
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-gfx12-wbinv.mir
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-hang.mir
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M llvm/test/CodeGen/AMDGPU/insert_subreg.ll
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M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.subtest-saddr.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
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M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/integer-select-src-modifiers.ll
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M llvm/test/CodeGen/AMDGPU/invalid-hidden-kernarg-in-kernel-signature.ll
M llvm/test/CodeGen/AMDGPU/invariant-image-load.ll
M llvm/test/CodeGen/AMDGPU/ipra.ll
M llvm/test/CodeGen/AMDGPU/irtranslator-whole-wave-functions.ll
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M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/isel-whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/issue121601-combine-concat-vectors-assumes-f16.ll
M llvm/test/CodeGen/AMDGPU/issue130120-eliminate-frame-index.ll
M llvm/test/CodeGen/AMDGPU/issue139317-bad-opsel-reg-sequence-fold.ll
M llvm/test/CodeGen/AMDGPU/issue153808-extract-subvector-legalize.ll
M llvm/test/CodeGen/AMDGPU/issue176966-extend-vector-inreg.ll
M llvm/test/CodeGen/AMDGPU/issue48473.mir
M llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
M llvm/test/CodeGen/AMDGPU/issue98474-assigned-physreg-interference.mir
M llvm/test/CodeGen/AMDGPU/issue98474-need-live-out-undef-subregister-def.ll
M llvm/test/CodeGen/AMDGPU/issue98474-virtregrewriter-live-out-undef-subregisters.mir
M llvm/test/CodeGen/AMDGPU/itofp.i128.bf.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
M llvm/test/CodeGen/AMDGPU/kernarg-size.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
M llvm/test/CodeGen/AMDGPU/kernel-mubuf-with-voffset.mir
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/kill-true-in-return-block.ll
M llvm/test/CodeGen/AMDGPU/known-never-nan.ll
M llvm/test/CodeGen/AMDGPU/known-never-snan.ll
M llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
M llvm/test/CodeGen/AMDGPU/large-alloca-graphics.ll
M llvm/test/CodeGen/AMDGPU/large-avgpr-assign-last.mir
M llvm/test/CodeGen/AMDGPU/large-constant-initializer.ll
M llvm/test/CodeGen/AMDGPU/large-phi-search.ll
M llvm/test/CodeGen/AMDGPU/large-work-group-promote-alloca.ll
M llvm/test/CodeGen/AMDGPU/lds-barrier-memoperand.ll
M llvm/test/CodeGen/AMDGPU/lds-bounds.ll
M llvm/test/CodeGen/AMDGPU/lds-branch-vmem-hazard.mir
M llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx11.mir
M llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx12.mir
M llvm/test/CodeGen/AMDGPU/lds-dma-hazards.mir
M llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir
M llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll
M llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-global-non-entry-func.ll
M llvm/test/CodeGen/AMDGPU/lds-initializer.ll
M llvm/test/CodeGen/AMDGPU/lds-limit-diagnostics-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/lds-limit-diagnostics.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-agpr.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-callgraph.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-named-barrier.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-typeid.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-named-barrier.ll
M llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
M llvm/test/CodeGen/AMDGPU/lds-mixed-absolute-addresses-unused.ll
M llvm/test/CodeGen/AMDGPU/lds-mixed-absolute-dynlds.ll
M llvm/test/CodeGen/AMDGPU/lds-no-realign-allocated-variables.ll
M llvm/test/CodeGen/AMDGPU/lds-reject-anonymous-kernels.ll
M llvm/test/CodeGen/AMDGPU/lds-reject-mixed-absolute-addresses.ll
M llvm/test/CodeGen/AMDGPU/lds-relocs.ll
M llvm/test/CodeGen/AMDGPU/lds-run-twice-absolute-md.ll
M llvm/test/CodeGen/AMDGPU/lds-run-twice.ll
M llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx950.ll
M llvm/test/CodeGen/AMDGPU/lds-size-pal-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/lds-size-pal-gfx950.ll
M llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll
M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/ldsdmacnt_sched.mir
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.dead.mir
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M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.ll
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M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f32.ll
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M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f32.ll
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M llvm/test/CodeGen/AMDGPU/legalize-fp-load-invariant.ll
M llvm/test/CodeGen/AMDGPU/legalize-soffset-mbuf.ll
M llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
M llvm/test/CodeGen/AMDGPU/licm-valu.mir
M llvm/test/CodeGen/AMDGPU/licm-wwm.mir
M llvm/test/CodeGen/AMDGPU/limit-soft-clause-reg-pressure.mir
M llvm/test/CodeGen/AMDGPU/literal-constant-like-operand-instruction-size.ll
M llvm/test/CodeGen/AMDGPU/literal64.ll
M llvm/test/CodeGen/AMDGPU/live-interval-bug-in-rename-independent-subregs.mir
M llvm/test/CodeGen/AMDGPU/liveout-implicit-def-subreg-redef-blender-verifier-error.mir
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.add.min.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.addrspacecast.nonnull.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.flat.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fract.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fract.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.mant.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.mant.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.store.async.from.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticsize.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.AFLCustomIRMutator.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.large.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.simple.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.small.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.single.2b.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.single.2c.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.flt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.pk.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.d16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.d16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.o.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.getlod.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.x.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.nsa.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.cd.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.cd.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.cd.g16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.cd.g16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.o.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.wave32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.direct.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.param.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lerp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.tr.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.clamp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mbcnt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.form.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.i8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.gfx1251.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.u32.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.msad.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mulhi.i24.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mulhi.u24.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.bcast.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.down.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.idx.gen.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.up.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.xor.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane32.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.prng.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.buffer.atomic.fadd_rtn_errors.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.queue.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.lds.ll
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.7
[skip ci]
Compare: https://github.com/llvm/llvm-project/compare/987bca0b729a...d6627298f304
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